Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and relates to a semiconductor structure, a forming method thereof and a memory. The semiconductor structure comprises a substrate, a word line structure, a conductive contact structure and a buffer layer, wherein: the substrate comprises an active region, the active region comprises a channel region and a source region and a drain region distributed on both sides of the channel region respectively, and the channel region has a word line trench; the word line structure is located in the word line trench; the conductive contact structure is connected with the top of the drain region; and the buffer layer is located between the conductive contact structure and the word line structure. The semiconductor structure can reduce leakage, improve device reliability and reduce standby power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high degree of integration and high transmission speed.

[0003] With the continuous advancement of semiconductor technology, the miniaturization of DRAM-related spatial dimensions greatly helps to save costs and generate revenue. However, the size of DRAM is positively correlated with its reliability. How to achieve DRAM size reduction while ensuring that its performance is not affected, or even improved, has become a research hotspot. However, with the reduction in size, the leakage current between the internal structures of DRAM increases, leading to reduced device reliability and increased standby power consumption.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce leakage current, improve device reliability, and reduce standby power consumption.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] The substrate includes an active region, the active region including a channel region and source and drain regions respectively distributed on both sides of the channel region, and the channel region having word line trenches;

[0008] The character line structure is located within the character line groove;

[0009] A conductive contact structure is connected to the top of the drain region;

[0010] A buffer layer is located between the conductive contact structure and the word line structure.

[0011] In one exemplary embodiment of this disclosure, the material of the buffer layer is titanium-containing silicon carbide or nickel-containing silicon carbide.

[0012] In one exemplary embodiment of this disclosure, the drain region includes a recessed portion extending inward from the top, and the semiconductor structure further includes:

[0013] A conductive material layer is conformally attached to the inner wall of the recess, and the conductive contact structure extends in a direction perpendicular to the substrate, with its end near the substrate extending into the recess and filling the recess having the conductive material layer.

[0014] In one exemplary embodiment of this disclosure, the material of the conductive material layer is silicon titanate or silicon nickelate.

[0015] In one exemplary embodiment of this disclosure, the top of the word line structure is lower than the top surface of the word line trench, and the semiconductor structure further includes:

[0016] A passivation layer covers the surface of the buffer layer and the substrate, and the passivation layer fills the word line trench.

[0017] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0018] An insulating layer covers the surface of the passivation layer, and the conductive contact structure penetrates the insulating layer and the passivation layer, filling the recess having the conductive material layer.

[0019] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0020] The bit line contact structure penetrates the insulating layer and the passivation layer and is connected to the source region. The orthographic projection of the bit line contact structure on the substrate does not overlap with the orthographic projection of the conductive contact structure on the substrate.

[0021] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0022] A substrate is provided, the substrate including an active region, the active region including a channel region and source and drain regions respectively distributed on both sides of the channel region, the channel region having word line trenches;

[0023] A character line structure is formed within the character line groove;

[0024] A conductive contact structure is formed on top of the drain region, and the conductive contact structure is connected to the drain region.

[0025] A buffer layer is formed between the conductive contact structure and the word line structure.

[0026] In one exemplary embodiment of this disclosure, the material of the buffer layer is titanium-containing silicon carbide or nickel-containing silicon carbide.

[0027] In one exemplary embodiment of this disclosure, the drain region includes a recessed portion extending inward from the top, and the forming method further includes:

[0028] A conductive material layer is formed to conformally adhere to the inner wall of the recess. The conductive contact structure extends in a direction perpendicular to the substrate, and its end near the substrate extends into the recess and fills the recess having the conductive material layer.

[0029] In one exemplary embodiment of this disclosure, the material of the conductive material layer is silicon titanate or silicon nickelate.

[0030] In one exemplary embodiment of this disclosure, the top of the character line structure is lower than the top surface of the character line groove, and the forming method further includes:

[0031] A passivation layer is formed covering the surface of the buffer layer and the substrate, and the passivation layer fills the word line trench.

[0032] In one exemplary embodiment of this disclosure, the forming method further includes:

[0033] An insulating layer is formed covering the surface of the passivation layer, and the conductive contact structure penetrates the insulating layer and the passivation layer, filling the recess having the conductive material layer.

[0034] In one exemplary embodiment of this disclosure, the forming method further includes:

[0035] A bit line contact structure is formed on top of the source region. The bit line contact structure penetrates the insulating layer and the passivation layer and is connected to the source region. The orthographic projection of the bit line contact structure on the substrate does not overlap with the orthographic projection of the conductive contact structure on the substrate.

[0036] In one exemplary embodiment of this disclosure, a conductive contact structure is formed on top of the drain region, the conductive contact structure being connected to the drain region, including:

[0037] The insulating layer, the passivation layer, and the drain region are etched to form a capacitor contact hole. The capacitor contact hole includes a recess formed in the drain region, a first segment exposing the buffer layer, and a second segment formed on the side of the first segment away from the recess. In a direction perpendicular to the substrate, the recess, the first segment, and the second segment are sequentially connected, and in a direction parallel to the substrate, the width of the recess is smaller than the width of the first segment and / or the second segment.

[0038] The capacitor contact hole is filled with conductive material to form a conductive contact structure.

[0039] In one exemplary embodiment of this disclosure, a buffer layer is formed between the conductive contact structure and the word line structure, comprising:

[0040] A mask layer is formed on the surface of the substrate, and the orthographic projection of the mask layer on the substrate does not overlap with the orthographic projection of the drain region on the substrate;

[0041] A buffer material layer is formed on the surface of the structure formed by the mask layer and the substrate;

[0042] The buffer material layer is etched, leaving only the buffer material layer located on the sidewall of the mask layer;

[0043] Remove the mask layer;

[0044] The remaining buffer material layer is annealed to form a buffer layer.

[0045] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0046] The semiconductor structure and its formation method disclosed herein, as well as the memory, allow the conductive contact structure to serve as the drain, and together with the word line structure and the subsequently formed bit line contact structure, constitute a buried transistor, thereby improving device integration. Simultaneously, since the buffer layer is located between the conductive contact structure and the word line structure, it increases the physical size between the word line structure and the capacitor contact plug, reducing the electric field between the drain and the gate, thus reducing gate-induced drain leakage (GIDL) current. Furthermore, the increased physical size not only effectively reduces standby power consumption and improves device reliability, but also effectively prevents excessive etching depth during etching, which could lead to large junction leakage currents in the substrate and source / drain doped regions (pn).

[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0049] Figure 1 This is a schematic diagram of the semiconductor structure in the embodiments of this disclosure;

[0050] Figure 2 This is a schematic diagram of the character line structure in the embodiments of this disclosure;

[0051] Figure 3This is a schematic diagram of the protective material layer in the embodiments of this disclosure;

[0052] Figure 4 This is a schematic diagram of the capacitor contact hole in the embodiment of this disclosure;

[0053] Figure 5 This is a schematic diagram of the conductive material layer in an embodiment of this disclosure;

[0054] Figure 6 This is a schematic diagram of the buffer layer in the embodiments of this disclosure;

[0055] Figure 7 This is a schematic diagram of the passivation layer in an embodiment of this disclosure;

[0056] Figure 8 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0057] Figure 9 This is a schematic diagram of the mask material layer 91 in the embodiments of this disclosure;

[0058] Figure 10 This is a schematic diagram showing the result after step S510 is completed in this embodiment of the present disclosure;

[0059] Figure 11 This is a schematic diagram showing the result after step S520 is completed in this embodiment of the present disclosure;

[0060] Figure 12 This is a schematic diagram showing the result after step S530 is completed in this embodiment of the present disclosure;

[0061] Figure 13 This is a schematic diagram after step S540 is completed in the embodiment of this disclosure.

[0062] Explanation of reference numerals in the attached figures:

[0063] 1. Substrate; 11. Active region; 111. Source region; 112. Drain region; 2. Word line structure; 21. Gate dielectric layer; 22. Conductive layer; 3. Conductive contact structure; 31. Capacitor contact hole; 311. Recess; 312. First hole segment; 313. Second hole segment; 4. Bit line contact structure; 400. Bit line; 5. Buffer layer; 51. Buffer material layer; 6. Conductive material layer; 7. Passivation layer; 71. Protective layer; 710. Protective material layer; 72. Passivation material layer; 8. Insulating layer; 9. First mask layer; 91. Mask material layer; 92. Photoresist layer; 93. Second mask layer. Detailed Implementation

[0064] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0065] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0066] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0067] This disclosure provides a semiconductor structure. Figure 1 A schematic diagram of the semiconductor structure in an embodiment of this disclosure is shown. See also Figure 1 As shown, the semiconductor structure includes a substrate 1, a word line structure 2, a conductive contact structure 3, and a buffer layer 5, wherein:

[0068] The substrate 1 may include an active region 11, which includes a channel region and a source region 111 and a drain region 112 distributed on both sides of the channel region, and the channel region has word line trenches.

[0069] Character line structure 2 is located within the character line groove;

[0070] The conductive contact structure 3 is connected to the top of the drain region 112;

[0071] The buffer layer 5 is located between the conductive contact structure 3 and the word line structure 2.

[0072] The semiconductor structure disclosed herein, comprising a source region 111, a drain region 112, and a portion of the word line structure located in the channel region, constitutes a buried transistor, thereby improving device integration. Simultaneously, a capacitor (not shown) is connected via a conductive contact structure 3 connecting the drain region 112. Since the buffer layer 5 is located between the conductive contact structure 3 and the word line structure 2, the physical dimensions between the word line structure 2 and the conductive contact structure 3 are increased, reducing the electric field between the drain and the gate, thus reducing gate-induced drain leakage (GIDL) current. Furthermore, the increased physical dimensions not only effectively reduce standby power consumption and improve device reliability but also effectively prevent excessive etching depth during etching, which could lead to large junction leakage currents in the substrate and the source / drain doped regions (pn).

[0073] The specific details of each part of the semiconductor structure in the embodiments of this disclosure are described in detail below:

[0074] like Figure 1 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0075] In one embodiment, the substrate 1 may be a silicon substrate, with multiple shallow trench isolation structures (not shown in the figure) formed therein. The shallow trench isolation structures are formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structures may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structures can be set according to actual needs. Multiple shallow trench isolation structures may be arranged side by side and can isolate several active regions 11 on the substrate 1. Each active region 11 may include a first doped region and a second doped region arranged at intervals.

[0076] The substrate 1 can be a p-type substrate, and the first doped region and the second doped region can be doped to form the source region 111 and the drain region 112, respectively. For example, both the first doped region and the second doped region can be n-type doped to form an n-type doped region, which can form a pn junction with the p-type substrate.

[0077] It should be noted that the area between the source region 111 and the drain region 112 can be a channel region (not shown in the figure) (that is, the active region 11 may include the channel region and the source region 111 and the drain region 112 respectively distributed on both sides of the channel region). The channel region can be used for current flow, and the current in the channel region can be controlled by the voltage of the word line structure 2 subsequently formed inside it to realize the gate control function.

[0078] In one exemplary embodiment of this disclosure, word line trenches may be formed within the channel region, and these word line trenches may be used to form word line structures 2. For example, the substrate 1 may be etched to form word line trenches, which may be continuous at both ends and may be strip-shaped. The word line trenches may pass through multiple active regions 11, and the portion of the trenches that passes through the active regions 11 may be located within the channel region of the active regions 11.

[0079] For example, a photoresist layer can be formed on the surface of substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without any special limitation.

[0080] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the pattern required for the word line trenches. Subsequently, the exposed photoresist layer can be developed to form developed areas, each of which exposes the surface of the substrate 1, and the pattern of the developed area can be the same as the pattern required for the word line trenches, and the size of the developed area can be matched with the size of the required word line trenches.

[0081] The substrate 1 can be etched in the developing area using a plasma etching process to form word line trenches within the substrate 1. After completing the etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing, thereby exposing the substrate 1 with the word line trenches.

[0082] The character line structure 2 can be located within the character line groove. In some embodiments of this disclosure, the top of the character line structure 2 can be lower than the top surface of the character line groove to leave space for the subsequent formation of the protective layer 71. That is, the character line structure 2 can be formed within the character line groove.

[0083] In one exemplary embodiment of this disclosure, Figure 2 A schematic diagram of the character line structure in an embodiment of this disclosure is shown. See also: Figure 2 As shown, the word line structure 2 may include an inter-gate dielectric layer 21 and a conductive layer 22, wherein:

[0084] A conformally attached inter-gate dielectric layer 21 can be formed on the sidewalls and bottom of each character line groove. The material of the inter-gate dielectric layer 21 may include silicon oxide or a combination of the aforementioned materials. Its thickness may be 1nm to 9nm. For example, it may be 1nm, 2nm, 4nm, 6nm, 8nm or 9nm. Of course, it may also be other thicknesses, which will not be listed here.

[0085] For example, conformally attached inter-gate dielectric layers 21 can be formed on the sidewalls and bottom of each word trench using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or thermal oxidation. Of course, other methods can also be used to form the inter-gate dielectric layers 21, and no special limitation is made here. For ease of fabrication, during the formation of the inter-gate dielectric layers 21, the inter-gate dielectric layers 21 can completely cover the top surface of the substrate 1. Subsequently, the inter-gate dielectric layers 21 located on the top surface of each substrate 1 can be removed, leaving only the inter-gate dielectric layers 21 located on the sidewalls and bottom of each word trench.

[0086] In some embodiments of this disclosure, a thermal oxidation process can be used to treat the surface of the inter-gate dielectric layer 21 to improve the density of the inter-gate dielectric layer 21, thereby reducing leakage current and improving gate control capability.

[0087] In one exemplary embodiment of this disclosure, see also Figure 2 As shown, the conductive layer 22 can fill the word line trench having the inter-gate dielectric layer 21, and the surface of the conductive layer 22 can be lower than the top surface of the word line trench, that is, the surface of the conductive layer 22 can be lower than the surface of the substrate 1. In some embodiments of this disclosure, the material of the conductive layer 22 can be tungsten or titanium nitride, and of course, it can also be other materials with strong conductivity, which will not be listed here.

[0088] The conductive layer 22 can be formed in the word line trench with the inter-gate dielectric layer 21 by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition or physical vapor deposition. Of course, the conductive layer 22 can also be formed by other means. No special limitation is made on the formation method of the conductive layer 22 here.

[0089] In some embodiments of this disclosure, the semiconductor structure may further include a protective layer 71. The protective layer 71 may be formed within the word line trench. It may be a thin film formed on the surface of the conductive layer 22 or a coating formed on the surface of the conductive layer 22. The specific form of the protective layer 71 is not specifically limited herein. The material of the protective layer 71 may be an insulating material, for example, SiCN. By insulating and protecting the surface of the word line structure 2 through the protective layer 71, damage to the surface of the word line structure 2 can be avoided by subsequent processes, and the possibility of coupling or short circuit between the word line structure 2 and other surrounding structures can be reduced, thereby improving product yield.

[0090] For example, the protective layer 71 can be formed on the surface of the conductive layer 22 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that the surface of the protective layer 71 facing away from the conductive layer 22 can be flush with the surface of the substrate 1.

[0091] In one exemplary embodiment of this disclosure, such as Figure 3As shown, during the formation of the protective layer 71, a protective material layer 710 can be formed on the surface of the structure jointly formed by the substrate 1 and the conductive layer 22 by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition. The protective material layer 710 can fill the word line trench and cover the surface of the substrate 1. Subsequently, the protective material layer 710 located outside the word line trench can be removed by etching process, leaving only the protective material layer 710 located in the word line trench. The protective material layer 710 located in the word line trench can be defined as the protective layer 71.

[0092] See also Figure 1 As shown, conductive contact structure 3 and bit line contact structure 4 can be formed on the top of substrate 1, respectively. Bit line contact structure 4 and conductive contact structure 3 can serve as source and drain, respectively, and together with word line structure 2, they form a buried transistor, which can improve device integration.

[0093] For example, a bit line contact structure 4 and a conductive contact structure 3 can be formed on the top of the source region 111 and the drain region 112 on both sides of the word line trench, respectively. The bit line contact structure 4, the conductive contact structure 3, and the word line structure 2 can be separated by an insulating material to avoid coupling or short circuit between the structures. For example, the bit line contact structure 4, the word line structure 2, and the conductive contact structure 3 can be separated by a protective layer 71, a passivation layer 7, or an insulating layer 8.

[0094] In one exemplary embodiment of this disclosure, the conductive contact structure 3 extends in a direction perpendicular to the substrate 1, and its end near the substrate 1 extends into the drain region 112. In the direction parallel to the substrate 1, the width of the portion of the conductive contact structure 3 extending into the drain region 112 is smaller than the width of its portion away from the substrate 1. This reduces the contact area between the conductive contact structure 3 and the drain region 112, helping to reduce contact resistance and thus improve product yield. The conductive contact structure 3 can be made of a conductive material, such as tungsten or titanium nitride. Of course, other materials with good conductivity can also be used; no specific limitation is made to the material of the conductive contact structure 3 here.

[0095] In some embodiments of this disclosure, such as Figure 4As shown, the drain region 112 may include a recess 311 that is recessed inward from the top. Due to the etching selectivity and the presence of the buffer layer 5 (e.g., SiC-TiO), the formation of the recess 311 can slow down the excessive etching depth on the substrate surface, thereby improving both the reduction of gate-induced drain leakage (GIDL) current and the reduction of pn junction leakage current. For example, the drain region 112 can be etched using an etching process to form the recess 311 in the drain region 112. The semiconductor structure of this disclosure may also include a conductive material layer 6. Figure 5 A schematic diagram of the conductive material layer 6 in an embodiment of this disclosure is shown. See also Figure 5 As shown, the conductive material layer 6 can be conformally attached to the inner wall of the recess 311. The conductive material layer 6 can be a thin film conformally attached to the sidewall and bottom of the recess 311, or it can be a coating conformally attached to the sidewall and bottom of the recess 311. No particular limitation is made to the form of the conductive material layer 6 here. The conductive material layer 6 can be formed on the sidewall and surface of the recess 311 by vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the conductive material layer 6. No particular limitation is made to the formation method of the conductive material layer 6 here.

[0096] See also Figure 1 As shown, the end of the conductive contact structure 3 near the substrate 1 can extend into the recess 311 and make contact with the conductive material layer 6 within the recess 311. For example, the conductive contact structure 3 can fill the recess 311 having the conductive material layer 6.

[0097] The material of the conductive material layer 6 may be different from the material of the conductive contact structure 3. In order to reduce the contact resistance, the resistance value of the material of the conductive material layer 6 may be less than the resistance value of the material of the conductive contact structure 3. For example, the material of the conductive contact structure 3 may be tungsten, and the material of the conductive material layer 6 may be silicon titanate or silicon nickelate.

[0098] In one exemplary embodiment of this disclosure, the conductive contact structure 3 extends in a direction perpendicular to the substrate 1, and its end near the substrate 1 extends into the drain region 112. In a direction parallel to the substrate 1, the width of the portion of the conductive contact structure 3 extending into the drain region 112 is smaller than the width of its portion away from the substrate 1. This reduces the contact area between the conductive contact structure 3 and the drain region 112, helping to reduce contact resistance and thus improve product reliability. The conductive contact structure 3 can be made of a conductive material, such as tungsten or titanium nitride. Of course, other materials with good conductivity can also be used; no specific limitation is made to the material of the conductive contact structure 3 here.

[0099] In some embodiments of this disclosure, such as Figure 1 As shown, the bit line contact structure 4 can be connected to the source region 111. For example, the source region 111 may include a groove recessed from the top inwards. For example, the source region 111 can be etched by an etching process to form the groove. One end of the bit line contact structure 4 can extend into the groove and fill the interior of the groove. In one embodiment, the bit line contact structure 4 can extend in a direction perpendicular to the substrate 1, and its orthographic projection on the substrate 1 does not overlap with the orthographic projection of the conductive contact structure 3 on the substrate 1.

[0100] In one exemplary embodiment of this disclosure, the semiconductor structure may further include an ohmic contact layer. This ohmic contact layer can be conformally attached to the inner wall of the groove. The ohmic contact layer can be a thin film conformally attached to the sidewalls and bottom of the groove, or a coating conformally attached to the sidewalls and bottom of the groove. No specific limitation is made to the specific form of the ohmic contact layer here. The ohmic contact layer can be formed on the sidewalls and surface of the groove by methods such as vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the ohmic contact layer. No specific limitation is made to the formation method of the ohmic contact layer here.

[0101] It should be noted that the end of the bit line contact structure 4 near the substrate 1 can extend into the groove and make contact with the ohmic contact layer in the groove. For example, the bit line contact structure 4 can fill the groove with the ohmic contact layer.

[0102] The material of the ohmic contact layer may be different from the material of the bit line contact structure 4. In order to reduce the contact resistance, the resistance value of the ohmic contact layer material may be less than the resistance value of the material of the bit line contact structure 4. For example, the material of the bit line contact structure 4 may be tungsten, and the material of the ohmic contact layer may be a metal silicide, such as cobalt silicide.

[0103] In some embodiments of this disclosure, Figure 6 A schematic diagram of the buffer layer in an embodiment of this disclosure is shown, see below. Figure 6As shown, the buffer layer 5 can be located between the conductive contact structure 3 and the word line contact structure. For example, the buffer layer 5 can be formed on the surface of the drain region 112, which can be in contact with the conductive contact structure 3. At the same time, the buffer layer 5 can also be insulated from the word line structure 2. In this embodiment, the buffer layer 5 can, for example, have an arc-shaped surface, so that it can be conformally attached to the surface of the conductive contact structure 3, and the size of the buffer layer 5 is larger the closer it is to the word line structure 2. This embodiment increases the physical size between the word line structure 2 and the conductive contact structure 3 by designing the buffer layer 5, thereby reducing the electric field between the drain and the gate, and thus reducing the gate-induced drain leakage (GIDL) current. At the same time, due to the increase in physical size, in addition to effectively reducing standby power consumption and improving device reliability, it can also effectively avoid excessive etching depth during etching, which would cause a large junction leakage current in the substrate and the source / drain doped region (pn).

[0104] In one exemplary embodiment of this disclosure, the buffer layer 5 may be made of a conductive material, such as titanium-containing silicon carbide or nickel-containing silicon carbide. These materials have good conductivity and adhesion, which can ensure the performance of the buffer layer. The buffer layer 5 can be formed on the surface of the drain region 112 by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, the buffer layer 5 can also be formed by other means, and no special limitation is made here on the formation method of the buffer layer 5.

[0105] In one exemplary embodiment of this disclosure, the semiconductor structure may further include a passivation layer 7. Figure 7 A schematic diagram of the passivation layer 7 in an embodiment of this disclosure is shown. See also Figure 7 As shown, the passivation layer 7 can cover the surface of the buffer layer 5 and the substrate 1, and the passivation layer 7 fills the word line trench. The conductive contact structure 3 can penetrate the passivation layer 7 and connect to the drain region 112; meanwhile, continue to refer to Figure 1 As shown, the bit line contact structure 4 can penetrate the passivation layer 7 and is connected to the source region 111.

[0106] In some embodiments of this disclosure, see also Figure 7 As shown, the passivation layer 7 may include a passivation material layer 72, which may cover the surface of the structure jointly formed by the substrate 1, the buffer layer 5, and the protective layer 71. The material of the passivation material layer 72 may be an insulating material with a low dielectric constant. (Continue to see...) Figure 1 As shown, the conductive contact structure 3 can penetrate the passivation material layer 72 and be connected to the drain region 112; at the same time, the bit line contact structure 4 can penetrate the passivation material layer 72 and be connected to the source region 111, thereby reducing the parasitic capacitance between the word line structure 2 and the conductive contact structure 3 and the bit line contact structure 4 through the passivation material layer 72 with a lower dielectric constant.

[0107] For example, the material of the passivation material layer 72 can be the same as that of the protective layer 71, such as SiCN. The passivation material layer 72 can be formed on the surface of the structure consisting of the substrate 1, the buffer layer 5, and the protective layer 71 by means of atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the passivation material layer 72; no specific limitation is made here. In some embodiments of this disclosure, the protective layer 71 and the passivation material layer 72 can together constitute the passivation layer 7, which can be made of a material with a low dielectric constant, thereby reducing the parasitic capacitance between the word line structure 2 and the bit line contact structure 4 and the conductive contact structure 3.

[0108] In one exemplary embodiment of this disclosure, see Figure 4 and Figure 5 As shown, the semiconductor structure disclosed herein may further include an insulating layer 8, which may cover the surface of the passivation layer 7. The conductive contact structure 3 may penetrate the insulating layer 8 and the passivation layer 7 and be connected to the drain region 112. Meanwhile, the bit line contact structure 4 may penetrate the insulating layer 8 and the passivation layer 7 and be connected to the source region 111.

[0109] In some embodiments of this disclosure, the insulating layer 8 can be made of an insulating material. The insulating layer 8 and the passivation layer 7 provide double insulation protection for the surface of the word line structure 2, preventing coupling or short circuits between the word line structure 2 and other structures, thus improving product yield. Simultaneously, the insulating layer 8 can also separate the bit line contact structure 4 from the conductive contact structure 3, preventing coupling or short circuits between them, further improving product yield. For example, the insulating layer 8 can be made of silicon oxide.

[0110] For example, an insulating layer 8 can be formed on the surface of the passivation layer 7 by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation or magnetron sputtering. Of course, the insulating layer 8 can also be formed by other means. No special limitation is made on the formation method of the insulating layer 8 here.

[0111] This disclosure also provides a method for forming a semiconductor structure. Figure 8 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure is shown. See also... Figure 8 As shown, the forming method may include steps S110-S140, wherein:

[0112] Step S110: Provide a substrate, the substrate including an active region, the active region including a channel region and a source region and a drain region respectively distributed on both sides of the channel region, the channel region having a word line trench;

[0113] Step S120: Form a character line structure within the character line groove;

[0114] Step S130: A conductive contact structure is formed on top of the drain region, and the conductive contact structure is connected to the drain region;

[0115] Step S140: A buffer layer is formed between the conductive contact structure and the word line structure.

[0116] The semiconductor structure formation method disclosed herein allows the conductive contact structure 3 to serve as the drain, and together with the word line structure 2 and the subsequently formed bit line contact structure 4, constitutes a buried transistor, thereby improving device integration. Simultaneously, since the buffer layer 5 is located between the conductive contact structure 3 and the word line structure 2, it increases the physical size between the word line structure 2 and the conductive contact structure 3, reducing the electric field between the drain and the gate, thus reducing gate-induced drain leakage (GIDL) current. Furthermore, the increased physical size not only effectively reduces standby power consumption and improves device reliability, but also effectively prevents excessive etching depth during etching, which could lead to large junction leakage currents in the substrate and source / drain doped regions (pn).

[0117] The steps of the method for forming the semiconductor structure disclosed herein are described in detail below:

[0118] In step S110, a substrate 1 is provided, the substrate 1 including an active region 11, the active region 11 including a channel region and a source region 111 and a drain region 112 respectively distributed on both sides of the channel region, and the channel region having a word line trench.

[0119] like Figure 1 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0120] In one embodiment, the substrate 1 may be a silicon substrate, with multiple shallow trench isolation structures (not shown in the figure) formed therein. The shallow trench isolation structures are formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structures may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structures can be set according to actual needs. Multiple shallow trench isolation structures may be arranged side by side and can isolate several active regions 11 on the substrate 1. Each active region 11 may include a first doped region and a second doped region arranged at intervals.

[0121] The substrate 1 can be a p-type substrate, and the first doped region and the second doped region can be doped to form the source region 111 and the drain region 112, respectively. For example, both the first doped region and the second doped region can be n-type doped to form an n-type doped region, which can form a pn junction with the p-type substrate.

[0122] It should be noted that the area between the source region 111 and the drain region 112 can be a channel region (not shown in the figure) (that is, the active region 11 may include the channel region and the source region 111 and the drain region 112 respectively distributed on both sides of the channel region). The channel region can be used for current flow, and the current in the channel region can be controlled by the voltage of the word line structure 2 subsequently formed inside it to realize the gate control function.

[0123] In one exemplary embodiment of this disclosure, word line trenches may be formed within the channel region, and these word line trenches may be used to form word line structures 2. For example, the substrate 1 may be etched to form word line trenches, which may be continuous at both ends and may be strip-shaped. The word line trenches may pass through multiple active regions 11, and the portion of the trenches that passes through the active regions 11 may be located within the channel region of the active regions 11.

[0124] For example, a photoresist layer can be formed on the surface of substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without any special limitation.

[0125] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can be matched with the pattern required for the word line trenches. Subsequently, the exposed photoresist layer can be developed to form developed areas, each of which exposes the surface of the substrate 1, and the pattern of the developed area can be the same as the pattern required for the word line trenches, and the size of the developed area can be matched with the size of the required word line trenches.

[0126] The substrate 1 can be etched in the developing area using a plasma etching process to form word line trenches within the substrate 1. After completing the etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing, thereby exposing the substrate 1 with the word line trenches.

[0127] In step S120, a character line structure 2 is formed within the character line groove.

[0128] The character line structure 2 can be located within the character line groove. In some embodiments of this disclosure, the top of the character line structure 2 can be lower than the top surface of the character line groove to leave space for the subsequent formation of the protective layer 71. That is, the character line structure 2 can be formed within the character line groove.

[0129] In one exemplary embodiment of this disclosure, forming the word line structure 2 within the word line groove (i.e., step S120) may include steps S210 and S220, wherein:

[0130] Step S210: A conformally attached inter-gate dielectric layer 21 is formed in the word line groove.

[0131] A conformally attached inter-gate dielectric layer 21 can be formed on the sidewalls and bottom of each character line groove. The material of the inter-gate dielectric layer 21 may include silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of the aforementioned materials. Its thickness can be 1nm to 9nm. For example, it can be 1nm, 2nm, 4nm, 6nm, 8nm or 9nm. Of course, it can also be other thicknesses, which will not be listed here.

[0132] For example, conformally attached inter-gate dielectric layers 21 can be formed on the sidewalls and bottom of each word trench using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or thermal oxidation. Of course, other methods can also be used to form the inter-gate dielectric layers 21, and no special limitation is made here. For ease of fabrication, during the formation of the inter-gate dielectric layers 21, the inter-gate dielectric layers 21 can completely cover the top surface of the substrate 1. Subsequently, the inter-gate dielectric layers 21 located on the top surface of each substrate 1 can be removed, leaving only the inter-gate dielectric layers 21 located on the sidewalls and bottom of each word trench.

[0133] In some embodiments of this disclosure, the surface of the inter-gate dielectric layer 21 can be treated by thermal oxidation to improve the density of the inter-gate dielectric layer 21, thereby reducing leakage current, improving gate control capability, and enhancing the barrier effect of the inter-gate dielectric layer 21 on impurities in the substrate 1, preventing impurities in the substrate 1 from diffusing into the word line trench, and improving structural stability.

[0134] Step S220: A conductive layer 22 is formed in the word line trench having the inter-gate dielectric layer 21, the surface of the conductive layer 22 being lower than the surface of the substrate 1.

[0135] In one exemplary embodiment of this disclosure, see Figure 2 As shown, the conductive layer 22 can fill the word line trench having the inter-gate dielectric layer 21, and the surface of the conductive layer 22 can be lower than the top surface of the word line trench, that is, the surface of the conductive layer 22 can be lower than the surface of the substrate 1. In some embodiments of this disclosure, the material of the conductive layer 22 can be tungsten or titanium nitride, and of course, it can also be other conductive materials, which will not be listed here.

[0136] The conductive layer 22 can be formed in the word line trench with the inter-gate dielectric layer 21 by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition or physical vapor deposition. Of course, the conductive layer 22 can also be formed by other means. No special limitation is made on the formation method of the conductive layer 22 here.

[0137] In step S130, a conductive contact structure 3 is formed on the top of the drain region 112, and the conductive contact structure 3 is connected to the drain region 112.

[0138] See also Figure 1 As shown, the drain and source in this embodiment, together with the word line structure 2, constitute a buried transistor, which can improve the device integration.

[0139] In one exemplary embodiment of this disclosure, a conductive contact structure 3 can be formed on the top of the drain region 112. The conductive contact structure 3 can extend in a direction perpendicular to the substrate 1, and its end near the substrate 1 can penetrate into the drain region 112. In the direction parallel to the substrate 1, the width of the portion of the conductive contact structure 3 extending into the drain region 112 can be smaller than the width of its portion away from the substrate 1, thereby reducing the contact area between the conductive contact structure 3 and the drain region 112, which helps to reduce the contact resistance and thus improve the product yield. The conductive contact structure 3 can be made of a conductive material, such as tungsten or titanium nitride. Of course, it can also be other materials with good conductivity. No special limitation is made to the material of the conductive contact structure 3 here.

[0140] In some embodiments of this disclosure, such as Figure 4 As shown, the drain region 112 may include a recess 311 that is recessed inward from the top. For example, the drain region 112 may be etched by an etching process to form the recess 311 in the drain region 112. The method for forming the semiconductor structure disclosed herein may further include:

[0141] In step S150, a conductive material layer 6 is formed that conformally adheres to the inner wall of the recess 311. The conductive contact structure 3 extends in a direction perpendicular to the substrate 1, and its end near the substrate 1 extends into the recess 311 and fills the recess 311 having the conductive material layer 6.

[0142] Figure 5 A schematic diagram of the conductive material layer 6 in an embodiment of this disclosure is shown. See also Figure 5 As shown, the conductive material layer 6 can be conformally attached to the inner wall of the recess 311. The conductive material layer 6 can be a thin film conformally attached to the sidewalls and bottom of the recess 311, or it can be a coating conformally attached to the sidewalls and bottom of the recess 311. No particular limitation is made to the form of the conductive material layer 6 here. The conductive material layer 6 can be formed on the sidewalls and surface of the recess 311 by vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the conductive material layer 6. No particular limitation is made to the formation method of the conductive material layer 6 here.

[0143] See also Figure 1As shown, the end of the conductive contact structure 3 near the substrate 1 can extend into the recess 311 and make contact with the conductive material layer 6 within the recess 311. For example, the conductive contact structure 3 can fill the recess 311 having the conductive material layer 6.

[0144] The material of the conductive material layer 6 may be different from the material of the conductive contact structure 3. In order to reduce the contact resistance, the resistance value of the material of the conductive material layer 6 may be less than the resistance value of the material of the conductive contact structure 3. For example, the material of the conductive contact structure 3 may be tungsten, and the material of the conductive material layer 6 may be silicon titanate or silicon nickelate.

[0145] In one exemplary embodiment of this disclosure, the conductive contact structure 3 extends in a direction perpendicular to the substrate 1, and its end near the substrate 1 extends into the drain region 112. In a direction parallel to the substrate 1, the width of the portion of the conductive contact structure 3 extending into the drain region 112 is smaller than the width of its portion away from the substrate 1. This reduces the contact area between the conductive contact structure 3 and the drain region 112, helping to reduce contact resistance and thus improve product reliability. The conductive contact structure 3 can be made of a conductive material, such as tungsten or titanium nitride. Of course, other materials with good conductivity can also be used; no specific limitation is made to the material of the conductive contact structure 3 here.

[0146] In some embodiments of this disclosure, the method for forming the semiconductor structure may further include:

[0147] In step S160, a bit line contact structure 4 is formed on the top of the source region 111. The bit line contact structure 4 penetrates the insulating layer 8 and the passivation layer 7 and is connected to the source region 111. The orthographic projection of the bit line contact structure 4 on the substrate 1 does not overlap with the orthographic projection of the conductive contact structure 3 on the substrate 1.

[0148] See also Figure 1 As shown, the bit line contact structure 4 can be connected to the source region 111. For example, the source region 111 may include a groove recessed from the top inwards. For example, the source region 111 can be etched by an etching process to form the groove. One end of the bit line contact structure 4 can extend into the groove and fill the interior of the groove. In one embodiment, the bit line contact structure 4 can extend in a direction perpendicular to the substrate 1, and its orthographic projection on the substrate 1 does not overlap with the orthographic projection of the conductive contact structure 3 on the substrate 1.

[0149] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0150] Step S170: An ohmic contact layer is formed that conforms to the inner wall of the groove.

[0151] The ohmic contact layer can be a thin film conformally attached to the sidewalls and bottom of the groove, or it can be a coating conformally attached to the sidewalls and bottom of the groove. No specific limitation is made to the specific form of the ohmic contact layer. The ohmic contact layer can be formed on the sidewalls and surface of the groove by methods such as vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the ohmic contact layer; no specific limitation is made to the formation method of the ohmic contact layer.

[0152] It should be noted that the end of the bit line contact structure 4 near the substrate 1 can extend into the groove and make contact with the ohmic contact layer in the groove. For example, the bit line contact structure 4 can fill the groove with the ohmic contact layer.

[0153] The material of the ohmic contact layer may be different from the material of the bit line contact structure 4. In order to reduce the contact resistance, the resistance value of the ohmic contact layer material may be less than the resistance value of the material of the bit line contact structure 4. For example, the material of the bit line contact structure 4 may be tungsten, and the material of the ohmic contact layer may be a metal silicide, such as cobalt silicide.

[0154] In step S140, a buffer layer 5 is formed between the conductive contact structure 3 and the word line structure 2.

[0155] Figure 6 A schematic diagram of the buffer layer in an embodiment of this disclosure is shown, see below. Figure 6 As shown, the buffer layer 5 can be formed on the surface of the drain region 112, and it can be in contact with the conductive contact structure 3. At the same time, the buffer layer 5 can also be insulated from the word line structure 2. In this embodiment, the buffer layer 5 can, for example, have an arc-shaped surface, so that it can be conformally attached to the surface of the conductive contact structure 3, and the size of the buffer layer 5 is larger the closer it is to the word line structure 2. In this embodiment, the design of the buffer layer 5 increases the physical size between the word line structure 2 and the conductive contact structure 3, reduces the electric field between the drain and the gate, and thus reduces the gate-induced drain leakage (GIDL) current. At the same time, due to the increase in physical size, in addition to effectively reducing standby power consumption and improving device reliability, it can also effectively avoid excessive etching depth during etching, which would cause a large junction leakage current in the substrate and the source / drain doped region (pn).

[0156] In one exemplary embodiment of this disclosure, the buffer layer 5 may be made of a conductive material, such as titanium-containing silicon carbide or nickel-containing silicon carbide. These materials have good conductivity and adhesion, which can ensure the performance of the buffer layer. The buffer layer 5 can be formed on the surface of the drain region 112 by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, the buffer layer 5 can also be formed by other means, and no special limitation is made here on the formation method of the buffer layer 5.

[0157] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0158] Step S180: A passivation layer 7 is formed covering the surface of the buffer layer 5 and the substrate 1, and the passivation layer 7 fills the word line trench.

[0159] Figure 7 A schematic diagram of the passivation layer 7 in an embodiment of this disclosure is shown. See also Figure 7 As shown, the passivation layer 7 can cover the surface of the buffer layer 5 and the substrate 1, and the passivation layer 7 fills the word line trench. The conductive contact structure 3 can penetrate the passivation layer 7 and connect to the drain region 112; meanwhile, continue to refer to Figure 1 As shown, the bit line contact structure 4 can penetrate the passivation layer 7 and is connected to the source region 111.

[0160] In some embodiments of this disclosure, forming a passivation layer 7 covering the surfaces of the buffer layer 5 and the substrate 1, wherein the passivation layer 7 fills the word line trench (i.e., step S180) may include steps S310 and S320, wherein:

[0161] Step S310: A protective layer 71 is formed covering the surface of the word line structure 2, the protective surface being flush with the surface of the substrate 1.

[0162] The protective layer 71 can be formed within the word line trench. It can be a thin film or a coating formed on the surface of the conductive layer 22. No specific limitation is made to the specific form of the protective layer 71. The material of the protective layer 71 can be an insulating material, such as SiCN. By insulating and protecting the surface of the word line structure 2 through the protective layer 71, damage to the surface of the word line structure 2 can be avoided by subsequent processes. Furthermore, it can reduce the possibility of coupling or short circuits between the word line structure 2 and other surrounding structures, thereby improving product yield.

[0163] For example, the material of the protective layer 71 can be silicon oxide or silicon nitride. The protective layer 71 can be formed on the surface of the conductive layer 22 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that the surface of the protective layer 71 away from the conductive layer 22 can be flush with the surface of the substrate 1.

[0164] In one exemplary embodiment of this disclosure, such as Figure 3 As shown, during the formation of the protective layer 71, a protective material layer 710 can be formed on the surface of the structure jointly formed by the substrate 1 and the conductive layer 22 by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition. The protective material layer 710 can fill the word line trench and cover the surface of the substrate 1. Subsequently, the protective material layer 710 located outside the word line trench can be removed by etching process, leaving only the protective material layer 710 located in the word line trench. The remaining protective material layer 710 located in the word line trench can be defined as the protective layer 71.

[0165] In step S320, a passivation material layer 72 is formed on the surface of the structure jointly formed by the substrate 1, the buffer layer 5 and the protective layer 71.

[0166] See also Figure 7 As shown, the passivation material layer 72 can cover the surface of the structure jointly formed by the substrate 1, the buffer layer 5, and the protective layer 71. Its material can be an insulating material with a low dielectric constant. (See also...) Figure 1 As shown, the conductive contact structure 3 can penetrate the passivation material layer 72 and be connected to the drain region 112; at the same time, the bit line contact structure 4 can penetrate the passivation material layer 72 and be connected to the source region 111, thereby reducing the parasitic capacitance between the word line structure 2 and the conductive contact structure 3 and the bit line contact structure 4 through the passivation material layer 72 with a lower dielectric constant.

[0167] For example, the material of the passivation material layer 72 can be the same as that of the protective layer 71, such as SiCN. The passivation material layer 72 can be formed on the surface of the structure consisting of the substrate 1, the buffer layer 5, and the protective layer 71 by means of atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Of course, other methods can also be used to form the passivation material layer 72; no specific limitation is made here. In some embodiments of this disclosure, the protective layer 71 and the passivation material layer 72 can together constitute the passivation layer 7, which can be made of a material with a low dielectric constant, thereby reducing the parasitic capacitance between the word line structure 2 and the bit line contact structure 4 and the conductive contact structure 3.

[0168] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0169] In step S190, an insulating layer 8 is formed covering the surface of the passivation layer 7. The conductive contact structure 3 can penetrate the insulating layer 8 and the passivation layer 7 and fill the recess 311 having the conductive material layer 6.

[0170] See Figure 4 and Figure 5 As shown, the insulating layer 8 can cover the surface of the passivation layer 7, the conductive contact structure 3 can penetrate the insulating layer 8 and the passivation layer 7, and be connected to the drain region 112; at the same time, the bit line contact structure 4 can penetrate the insulating layer 8 and the passivation layer 7, and be connected to the source region 111.

[0171] In some embodiments of this disclosure, the insulating layer 8 can be made of an insulating material. The insulating layer 8 and the passivation layer 7 provide double insulation protection for the surface of the word line structure 2, preventing coupling or short circuits between the word line structure 2 and other structures, thus improving product yield. Simultaneously, the insulating layer 8 can also separate the bit line contact structure 4 from the conductive contact structure 3, preventing coupling or short circuits between them, further improving product yield. For example, the insulating layer 8 can be made of silicon oxide.

[0172] For example, an insulating layer 8 can be formed on the surface of the passivation layer 7 by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, vacuum evaporation or magnetron sputtering. Of course, the insulating layer 8 can also be formed by other means. No special limitation is made on the formation method of the insulating layer 8 here.

[0173] In one exemplary embodiment of this disclosure, a conductive contact structure 3 is formed on top of the drain region 112. The connection between the conductive contact structure 3 and the drain region 112 may include steps S410 and S420, wherein:

[0174] Step S410: Etch the insulating layer 8, the passivation layer 7, and the drain region 112 to form a capacitor contact hole 31. The capacitor contact hole 31 includes a recess 311 formed in the drain region 112, a first hole segment 312 exposing the buffer layer 5, and a second hole segment 313 formed on the side of the first hole segment 312 away from the recess 311. In the direction perpendicular to the substrate 1, the recess 311, the first hole segment 312, and the second hole segment 313 are sequentially connected. In the direction parallel to the substrate 1, the width of the recess 311 is smaller than the width of the first hole segment 312 and / or the second hole segment 313.

[0175] In some embodiments of this disclosure, conductive contact structure 3 and bit line contact structure 4 may be formed after the passivation layer 7 and insulating layer 8 are formed. After the bit line contact structure 4 is formed, bit line 400 may be formed on the side of bit line contact structure 4 away from substrate 1. For example, anisotropic etching may be performed on insulating layer 8, passivation layer 7 and drain region 112 of substrate 1 to form capacitor contact hole 31. Figure 4 A schematic diagram of the capacitor contact hole 31 in this embodiment is shown. See also: Figure 4 As shown, the capacitor contact hole 31 can be a blind hole. For example, the capacitor contact hole 31 can penetrate the insulating layer 8 and the passivation layer 7, and can extend to the drain region 112 of the substrate 1. The capacitor contact hole 31 does not penetrate the drain region 112 of the substrate 1, and the portion of it extending to the drain region 112 is distributed at intervals from the channel region.

[0176] In one exemplary embodiment of this disclosure, the capacitor contact hole 31 may include a recess 311, a first hole segment 312 and a second hole segment 313. In a direction perpendicular to the substrate 1, the recess 311, the first hole segment 312 and the second hole segment 313 may be connected in sequence to form a capacitor contact hole 31 that is connected in sequence. For example, the recess 311 may be located within the source region 111 of the substrate 1, and its opening may face the side where the passivation layer 7 and the insulating layer 8 are located; the first hole segment 312 may penetrate the passivation layer 7 and pass through a portion of the thickness of the insulating layer 8. The first hole segment 312 may include a first open end and a second open end that are interconnected. The first open end may be connected to the opening of the recess 311, and the second open end may extend away from the first open end in a direction perpendicular to the substrate 1. The sidewall of the first hole segment 312 may expose the buffer layer 5 so that the conductive contact structure 3 formed in the second hole segment 313 can be connected to the buffer layer 5 to improve the performance of the semiconductor structure; the second hole segment 313 may be a through hole, one end of which may be flush with the surface of the insulating layer 8, and the other end of which may be connected to the second open end of the first hole segment 312.

[0177] In some embodiments of this disclosure, the width of the recess 311 located in the drain region 112 in the direction parallel to the substrate 1 may be smaller than the width of the first hole segment 312 and / or the second hole segment 313, thereby reducing the contact area between the conductive contact structure 3 subsequently formed therein and the substrate 1, and reducing the contact resistance.

[0178] Step S420: Fill the capacitor contact hole 31 with conductive material to form a conductive contact structure 3.

[0179] Conductive material can be filled into the capacitor contact hole 31 by means of vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, or physical vapor deposition, thereby forming a conductive contact structure 3. In one embodiment, the conductive material can be tungsten. Of course, the conductive material can also be other materials with strong conductivity, which will not be listed here.

[0180] It should be noted that the conductive material can fill the capacitor contact hole 31, that is, the surface of the conductive contact structure 3 can be flush with the surface of the substrate 1. In the direction parallel to the substrate 1, the width of the portion of the conductive contact structure 3 located in the drain region 112 is smaller than the width of the portion located outside the substrate 1, thereby reducing the contact area between the conductive contact structure 3 and the substrate 1 and reducing the contact resistance.

[0181] It should be noted that before forming the conductive contact structure, a conductive material layer 6 can be formed in the recess 311 of the drain region 112. For example, after forming the capacitor contact hole 31, a conformally attached metal conductive layer 22 can be formed in the recess 311. The material of the metal conductive layer 22 can be titanium or nickel. Subsequently, the metal conductive layer 22 can be annealed. During the annealing process, the titanium or nickel in the metal conductive layer 22 can react with the silicon in the substrate 1 to form the conductive material layer 6. When the substrate 1 is a silicon substrate, the material of the conductive material layer 6 can be silicon titanate or silicon nickelate.

[0182] In one exemplary embodiment of this disclosure, forming a buffer layer 5 between the conductive contact structure 3 and the word line structure 2 (i.e., step S140) may include steps S510-S550, wherein:

[0183] In step S510, a first mask layer 9 is formed on the surface of the substrate 1, wherein the orthographic projection of the first mask layer 9 on the substrate 1 does not overlap with the orthographic projection of the drain region 112 on the substrate 1.

[0184] In some embodiments of this disclosure, a mask material layer 91 can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other methods. The mask material layer 91 can be a multilayer film structure or a single-layer film structure. Its material can be at least one of polymer, SiO2, SiN, polycrystalline silicon and SiCN. Of course, it can also be other materials, which will not be listed here. Figure 9 A schematic diagram of the mask material layer 91 in an embodiment of this disclosure is shown.

[0185] In some embodiments, the mask material layer 91 may be multilayered, including a polymer layer, an oxide layer, and a hard mask layer. The polymer layer may be formed on the surface of the substrate 1, and the oxide layer may be located between the hard mask layer and the polymer layer. The polymer layer can be formed on the surface of the substrate 1 using a chemical vapor deposition process, the oxide layer can be formed on the surface of the polymer layer using a vacuum evaporation process, and the hard mask layer can be formed on the surface of the oxide layer using an atomic layer deposition process.

[0186] A photoresist layer 92 can be formed on the surface of the mask material layer 91 away from the substrate by spin coating or other methods. The material of the photoresist layer 92 can be positive or negative photoresist, and no special limitation is made here.

[0187] A photoresist layer 92 can be exposed using a photomask, the pattern of which, when projected onto the substrate 1, at least partially overlaps with the drain region 112. Subsequently, the exposed photoresist layer 92 can be developed to form multiple spaced-apart development areas, each exposing the surface of the mask material layer 91. The pattern of the development area can be the same as the required pattern of the first mask layer 9, and the size of the development area can be the same as the required size of the first mask layer 9.

[0188] The mask material layer 91 can be etched in each developing area using an anisotropic etching process, exposing the substrate 1 in the etched areas, thereby forming multiple mask patterns on the mask material layer 91. The mask material layer 91 with the mask patterns can be defined as the first mask layer 9. It should be noted that when the mask material layer 91 is a single-layer structure, a single etching process can be used to form the mask pattern. When the mask material layer 91 is a multi-layer structure, each layer can be etched layer by layer. That is, a single etching process can etch one layer, and multiple etching processes can be used to etch through the mask material layer 91 to form the mask pattern. In one embodiment, the shape and size of the mask pattern can be the same as the required pattern and size of each first mask layer 9.

[0189] It should be noted that after the above etching process is completed, the photoresist layer 92 can be removed by cleaning with a cleaning solution or by ashing, so that the first mask layer 9 after etching is no longer covered by the photoresist layer 92. Figure 10 A schematic diagram is shown after step S510 is completed in an embodiment of this disclosure.

[0190] Step S520: A buffer material layer 51 is formed on the surface of the structure formed by the first mask layer 9 and the substrate 1.

[0191] A buffer material layer 51 can be formed on the surface of the structure formed by the first mask layer 9 and the substrate 1 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition, or other methods. The buffer material layer 51 can at least cover the sidewalls and surface of the first mask layer 9. In some embodiments of this disclosure, the material of the buffer material layer 51 can be silicon carbide. Figure 11 A schematic diagram is shown after step S520 is completed in an embodiment of this disclosure.

[0192] Step S530: Etch the buffer material layer 51, leaving only the buffer material layer 51 located on the sidewall of the first mask layer 9.

[0193] A dry etching process can be used to etch the buffer material layer 51 to remove the area of ​​the buffer material layer 51 located outside the sidewalls of the first mask layer 9, leaving only the buffer material layer 51 located on the sidewalls of the first mask layer 9. It should be noted that during the removal of the buffer material layer 51, the remaining portion of the buffer material layer 51 on the sidewalls of the first mask layer 9 near the substrate 1 can contact and connect with the substrate 1. This allows the substrate 1 to support the buffer material layer 51, preventing it from collapsing after the subsequent removal of the first mask layer 9, thus improving product yield. See also... Figure 11 As shown, during the removal of the buffer material layer 51, a second mask layer 93 is formed on the surface of the buffer material layer 51, and the second mask layer 93 can be consumed during the etching of the buffer material layer 51. Figure 12 A schematic diagram is shown after step S530 is completed in an embodiment of this disclosure.

[0194] Step S540: Remove the first mask layer 9.

[0195] The first mask layer 9 can be removed by selective etching. The etching gas or etching solution can be set according to the specific material of the first mask layer 9. No special limitation is made on the etching gas or etching solution of the first mask layer 9, as long as the first mask layer 9 can be removed without damaging other film structures.

[0196] In step S550, the remaining buffer material layer 51 is annealed to form the buffer layer 5.

[0197] In one exemplary embodiment of this disclosure, the buffer material layer 51 and the metal conductive layer 22 can be transformed into a buffer layer 5 and a conductive material layer 6 by the same annealing process. For example, after forming the capacitor contact hole 31, a metal conductive layer 22 can be formed inside the capacitor contact hole 31. The metal conductive layer 22 can be conformally attached to the bottom and sidewalls of the capacitor contact hole 31, that is, the metal conductive layer 22 can be conformally attached to the sidewalls and bottom of the recess 311, and can also be attached to the surface of the buffer layer 5. The capacitor contact hole 31 with the metal conductive layer 22 can be annealed. During this process, when the material of the metal conductive layer 22 is titanium or nickel, the silicon carbide in the buffer layer 5 can react with titanium or nickel to form titanium-containing silicon carbide or nickel-containing silicon carbide; at the same time, the silicon in the substrate 1 can react with titanium or nickel to form titanium silicon carbide or nickel silicon carbide, and the material in the sidewalls inside the capacitor contact hole 31 does not react with titanium or nickel.

[0198] In the above process, the buffer layer 5 is made of titanium-containing silicon carbide or nickel-containing silicon carbide. These materials have good conductivity and adhesion, which can ensure the performance of the buffer layer. At the same time, since the buffer layer 5 is located between the conductive contact structure 3 and the word line structure 2, it increases the physical size between the word line structure 2 and the conductive contact structure 3, reduces the electric field between the drain and the gate, and thus reduces the gate-induced drain leakage (GIDL) current. In addition, due to the increase in physical size, in addition to effectively reducing standby power consumption and improving device reliability, it can also effectively avoid excessive etching depth during etching, which would cause a large junction leakage current in the substrate and the source / drain doped region (pn).

[0199] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0200] This disclosure also provides a memory, which may include the semiconductor structure in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and semiconductor structure formation method, and will not be repeated here.

[0201] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0202] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an active region, the active region including a channel region and source and drain regions respectively distributed on both sides of the channel region, and the channel region having word line trenches; The character line structure is located within the character line groove; A conductive contact structure is connected to the top of the drain region; A buffer layer is located between the conductive contact structure and the word line structure, and the material of the buffer layer is titanium-containing silicon carbide or nickel-containing silicon carbide.

2. The semiconductor structure according to claim 1, characterized in that, The drain region includes a recessed portion extending inward from the top, and the semiconductor structure further includes: A conductive material layer is conformally attached to the inner wall of the recess, and the conductive contact structure extends in a direction perpendicular to the substrate, with its end near the substrate extending into the recess and filling the recess having the conductive material layer.

3. The semiconductor structure according to claim 2, characterized in that, The conductive material layer is made of silicon titanate or silicon nickelate.

4. The semiconductor structure according to claim 2, characterized in that, The top of the word line structure is lower than the top surface of the word line trench, and the semiconductor structure further includes: A passivation layer covers the surface of the buffer layer and the substrate, and the passivation layer fills the word line trench.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: An insulating layer covers the surface of the passivation layer, and the conductive contact structure penetrates the insulating layer and the passivation layer, filling the recess having the conductive material layer.

6. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes: The bit line contact structure penetrates the insulating layer and the passivation layer and is connected to the source region. The orthographic projection of the bit line contact structure on the substrate does not overlap with the orthographic projection of the conductive contact structure on the substrate.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an active region, the active region including a channel region and source and drain regions respectively distributed on both sides of the channel region, the channel region having word line trenches; A character line structure is formed within the character line groove; A conductive contact structure is formed on top of the drain region, and the conductive contact structure is connected to the drain region. A buffer layer is formed between the conductive contact structure and the word line structure, and the material of the buffer layer is titanium-containing silicon carbide or nickel-containing silicon carbide.

8. The forming method according to claim 7, characterized in that, The drain region includes a recessed portion extending inward from the top, and the method of forming it further includes: A conductive material layer is formed to conformally adhere to the inner wall of the recess. The conductive contact structure extends in a direction perpendicular to the substrate, and its end near the substrate extends into the recess and fills the recess having the conductive material layer.

9. The forming method according to claim 8, characterized in that, The conductive material layer is made of silicon titanate or silicon nickelate.

10. The forming method according to claim 8, characterized in that, The top of the character line structure is lower than the top surface of the character line groove, and the forming method further includes: A passivation layer is formed covering the surface of the buffer layer and the substrate, and the passivation layer fills the word line trench.

11. The forming method according to claim 10, characterized in that, The forming method further includes: An insulating layer is formed covering the surface of the passivation layer, and the conductive contact structure penetrates the insulating layer and the passivation layer, filling the recess having the conductive material layer.

12. The forming method according to claim 11, characterized in that, The forming method further includes: A bit line contact structure is formed on top of the source region. The bit line contact structure penetrates the insulating layer and the passivation layer and is connected to the source region. The orthographic projection of the bit line contact structure on the substrate does not overlap with the orthographic projection of the conductive contact structure on the substrate.

13. The forming method according to claim 11, characterized in that, A conductive contact structure is formed on top of the drain region, and the conductive contact structure is connected to the drain region, including: The insulating layer, the passivation layer, and the drain region are etched to form a capacitor contact hole. The capacitor contact hole includes a recess formed in the drain region, a first segment exposing the buffer layer, and a second segment formed on the side of the first segment away from the recess. In a direction perpendicular to the substrate, the recess, the first segment, and the second segment are sequentially connected, and in a direction parallel to the substrate, the width of the recess is smaller than the width of the first segment and / or the second segment. The capacitor contact hole is filled with conductive material to form a conductive contact structure.

14. The forming method according to any one of claims 7-13, characterized in that, A buffer layer is formed between the conductive contact structure and the word line structure, comprising: A mask layer is formed on the surface of the substrate, and the orthographic projection of the mask layer on the substrate does not overlap with the orthographic projection of the drain region on the substrate; A buffer material layer is formed on the surface of the structure formed by the mask layer and the substrate; The buffer material layer is etched, leaving only the buffer material layer located on the sidewall of the mask layer; Remove the mask layer; The remaining buffer material layer is annealed to form a buffer layer.

15. A memory comprising the semiconductor structure according to any one of claims 1-6.

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