Silicon carbide-based trench MOSFET with integrated superjunction structure and its fabrication method

Abstract

This invention discloses a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. The structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p-type shielding layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on the first surface of the n++ type silicon carbide substrate. A superjunction structure is integrated below the p-type channel layer and the p-type shielding layer. The superjunction structure includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. A second n+ pillar region is provided on the outer side of each of the two p+ pillar regions. A p-type channel layer is provided on the n-type drift layer on both sides of the superjunction structure and the first trench. Adjacent p++ type source region layers and n++ type source region layers are provided on the p-type channel layer. A gate electrode is provided above the p-type shielding layer. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench, which reduces the on-resistance and the electric field in the gate oxide layer at the bottom corner of the trench.

Description

Technical Field

[0001] This invention relates to the field of MOSFETs, and more particularly to a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. Background Technology

[0002] Compared to silicon, a traditional semiconductor material, SiC offers advantages in breakdown field strength, bandgap width, electron saturation velocity, melting point, and thermal conductivity. Compared to traditional Si devices, SiC devices exhibit lower impedance, leading to smaller product designs and higher efficiency. Higher frequency operation allows for smaller passive components and operation at higher temperatures, implying simpler cooling systems. Modern electronics technology places new demands on semiconductor materials, including high temperature, high power, high voltage, high frequency, and radiation resistance. The wide-bandgap third-generation semiconductor material SiC, with its superior switching performance, temperature stability, and low electromagnetic interference (EMI), is ideally suited for next-generation power conversion applications such as solar inverters, power supplies, electric vehicles, and industrial power.

[0003] Vertical MOSFET structures include vertical double-injection planar gate (DMOSFET) and trench gate (UMOSFET). Trench structures offer advantages such as small size and high channel mobility, theoretically providing better performance than vertical double-injection structures, and are therefore widely used in MOSFET devices. While trench structures offer many advantages, they also present several potential problems, such as susceptibility to trench sidewall damage, gate oxide reliability issues, and unstable threshold voltage. One key challenge is reducing the maximum electric field (Eox-max) in the gate oxide at the bottom corner of the trench and minimizing carrier aggregation that could lead to thermal decomposition of the gate oxide. Lowering the gate oxide's electric field comes at the cost of increased on-resistance, which negatively impacts the device's electrical characteristics.

[0004] Therefore, it is crucial to design a silicon carbide-based trench MOSFET that can reduce the electric field of the gate oxide layer at the bottom corner of the trench and reduce the on-resistance of the device. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A silicon carbide-based trench MOSFET with an integrated superjunction structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on a first surface of the n++ type silicon carbide substrate and has a first trench. The first trench is filled with a superjunction structure, which includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are located on both sides of the first n+ pillar region. A second n+ pillar region is located on the outer side of each of the two p+ pillar regions. The superjunction structure is integrated with the first trench on both sides. A p-type channel layer is provided on the n-type drift layer. An adjacent p++ type source region layer and an n++ type source region layer are provided on the p-type channel layer. The p++ type source region layer is located outside the n++ type source region layer. A second trench is provided extending from the middle of the n++ type source region layer to the preset position of the superjunction structure. A p-type shielding layer is provided below the bottom of the second trench. A gate electrode is filled in the second trench. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench. A source electrode is provided above the p++ type source region layer and the n++ type source region layer. A drain electrode is provided on the second surface of the n++ type silicon carbide substrate.

[0008] Preferably, the first n+ column region, the p+ column region, and the second n+ column region are vertically disposed at the bottom of the first trench, the p+ column region is disposed between the first n+ column region and the second n+ column region, the inner side of the p+ column region is connected to the outer side of the first n+ column region, the inner side of the second n+ column region is connected to the outer side of the p+ column region, and the outer side of the second n+ column region is connected to the sidewall of the first trench.

[0009] Preferably, the outer side of the p+ pillar area is flush with the side of the second trench, the bottom surface of the p-type shielding layer is connected to the first n+ pillar area and the p+ pillar area, the bottom surface of the p-type trench layer is connected to the top of the second n+ pillar area, and the side of the p-type shielding layer is connected to the second n+ pillar area.

[0010] Preferably, the width of the p+ column region is greater than 0 and less than or equal to 2 μm.

[0011] Preferably, the height of the first n+ column region and the p+ column region is 1 to 3 μm, and the height of the second n+ column region is 2 to 4 μm.

[0012] Preferably, the doping concentration of the first n+ pillar region and the second n+ pillar region is 1×10⁻⁶. 16 cm -3 ~6×10 16 cm -3 The doping concentration in the p+ column region is 1.0 × 10⁻⁶. 17 cm -3 ~3×10 17 cm -3 .

[0013] Preferably, the bottom of the second trench is located below the p-type channel layer, and the distance between the second trench and the lower surface of the p-type channel layer is 0.5 to 1.5 μm, and the thickness of the p-type shielding layer is 0.1 to 0.5 μm.

[0014] Preferably, the p-type channel layer is doped with 0.5 × 10⁻⁶. 17 cm -3 Up to 4.5×10 17 cm -3 The doping concentration of the n++ type source region is 1.0 × 10⁻⁶. 19 cm -3 ~5.0×10 19 cm -3 The doping concentration of the p++ source region is 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 20 cm -3 The doping concentration of the p-type shielding layer is 1.0 × 10⁻⁶. 18 cm -3 Up to 1.0×10 20 cm -3 .

[0015] Preferably, the source electrode and drain electrode are made of AlTi, Ni, TiW or AlTi, and a passivation layer is provided above the gate electrode and the source electrode, with an external connection at the opening on the passivation layer.

[0016] A method for fabricating a silicon carbide-based trench MOSFET based on the above-described integrated superjunction structure includes the following steps:

[0017] 1) Provide an n++ type silicon carbide substrate, and epitaxially grow an n-type drift layer on the first surface of the n++ type silicon carbide substrate;

[0018] 2) The first trench is etched in the n-type drift layer, and n+ pillar regions are epitaxially grown inside and outside the first trench. The n+ pillar regions are etched to form the first n+ pillar region and the second n+ pillar region. Then, p+ pillar regions are epitaxially grown to form a superjunction structure. In the superjunction structure, the first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. The second n+ pillar region is provided on the outer side of both p+ pillar regions.

[0019] 3) A p-type channel layer is epitaxially grown on the superjunction structure and the n-type drift layer. An n++ type source region layer is epitaxially grown on the p-type channel layer. A mask layer is fabricated above the middle part of the n++ type source region layer, and ion implantation is performed to form a p++ type source region layer located outside the n++ type source region layer.

[0020] 4) A second trench is etched from the middle of the n++ type source region to a predetermined position of the superjunction structure, and a p-type shielding layer is formed below the bottom of the second trench by ion implantation;

[0021] 5) A gate oxide layer is formed on the top of the p-type shielding layer and the side of the second trench, and a gate electrode is filled in the second trench where the gate oxide layer is formed;

[0022] 6) Fabricate source electrodes on the n++ type source region layer and the p++ type source region layer, and fabricate drain electrodes on the second surface of the n++ type silicon carbide substrate.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] (1) The silicon carbide-based trench MOSFET with integrated superjunction structure of the present invention has a high cell integration density. The second n+ pillar region on the side of the p-type channel layer increases the carrier electron concentration accumulated in the device accumulation layer, improves the carrier mobility, reduces the on-resistance of the device, and improves the on-state characteristics of the device.

[0025] (2) In the reverse blocking state, the free charges in the p+ pillar region, the first n+ pillar region and the second n+ pillar region of the superjunction structure of the present invention are completely depleted, making it equivalent to an intrinsic semiconductor and having extremely high voltage resistance.

[0026] (3) Compared with traditional silicon carbide-based trench MOSFET devices, the integrated superjunction structure of the present invention has improved gate charge and reverse transfer capacitance, which can reduce the electric field in the gate oxide layer at the bottom corner of the trench below the gate electrode and reduce the dynamic switching loss of the device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a silicon carbide-based trench MOSFET with an integrated superjunction structure, according to an embodiment of the present invention.

[0028] Figure 2-9 This is a schematic flowchart illustrating a method for fabricating a silicon carbide-based trench MOSFET with an integrated superjunction structure, according to an embodiment of the present invention.

[0029] Figure 10 This is a comparison chart of the output characteristics of embodiments and comparative examples of the present invention;

[0030] Figure 11 This is a graph showing the comparison of current density between embodiments and comparative examples of the present invention;

[0031] Figure 12 This is a comparison diagram of the breakdown characteristics of embodiments and comparative examples of the present invention;

[0032] Figure 13 This is a schematic diagram of the electric field distribution for embodiments and comparative examples of the present invention;

[0033] Figure reference numerals: 1. n++ type silicon carbide substrate; 2. n-type drift layer; 3. superjunction structure; 31. first n+ pillar region; 32. p+ pillar region; 33. second n+ pillar region; 4. p-type shielding layer; 5. p-type channel layer; 6. n++ type source region layer; 7. p++ type source region layer; 8. gate electrode; 9. gate oxide layer; 10. source electrode; 11. drain electrode. Detailed Implementation

[0034] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The accompanying drawings are merely illustrative to facilitate understanding of the invention, and their specific proportions can be adjusted according to design requirements. The vertical relationships of relative elements and the definitions of front / back in the graphics described herein should be understood by those skilled in the art to refer to the relative positions of the components; therefore, they can all be flipped to present the same component, and all of this should fall within the scope disclosed in this specification.

[0035] Example

[0036] refer to Figure 1 This application proposes a silicon carbide-based trench MOSFET with an integrated superjunction structure 3, comprising an n++ type silicon carbide substrate 1, an n-type drift layer 2, a p-type channel layer 5, a p++ type source layer 7, and an n++ type source layer 6. The thickness of the n++ type silicon carbide substrate 1 is a standard 350–1000 μm, or it is thinned, ground, polished, and cleaned through mechanical processing and chemical reactions to achieve the required thickness and flatness. The n-type drift layer 2 is disposed on the first surface of the n++ type silicon carbide substrate 1, and a first trench is provided in the n-type drift layer 2. The first trench is filled with a superjunction structure 3, which includes a first n+ pillar region 31, a p+ pillar region 32, and a second n+ pillar region 33. The first n+ pillar region 31 is located in the middle, and p+ pillar regions 32 are provided on both sides of the first n+ pillar region 31. A second n+ pillar region 33 is provided on the outer side of each of the two p+ pillar regions 32. A p-type channel layer 5 is provided on the n-type drift layer 2 on both sides of the superjunction structure 3 and the first trench. The p-type channel layer 5 is doped with 0.5 × 10⁻⁶. 17 cm -3 Up to 4.5×10 17 cm -3 The p-type channel layer 5 has adjacent p++ type source layer 7 and n++ type source layer 6, with n++ type source layer 6 located in the middle and p++ type source layer 7 located outside of n++ type source layer 6. The doping concentration of n++ type source layer 6 is 1.0 × 10⁻⁶. 19 cm -3~5.0×10 19 cm -3 The doping concentration of the p++ source layer 7 is approximately 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 20 cm -3 The thickness of the p++ type source layer 7 is 0.2–0.5 μm. A second trench extends from the middle of the n++ type source layer 6 to a predetermined position of the superjunction structure 3. A p-type shielding layer 4 is provided below the bottom of the second trench, and the doping concentration of the p-type shielding layer 4 is 1.0 × 10⁻⁶. 18 cm -3 Up to 1.0×10 20 cm -3 The second trench is filled with a gate electrode 8. A gate oxide layer 9 is provided between the gate electrode 8, the p-type shielding layer 4, and the sidewalls of the second trench. A source electrode 10 is provided above the p++ type source layer 7 and the n++ type source layer 6. A drain electrode 11 is provided on the second surface of the n++ type silicon carbide substrate 1. By adding one n+ pillar region, two p+ pillar regions 32, and two second n+ pillar regions 33 below the second trench, the p-type shielding layer 4, and the p-type channel layer 5, a superjunction structure 3 is formed. This superjunction structure 3 is integrated below the second trench and the p-type shielding layer 4 of the MOSFET. The MOSFET device with integrated superjunction structure 3 can reduce the on-resistance of the device while increasing the breakdown voltage, achieving a trade-off between on-resistance and breakdown voltage. It can mitigate the electric field crowding effect, reduce the on-state resistance, and enhance the high-temperature resistance of the device.

[0037] In a specific embodiment, the first n+ column region 31, the p+ column region 32, and the second n+ column region 33 are vertically disposed at the bottom of the first trench, with the p+ column region 32 located between the first n+ column region 31 and the second n+ column region 33. Specifically, the inner side of the p+ column region 32 is connected to the outer side of the first n+ column region 31, the inner side of the second n+ column region 33 is connected to the outer side of the p+ column region 32, and the outer side of the second n+ column region 33 is connected to the sidewall of the first trench. The tops of the first n+ pillar region 31 and p+ pillar region 32 are connected to the bottom surface of the p-type shielding layer 4. The outer side of the p+ pillar region 32 is flush with the side edge of the second trench. The top of the second n+ pillar region 33 is connected to the bottom surface of the p-type channel layer 5. The side edge of the p-type shielding layer 4 is connected to the second n+ pillar region 33. That is, the first n+ pillar region 31 and the p+ pillar regions 32 on both sides are located below the p-type shielding layer 4, and the second n+ pillar region 33 is located below the p-type channel layer 5. The second n+ pillar region 33 is connected to both the p-type channel layer 5 and the p-type shielding layer 4. The p-type channel layers 5 on both sides of the second trench are provided with adjacent p++ type source region layers 7 and n++ type source region layers 6.

[0038] In a specific embodiment, the width of the p+ pillar region 32 is greater than 0 and less than or equal to 2 μm. The height of the first n+ pillar region 31 and the p+ pillar region 32 is 1–3 μm, and the height of the second n+ pillar region 33 is 2–4 μm, meaning the etching depth of the first trench is 2–4 μm. The doping concentration of the first n+ pillar region 31 and the second n+ pillar region 33 is 1 × 10⁻⁶. 16 cm -3 ~6×10 16 cm -3 The doping concentration of p+ column 32 is 1.0 × 10⁻⁶. 17 cm -3 ~3×10 17 cm -3 The first n+ pillar region 31 and the second n+ pillar region 33 have the same doping concentration, and their width and doping concentration can be adjusted according to specific requirements. The width of the p+ pillar region 32 can be determined by the doping of the first n+ pillar region 31, the second n+ pillar region 33 and the p+ pillar region 32.

[0039] In a specific embodiment, the bottom of the second trench is located below the p-type channel layer 5, and the distance between it and the lower surface of the p-type channel layer 5 is 0.5–1.5 μm. The height of the first n+ pillar region 31 and the p+ pillar region 32 is 1–3 μm, meaning the distance between the lower surface of the p-type shielding layer 4 and the upper surfaces of the first n+ pillar region 31 and the p+ pillar region 32 is 1–3 μm. The thickness of the p-type shielding layer 4 is 0.1–0.5 μm, and the lower surface of the p-type shielding layer 4 is the upper surface of the first n+ pillar region 31 and the p+ pillar region 32. Therefore, the distance between the upper surface of the p-type shielding layer 4 and the lower surface of the first n+ pillar region 31 and the p+ pillar region 32 is 1.1–3.5 μm. The second trench extends from below the n++ source region layer 6, through the p-type channel layer 5, into the interior of the superjunction structure 3. The n++ source region layer 6 is retained on both sides of the second trench, extending downward to the superjunction structure 3 below the p-type channel layer 5. The tops of the first n+ pillar region 31 and the p+ pillar region 32 are implanted with ions to form a p-type shielding layer 4.

[0040] In a specific embodiment, the source electrode 10 and drain electrode 11 are made of AlTi, Ni, TiW, or AlTi to form ohmic contacts with external components. A passivation layer (not shown) is provided above the gate electrode 8 and the source electrode 10, and an external connection is provided at the opening on the passivation layer. Specifically, the external connection can be a pad.

[0041] The working principle of the silicon carbide-based trench MOSFET with integrated superjunction structure 3 in the embodiments of this application is as follows:

[0042] During forward conduction, as the voltage of the gate electrode 8 increases, the positive charge on the gate surface strengthens, further attracting electrons from the p-type channel layer 5 to the surface. Therefore, negative charges accumulate in the p-type channel layer 5 on the side of the gate electrode 8. As the voltage of the gate electrode 8 increases further, the p-type channel layer 5 forms an N-type inversion layer over a wider range. The first n+ pillar region 31 and the second n+ pillar region 33 return to their original highly doped state, forming a current path with low on-resistance, giving the device better forward conduction characteristics. When reverse conduction is blocked, the p-type channel layer 5 under the gate electrode 8 cannot form an inversion layer to generate a conductive channel. The p+ pillar region 32 on the left and the first n+ pillar region 31, which is vertically conductive in the middle, form a PN junction with reverse bias. The p+ pillar region 32 on the right and the first n+ pillar region 31, which is vertically conductive in the middle, also form a PN junction with reverse bias. The depletion layer of the PN junction increases, and a lateral horizontal electric field is established. When the doping concentration and width of the first n+ pillar region 31 and the second n+ pillar region 33 are properly controlled, the first n+ pillar region 31 and the second n+ pillar region 33 can be completely depleted. In this way, the first n+ pillar region 31, the p+ pillar region 32, and the second n+ pillar region 33 have no free charges, which is equivalent to an intrinsic semiconductor. The lateral electric field in the middle is extremely high. Only an external voltage greater than the internal lateral electric field can break down this region, so the breakdown voltage of this region is extremely high. Therefore, this superjunction structure 3 alleviates the electric field congestion effect at the corner of the p-type shielding layer 4, while increasing the on-state current and reducing the on-state resistance.

[0043] refer to Figure 1-9 The embodiments of this application propose a method for fabricating a silicon carbide-based trench MOSFET based on the above-described integrated superjunction structure 3, comprising the following steps:

[0044] (1)Reference Figure 2 An n++ type silicon carbide substrate 1 is provided, and an n-type drift layer 2 is epitaxially grown on the first surface of the n++ type silicon carbide substrate 1. The thickness of the n++ type silicon carbide substrate 1 is a standard 350-1000 μm, or it is subjected to a series of thinning, grinding, polishing, and cleaning processes such as mechanical processing and chemical reaction to achieve the required thickness and flatness on the surface. Specifically, the n-type drift layer 2 is epitaxially grown on the n++ type silicon carbide substrate 1 using chemical vapor deposition or other epitaxial growth methods. When the gas source for epitaxial growth is silane or trichlorosilane, ethylene or propane, etc., the thickness of the n-type drift layer 220 is 13 μm, and the doping concentration of the n-type drift layer 2 is 1.0 × 10⁻⁶. 15 cm -3 ~9.0×10 15 cm -3 The doping source used is ammonia or other gas sources, and the epitaxial growth temperature is 1500-1700℃.

[0045] (2)Reference Figure 3A first trench is etched into the n-type drift layer 2, and n+ pillar regions are epitaxially grown inside and outside the first trench using HF or similar sources, with an etching depth of 2-4 μm. The n+ pillar regions are then etched to form first n+ pillar regions 31 and second n+ pillar regions 33, followed by epitaxial growth to form p+ pillar regions 32. A trimethylaluminum gas source is used as the doping source, and the epitaxial growth temperature is 1500–1700 °C, ultimately producing a superjunction structure 3. In this structure, the first n+ pillar region 31 is located in the middle, with p+ pillar regions 32 on both sides of it, and second n+ pillar regions 33 on the outer sides of each p+ pillar region 32. The doping concentration of the p+ pillar regions 32 depends on the doping of the first n+ pillar regions 31 and second n+ pillar regions 33; preferably, the doping concentration of the p+ pillar regions 32 is 1.0 × 10⁻⁶. 17 cm -3 ~3×10 17 cm -3 The width of the p+ column region 32 is determined by the doping of the first n+ column region 31, the second n+ column region 33 and the p+ column region 32. Preferably, the width of the p+ column region 32 is 0 to 2 μm.

[0046] (3)Reference Figure 4 A p-type channel layer 5 is epitaxially grown on the superjunction structure 3 and the n-type drift layer 2. The doping source for epitaxial growth is a gas source such as trimethylaluminum. Preferably, the thickness of the p-type channel layer 5 is 0.1–0.5 μm, and the doping concentration of the p-type channel layer 5 is 0.5 × 10⁻⁶. 17 cm -3 ~4.5×10 17 cm -3 The epitaxial growth temperature is 1500–1700℃. An n++ type source layer 6 is epitaxially grown on the p-type channel layer 5. The epitaxial growth source is silane, trichlorosilane, ethylene, or propane, etc., and the doping source is ammonia or other gas sources. Preferably, the thickness of the n++ type source layer 6 is 0.1–0.4 μm, and the doping concentration of the n++ type source layer 6 is 1.0 × 10⁻⁶. 19 cm -3 ~5.0×10 19 cm -3 The epitaxial growth temperature is 1500–1700℃. A mask layer is fabricated above the middle portion of the n++ type source region layer 6, and ion implantation is performed to form the p++ type source region layer 7. Specifically, the mask layer is formed using photolithographic pattern transfer, with an implantation energy of 28 keV and an implantation dose of 2.36 × 10⁻⁶. 13 cm -2 The injection energy was 60 keV, and the injection dose was 4.6 × 10⁻⁶. 12 cm -2 The injection energy was 100 keV, and the injection dose was 6.3 × 10⁻⁶. 14 cm -2Three Al atom implantations resulted in a doping concentration of approximately 1.0 × 10⁻⁶. 19 cm -3 ~1.0×10 20 cm -3 The p++ type source layer 7 has an ion implantation depth of 0.2–1 μm, and the implanted atoms can also be boron atoms. Here, the p++ type source layer 7 can extend downward to the lower surface of the p-type channel layer 5, which can reduce the device current to a certain extent and reduce the electric field.

[0047] (4)Reference Figure 5 and Figure 6 A second trench is etched from a predetermined position in the middle of the n++ type source layer 6 to the superjunction structure 3, and a p-type shielding layer 4 is formed below the bottom of the second trench by ion implantation. Specifically, thin film deposition, photolithography, dry and wet etching, and ion implantation are used to sequentially form the second trench and the p-type shielding layer 4. The sidewalls of the second trench need to be {11-20} planes, the two corners of the second trench have rounded structures, and the bottom of the second trench is planarized, where the p-type shielding layer 4 is formed. The etching endpoint of the second trench is located below the bottom of the p-type channel layer 5, and the p-type shielding layer 4 is formed by ion implantation. Specifically, a barrier layer of silicon dioxide, polysilicon, or a metal dielectric of a certain thickness is deposited using physical and chemical vapor deposition or other thin film deposition methods. This barrier layer is then patterned by photolithography and dry etched to form an etching mask layer. When the etching mask layer is silicon dioxide, its thickness is 2μm to 5μm, and it needs to be annealed and densified at temperatures above 1000℃ under O2 conditions. When the etching mask layer is a metal such as Al or Ni, its thickness is around 1μm, and the dry etching gas can be C4F8, CHF3, Cl2, or other gases. Using an etching mask layer, the second trench is dry-etched by physical or chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP). The etching gas can be a combination of gases such as SF6 / O2, NF3 / Ar, CF4, CHF3 / O2, and C4F8 / O2. For example, SF6 / O2 / HBr is used as the etching gas, with an ICP power of 600-1000W, a bias power of 100-300W, and a temperature of 20℃. The second trench needs to pass through the bottom of the p-type channel layer 5 and enter the first n+ pillar region 31 and p+ pillar region 32. After removing the etching mask layer, a barrier layer of silicon dioxide, polysilicon, or metal dielectric of a certain thickness is deposited using physical and chemical vapor deposition or other thin film deposition methods. This barrier layer is then patterned by photolithography and dry etched to form an implantation mask layer. Ion implantation forms a p-type shielding layer 4. The implanted impurity can be B or Al, and the implantation dose can be 1.0 × 10⁻⁶. 18 cm -2 Up to 1.0×10 20 cm-2 The injection energy can range from 20 keV to 700 keV. This ultimately forms the p-type shielding layer 4. Preferably, the doping concentration of the p-type shielding layer 4 is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 After ion implantation, annealing is required. Specifically, the implantation mask layer is removed, the surface is cleaned, and annealing is carried out at a high temperature of 1600℃ and a pressure of 600-700 Torr for about half an hour using methods such as carbon film, AlN film covering, and silane suppression. This activates the ion implantation doping in the previous steps, and removes the carbon film, AlN film, etc., that covered the surface after annealing, and then cleans the surface.

[0048] (5)Reference Figure 7 and Figure 8A gate oxide layer 9 is fabricated at the bottom and sides of the second trench, and a gate electrode 8 is filled into the second trench where the gate oxide layer 9 is formed. The SiC substrate obtained in step 4 undergoes standard cleaning (RCA), followed by physical or chemical vapor deposition, high-temperature thermal oxidation and post-oxidation annealing, atomic layer deposition (ALD), etc., to finally obtain the gate oxide layer 9. Specifically, the SiC substrate obtained in step 4 is ultrasonically cleaned sequentially with acetone and ethanol, and then rinsed with deionized water; the organically ultrasonicated SiC substrate is boiled in concentrated sulfuric acid and hydrogen peroxide solution for at least 10 minutes; the SiC substrate boiled in concentrated sulfuric acid is then boiled sequentially with solution one and solution two for at least 10 minutes each, then rinsed with deionized water and dried with nitrogen gas. Solution one is a mixture of ammonia, hydrogen peroxide, and deionized water, and solution two is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water. The rinsed SiC substrate is then immersed in hydrofluoric acid for at least 1 minute to remove the surface oxide layer. The SiC substrate, after standard cleaning (RCA), needs to be oxidized in a humid oxygen environment at around 1100℃ for about half an hour to form a sacrificial oxide layer, which is then removed by ultrasonic rinsing with diluted HF. Dry oxygen oxidation is then performed at 1100-1400℃ for about half an hour, followed by annealing at 1200-1400℃ in a NO atmosphere for 1-3 hours. This annealing atmosphere can be POCl3, H2, N2O, P2O5, Sb+NO, etc., ultimately yielding the gate oxide layer 9. Preferably, the gate oxide layer 9 can also be formed using methods such as atomic layer deposition (ALD). Doped polysilicon is filled into the second trench and planarized to form the gate electrode 8. Specifically, the second trench of the gate oxide layer 9 is filled using isotropic deposition technology. The filler can be doped polysilicon or silicide with high conductivity to form the gate electrode 8. The deposited gate electrode 8 is etched back using dry etching, wet etching, or other methods. The process is repeated until the area is planarized and only the gate electrode 8 in the second trench is retained. The gate oxide layer 9 on the p++ source layer 7 and the n++ source layer 6 is removed using diluted HF, exposing the surfaces of the n++ source layer 6 and the p++ source layer 7.

[0049] (6)Reference Figure 9 and Figure 1Source electrodes 10 are fabricated on n++ type source layer 6 and p++ type source layer 7, and drain electrodes 11 are fabricated on the second surface of n++ type silicon carbide substrate 1. Specifically, photolithography is used to pattern the substrate, and multilayer metals of 60-100 nm Ni, 20-40 nm Ti, and 60-100 nm Al are sequentially deposited using thin film deposition methods such as electron beam evaporation or sputtering. The remaining photoresist is then removed to form source electrodes 10. Source electrodes 10 must simultaneously cover the surfaces of p++ type source layer 7 and n++ type source layer 6. Source electrodes 10 can also be other metal combinations such as AlTi, Ni, and TiW. A protective coating is applied to the front source electrodes 10, and the oxide layer on the second surface of the n++ type silicon carbide substrate 1 is removed using diluted HF. A 10-30 nm thick AlTi and a 300-500 nm thick Ni metal layer are deposited on the second surface using thin film deposition methods such as electron beam evaporation or sputtering to serve as drain electrodes 11. Preferably, drain electrodes 11 can also be other metal combinations such as AlTi, Ni, TiW, and AlTi. Ohmic contacts are achieved through rapid thermal annealing. Specifically, the source electrode 10 and drain electrode 11 are annealed at 800–1200°C in an N2 environment for 1–3 minutes. The annealing atmosphere can also be Ar or H2+N2. A passivation layer of approximately 1 μm thickness, consisting of SiO2 / Si3N4, is deposited on the gate electrode 8 and source electrode 10 using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Specifically, photolithography is first used to pattern the passivation layer, followed by dry etching with an etching gas to form an opening. A metal layer of 1–3 μm thickness is then deposited at the opening using electron beam evaporation or sputtering, and photolithography is used to pattern the external portion, interconnecting it with the gate electrode 8 and source electrode 10, thus completing device fabrication.

[0050] Comparative Example

[0051] A silicon carbide-based trench MOSFET without a superjunction structure 3 below the p-type channel layer 5 and the p-type shielding layer 4 is used as a comparative example. In the comparative example, the silicon carbide-based trench MOSFET does not have a first n+ pillar region 31 and its two sides of the p+ pillar regions 32 below the p-type shielding layer 4, and there is no second n+ pillar region 33 below the p-type channel layer 5.

[0052] CT-UMOS represents the silicon carbide-based trench MOSFET in the comparative example, and ST-UMOS represents the silicon carbide-based trench MOSFET with integrated superjunction structure in the embodiment of this application. Figure 10 The output characteristics of CT-UMOS and ST-UMOS structures are compared. Figure 11 The results show a comparison of the current densities of CT-UMOS and ST-UMOS structures. Figure 10 and Figure 11This indicates that during forward conduction, the second n+ pillar region 33 on both sides of the p-type channel layer 5 increases the concentration of carrier electrons accumulated in the device accumulation layer, improves carrier mobility, reduces the on-resistance of the device, and improves the on-state characteristics of the device.

[0053] Figure 12 The results show a comparison of the breakdown characteristics of CT-UMOS and ST-UMOS structures. Figure 13 This diagram illustrates the electric field distribution of CT-UMOS and ST-UMOS structures. Figure 12 and Figure 13 This indicates that under reverse blocking conditions, the free charges in the first n+ pillar region 31, p+ pillar region 32, and second n+ pillar region 33 of the superjunction structure are completely depleted, making it equivalent to an intrinsic semiconductor. This alleviates the electric field congestion at the corner of the p-type shielding layer 4 and has extremely high withstand voltage, with the breakdown voltage rising from 1250V to 1556V.

[0054] The above embodiments are only used to further illustrate the technical solution of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A silicon carbide-based trench MOSFET with an integrated superjunction structure, characterized in that, The device includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p++ type source layer, and an n++ type source layer. The n-type drift layer is disposed on a first surface of the n++ type silicon carbide substrate and has a first trench. The first trench is filled with a superjunction structure, which includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and the p+ pillar regions are located on both sides of the first n+ pillar region. The second n+ pillar region is located on the outer side of each of the two p+ pillar regions. The first n+ pillar region, p+ pillar region, and second n+ pillar region are vertically disposed at the bottom of the first trench. The p+ pillar region is located between the first n+ pillar region and the second n+ pillar region. The inner side of the p+ pillar region is connected to the outer side of the first n+ pillar region, and the inner side of the second n+ pillar region is connected to the outer side of the first n+ pillar region. The outer side of the p+ pillar region is connected, and the outer side of the second n+ pillar region is connected to the sidewall of the first trench. The superjunction structure and the n-type drift layer on both sides of the first trench are provided with the p-type channel layer. The p-type channel layer is provided with adjacent p++ type source region layer and n++ type source region layer. The p++ type source region layer is located outside the n++ type source region layer. A second trench is provided extending from the middle of the n++ type source region layer to a predetermined position of the superjunction structure. A p-type shielding layer is provided below the bottom of the second trench. The second trench is filled with a gate electrode. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench. A source electrode is provided above the p++ type source region layer and the n++ type source region layer. A drain electrode is provided on the second surface of the n++ type silicon carbide substrate.

2. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The outer side of the p+ pillar area is flush with the side of the second trench. The bottom surface of the p-type shielding layer is connected to the first n+ pillar area and the p+ pillar area. The bottom surface of the p-type trench layer is connected to the top of the second n+ pillar area. The side of the p-type shielding layer is connected to the second n+ pillar area.

3. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The width of the p+ column region is greater than 0 and less than or equal to 2 μm.

4. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The height of the first n+ column region and the p+ column region is 1 to 3 μm, and the height of the second n+ column region is 2 to 4 μm.

5. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The doping concentration of the first n+ pillar region and the second n+ pillar region is 1 x 10 16 cm -3 ~6 x 10 16 cm -3 The doping concentration of the p+ pillar region is 1.0 x 10 17 cm -3 ~3 x 10 17 cm -3 .

6. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The bottom of the second trench is located below the p-type channel layer, and the distance between it and the lower surface of the p-type channel layer is 0.5 to 1.5 μm. The thickness of the p-type shielding layer is 0.1 to 0.5 μm.

7. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The p-type channel layer is doped at 0.5 x 10 17 cm -3 to 4.5 x 10 17 cm -3 , the n++ type source region layer is doped at 1.0 x 10 19 cm -3 ~ 5.0 x 10 19 cm -3 , the p++ type source region layer is doped at 1.0 x 10 19 cm -3 ~ 1.0 x 10 20 cm -3 , and the p-type shielding layer is doped at 1.0 x 10 18 cm -3 to 1.0 x 10 20 cm -3 .

8. The silicon carbide-based trench MOSFET with integrated superjunction structure according to claim 1, characterized in that, The source electrode and drain electrode are made of AlTi, Ni, TiW or AlTi. A passivation layer is provided above the gate electrode and the source electrode, and an external connection is provided at the opening on the passivation layer.

9. A method for fabricating a silicon carbide-based trench MOSFET with an integrated superjunction structure according to any one of claims 1-8, characterized in that, Includes the following steps: 1) Provide an n++ type silicon carbide substrate, and epitaxially grow an n-type drift layer on the first surface of the n++ type silicon carbide substrate; 2) A first trench is etched in the n-type drift layer, and n+ pillar regions are epitaxially grown inside and outside the first trench. The n+ pillar regions are etched to form a first n+ pillar region and a second n+ pillar region. Then, p+ pillar regions are epitaxially grown to form a superjunction structure. In the superjunction structure, the first n+ pillar region is located in the middle, and the p+ pillar regions are provided on both sides of the first n+ pillar region. The second n+ pillar region is provided on the outer side of both p+ pillar regions. 3) A p-type channel layer is epitaxially grown on the superjunction structure and the n-type drift layer, an n++ type source region layer is epitaxially grown on the p-type channel layer, a mask layer is fabricated above the middle part of the n++ type source region layer, and ion implantation is performed to form a p++ type source region layer located outside the n++ type source region layer. 4) A second trench is etched from the middle of the n++ type source region layer to a predetermined position of the superjunction structure, and a p-type shielding layer is formed below the bottom of the second trench by ion implantation; 5) A gate oxide layer is formed on the top of the p-type shielding layer and the side of the second trench, and a gate electrode is filled in the second trench where the gate oxide layer is formed; 6) A source electrode is fabricated on the n++ type source region layer and the p++ type source region layer, and a drain electrode is fabricated on the second surface of the n++ type silicon carbide substrate.

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