An electronic integrable double-sided architecture silicon carbide thin film device and a preparation method thereof

Abstract

The application provides an electronic-integrable double-sided architecture silicon carbide thin film device and a preparation method, and belongs to the technical field of semiconductor devices. By adopting the electronic-integrable double-sided architecture silicon carbide thin film device and the preparation method provided in the embodiment of the application, through innovative technologies such as double-sided architecture design, multi-layer epitaxial structure optimization, ultra-thin substrate thinning and front vertical interconnection, excellent performances such as low leakage current, high quantum efficiency, high frequency response, high integration degree and small packaging volume are achieved. Compared with traditional silicon carbide devices, the application has significant advantages, provides an innovative solution for the application of high-performance silicon carbide devices in the fields of ultraviolet detection, high-speed optical communication, quantum precision measurement and sensors, and has important technical value and broad application prospect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an electronically integrable double-sided silicon carbide thin-film device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a wide-bandgap semiconductor material, has become one of the ideal materials for fabricating high-power electronic devices, high-frequency optoelectronic devices, and high-temperature sensors due to its high breakdown field strength, high saturated electron drift velocity, high thermal conductivity, and excellent chemical stability. In the field of power electronics, silicon carbide-based devices can significantly reduce switching losses and improve system efficiency. In the field of ultraviolet photodetection, its intrinsic absorption edge is located in the short-wavelength ultraviolet region, possessing advantages such as visible blindness, fast response, and strong radiation resistance, making it suitable for special environments such as deep space exploration and flame sensing.

[0003] Currently, mainstream silicon carbide devices mostly adopt a single-sided epitaxial layer and single-sided electrode layout in their architecture and epitaxial structure. This structure typically involves sequentially growing epitaxial layers and constructing functional regions on the same substrate surface. The photosensitive units of optoelectronic devices or the switching units of power devices are concentrated on the front side of the material, and their signal output and connection to external circuits rely entirely on the metal electrodes located on the front side. This design is relatively straightforward in terms of process implementation and has high compatibility with traditional planar integrated circuit processes.

[0004] However, the aforementioned single-sided epitaxy and electrode design has several inherent drawbacks: First, to guide the signal from the front electrode to the chip edge or package pins, complex metal interconnect traces are often required. These extended wires introduce significant parasitic capacitance and resistance, limiting the device's performance under high-frequency or high-speed switching. Second, for devices such as photodetectors, incident light typically enters from the front, and since the metal electrode and photosensitive area are on the same side, the electrode inevitably blocks part of the effective photosensitive area, reducing the device's effective light fill factor and affecting optical response efficiency. Furthermore, since all electrical interfaces are concentrated on one side, when integrating the detector chip with the back-end readout circuitry, a horizontal side-by-side layout or additional wire bonding is usually required. This not only increases interconnection difficulty and parasitic effects but also occupies a significant amount of printed circuit board area, making it difficult to meet the increasingly urgent demands for system miniaturization and high-density integration, ultimately resulting in a significant limitation on the overall module's package size. Summary of the Invention

[0005] This invention provides an electronically integrable double-sided silicon carbide thin-film device and its fabrication method. This overcomes the limitations of traditional single-sided silicon carbide device processes, reduces parasitic capacitance and resistance in long-distance metal wiring, improves device functionality and integration, and significantly reduces package size. The technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide an electronically integrable double-sided silicon carbide thin-film device, comprising a substrate layer, a first silicon carbide layer, a second silicon carbide layer, and a circuit board disposed from bottom to top. An electronic chip is disposed on the circuit board. The first silicon carbide layer and the second silicon carbide layer have different doping types. The first silicon carbide layer has a first patterned region and a second patterned region surrounding the first patterned region. The second silicon carbide layer is located in the first patterned region. A first electrode is disposed on the first silicon carbide layer located in the second patterned region, and the first electrode forms an ohmic contact with the first silicon carbide layer. A second electrode is disposed on the second silicon carbide layer, and the second electrode forms an ohmic contact with the second silicon carbide layer. A passivation layer is deposited between the first electrode and the first silicon carbide layer, and between the second electrode and the second silicon carbide layer. The first electrode and the second electrode are interconnected with a readout circuit on the circuit board.

[0007] Optionally, the first silicon carbide layer is P-type doped, and the second silicon carbide layer is N-type doped.

[0008] Optionally, both the first silicon carbide layer and the second silicon carbide layer are stacked in at least two layers.

[0009] Optionally, both the first silicon carbide layer and the second silicon carbide layer are provided in two layers, with the doping concentration of the lower first silicon carbide layer ranging from 1×10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm; the doping concentration of the first silicon carbide layer located above it ranges from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm; the doping concentration of the second silicon carbide layer below ranges from 1 × 10⁻⁶. 12 ~1×10 19 cm -3 The thickness ranges from 1 to 120 μm; the doping concentration of the second silicon carbide layer above it ranges from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm.

[0010] Optionally, the substrate layer is an ultrathin silicon carbide substrate layer, and the thickness of the substrate layer ranges from 1 to 500 μm.

[0011] Optionally, the surface roughness at the bottom of the substrate layer is ≤0.5nm.

[0012] Optionally, the materials of the first electrode and the second electrode are at least one of nickel, titanium, aluminum or gold.

[0013] In a second aspect, embodiments of the present invention provide a fabrication method for manufacturing the electronically integrable double-sided silicon carbide thin-film device described in the first aspect, comprising:

[0014] Step 1: The first silicon carbide layer and the second silicon carbide layer are epitaxially grown sequentially on the substrate to form a vertical thin film structure;

[0015] Step 2: Fabricate a detection unit on the front side of the device;

[0016] Step 3: Perform processing on the substrate layer to thin it to the target thickness, forming a back-incident optical window;

[0017] Step 4: Vertical interconnection between the first electrode, the second electrode and the readout circuit on the circuit board is achieved through surface mount and wire bonding processes.

[0018] Optionally, step three includes:

[0019] The substrate layer is ground using a diamond grinding wheel during the rough grinding stage;

[0020] The substrate layer is chemically polished during the fine grinding stage;

[0021] In the final polishing stage, the substrate layer is etched using a hydrofluoric acid-nitric acid mixed solution to remove the surface damage layer.

[0022] Optionally, the grinding of the substrate layer using a diamond grinding wheel in the rough grinding stage includes:

[0023] First, the substrate layer is ground using a diamond grinding wheel with a grit size of #2000 to make the surface material scratch depth of the substrate layer ≤1μm;

[0024] The substrate layer is then ground using a diamond grinding wheel with a grit size of #8000 to achieve a surface roughness Ra ≤ 10 nm.

[0025] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0026] This invention features a double-sided architecture design. The back side is precisely thinned to form a back-incident optical window, while the front side integrates electrodes and a circuit board with electronic chips. This design breaks through the limitations of traditional single-sided processes and improves the functionality and integration of the device.

[0027] Furthermore, the present invention, through a carefully designed multilayer epitaxial structure, increases the width of the depletion region and makes the electric field distribution more uniform by using a drift region with a larger thickness and lower doping. This effectively suppresses the peak electric field, significantly reduces the leakage current of the device, and improves the breakdown voltage and operating stability.

[0028] Furthermore, this invention thins the silicon carbide substrate layer 1 to 1–500 μm, achieving an ultrathin substrate. The ultrathin substrate significantly reduces optical absorption loss, substantially improves the transmittance of back-incident light and the quantum efficiency of the device, while shortening the carrier transport path and improving the device's response speed.

[0029] Furthermore, this invention employs a front-side vertical interconnect method, where the first and second electrodes are directly connected to the readout circuit on the circuit board via wire bonding, resulting in an extremely short interconnect distance. This significantly reduces parasitic capacitance and resistance, improves the high-frequency response characteristics of the device, reduces circuit noise, and enhances the signal-to-noise ratio.

[0030] Furthermore, the process technologies used in this invention are all mature semiconductor manufacturing processes, which are highly compatible with existing silicon carbide device production lines and integrated circuit production lines. The process parameters have good repeatability and controllability, making them suitable for large-scale mass production. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the hierarchical structure of the vertical thin film structure of the electronically integrable double-sided silicon carbide thin film device provided in this embodiment of the invention.

[0033] Figure 2 yes Figure 1 A schematic diagram of the hierarchical structure after the detection unit is fabricated on the front side of the device;

[0034] Figure 3 yes Figure 2 A top-view structural diagram;

[0035] Figure 4 This is a three-dimensional structural schematic diagram of the electronically integrable double-sided silicon carbide thin-film device provided in an embodiment of the present invention;

[0036] Figure 5 This is a flowchart of the preparation method provided in the embodiments of the present invention.

[0037] In the figure: 1-substrate layer; 2-first silicon carbide layer; 21-first lower layer; 22-first upper layer; 2a-first patterned area; 2b-second patterned area; 3-second silicon carbide layer; 31-second lower layer; 32-second upper layer; 4-circuit board; 5-first electrode; 6-second electrode; 7-passivation layer; 41-electronic chip. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of the hierarchical structure of the vertical thin film structure of the electronically integrable double-sided silicon carbide thin film device provided in an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the hierarchical structure after the detection unit is fabricated on the front side of the device; Figure 3 yes Figure 2 A top-view structural diagram; Figure 4 This is a three-dimensional structural schematic diagram of the electronically integrable double-sided silicon carbide thin-film device provided in an embodiment of the present invention. Figures 1 to 4 As shown, this embodiment of the invention provides an electronically integrable double-sided silicon carbide thin-film device, including a substrate layer 1, a first silicon carbide layer 2, a second silicon carbide layer 3, and a circuit board 4 arranged from bottom to top. An electronic chip 41 is disposed on the circuit board. The first silicon carbide layer 2 and the second silicon carbide layer 3 have different doping types. The first silicon carbide layer 2 has a first patterned region 2a and a second patterned region 2b surrounding the first patterned region 2a. The second silicon carbide layer 3 is located in the first patterned region 2a. A first electrode 5 is disposed on the first silicon carbide layer 2 located in the second patterned region 2b, and the first electrode 5 forms an ohmic contact with the first silicon carbide layer 2. A second electrode 6 is disposed on the second silicon carbide layer 3, and the second electrode 6 forms an ohmic contact with the second silicon carbide layer 3. A passivation layer 7 is deposited between the first electrode 5 and the first silicon carbide layer 2, and between the second electrode 6 and the second silicon carbide layer 3. The first electrode 5 and the second electrode 6 are interconnected with a readout circuit on the circuit board 4.

[0040] In this embodiment of the invention, substrate 1 is an ultrathin silicon carbide substrate with a thickness ranging from 1 to 500 μm. Preferably, a silicon carbide substrate with a thickness of 50 μm is used in this embodiment. After undergoing a mechanical-chemical co-polishing process, the bottom surface roughness of substrate 1 is ≤0.5 nm, preferably 0.1 nm, achieving atomic-level flatness. The ultrathin substrate 1 significantly reduces optical absorption loss, allowing back-incident light to efficiently pass through substrate 1 to reach the functional layer, while also shortening the carrier transport path and improving the device's response speed.

[0041] The first silicon carbide layer 2 is formed on the substrate layer 1 by an epitaxial growth process, and its doping type is different from that of the second silicon carbide layer 3. In this embodiment, the first silicon carbide layer 2 is p-type doped. Figure 1 As shown, the first silicon carbide layer 2 has a first patterned region 2a and a second patterned region 2b surrounding the first patterned region 2a.

[0042] Preferably, the first silicon carbide layer 2 is provided with a stacked structure consisting of two layers, including a first lower layer 21 and a first upper layer 22 stacked from bottom to top: the first lower layer 21 has a doping concentration of 6×10⁻⁶. 18 cm -3 The thickness is 1 μm; the doping concentration of the first upper layer 22 is 1 × 10⁻⁶. 19 cm -3 The thickness is 0.5 μm. The first lower layer 21 is a P-type drift region with a relatively thick thickness, which can effectively form a depletion region and realize photoelectric conversion; the first upper layer 22 has a high doping concentration, which can form a good ohmic contact with the first electrode 5 and reduce the contact resistance.

[0043] In other embodiments, the doping concentration of the lower first layer 21 can be in the range of 1×10⁻⁶. 16 ~1×10 20 cm -3 The thickness can range from 0.1 to 5 μm; the doping concentration of the first upper layer 22 can range from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm and can be adjusted according to specific application requirements.

[0044] The second silicon carbide layer 3 is located on the first patterned region 2a and is formed on the first silicon carbide layer 2 through an epitaxial growth process. In this embodiment, the second silicon carbide layer 3 is N-type doped, forming a PN junction structure with the P-type doped first silicon carbide layer 2. This PN junction is the core structure for the device to realize photoelectric detection, signal processing and other functions.

[0045] Preferably, the second silicon carbide layer 3 also adopts a stacked structure with two layers, including a second lower layer 31 and a second upper layer 32 stacked from bottom to top: the lower second layer 31 has a doping concentration of 8×10⁻⁶. 13 cm -3 The thickness is 50 μm; the second upper layer has a doping concentration of 1 × 10⁻⁶. 18 cm -3The thickness is 0.5 μm. The second lower layer 31 has a low doping concentration and a large thickness, forming an intrinsic absorption region or a low-doped drift region, which can form a wide depletion region under reverse bias, effectively collecting photogenerated carriers while suppressing dark current; the second upper layer 32 has a high doping concentration, which can form a good ohmic contact with the second electrode 6.

[0046] In other embodiments, the doping concentration of the lower second layer 31 can be in the range of 1×10⁻⁶. 12 ~1×10 19 cm -3 The thickness can range from 1 to 120 μm; the doping concentration of the second upper layer 32 can range from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness range can be 0.1 to 5 μm.

[0047] The aforementioned multilayer epitaxial structure design, through careful optimization of doping concentration and thickness distribution, results in a more uniform electric field distribution, effectively suppressing the peak electric field at the PN junction interface and avoiding tunneling current and early breakdown caused by excessively high electric field strength. Simultaneously, the layered doping structure achieves a smooth transition of the electric field gradient, significantly reducing the device's leakage current and improving breakdown voltage and operational stability. Experimental tests show that the leakage current density of the device using this multilayer structure under reverse bias can be as low as 10⁻⁸ A / cm², which is more than two orders of magnitude lower than that of the traditional single-layer structure.

[0048] The materials of the first electrode 5 and the second electrode 6 are preferably at least one of nickel, titanium, aluminum, or gold. In this embodiment, a Ti / Al / Ni / Au multilayer stacked structure is preferably adopted, wherein the Ti layer serves as an adhesion layer to ensure good bonding between the electrode and the silicon carbide surface; the Al layer provides a low resistivity conductive path; the Ni layer serves as a barrier layer to prevent gold diffusion; and the Au layer serves as an anti-oxidation protective layer and a wire bonding layer to ensure the long-term stability and interconnect reliability of the device.

[0049] Electrode formation employs a metal deposition-lift-off process: first, electrode patterns are defined at the contact hole locations of passivation layer 7 using photolithography; then, multilayer metals of Ti / Al / Ni / Au are sequentially deposited using electron beam evaporation or magnetron sputtering; finally, the photoresist and excess metal are removed using a lift-off process to form a precisely patterned electrode structure. After electrode formation, rapid thermal annealing (RTA) is performed to achieve good ohmic contact.

[0050] The passivation layer 7 covers the exposed surfaces of the first silicon carbide layer 2 and the second silicon carbide layer 3, with contact holes only opened in the electrode contact area, so that the first electrode 5 and the second electrode 6 can form ohmic contact with the corresponding silicon carbide layers.

[0051] The passivation layer 7 is preferably made of silicon dioxide (SiO2) or silicon nitride (Si3N4) material, with a thickness ranging from 50 to 500 nm. In this embodiment, a 200 nm silicon dioxide layer is preferred. The main functions of the passivation layer 7 include: 1. Passivating dangling bonds and defect states on the silicon carbide surface, reducing surface recombination rate, and reducing dark current; 2. Protecting the device surface from environmental pollution and mechanical damage; 3. Providing electrical isolation to prevent short circuits between adjacent electrodes; 4. Improving the long-term stability and reliability of the device.

[0052] The circuit board 4 is fixed above the first electrode 5 and the second electrode 6 by surface mount technology. The first electrode 5 and the second electrode 6 are interconnected with the readout circuit on the circuit board 4 by wire bonding technology, realizing the vertical interconnection between the front electrode and the readout circuit.

[0053] Circuit board 4 is a ceramic circuit board or PCB board, and the electronic chip 41 on it may include, but is not limited to: charge-sensitive preamplifier, transimpedance amplifier, analog-to-digital converter (ADC), timing control circuit, signal processing unit, etc. In photoelectric detection applications, when light is incident from the bottom of the back substrate layer, photogenerated carriers are generated at the PN junction formed by the first silicon carbide layer 2 and the second silicon carbide layer 3. The carriers are collected by the first electrode 5 and the second electrode 6 under the action of the built-in electric field or the applied bias voltage. The generated photocurrent signal is directly transmitted to the electronic chip 41 through wire bonding for amplification, filtering, analog-to-digital conversion, and other processing.

[0054] Due to the adoption of a front-side vertical interconnect, the signal transmission path is extremely short, typically only a few hundred micrometers to a few millimeters. Compared to traditional long-distance metal wiring, parasitic capacitance can be reduced by more than 80%, from tens of pF to a few pF, and parasitic resistance can be reduced by more than 90%, from a few ohms to tens of milliohms, significantly improving the high-frequency response characteristics and signal-to-noise ratio of the device. At the same time, the vertical interconnect architecture allows for high integration of silicon carbide thin-film devices and electronic chips 41, greatly reducing the system package size, which can be reduced by more than 50% compared to traditional solutions.

[0055] It should be noted that, Figure 4 The main focus is on the connection between the electronic chip 41 and the readout circuit on the circuit board 4 and the first electrode 5 and the second electrode 6 on the front of the device below. The hierarchical structure of the device below is only for illustration.

[0056] For example, in the embodiments of the present invention, the double-sided silicon carbide thin film device can be a photodetector, a charge-coupled device (CCD), a quantum precision measurement device, an analog signal processing device, an electronic integrated chip, or a sensor.

[0057] Figure 5This is a flowchart of the preparation method provided in the embodiments of the present invention. For example... Figure 5 As shown, the electronically integrable double-sided silicon carbide thin-film device of this invention is fabricated based on this method, including the following steps:

[0058] S1. A first silicon carbide layer 2 and a second silicon carbide layer 3 are epitaxially grown sequentially on the substrate layer 1 to form a vertical thin film structure.

[0059] Specifically, a suitable silicon carbide substrate is first selected, and epitaxial growth is performed using chemical vapor deposition (CVD) technology, preferably high-temperature vapor deposition (HTCVD) or chemical vapor deposition (CVD). The lower P-type first silicon carbide layer 2 is grown first. Trimethylaluminum (TMAl) is used as the dopant source for P-type doping, silane (SiH4) is used as the silicon source, and propane (C3H8) or ethylene (C2H4) is used as the carbon source. The doping concentration is adjusted by precisely controlling the flow rate of TMAl. In this embodiment, the doping concentration of the two first silicon carbide layers 2 is 6 × 10⁻⁶. 18 cm -3 The thickness is 1μm.

[0060] After the first silicon carbide layer 2 is completed, the doping source is changed, and nitrogen (N2) or ammonia (NH3) is used as the N-type doping source. The next N-type second silicon carbide layer 3 is then grown, and the doping concentration is controlled at 8 × 10⁻⁶ by reducing the doping source flux. 13 cm -3 The low-doping layer, with a thickness of 50 μm, forms the intrinsic absorption region or low-doped drift region and is the main functional layer of the device. Then, an upper N-type second silicon carbide layer 3 is grown, and the doping source flux is increased to achieve a doping concentration of 1 × 10⁻⁶. 18 cm -3 The thickness is 0.5 μm, which serves as a heavily doped layer to form an ohmic contact with the electrode.

[0061] After epitaxial growth, a cooling process is required. The cooling rate should be controlled at 5–10 °C / min to avoid lattice defects caused by thermal stress due to rapid cooling. The crystal quality and interface quality of the epitaxial layer are crucial to device performance. By optimizing growth parameters, a low dislocation density ≤102 can be achieved. 3 cm -2 And an atomically flat interface.

[0062] S2. Fabricate the detection unit on the front side of the device.

[0063] Specifically, on the wafer after epitaxial growth, a detection unit is fabricated on the front side of the device through photolithography, etching, and metal deposition-lifting processes to form a first patterned region 2a, a second patterned region 2b, a first electrode 5, and a second electrode 6.

[0064] First, a passivation layer 7 is deposited on the surface of the epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD) or thermal oxidation. Then, photolithography and etching are performed on the passivation layer 7 to open contact holes and expose the silicon carbide surface where electrodes will be formed. Next, the second silicon carbide layer 3 is selectively etched to define a first patterned region 2a and a second patterned region 2b. Inductively coupled plasma (ICP) etching is used to completely etch through the second silicon carbide layer 3 and slightly penetrate the first silicon carbide layer 2. A first electrode 5 and a second electrode 6 are formed using a metal deposition-lift process; the electrode material is a Ti / Al / Ni / Au multilayer stacked structure. Annealing is performed in a rapid thermal annealing (RTA) furnace to promote the alloying reaction at the metal-silicon carbide interface, forming a low-impedance ohmic contact.

[0065] S3. Perform a process on substrate layer 1 to thin it to the target thickness, forming a back-incident optical window.

[0066] Specifically, the substrate layer 1 is thinned using a mechanical-chemical co-processing polishing process, reducing the initial thickness of the substrate layer 1 from 400 μm to 1 μm to form a back-incident optical window.

[0067] This process includes three stages:

[0068] Rough grinding stage: Diamond grinding wheels are used to remove more than 90% of the substrate material. The grit size of the diamond grinding wheels adopts a gradient decreasing strategy: the initial grinding uses a #2000 grit wheel, and the depth of residual scratches on the surface is ≤1μm; the final grinding uses a #8000 grit wheel, and the surface roughness Ra is ≤10nm.

[0069] Fine grinding stage: Chemical mechanical polishing (CMP) process is used. The polishing pad is made of porous polyurethane material with a porosity of 40% and a compressibility of 20%. The polishing slurry is an alkaline colloidal silica solution with a pH of 9, a particle size of 20 nm, and a pressure of 1 Pa. A balance between material removal rate and surface quality is achieved by using a polishing speed of 300 rpm.

[0070] Final polishing stage: Chemical etching is performed using a mixed solution of hydrofluoric acid and nitric acid with a volume ratio of 1:3 to 1:5 to remove the surface damage layer and obtain an atomic-level step flow morphology with a surface roughness of 0.1 nm.

[0071] Annealing treatment: After the final polishing stage, annealing treatment is performed. The temperature is increased to 800-1000℃ in an argon atmosphere at a rate of 10℃ / min, and held for 10-30 min to repair lattice defects and reduce the dislocation density to ≤10³cm. - ².

[0072] After the above-mentioned mechanical-chemical synergistic grinding and polishing process, a high-quality back-incident optical window is formed at the bottom of the ultrathin substrate layer 1, which significantly reduces optical absorption loss and improves the transmittance of back-incident light.

[0073] S4. Vertical interconnection between the first electrode 5, the second electrode 6 and the readout circuit on the circuit board 4 is achieved through surface mount and wire bonding processes.

[0074] Specifically, the circuit board 4 is first fixed to a suitable position on the front of the device using a surface mount process. Then, electrical interconnection is achieved using wire bonding technology, with one end of a gold wire bonded to the first electrode 5 or the second electrode 6, and the other end bonded to the corresponding pad on the circuit board 4. The circuit board 4 integrates a readout circuit, which can be connected to the upper electronics chip 41 according to the requirements of different devices, providing signal processing and driving functions.

[0075] With the front-side vertical interconnection method, the interconnection distance between the first electrode 5, the second electrode 6 and the circuit board 4 is extremely short, which significantly reduces parasitic capacitance and resistance, improves the high-frequency response characteristics of the device, and at the same time achieves a high degree of integration between the silicon carbide thin film device and the circuit board 4, greatly reducing the system's package size.

[0076] The electronically integrable double-sided silicon carbide thin-film device prepared by the method provided in this invention has the following significant advantages compared to the prior art:

[0077] Traditional silicon carbide devices employ single-sided epitaxy and single-sided electrode designs, which limit the functional expansion of the devices. This invention, through a double-sided architecture design, uses a back-incident optical window formed by precision thinning on the back side, while integrating electrodes and a circuit board 4 with electronic chips 41 on the front side. This breaks through the limitations of traditional single-sided processes and improves the functionality and integration of the devices.

[0078] Furthermore, the present invention, through a carefully designed multilayer epitaxial structure, increases the width of the depletion region and makes the electric field distribution more uniform by using a drift region with a larger thickness and lower doping. This effectively suppresses the peak electric field, significantly reduces the leakage current of the device, and improves the breakdown voltage and operating stability.

[0079] Furthermore, this invention thins the silicon carbide substrate layer 1 to 1–500 μm, achieving an ultrathin substrate. The ultrathin substrate significantly reduces optical absorption loss, substantially improves the transmittance of back-incident light and the quantum efficiency of the device, while shortening the carrier transport path and improving the device's response speed.

[0080] Furthermore, this invention employs a front-side vertical interconnect method, where the first electrode 5 and the second electrode 6 are directly connected to the circuit board 4 via wire bonding, resulting in an extremely short interconnection distance. This significantly reduces parasitic capacitance and resistance, improves the high-frequency response characteristics of the device, reduces circuit noise, and enhances the signal-to-noise ratio.

[0081] Furthermore, the process technologies used in this invention are all mature semiconductor manufacturing processes, which are highly compatible with existing silicon carbide device production lines and integrated circuit production lines. The process parameters have good repeatability and controllability, making them suitable for large-scale mass production.

[0082] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art described herein. The terms "first," "second," and similar terms used in this application and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including" and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed after "comprising" or "including," and do not exclude other elements or objects. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0083] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An electronically integrable double-sided silicon carbide thin-film device, characterized in that, The system comprises, from bottom to top, a substrate layer (1), a first silicon carbide layer (2), a second silicon carbide layer (3), and a circuit board (4). An electronic chip (41) is disposed on the circuit board (4). The first silicon carbide layer (2) and the second silicon carbide layer (3) have different doping types. The first silicon carbide layer (2) has a first patterned region (2a) and a second patterned region (2b) surrounding the first patterned region (2a). The second silicon carbide layer (3) is located within the first patterned region (2a), and the first silicon carbide layer (3) is located within the second patterned region (2b). A first electrode (5) is disposed on a silicon carbide layer (2), and the first electrode (5) forms an ohmic contact with the first silicon carbide layer (2). A second electrode (6) is disposed on a second silicon carbide layer (3), and the second electrode (6) forms an ohmic contact with the second silicon carbide layer (3). A passivation layer (7) is deposited between the first electrode (5) and the first silicon carbide layer (2) and between the second electrode (6) and the second silicon carbide layer (3). The first electrode (5), the second electrode (6) and the readout circuit on the circuit board (4) are interconnected.

2. The electronically integrable double-sided silicon carbide thin-film device according to claim 1, characterized in that, The first silicon carbide layer (2) is doped with P-type, and the second silicon carbide layer (3) is doped with N-type.

3. The electronically integrable double-sided silicon carbide thin-film device according to claim 2, characterized in that, The first silicon carbide layer (2) and the second silicon carbide layer (3) are both stacked with at least two layers.

4. The electronically integrable double-sided silicon carbide thin-film device according to claim 3, characterized in that, Both the first silicon carbide layer (2) and the second silicon carbide layer (3) are provided in two layers, with the doping concentration of the lower first silicon carbide layer (2) ranging from 1×10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm; the doping concentration of the first silicon carbide layer (2) located above it ranges from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm; the doping concentration of the second silicon carbide layer (3) located below ranges from 1 × 10⁻⁶. 12 ~1×10 19 cm -3 The thickness ranges from 1 to 120 μm; the doping concentration of the second silicon carbide layer (3) located above it ranges from 1 × 10⁻⁶. 16 ~1×10 20 cm -3 The thickness ranges from 0.1 to 5 μm.

5. The electronically integrable double-sided silicon carbide thin-film device according to claim 1, characterized in that, The substrate (1) is an ultrathin silicon carbide substrate (1), and the thickness of the substrate (1) ranges from 1 to 500 μm.

6. The electronically integrable double-sided silicon carbide thin-film device according to claim 5, characterized in that, The surface roughness of the bottom of the substrate layer (1) is ≤0.5nm.

7. The electronically integrable double-sided silicon carbide thin-film device according to claim 1, characterized in that, The first electrode (5) and the second electrode (6) are made of at least one of nickel, titanium, aluminum or gold.

8. A method for fabricating an electronically integrable double-sided silicon carbide thin-film device, used to fabricate the electronically integrable double-sided silicon carbide thin-film device as described in any one of claims 1 to 7, characterized in that, include: Step 1: The first silicon carbide layer (2) and the second silicon carbide layer (3) are epitaxially grown sequentially on the substrate layer (1) to form a vertical thin film structure; Step 2: Fabricate the detection unit on the front side of the device; Step 3: Process the substrate layer (1) to thin it to the target thickness to form a back-incident optical window; Step 4: Vertical interconnection between the first electrode (5), the second electrode (6) and the readout circuit on the circuit board (4) is achieved through surface mount and wire bonding processes.

9. The preparation method according to claim 8, characterized in that, Step three includes: The substrate layer (1) is ground using a diamond grinding wheel during the rough grinding stage; The substrate layer (1) is chemically polished during the fine grinding stage; In the final polishing stage, the substrate layer (1) is etched using a hydrofluoric acid-nitric acid mixed solution to remove the surface damage layer.

10. The preparation method according to claim 9, characterized in that, The grinding of the substrate layer (1) using a diamond grinding wheel in the rough grinding stage includes: First, the substrate layer (1) is ground with a diamond grinding wheel of #2000 grit so that the surface material scratch depth of the substrate layer (1) is ≤1μm; The substrate layer (1) is then ground using a diamond grinding wheel with a grit size of #8000 to make the surface roughness Ra of the substrate layer (1) ≤ 10nm.

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