Drive circuit and half-bridge drive circuit

Abstract

This invention discloses a driving circuit and a half-bridge driving circuit for driving a target power transistor. The circuit includes: a floating rail circuit connected between a first node and a second node, used to generate a floating voltage and a clamping voltage; a control signal generation circuit connected between the first node and the floating voltage, generating a control signal based on a PWM signal; and a gate driving circuit connected between the first node and the second node and connected to the clamping voltage, used to generate a target driving signal based on several control signals to drive the target power transistor. This invention generates a floating voltage through the floating rail circuit, allowing the control signal generation circuit to operate in the floating voltage domain, thus avoiding the risk of high-voltage transistor breakdown; it generates a clamping voltage through the floating rail circuit, allowing the output transistor of the gate driving circuit to be a low-voltage transistor, improving the response speed of the gate driving circuit; and it achieves half-bridge driving based on only two sets of floating rail circuits, saving circuit area.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a driving circuit and a half-bridge driving circuit. Background Art

[0002] Refer Figure 1 As shown in the figure, it is a half-bridge driving circuit in the prior art. The driving voltage PVCC is a high voltage (for example, 7.5V), and the high-voltage process does not support thick gate oxide. That is, when the V of the high-voltage transistor GS ≤5V, an internal floating drive with a low voltage (for example, 5V) needs to be performed to ensure that the V of the high-voltage transistor GS will not be broken down.

[0003] Refer Figure 2 As shown in the figure, it is a floating rail circuit in the prior art, which generates a floating voltage through a driving transistor and a voltage stabilizing capacitor. For example, on the PMOS driving side, a floating voltage of PVCC - 5V (or BST - 5V) is generated; on the NMOS driving side, a floating voltage of PGND + 5V (or SW + 5V) is generated.

[0004] The disadvantages of the prior art are that the driving transistor and the stabilizing capacitor of the floating rail circuit will occupy a relatively large circuit area. As Figure 3 shown in the figure, for a half-bridge driving circuit, in order to obtain sufficient driving ability and stable driving voltage, four floating voltages (PVCC - 5V, BST - 5V, PGND + 5V, and SW + 5V) need to be generated through 4 groups of floating rail circuits, so a larger circuit area needs to be occupied.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a driving circuit and a half-bridge driving circuit. Summary of the Invention

[0006] The purpose of the present invention is to provide a driving circuit and a half-bridge driving circuit, which can generate a floating voltage domain with a relatively small circuit area to adapt to the thin gate process of high-voltage driving.

[0007] To achieve the above purpose, the technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A driving circuit for driving a target power transistor, the driving circuit comprising:

[0009] A floating rail circuit connected between a first node and a second node, configured to generate a floating voltage based on the voltage on the first node and generate a clamping voltage based on the voltage on the second node, the floating voltage being less than the voltage on the first node, and the clamping voltage being greater than the voltage on the second node;

[0010] A control signal generation circuit is connected between the first node and the floating voltage, and is used to generate several control signals based on the PWM signal;

[0011] A gate drive circuit is connected between the first node and the second node and is connected to the clamping voltage. The gate drive circuit has a multi-stage structure, and each stage of the gate drive circuit corresponds to at least one control signal. The gate drive circuit is used to generate a target drive signal based on several control signals to drive the target power transistor.

[0012] In one or more embodiments of the present invention, the floating rail circuit includes a first Zener transistor, a first resistor, a second resistor, a first MOSFET, a third resistor, and a second Zener transistor; wherein,

[0013] The first end of the first Zener diode is connected to the first end of the first resistor, the second end of the first Zener diode is connected to the first node, and the second end of the first resistor is connected to the second node.

[0014] The first end of the second resistor is connected to the first node, the second end of the second resistor is connected to the floating voltage, the first end of the first MOSFET is connected to the floating voltage, the second end of the first MOSFET is connected to the second node, and the control terminal of the first MOSFET is connected to the first end of the first Zener transistor.

[0015] The first end of the third resistor is connected to the first node, the second end of the third resistor is connected to the clamping voltage, the first end of the second Zener diode is connected to the second node, and the second end of the second Zener diode is connected to the clamping voltage.

[0016] In one or more embodiments of the present invention, the floating rail circuit further includes:

[0017] A first capacitor, the first terminal of the first capacitor is connected to a first node, and the second terminal of the first capacitor is connected to a floating voltage.

[0018] The second capacitor has its first terminal connected to the clamping voltage and its second terminal connected to the second node.

[0019] In one or more embodiments of the present invention, the gate driving circuit includes a latch unit, a first driving unit, a second driving unit, a first power transistor, and a second power transistor; wherein,

[0020] The latching unit is connected to the control signal generation circuit. The latching unit generates a latching signal based on a first control signal and a second control signal. The first control signal and the second control signal are out of phase.

[0021] The first driving unit is connected to the control signal generation circuit and the latch unit. The first driving unit is used to generate a first driving signal based on the latch signal and the second control signal.

[0022] The second driving unit is connected to the first driving unit, and the second driving unit is used to generate a power transistor driving signal based on the first driving signal and the third control signal;

[0023] The first end of the first power transistor is connected to the first node, the control end of the first power transistor receives the fourth control signal, and the second end of the first power transistor is connected to the control end of the target power transistor.

[0024] The first end of the second power transistor is connected to the second node, the control end of the second power transistor is connected to the second drive unit and receives the power transistor drive signal, and the second end of the second power transistor is connected to the control end of the target power transistor.

[0025] In one or more embodiments of the present invention, the first driving unit includes a third input transistor, a third clamping transistor, and a third output transistor; wherein...

[0026] The first end of the third input tube is connected to the first node, the second end of the third input tube is connected to the second end of the third clamping tube, and the control end of the third input tube receives the second control signal.

[0027] The control terminal of the third clamping transistor is connected to the clamping voltage, and the first terminal of the third clamping transistor is connected to the second terminal of the third output transistor.

[0028] The control terminal of the third output tube is connected to the latch unit and receives the latch signal. The first end of the third output tube is connected to the second node, and the second end of the third output tube is connected to the second drive unit and generates the first drive signal.

[0029] In one or more embodiments of the present invention, the second driving unit includes a fourth input transistor, a fourth clamping transistor, and a fourth output transistor; wherein,

[0030] The first end of the fourth input tube is connected to the first node, the second end of the fourth input tube is connected to the second end of the fourth clamping tube, and the control end of the fourth input tube receives the third control signal.

[0031] The control terminal of the fourth clamping transistor is connected to the clamping voltage, and the first terminal of the fourth clamping transistor is connected to the second terminal of the fourth output transistor.

[0032] The control terminal of the fourth output transistor is connected to the first driving unit and receives the first driving signal. The first end of the fourth output transistor is connected to the second node, and the second end of the fourth output transistor is connected to the control terminal of the second power transistor and generates a power transistor driving signal.

[0033] In one or more embodiments of the present invention, the control signal generation circuit includes a plurality of interconnected inverters, which are used to invert and delay the PWM signal to generate a first control signal, a second control signal, a third control signal, and a fourth control signal; wherein,

[0034] The first control signal is in phase with the PWM signal;

[0035] The second control signal is inverted compared to the PWM signal, and the second control signal is delayed compared to the first control signal;

[0036] The third control signal is in phase with the PWM signal, and the third control signal is delayed compared to the second control signal;

[0037] The fourth control signal is out of phase with the PWM signal and is delayed compared to the third control signal.

[0038] In one or more embodiments of the present invention, the latching unit includes a first input transistor, a second input transistor, a first clamping transistor, a second clamping transistor, a first output transistor, and a second output transistor; wherein,

[0039] The first end of the first input tube is connected to the first node, the second end of the first input tube is directly or indirectly connected to the second end of the first clamping tube, and the control end of the first input tube receives the second control signal.

[0040] The first end of the second input tube is connected to the first node, the second end of the second input tube is directly or indirectly connected to the second end of the second clamping tube, and the control end of the second input tube receives the first control signal.

[0041] The control terminals of the first clamping transistor and the second clamping transistor are connected to the clamping voltage. The first terminal of the first clamping transistor is directly or indirectly connected to the second terminal of the first output transistor, and the first terminal of the second clamping transistor is directly or indirectly connected to the second terminal of the second output transistor.

[0042] The first end of the first output tube is connected to the second node, and the control end of the first output tube is connected to the first end of the second clamping tube.

[0043] The first end of the second output tube is connected to the second node, and the control end of the second output tube is connected to the first end of the first clamping tube.

[0044] In one or more embodiments of the present invention, the latching unit further includes a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; wherein,

[0045] The first end of the fourth resistor is connected to the second end of the first input transistor, and the second end of the fourth resistor is connected to the second end of the first clamping transistor.

[0046] The first end of the fifth resistor is connected to the second end of the second input transistor, and the second end of the fifth resistor is connected to the second end of the second clamping transistor.

[0047] The first end of the sixth resistor is connected to the first end of the first clamping transistor, and the second end of the sixth resistor is connected to the second end of the first output transistor.

[0048] The first end of the seventh resistor is connected to the first end of the second clamping transistor, and the second end of the seventh resistor is connected to the second end of the second output transistor.

[0049] In one or more embodiments of the present invention, the first node is connected to the BST pin in the driving circuit, the second node is connected to the SW pin in the driving circuit, and the target power transistor is a high-voltage side power transistor.

[0050] In one or more embodiments of the present invention, the first node is connected to the power supply voltage, the second node is connected to the ground potential, and the target power transistor is a low-voltage side power transistor.

[0051] Another specific embodiment of the present invention provides the following technical solution:

[0052] A half-bridge drive circuit, comprising a first drive circuit and a second drive circuit; wherein,

[0053] The first driving circuit is the driving circuit described above; and / or,

[0054] The second driving circuit is the driving circuit described above.

[0055] Compared with the prior art, the driving circuit and half-bridge driving circuit of the present invention generate a floating voltage through the floating rail circuit, so that the control signal generation circuit operates in the floating voltage domain, thereby making the control signals all signals within the floating voltage domain. The input tube in the gate driving circuit operates in the floating voltage domain of about 5V, preventing the input tube in the gate driving circuit from being broken down.

[0056] The clamping voltage generated by the floating rail circuit allows the output transistor in the gate drive circuit to be a low-voltage transistor, and prevents the output transistor in the gate drive circuit from being broken down, thereby improving the response speed of the gate drive circuit and reducing power consumption.

[0057] The gate drive circuit adopts a push-pull stage structure, which generates a stable target drive signal that meets the target drive capability through step-by-step driving;

[0058] For half-bridge drive circuits, only two sets of floating rail circuits are needed to obtain sufficient driving capability and stable driving voltage, saving circuit area. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of a half-bridge drive circuit in the prior art;

[0061] Figure 2 This is a schematic diagram of a floating rail circuit in another prior art.

[0062] Figure 3 This is a schematic diagram of a half-bridge drive circuit in another prior art.

[0063] Figure 4 This is a schematic diagram of the driving circuit in Embodiment 1 of the present invention;

[0064] Figure 5 This is a schematic diagram of the floating rail circuit of the driving circuit in Embodiment 1 of the present invention;

[0065] Figure 6 This is a schematic diagram of the control signal generation circuit of the driving circuit in Embodiment 1 of the present invention;

[0066] Figure 7 This is a schematic diagram of the gate driving circuit of the driving circuit in Embodiment 1 of the present invention;

[0067] Figure 8 This is a schematic diagram of the driving circuit in Embodiment 2 of the present invention;

[0068] Figure 9 This is a schematic diagram of the half-bridge drive circuit in Embodiment 3 of the present invention. Detailed Implementation

[0069] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0070] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0071] Example 1:

[0072] like Figure 4 As shown, in one embodiment, a driving circuit is used to drive a target power transistor. The driving circuit includes a floating rail circuit 10, a control signal generation circuit 20, and a gate driving circuit 30.

[0073] The floating rail circuit 10, connected between the first node and the second node, is used to generate a floating voltage VFLOAT based on the voltage at the first node and a clamping voltage VCLAMP based on the voltage at the second node. The floating voltage VFLOAT is less than the voltage at the first node, and the clamping voltage VCLAMP is greater than the voltage at the second node.

[0074] In one embodiment, the target power transistor is a high-voltage side power transistor. Therefore, the first node is connected to the BST pin of the drive circuit, and the second node is connected to the SW pin of the drive circuit. The voltage difference between the BST pin and the SW pin is approximately 7.5V. For ease of distinction, in one embodiment, BST refers to the first node and SW refers to the second node.

[0075] The control signal generation circuit 20 is connected between the first node BST and the floating voltage VFLOAT, and is used to generate several control signals based on the PWM signal.

[0076] The gate drive circuit 30 is connected between the first node BST and the second node SW, and is connected to the clamping voltage VCLAMP. The gate drive circuit 30 has a multi-stage structure, and each stage of the gate drive circuit 30 corresponds to at least one control signal. The gate drive circuit 30 is used to generate a target drive signal HO based on several control signals to drive the target power transistor.

[0077] like Figure 5 As shown, in one embodiment, the floating rail circuit 10 includes a first Zener diode D1, a first resistor R1, a second resistor R2, a first MOSFET M1, a third resistor R3, a second Zener diode D2, a first capacitor C1, and a second capacitor C2.

[0078] Specifically, the first end of the first Zener diode D1 is connected to the first end of the first resistor R1, the second end of the first Zener diode D1 is connected to the first node BST, and the second end of the first resistor R1 is connected to the second node SW.

[0079] The first terminal of the second resistor R2 is connected to the first node BST, and the second terminal of the second resistor R2 is connected to the floating voltage VFLOAT. The first terminal of the first MOSFET M1 is connected to the floating voltage VFLOAT, and the second terminal of the first MOSFET M1 is connected to the second node SW. The control terminal of the first MOSFET M1 is connected to the first terminal of the first Zener transistor D1. In this embodiment, the first MOSFET M1 is a high-voltage PMOS, with the first terminal of the first MOSFET M1 being the source, the second terminal being the drain, and the control terminal being the gate.

[0080] The first end of the third resistor R3 is connected to the first node BST, and the second end of the third resistor R3 is connected to the clamping voltage VCLAMP. The first end of the second Zener diode D2 is connected to the second node SW, and the second end of the second Zener diode D2 is connected to the clamping voltage VCLAMP.

[0081] The first terminal of the first capacitor C1 is connected to the first node BST, and the second terminal of the first capacitor C1 is connected to the floating voltage VFLOAT. The first terminal of the second capacitor C2 is connected to the clamping voltage VCLAMP, and the second terminal of the second capacitor C2 is connected to the second node SW.

[0082] like Figure 5 As shown, the floating rail circuit 10 utilizes the reverse breakdown voltage Vzener (approximately 6V) of the first Zener diode D1 and the second Zener diode D2 to generate a floating voltage VFLOAT and a clamping voltage VCLAMP to achieve voltage regulation. The floating voltage VFLOAT is equal to BST - Vzener + VGS. M1 Clamping voltage VCLAMP = SW + Vzener.

[0083] Specifically, the control terminal potential of the first MOSFET M1 is clamped to BST-Vzener by the first Zener transistor D1, and the floating voltage VFLOAT is equal to BST-Vzener + VGS. M1 Therefore, the floating voltage domain BST-VFLOAT between the first node BST and the floating voltage VFLOAT is Vzener-VGS. M1 The floating voltage domain BST-VFLOAT ranges from approximately 5V, which can prevent high-voltage transistors in thin-gate processes from being broken down.

[0084] like Figure 6 As shown, the control signal generation circuit 20 includes multiple interconnected inverters, each of which operates in the floating voltage domain BST-VFLOAT.

[0085] like Figure 7 As shown, the gate drive circuit 30 in this embodiment includes a latch unit 31, a first drive unit 32, a second drive unit 33, a first power transistor HV_PMOS, and a second power transistor HV_NMOS. It can be understood that the gate drive circuit 30 has a multi-stage structure, where the latch unit 31 can be considered as the first stage, the first drive unit 32 as the second stage, the second drive unit 33 as the third stage, and the first power transistor HV_PMOS and the second power transistor HV_NMOS as the output stage.

[0086] The latch unit 31 is connected to the control signal generation circuit 20. The latch unit 31 generates a latch signal based on the first control signal A1 and the second control signal A2, where the first control signal A1 and the second control signal A2 are out of phase. It can be understood that the latch signal is... Figure 7 The potential at point B2 is shown.

[0087] The first driving unit 32 is connected to the control signal generation circuit 20 and the latch unit 31. The first driving unit 32 is used to generate the first driving signal B3 based on the latch signal and the second control signal A2.

[0088] The second driving unit 33 is connected to the first driving unit 32. The second driving unit 33 is used to generate a power transistor driving signal NGATE based on the first driving signal B3 and the third control signal A3. It can be understood that the power transistor driving signal is... Figure 7 The NGATE point potential is shown.

[0089] The first power transistor HV_PMOS and the second power transistor HV_NMOS constitute the output stage. The second terminals of the first power transistor HV_PMOS and the second power transistor HV_NMOS are connected to the control terminal of the target power transistor, and a target drive signal HO is generated to the control terminal of the target power transistor. In one embodiment, both the first power transistor HV_PMOS and the second power transistor HV_NMOS are high-voltage transistors.

[0090] Specifically, the first terminal of the first power transistor HV_PMOS is connected to the first node BST, the control terminal of the first power transistor HV_PMOS receives the fourth control signal A4, and the second terminal of the first power transistor HV_PMOS is connected to the control terminal of the target power transistor. The first terminal of the second power transistor HV_NMOS is connected to the second node SW, the control terminal of the second power transistor HV_NMOS is connected to the second driving unit 33 and receives the power transistor driving signal NGATE, and the second terminal of the second power transistor HV_NMOS is connected to the control terminal of the target power transistor.

[0091] It is understood that latch unit 31, first drive unit 32, and second drive unit 33 each include a corresponding input transistor, clamping transistor, and output transistor. The input transistor is connected to the first node BST, and its second end is directly or indirectly connected to the second end of the clamping transistor. The control terminal of the input transistor receives the corresponding control signal. The control terminal of the clamping transistor is connected to the clamping voltage VCLAMP, and its first end is directly or indirectly connected to the second end of the output transistor. The first end of the output transistor is connected to the second node SW.

[0092] Furthermore, the input transistors of latch unit 31, first drive unit 32, and second drive unit 33 are all high-voltage transistors. As can be seen from the above analysis, the control signal generation circuit 20 is connected between the first node BST and the floating voltage VFLOAT. The control signals it generates are all signals within the floating voltage domain BST-VFLOAT. Therefore, the VGS of the input transistors of latch unit 31, first drive unit 32, and second drive unit 33 all operate within the range of Vzener-VGS (approximately 5V) and will not be broken down by high voltage.

[0093] The clamping transistors of latch unit 31, first drive unit 32, and second drive unit 33 are all high-voltage transistors, and can be considered to be always in a conducting state. The output transistors of latch unit 31, first drive unit 32, and second drive unit 33 are all low-voltage transistors. The first terminal voltage of the clamping transistor, i.e., the source voltage of the clamping transistor, is clamped to VCLAMP-VGS, therefore the output transistor operates within a voltage range of approximately 5V. Specifically, node B1 is clamped to VCLAMP-VGS. Q3 Node B2 is clamped to VCLAMP-VGS Q4 Node B3 is clamped to VCLAMP-VGS Q8 The NGATE node is clamped to VCLAMP-VGS Q11 .

[0094] It is understood that the control terminal voltage of the second power transistor HV_NMOS is approximately SW+5V, and the control terminal voltage of the first power transistor HV_PMOS is approximately BST-5V. That is, in one embodiment, the driving circuit generates two floating voltages (SW+5V and BST-5V) through a floating rail circuit.

[0095] Specifically, the latch unit 31 includes a first input transistor Q1, a second input transistor Q2, a first clamping transistor Q3, a second clamping transistor Q4, a first output transistor Q5, and a second output transistor Q6. The first input transistor Q1 and the second input transistor Q2 are high-voltage PMOS transistors, the first clamping transistor Q3 and the second clamping transistor Q4 are high-voltage NMOS transistors, and the first output transistor Q5 and the second output transistor Q6 are low-voltage NMOS transistors.

[0096] The first end of the first input tube Q1 is connected to the first node BST, the second end of the first input tube Q1 is directly or indirectly connected to the second end of the first clamping tube Q3, and the control end of the first input tube Q1 receives the second control signal A2.

[0097] The first end of the second input tube Q2 is connected to the first node BST, and the second end of the second input tube Q2 is directly or indirectly connected to the second end of the second clamping tube Q4. The control end of the second input tube Q2 receives the first control signal A1.

[0098] The control terminals of the first clamping transistor Q3 and the second clamping transistor Q4 are connected to the clamping voltage VCLAMP. The first terminal of the first clamping transistor Q3 is directly or indirectly connected to the second terminal of the first output transistor Q5, and the first terminal of the second clamping transistor Q4 is directly or indirectly connected to the second terminal of the second output transistor Q6.

[0099] The first end of the first output transistor Q5 is connected to the second node SW, and the control terminal of the first output transistor Q5 is connected to the first end of the second clamping transistor Q4. The first end of the second output transistor Q6 is connected to the second node SW, and the control terminal of the second output transistor Q6 is connected to the first end of the first clamping transistor Q3.

[0100] Furthermore, in one embodiment, the latching unit 31 further includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The first end of the fourth resistor R4 is connected to the second end of the first input transistor Q1, and the second end of the fourth resistor R4 is connected to the second end of the first clamping transistor Q3. The first end of the fifth resistor R5 is connected to the second end of the second input transistor Q2, and the second end of the fifth resistor R5 is connected to the second end of the second clamping transistor Q4. The first end of the sixth resistor R6 is connected to the first end of the first clamping transistor Q3, and the second end of the sixth resistor R6 is connected to the second end of the first output transistor Q5. The first end of the seventh resistor R7 is connected to the first end of the second clamping transistor Q4, and the second end of the seventh resistor R7 is connected to the second end of the second output transistor Q6.

[0101] like Figure 7 As shown, in one embodiment, the first driving unit 32 includes a third input transistor Q7, a third clamping transistor Q8, and a third output transistor Q9. The third input transistor Q7 is a high-voltage PMOS transistor, the third clamping transistor Q8 is a high-voltage NMOS transistor, and the third output transistor Q9 is a low-voltage NMOS transistor.

[0102] The first end of the third input transistor Q7 is connected to the first node BST, the second end of the third input transistor Q7 is connected to the second end of the third clamping transistor Q8, and the control end of the third input transistor Q7 receives the second control signal A2.

[0103] The control terminal of the third clamping transistor Q8 is connected to the clamping voltage VCLAMP, and the first terminal of the third clamping transistor Q8 is connected to the second terminal of the third output transistor Q9.

[0104] The control terminal of the third output transistor Q9 is connected to the latch unit 31 and receives the latch signal. The first terminal of the third output transistor Q9 is connected to the second node SW. The second terminal of the third output transistor Q9 generates the first drive signal B3.

[0105] like Figure 7 As shown, in one embodiment, the second driving unit 33 includes a fourth input transistor Q10, a fourth clamping transistor Q11, and a fourth output transistor Q12. The fourth input transistor Q10 is a high-voltage PMOS transistor, the fourth clamping transistor Q11 is a high-voltage NMOS transistor, and the fourth output transistor Q12 is a low-voltage NMOS transistor.

[0106] The first end of the fourth input transistor Q10 is connected to the first node BST, the second end of the fourth input transistor Q10 is connected to the second end of the fourth clamping transistor Q11, and the control terminal of the fourth input transistor Q10 receives the third control signal A3.

[0107] The control terminal of the fourth clamping transistor Q11 is connected to the clamping voltage VCLAMP, and the first terminal of the fourth clamping transistor Q11 is connected to the second terminal of the fourth output transistor Q12.

[0108] The control terminal of the fourth output transistor Q12 is connected to the second terminal of the third output transistor Q9 of the first drive unit 32 and receives the first drive signal B3. The first terminal of the fourth output transistor Q12 is connected to the second node SW. The second terminal of the fourth output transistor Q12 is connected to the control terminal of the second power transistor HV_NMOS and generates the power transistor drive signal NGATE.

[0109] Combination Figure 6 and Figure 7 It can be seen that the control signal generation circuit 20 is used to cooperate with the gate drive circuit 30 to enable the gate drive circuit 30 to achieve step-by-step driving. Therefore, for example... Figure 7 The gate drive circuit 30 shown and the control signal generation circuit 20 need to generate four control signals, namely the first control signal A1, the second control signal A2, the third control signal A3 and the fourth control signal A4.

[0110] Furthermore, the driving capability of the first control signal A1, the second control signal A2, the third control signal A3 to the first control signal A4 is gradually increased, and the phase is gradually delayed, so that the input transistor of the latch unit 31 of the gate drive circuit 30, the input transistor of the first drive unit 32, the input transistor of the second drive unit 33, and the first power transistor HV_PMOS are turned on step by step.

[0111] Specifically, the first control signal A1 is in phase with the PWM signal; the second control signal A2 is out of phase with the PWM signal and is delayed by the first control signal A1; the third control signal A3 is in phase with the PWM signal and is delayed by the second control signal A2; the fourth control signal A4 is out of phase with the PWM signal and is delayed by the third control signal A3.

[0112] like Figure 6 As shown, in one embodiment, the control signal generation circuit 20 includes multiple interconnected inverters, each inverter comprising an NMOS transistor and a PMOS transistor. The first terminal of the PMOS transistor is connected to the first node BST, the second terminal of the PMOS transistor is connected to the second terminal of the NMOS transistor, the control terminal of the PMOS transistor is connected to the control terminal of the NMOS transistor and serves as the input terminal of the inverter, the first terminal of the NMOS transistor is connected to the floating voltage VFLOAT, and the second terminal of the NMOS transistor is connected to the second terminal of the PMOS transistor and serves as the output terminal of the inverter. The input terminal of the first inverter receives the PWM signal, the output terminal of the first inverter is connected to the input terminal of the next inverter, and so on, obtaining the corresponding control signal through the output terminals of different inverters.

[0113] Specifically, in one embodiment, the PWM signal is passed through two inverters to generate a first control signal A1, which is in phase with the PWM signal. The first control signal A1 is passed through one inverter to generate a second control signal A2, which is out of phase with the first control signal A1. The second control signal A2 is passed through three inverters to generate a third control signal A3, which is also out of phase with the second control signal A2. The first control signal A1 is passed through five inverters to generate a fourth control signal A4, which is also out of phase with the first control signal A1.

[0114] When the PWM signal is high, the first control signal A1 is high, the second control signal A2 is low, the third control signal A3 is high, and the fourth control signal A4 is low. The first input transistor Q1 is on, the second input transistor Q2 is off, and node B1 is pulled up. Therefore, the second output transistor Q6 is on, node B2 is pulled low, and the third output transistor Q9 is off. Since the third input transistor Q7 is on, node B3 is pulled high, the fourth output transistor Q12 is on, and the fourth input transistor Q10 is off. The power transistor drive signal (i.e., the NGATE node voltage) is pulled low, the second power transistor HV_NMOS is off, the first power transistor HV_PMOS is on, and the target drive signal HO is pulled high.

[0115] When the PWM signal is low, the first control signal A1 is low, the second control signal A2 is high, the third control signal A3 is low, and the fourth control signal A4 is high. The first input transistor Q1 is off, the second input transistor Q2 is on, and node B2 is pulled up. Therefore, the first output transistor Q5 is on, node B1 is pulled low, and the third output transistor Q9 is on. Since the third input transistor Q7 is off, node B3 is pulled low, the fourth output transistor Q12 is off, and the fourth input transistor Q10 is on. The power transistor drive signal (i.e., the NGATE node voltage) is pulled high, the second power transistor HV_NMOS is on, the first power transistor HV_PMOS is off, and the target drive signal HO is pulled low.

[0116] The voltage range of the target drive signal HO is between the voltage on the first node BST and the voltage on the second node SW. However, the other MOS transistors in the drive unit 32 operate in a voltage range of about 5V under the action of the clamping voltage VCLAMP to avoid being broken down.

[0117] Furthermore, by setting the phases of the first control signal A1, the second control signal A2, the third control signal A3, and finally the first control signal A4 to be progressively delayed, the gate drive circuit 30 is started up step by step. This also ensures that the first power transistor HV_PMOS and the second power transistor HV_NMOS will not be turned on or off simultaneously. Once the on or off state of the second power transistor HV_NMOS is determined, the first power transistor HV_PMOS is controlled to turn on or off, avoiding potential damage to the circuit from large currents.

[0118] Example 2:

[0119] like Figure 8 As shown, in one embodiment, a driving circuit is used to drive a target power transistor. The driving circuit includes a floating rail circuit 10, a control signal generation circuit 20, and a gate driving circuit 30.

[0120] It is understood that the specific circuit structure of the driving circuit in one embodiment is consistent with that in embodiment 1. The difference lies in that the target power transistor in one embodiment is a low-voltage side power transistor, and the gate driving circuit 30 generates a target driving signal LO to control the low-voltage side power transistor. Therefore, in this embodiment, the first node is connected to the power supply voltage PVCC, and the second node is connected to the ground potential PGND. The difference between the power supply voltage PVCC and the ground potential PGND is approximately 7.5V.

[0121] The floating rail circuit 10 utilizes the reverse breakdown voltage Vzener (approximately 6V) of the first Zener diode D1 and the second Zener diode D2 to generate a floating voltage VFLOAT and a clamping voltage VCLAMP for voltage regulation. The floating voltage VFLOAT = PVCC - Vzener + VGS, and the clamping voltage VCLAMP = PGND + Vzener.

[0122] Specifically, the control terminal node of the first MOSFET M1 is clamped to PVCC-Vzener by the first Zener diode D1. Therefore, the floating voltage domain PVCC-VFLOAT between the first node and the floating voltage VFLOAT is Vzener-VGS. The value of this floating voltage domain PVCC-VFLOAT is about 5V, which can ensure that the high voltage transistor under the thin gate process will not be broken down.

[0123] The working principle of this embodiment is similar to that of Embodiment 1, and will not be repeated here.

[0124] Example 3:

[0125] like Figure 9 As shown, a half-bridge drive circuit in one embodiment includes a first drive circuit 41 and a second drive circuit 42. The first drive circuit 41 is the drive circuit in Embodiment 1, with its first node connected to the BST pin of the half-bridge drive circuit and its second node connected to the SW pin of the half-bridge drive circuit, used to drive the high-voltage side power transistor.

[0126] The second driving circuit 42 is the driving circuit in Embodiment 2. The first node is connected to the power supply voltage PVCC, and the second node is connected to the ground potential PVCC. It is used to drive the low-voltage side power transistor.

[0127] The output terminal of the first driving circuit 41 (i.e., the second terminal of the first power transistor HV_PMOS and the second terminal of the second power transistor HV_NMOS) is connected to the logic combination unit of the second driving circuit 42 through a level conversion unit LVL_H2L. The logic combination unit of the second driving circuit 42 is used to receive the corresponding PWM signal, and its output terminal is connected to the corresponding control signal generation circuit.

[0128] The output terminal of the second driving circuit 42 (i.e., the second terminal of the first power transistor HV_PMOS and the second terminal of the second power transistor HV_NMOS) is connected to the logic combination unit of the first driving circuit 41 through a level conversion unit LVL_H2L. The logic combination unit of the first driving circuit 41 is used to receive the corresponding PWM signal, and its output terminal is connected to the corresponding control signal generation circuit.

[0129] As can be seen from the above technical solutions, the present invention has the following beneficial effects:

[0130] This invention can be applied to high-voltage drive circuits. However, high-voltage processes do not have thick gate oxide and do not support high-voltage VGS. This invention generates a floating voltage through a floating rail circuit, so that the control signal generation circuit operates in the floating voltage domain. That is, the control signals are all generated within the floating voltage domain BST-VFLOAT. Therefore, the VGS of the input transistors in the gate drive circuit all operate within the range of Vzener-VGS (approximately 5V), preventing the input transistors from being damaged.

[0131] This invention generates a clamping voltage through a floating rail circuit, so that the output transistor in the gate drive circuit can be a low-voltage transistor and will not be broken down by high voltage, thereby improving the response speed of the gate drive circuit and reducing power consumption.

[0132] The gate drive circuit of this invention adopts a push-pull stage structure, generating a stable target drive signal that meets certain drive capabilities through stage-by-stage driving. For a single drive circuit, only one set of floating rail circuits is needed to ensure that the voltage variation range of the target drive signal is between the voltage at the first node and the voltage at the second node. Furthermore, for a half-bridge drive circuit, only two sets of floating rail circuits are needed to obtain sufficient drive capability and a stable drive voltage, compared to... Figure 2 The existing technology shown saves approximately 40% of the area;

[0133] The half-bridge drive circuit of this invention adopts a symmetrical structure. When the target drive signal generated under the low-voltage domain PVCC-PGND is quickly switched to the high-voltage domain BST-SW, the instantaneous change rate of DC current is avoided from affecting the generation of the floating domain.

[0134] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0135] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A driving circuit for driving a target power transistor, characterized in that, The driving circuit includes: A floating rail circuit, connected between a first node and a second node, is used to generate a floating voltage based on the voltage at the first node and a clamping voltage based on the voltage at the second node, wherein the floating voltage is less than the voltage at the first node and the clamping voltage is greater than the voltage at the second node; A control signal generation circuit is connected between the first node and the floating voltage, and is used to generate several control signals based on the PWM signal; A gate drive circuit is connected between the first node and the second node and is connected to the clamping voltage. The gate drive circuit has a multi-stage structure, and each stage of the gate drive circuit corresponds to at least one control signal. The gate drive circuit is used to generate a target drive signal based on several control signals to drive the target power transistor.

2. The driving circuit according to claim 1, characterized in that, The floating rail circuit includes a first Zener diode, a first resistor, a second resistor, a first MOSFET, a third resistor, and a second Zener diode; wherein, The first end of the first Zener diode is connected to the first end of the first resistor, the second end of the first Zener diode is connected to the first node, and the second end of the first resistor is connected to the second node. The first end of the second resistor is connected to the first node, the second end of the second resistor is connected to the floating voltage, the first end of the first MOSFET is connected to the floating voltage, the second end of the first MOSFET is connected to the second node, and the control terminal of the first MOSFET is connected to the first end of the first Zener transistor. The first end of the third resistor is connected to the first node, the second end of the third resistor is connected to the clamping voltage, the first end of the second Zener diode is connected to the second node, and the second end of the second Zener diode is connected to the clamping voltage.

3. The driving circuit according to claim 2, characterized in that, The floating rail circuit also includes: A first capacitor, the first terminal of the first capacitor is connected to a first node, and the second terminal of the first capacitor is connected to a floating voltage. The second capacitor has its first terminal connected to the clamping voltage and its second terminal connected to the second node.

4. The driving circuit according to claim 1, characterized in that, The gate drive circuit includes a latch unit, a first drive unit, a second drive unit, a first power transistor, and a second power transistor; wherein, The latching unit is connected to the control signal generation circuit. The latching unit generates a latching signal based on a first control signal and a second control signal. The first control signal and the second control signal are out of phase. The first driving unit is connected to the control signal generation circuit and the latch unit. The first driving unit is used to generate a first driving signal based on the latch signal and the second control signal. The second driving unit is connected to the first driving unit, and the second driving unit is used to generate a power transistor driving signal based on the first driving signal and the third control signal; The first end of the first power transistor is connected to the first node, the control end of the first power transistor receives the fourth control signal, and the second end of the first power transistor is connected to the control end of the target power transistor. The first end of the second power transistor is connected to the second node, the control end of the second power transistor is connected to the second drive unit and receives the power transistor drive signal, and the second end of the second power transistor is connected to the control end of the target power transistor.

5. The driving circuit according to claim 4, characterized in that, The first driving unit includes a third input transistor, a third clamping transistor, and a third output transistor; wherein, The first end of the third input tube is connected to the first node, the second end of the third input tube is connected to the second end of the third clamping tube, and the control end of the third input tube receives the second control signal. The control terminal of the third clamping transistor is connected to the clamping voltage, and the first terminal of the third clamping transistor is connected to the second terminal of the third output transistor. The control terminal of the third output tube is connected to the latch unit and receives the latch signal. The first end of the third output tube is connected to the second node, and the second end of the third output tube is connected to the second drive unit and generates the first drive signal.

6. The driving circuit according to claim 4, characterized in that, The second drive unit includes a fourth input transistor, a fourth clamping transistor, and a fourth output transistor; wherein, The first end of the fourth input tube is connected to the first node, the second end of the fourth input tube is connected to the second end of the fourth clamping tube, and the control end of the fourth input tube receives the third control signal. The control terminal of the fourth clamping transistor is connected to the clamping voltage, and the first terminal of the fourth clamping transistor is connected to the second terminal of the fourth output transistor. The control terminal of the fourth output transistor is connected to the first driving unit and receives the first driving signal. The first end of the fourth output transistor is connected to the second node, and the second end of the fourth output transistor is connected to the control terminal of the second power transistor and generates a power transistor driving signal.

7. The driving circuit according to claim 4, characterized in that, The control signal generation circuit includes multiple interconnected inverters, which are used to invert and delay the PWM signal to generate a first control signal, a second control signal, a third control signal, and a fourth control signal; wherein, The first control signal is in phase with the PWM signal; The second control signal is inverted compared to the PWM signal, and the second control signal is delayed compared to the first control signal; The third control signal is in phase with the PWM signal, and the third control signal is delayed compared to the second control signal; The fourth control signal is out of phase with the PWM signal and is delayed compared to the third control signal.

8. The driving circuit according to claim 4, characterized in that, The latching unit includes a first input transistor, a second input transistor, a first clamping transistor, a second clamping transistor, a first output transistor, and a second output transistor; wherein, The first end of the first input tube is connected to the first node, the second end of the first input tube is directly or indirectly connected to the second end of the first clamping tube, and the control end of the first input tube receives the second control signal. The first end of the second input tube is connected to the first node, the second end of the second input tube is directly or indirectly connected to the second end of the second clamping tube, and the control end of the second input tube receives the first control signal. The control terminals of the first clamping transistor and the second clamping transistor are connected to the clamping voltage. The first terminal of the first clamping transistor is directly or indirectly connected to the second terminal of the first output transistor, and the first terminal of the second clamping transistor is directly or indirectly connected to the second terminal of the second output transistor. The first end of the first output tube is connected to the second node, and the control end of the first output tube is connected to the first end of the second clamping tube. The first end of the second output tube is connected to the second node, and the control end of the second output tube is connected to the first end of the first clamping tube.

9. The driving circuit according to claim 8, characterized in that, The latching unit further includes a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; wherein, The first end of the fourth resistor is connected to the second end of the first input transistor, and the second end of the fourth resistor is connected to the second end of the first clamping transistor. The first end of the fifth resistor is connected to the second end of the second input transistor, and the second end of the fifth resistor is connected to the second end of the second clamping transistor. The first end of the sixth resistor is connected to the first end of the first clamping transistor, and the second end of the sixth resistor is connected to the second end of the first output transistor. The first end of the seventh resistor is connected to the first end of the second clamping transistor, and the second end of the seventh resistor is connected to the second end of the second output transistor.

10. The driving circuit according to claim 1, characterized in that, The first node is connected to the BST pin in the driving circuit, the second node is connected to the SW pin in the driving circuit, and the target power transistor is a high-voltage side power transistor.

11. The driving circuit according to claim 1, characterized in that, The first node is connected to the power supply voltage, the second node is connected to the ground potential, and the target power transistor is a low-voltage side power transistor.

12. A half-bridge drive circuit, characterized in that, The half-bridge drive circuit includes a first drive circuit and a second drive circuit; wherein... The first driving circuit is the driving circuit according to any one of claims 1 to 10; and / or, The second driving circuit is the driving circuit according to any one of claims 1 to 9 or 11.

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