Long distance communication and verification method and system for power line host communication core chip architecture

Abstract

The present invention relates to the technical field of power line communication systems, and more specifically, to a long-distance communication and verification method and system of a power line host communication core chip architecture. The scheme includes setting four links, and the four links are used for communication links for parallel data calculation and processing; a noise elimination module and a signal shaping module are set in the receiving link, and the acquired data is processed and decoded and stored in the receiving cache module; high, medium and low level controller signals are generated and sent to the pulse width modulation module; the voltage sampling value and L+ voltage sampling value of the slave sampling current are collected in real time, and quality control is completed after low-pass filtering and AD conversion; data is read in the receiving cache module and decoded and analyzed by a single-chip microcomputer; and L+ power supplies and transmission signals of three voltage sources of high, medium and low are generated. The scheme realizes higher computing power real-time signal quality monitoring and analysis through the power line host communication core chip architecture, and reduces MCU performance requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of power line communication systems, and more specifically, to a long-distance communication and verification method and system for a power line host communication core chip architecture. Background Art

[0002] Power line technology is a technology that combines two power lines and two signal lines into two lines to achieve signal and power sharing. It saves construction and cable costs and brings great convenience to on-site construction and later maintenance. It has been widely used in fire protection, instrumentation, sensors, industrial control and other fields.

[0003] In the prior art, power line communication is implemented through two modulation methods. The data downlink adopts voltage pulse width modulation technology. The voltage signal sequence on the power line is used to power the slave device and transmit information to the slave device. The uplink adopts current loop modulation technology. When the slave device receives the information from the host device, if a response is required, it will turn on the internal current source circuit to generate a current signal sequence to the power line, and finally realize one-to-many communication and power supply between the host and the slave. However, with the increase of transmission distance, number of slaves and power line loops, the existing long-distance verification system structure and method have higher requirements. It is necessary to accurately monitor and analyze the status of each slave device and the quality of the communication link in real time, and monitor and analyze the communication quality level, short circuit, open circuit and other abnormal conditions of each power line loop in real time. These complex situation signals and quality monitoring and analysis are difficult to achieve with the existing technology. Summary of the invention

[0004] In view of the above problems, the present invention proposes a long-distance communication and verification method and system for a power line host communication core chip architecture. Through a power line host communication core chip architecture, the above-mentioned higher bandwidth communication rate requirements, higher stability and reliability requirements, and higher computing power real-time signal quality monitoring and analysis requirements are flexibly solved, while also greatly reducing the requirements for MCU computing power performance.

[0005] According to a first aspect of an embodiment of the present invention, a long distance communication and calibration method of a power line host communication core chip architecture is provided.

[0006] In one or more embodiments, preferably, the long-distance communication and verification method of the power line host communication core chip architecture includes:

[0007] Setting up four-link communication links for parallel data computation and processing;

[0008] A noise elimination and signal shaping module is provided in the receiving link to process the acquired data and decode and store it in the receiving buffer module;

[0009] Generate high, medium and low level controller signals and send them to the pulse width modulation module;

[0010] The voltage sampling value and L+ voltage sampling value of the slave sampling current are collected in real time, and quality control is completed after low-pass filtering and AD conversion;

[0011] Read data in the cache module and decode and analyze it through the microcontroller;

[0012] According to the high, medium and low level controller signals (BUS_H, BUS_M, BUS_L), the L+ power supply and sending signals of the high, medium and low voltage sources are generated online.

[0013] In one or more embodiments, preferably, the communication link for setting four links for parallel data calculation and processing specifically includes:

[0014] Set up four links for high-speed parallel data calculation and processing, namely the sending link, receiving link, quality link and software link;

[0015] The sending link is responsible for receiving the data to be sent from the MCU subsystem module to the sending buffer module;

[0016] The receiving link is responsible for receiving data collected by the high-speed and high-precision ADC;

[0017] The quality link is responsible for analyzing the raw ADC data;

[0018] The software link obtains data from the local ADC data cache module on the one hand, and reads data from the receive cache module on the other hand, and performs program processing, data decoding and correctness confirmation.

[0019] In one or more embodiments, preferably, a noise elimination and signal shaping module is provided in the receiving link, and the acquired data is processed, decoded and stored in the receiving buffer module, which specifically includes:

[0020] A noise elimination module is provided in the receiving link, and the noise elimination module suppresses and eliminates the interference of electromagnetic radiation in the external harsh environment in real time;

[0021] Use signal shaping and equalization technology to determine whether the signal frequency is distorted. If it is distorted, it will automatically compensate the information. Determine whether the signal waveform is distorted. If there is distortion, it will automatically compensate the signal.

[0022] The signal after signal shaping is decoded and stored in the receiving buffer module.

[0023] In one or more embodiments, preferably, the generating of the controller signals of the high, medium and low levels and sending them to the pulse width modulation module specifically includes:

[0024] After being unpacked by the Frame packet module, CRC check is inserted and converted into a serial bit code stream;

[0025] Manchester encoding is performed on the serial bit code stream through a pulse encoding module and a frame start and frame end mark is inserted;

[0026] A basic pulse width generating module is set to generate high, medium and low level controller signals according to the internal timer and the control signal received from the pulse encoding module.

[0027] In one or more embodiments, preferably, the real-time acquisition of the voltage sampling value and the L+ voltage sampling value of the slave sampling current is performed after low-pass filtering and AD conversion to complete quality control, specifically including:

[0028] The current returned from the slave flows through the sampling resistor, forming a voltage at the + input terminal of the operational amplifier OPA. After impedance conversion and low-pass filtering by the operational amplifier, the voltage sampling value of the slave sampling current is output to the ADC.

[0029] The voltage value between the L+ terminal and the L- terminal is also output to the ADC after low-pass filtering;

[0030] Collect the voltage sampling value of the slave sampling current in real time, calculate the noise density, time domain transformation, frequency domain transformation, spectrum analysis and signal distortion curve;

[0031] Collect the voltage sampling value between the L+ terminal and the L- terminal in real time, monitor and calculate the actual signal amplitude of the three levels of high, medium and low, and whether there are any abnormalities in the communication link;

[0032] The quality levels of different channels are obtained and stored in the cache module.

[0033] In one or more embodiments, preferably, the data is read in the cache module and decoded and analyzed by the single-chip microcomputer, specifically including:

[0034] The MCU subsystem module processes and decodes the data in the receiving buffer module and the local ADC data buffer module using a software program;

[0035] When the software decoding result is inconsistent with the hardware result of the receiving link, the data is deleted.

[0036] In one or more embodiments, preferably, the online generation of L+ power supplies and transmission signals of three voltage sources of high, medium and low according to the controller signals (BUS_H, BUS_M, BUS_L) of three levels of high, medium and low specifically includes:

[0037] When the controller signal (BUS_H) of pulse modulation and current sampling to a high level is 1, the corresponding multiple sets of parallel NMOS tubes are turned on to enable the high-level voltage source VCC_H to be output to the L+ power line, wherein the multiple sets of parallel NMOS tubes are part of the pulse width modulation module;

[0038] When the high-level controller signal (BUS_H) of pulse modulation and current sampling is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the high-level voltage source VCC_H is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the medium-level and low-level controller signals;

[0039] When the controller signal (BUS_M) of the pulse modulation and current sampling is 1, the corresponding multiple sets of parallel NMOS tubes are turned on to enable the output of the medium-level voltage source VCC_M to the L+ power line;

[0040] When the pulse modulation and current sampling controller signal (BUS_M) of the middle level is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the middle level voltage source VCC_M is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high level and low level controller signals;

[0041] When the pulse modulation and current sampling controller signal (BUS_L) of the low level is 1, the corresponding multiple groups of parallel NMOS tubes are turned on to enable the low level voltage source to be output to the L+ power line, wherein the low level voltage source is the ground potential;

[0042] When the pulse modulation and current sampling low-level controller signal (BUS_L) is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the low-level voltage source is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high-level and medium-level controller signals.

[0043] According to a second aspect of an embodiment of the present invention, a long distance communication and calibration system of a power line host communication core chip architecture is provided.

[0044] In one or more embodiments, preferably, the long distance communication and verification system of the power line host communication core chip architecture includes:

[0045] A link setting module is used to set up four communication links for parallel data calculation and processing;

[0046] A receiving setting module is used to set a noise elimination and signal shaping module in the receiving link, process the acquired data, decode it and store it in the receiving buffer module;

[0047] A sending setting module is used to generate high, medium and low level controller signals and send them to the pulse width modulation module;

[0048] The quality analysis module is used to collect the voltage sampling value and L+ voltage sampling value of the slave sampling current in real time, and complete the quality control after low-pass filtering and AD conversion;

[0049] A soft analysis module, used to read data in the cache module and decode and analyze it through the microcontroller;

[0050] The pulse width modulation control module is used to generate L+ power supply and transmission signal of high, medium and low voltage sources online according to the controller signals of high, medium and low levels (BUS_H, BUS_M, BUS_L).

[0051] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0052] According to a fourth aspect of an embodiment of the present invention, there is provided an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement any one of the methods described in the first aspect of the embodiment of the present invention.

[0053] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0054] In the solution of the present invention, a power host communication core chip architecture, equipment and device are provided, which adopts technical means such as high-speed parallel processing of four links, real-time noise elimination, and real-time quality monitoring and analysis of vector processing engine.

[0055] In the solution of the present invention, through real-time signal shaping, real-time receiving decoding and real-time encoding, the quality of the communication channel is analyzed and monitored in real time, while also greatly reducing the requirements on the MCU computing power performance, freeing up the MCU performance to handle more complex applications.

[0056] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0057] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 It is a flow chart of a long distance communication and calibration method of a power line host communication core chip architecture according to an embodiment of the present invention.

[0060] Figure 2 It is a flow chart of setting four-link communication links for parallel data calculation and processing in a long-distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention.

[0061] Figure 3 It is a flowchart of a long-distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention, in which a noise elimination and signal shaping module is set in a receiving link, and the acquired data is processed, decoded and stored in a receiving cache module.

[0062] Figure 4 It is a flow chart of generating high, medium and low level controller signals and sending them to a pulse width modulation module in a long distance communication and verification method of a power line host communication core chip architecture according to an embodiment of the present invention.

[0063] Figure 5 It is a flowchart of a long-distance communication and calibration method of a power line host communication core chip architecture in an embodiment of the present invention, which collects voltage sampling values ​​and L+ voltage sampling values ​​of slave sampling current in real time, and completes quality control after low-pass filtering and AD conversion.

[0064] Figure 6 It is a flow chart of a long distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention, in which data is read in a cache module and decoded and analyzed by a single chip microcomputer.

[0065] Figure 7 It is a flowchart of the long-distance communication and verification method of the power line host communication core chip architecture of an embodiment of the present invention, which generates L+ power and sending signals of high, medium and low voltage sources online according to controller signals (BUS_H, BUS_M, BUS_L) of high, medium and low levels.

[0066] Figure 8 It is a structural diagram of a long-distance communication and calibration system of a power line host communication core chip architecture according to an embodiment of the present invention.

[0067] Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention.

[0068] Fig.10 This is the architecture diagram of the power line host communication chip.

[0069] Fig.11 This is a diagram of pulse modulation and current sampling. DETAILED DESCRIPTION

[0070] In some of the processes described in the specification and claims of the present invention and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0072] Power line technology is a technology that combines two power lines and two signal lines into two lines to achieve signal and power sharing. It saves construction and cable costs and brings great convenience to on-site construction and later maintenance. It has been widely used in fire protection, instrumentation, sensors, industrial control and other fields.

[0073] In the prior art, power line communication is implemented through two modulation methods. The data downlink adopts voltage pulse width modulation technology. The voltage signal sequence on the power line is used to power the slave device and transmit information to the slave device. The uplink adopts current loop modulation technology. When the slave device receives the information from the host device, if a response is required, it will turn on the internal current source circuit to generate a current signal sequence to the power line, and finally realize one-to-many communication and power supply between the host and the slave. However, with the increase of transmission distance, number of slaves and power line loops, the existing long-distance verification system structure and method have higher requirements. It is necessary to accurately monitor and analyze the status of each slave device and the quality of the communication link in real time, and monitor and analyze the communication quality level, short circuit, open circuit and other abnormal conditions of each power line loop in real time. These complex situation signals and quality monitoring and analysis are difficult to achieve with the existing technology.

[0074] In the embodiment of the present invention, a long-distance communication and verification method and system of a power line host communication core chip architecture are provided. The solution flexibly solves the above-mentioned higher bandwidth communication rate requirements, higher stability and reliability requirements, and higher computing power real-time signal quality monitoring and analysis requirements through a power line host communication core chip architecture, and also greatly reduces the requirements for MCU computing power performance.

[0075] According to a first aspect of an embodiment of the present invention, a long distance communication and calibration method of a power line host communication core chip architecture is provided.

[0076] Figure 1 It is a flow chart of a long distance communication and calibration method of a power line host communication core chip architecture according to an embodiment of the present invention.

[0077] In one or more embodiments, preferably, the long-distance communication and verification method of the power line host communication core chip architecture includes:

[0078] S101, setting four communication links for parallel data calculation and processing;

[0079] S102, a noise elimination and signal shaping module is provided in the receiving link to process the acquired data and decode and store it in the receiving buffer module;

[0080] S103, generating controller signals of three levels: high, medium and low, and sending them to the pulse width modulation module;

[0081] S104, collecting the voltage sampling value and L+ voltage sampling value of the slave sampling current in real time, and completing quality control after low-pass filtering and AD conversion;

[0082] S105, reading data in the cache module and decoding and analyzing it through the single chip microcomputer;

[0083] S106 , generating L+ power supplies and sending signals of three voltage sources of high, medium and low online according to the controller signals of high, medium and low levels (BUS_H, BUS_M, BUS_L).

[0084] In the embodiments of the present invention, as the equipment terminals and overall solution products develop in the direction of intelligence (AI), networking, and multifunctionality, it is required that a power line loop can communicate as far as possible (up to 1 to 3 kilometers), a power line loop can mount as many slave devices as possible (up to 256 slave devices), and a host device (host SoC chip) can manage and control as many power line loops as possible (up to 8 power line loops), while ensuring communication stability and reliability; the requirements for communication rate are also getting higher and higher, and it is necessary to ensure that the data of each slave device (usually analog data detected by sensors) can be quickly transmitted back to the host device for training, reasoning, and upgrading of AI models; in addition, it is necessary to monitor and analyze the status of each slave device and the quality of the communication link in real time and accurately, and monitor and analyze the communication quality level, short circuit, open circuit and other abnormal conditions of each power line loop in real time. These complex situation signals and quality monitoring and analysis have put forward higher requirements on the digital signal processing capabilities and core computing power of the host device (host SoC chip). Specifically, Fig.10 Shown is the power line host communication chip architecture diagram.

[0085] Figure 2 It is a flow chart of setting four-link communication links for parallel data calculation and processing in a long-distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention.

[0086] like Figure 2 As shown, in one or more embodiments, preferably, the communication link for setting four links for parallel data calculation and processing specifically includes:

[0087] S201, setting four links for high-speed parallel data calculation and processing, namely a sending link, a receiving link, a quality link and a software link;

[0088] S202, the sending link is responsible for receiving the data to be sent from the MCU subsystem module to the sending buffer module;

[0089] S203, the receiving link is responsible for receiving the high-speed and high-precision ADC acquisition data;

[0090] S204, the quality link is responsible for analyzing the original ADC data;

[0091] S205, the software link obtains data in the local ADC data cache module on the one hand, and reads data in the receiving cache module on the other hand, and performs program processing, data decoding and correctness confirmation.

[0092] In an embodiment of the present invention, first, the sending link is responsible for receiving the data to be sent by the MCU subsystem module and filling it into the sending buffer module. In this process, the MCU subsystem module puts the data to be sent into the sending buffer module, and then sends the data out through the sending link. This method can ensure the fast transmission and accuracy of the data. Secondly, the receiving link is responsible for receiving the data collected by the high-speed and high-precision ADC. Here, ADC is the abbreviation of analog-to-digital converter, which is a device that converts analog signals into digital signals. By using a high-speed and high-precision ADC, it can be ensured that the received data has sufficient accuracy and speed to meet the needs of the system. Next, the quality link is responsible for analyzing the original ADC data. In this process, the data collected from the ADC is analyzed in real time to evaluate its quality and reliability. This helps to discover and solve possible problems in a timely manner, thereby improving the reliability and stability of the system. Finally, the software link is responsible for the MCU subsystem module to obtain the data in the local ADC data cache module, and perform program processing, data decoding and correctness confirmation. In this process, the MCU subsystem module will read data from the local ADC data cache module, and then process, decode and verify it. This helps to ensure the integrity and correctness of the data, and also provides convenience for subsequent data analysis and application. Through the implementation of the above four steps, the present invention realizes an efficient and reliable power line host communication core chip architecture. This architecture can not only meet the requirements of high bandwidth communication rate, stability and reliability, but also realize real-time signal quality monitoring and analysis, thereby greatly improving the performance and efficiency of the entire system.

[0093] Figure 3 It is a flowchart of a long-distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention, in which a noise elimination and signal shaping module is set in a receiving link, and the acquired data is processed, decoded and stored in a receiving cache module.

[0094] like Figure 3 As shown, in one or more embodiments, preferably, a noise elimination and signal shaping module is provided in the receiving link, and the acquired data is processed and decoded and stored in the receiving buffer module, which specifically includes:

[0095] S301, a noise elimination module is provided in the receiving link, and the noise elimination module suppresses and eliminates the interference of electromagnetic radiation in an external harsh environment in real time;

[0096] S302, using signal shaping and equalization technology to determine whether the frequency of the signal is distorted, and if so, automatically performing information compensation, and determining whether the signal waveform is distorted, and if so, automatically performing signal compensation;

[0097] S303: Decode the signal after signal shaping and store it in a receiving buffer module.

[0098] In the embodiment of the present invention, first, the noise elimination module suppresses and eliminates the interference of electromagnetic radiation in the external harsh environment in real time to ensure the accuracy and reliability of the data. Then, the signal shaping and equalization technology is used to determine whether the frequency of the signal is distorted, and if it is distorted, the information compensation is automatically performed; at the same time, it is determined whether the signal waveform is distorted, and if there is distortion, the signal compensation is automatically performed. Finally, the signal after signal shaping is decoded and stored in the receiving buffer module. In this way, through the processing of the noise elimination and signal shaping modules, the impact of environmental noise on communication quality can be effectively reduced, and the reliability and stability of data can be improved.

[0099] Figure 4 It is a flow chart of generating high, medium and low level controller signals and sending them to a pulse width modulation module in a long distance communication and verification method of a power line host communication core chip architecture according to an embodiment of the present invention.

[0100] like Figure 4 As shown, in one or more embodiments, preferably, the generating of the controller signals of the high, medium and low levels and sending them to the pulse width modulation module specifically includes:

[0101] S401, unpacking through the Frame packet module, inserting CRC check and converting into a serial bit code stream;

[0102] S402, performing Manchester encoding on the serial bit code stream through a pulse encoding module and inserting frame start and frame end marks;

[0103] S403, setting a basic pulse width generating module to generate high, medium and low level controller signals according to an internal timer and a control signal received from a pulse encoding module.

[0104] In an embodiment of the present invention, a method is designed to generate high, medium and low level controller signals and send them to a pulse width modulation module. The method first unpacks the data through a Frame package module and inserts a CRC check bit to ensure the accuracy and integrity of data transmission. Then, the data after CRC check is converted into a serial bit code stream for subsequent processing. Next, the serial bit code stream is Manchester encoded using a pulse encoding module, and a frame start and frame end flags are inserted into the encoded data so that the receiving end can correctly parse the data. Finally, a basic pulse width generation module is set, which generates high, medium and low three different levels of controller signals according to the timing result of an internal timer and the control signal of the received pulse encoding module. These controller signals are then sent to the pulse width modulation module to achieve accurate control of external devices. Through this implementation, the present invention can effectively generate and send controller signals of multiple levels to meet the needs of different application scenarios.

[0105] Figure 5 It is a flowchart of a long-distance communication and calibration method of a power line host communication core chip architecture in an embodiment of the present invention, which collects voltage sampling values ​​and L+ voltage sampling values ​​of slave sampling current in real time, and completes quality control after low-pass filtering and AD conversion.

[0106] like Figure 5 As shown, in one or more embodiments, preferably, the real-time acquisition of the voltage sampling value and the L+ voltage sampling value of the slave sampling current is performed after low-pass filtering and AD conversion to complete quality control, specifically including:

[0107] S501, the current returned from the slave flows through the sampling resistor, forms a voltage at the + input terminal of the operational amplifier OPA, and after impedance conversion and low-pass filtering of the operational amplifier, outputs the voltage sampling value of the slave sampling current to the ADC;

[0108] S502, the voltage value between the L+ terminal and the L- terminal is also output to the ADC after low-pass filtering;

[0109] S503, collecting the voltage sampling value of the slave sampling current in real time, calculating the noise density, time domain transformation, frequency domain transformation, spectrum analysis and signal distortion curve;

[0110] S504, collecting the voltage sampling value between the L+ terminal and the L- terminal in real time, monitoring and calculating the actual signal amplitudes of the high, medium and low levels, and whether there are any abnormalities in the communication link;

[0111] S505: Obtain quality levels of different channels and store them in a cache module.

[0112] In an embodiment of the present invention, the voltage sampling values ​​collected in real time are first filtered by a low-pass filter to remove high-frequency noise and interference signals. Then, the data after low-pass filtering is subjected to analog-to-digital conversion (AD conversion) to convert the analog signal into a digital signal for subsequent processing and analysis. Next, the converted digital signal is subjected to quality control. This includes calculating parameters such as noise density, time domain transformation, frequency domain transformation, spectrum analysis, and signal distortion curve. By analyzing these parameters, the quality levels of different channels can be obtained, and these quality levels are stored in the cache module. In this way, these quality level information can be read and used at any time as needed, thereby realizing real-time monitoring and control of the system.

[0113] Figure 6 It is a flow chart of a long distance communication and verification method of a power line host communication core chip architecture in an embodiment of the present invention, in which data is read in a cache module and decoded and analyzed by a single chip microcomputer.

[0114] like Figure 6 As shown, in one or more embodiments, preferably, the data is read in the cache module and decoded and analyzed by the single-chip microcomputer, specifically including:

[0115] S601, the MCU subsystem module processes and decodes the data in the receiving buffer module and the local ADC data buffer module using a software program;

[0116] S602: When the software decoding result is inconsistent with the hardware result of the receiving link, the data is deleted.

[0117] In an embodiment of the present invention, the architecture includes four links of communication links for parallel data calculation and processing. Specifically, the four links are a sending link, a receiving link, a quality link and a software link. First, the sending link is responsible for receiving the data to be sent by the MCU subsystem module to the sending buffer module. In this process, the MCU subsystem module puts the data to be sent into the sending buffer module, and then sends the data out through the sending link. This method can ensure the fast transmission and accuracy of the data. Secondly, the receiving link is responsible for receiving the data collected by the high-speed and high-precision ADC. Here, ADC is the abbreviation of analog-to-digital converter, which is a device that converts analog signals into digital signals. By using a high-speed and high-precision ADC, it can be ensured that the received data has sufficient accuracy and speed to meet the needs of the system. Next, the quality link is responsible for analyzing the original ADC data. In this process, the data collected from the ADC is analyzed in real time to evaluate its quality and reliability. This helps to promptly discover and solve possible problems, thereby improving the reliability and stability of the system. Finally, the software link is responsible for obtaining the data in the local ADC data cache module by the MCU subsystem module, and performing program processing, data decoding and correctness confirmation. During this process, the MCU subsystem module reads data from the local ADC data cache module, and then processes, decodes, and verifies it. This helps ensure the integrity and correctness of the data, and also facilitates subsequent data analysis and application.

[0118] Figure 7 It is a flowchart of the long-distance communication and verification method of the power line host communication core chip architecture of an embodiment of the present invention, which generates L+ power and sending signals of high, medium and low voltage sources online according to controller signals (BUS_H, BUS_M, BUS_L) of high, medium and low levels.

[0119] like Figure 7 As shown, in one or more embodiments, preferably, the online generation of the L+ power supply and the sending signal of the three voltage sources of high, medium and low according to the controller signals (BUS_H, BUS_M, BUS_L) of the three levels of high, medium and low specifically includes:

[0120] S701, when the controller signal (BUS_H) of the pulse modulation and current sampling to a high level is 1, the corresponding multiple sets of parallel NMOS tubes are turned on to enable the high level voltage source VCC_H to be output to the L+ power line, wherein the multiple sets of parallel NMOS tubes are part of the pulse width modulation module;

[0121] S702, when the pulse modulation and current sampling controller signal (BUS_H) of high level is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the high level voltage source VCC_H is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the middle level and low level controller signals;

[0122] S703, when the controller signal (BUS_M) of the pulse modulation and current sampling is 1, the corresponding multiple groups of parallel-connected NMOS tubes are turned on to enable the output of the medium-level voltage source VCC_M to the L+ power line;

[0123] S704, when the pulse modulation and current sampling controller signal (BUS_M) of the middle level is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the middle level voltage source VCC_M is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high level and low level controller signals;

[0124] S705, when the pulse modulation and current sampling controller signal (BUS_L) of the low level is 1, the corresponding multiple groups of parallel NMOS tubes are turned on to enable the low level voltage source to be output to the L+ power line, wherein the low level voltage source is the ground potential;

[0125] S706, when the pulse modulation and current sampling low-level controller signal (BUS_L) is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the low-level voltage source is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high-level and medium-level controller signals.

[0126] In an embodiment of the present invention, the architecture can generate L+ power supplies and transmission signals of three voltage sources of high, medium and low online according to the controller signals of high, medium and low levels (BUS_H, BUS_M, BUS_L). When the controller signal of pulse modulation and current sampling to a high level is 1, the corresponding multiple groups of parallel NMOS tubes are turned on, so that VCC_H outputs a high level; when the controller signal of pulse modulation and current sampling to a high level is 0, the corresponding multiple groups of parallel NMOS tubes are turned off, so that VCC_H outputs a low level. Similarly, when the controller signal of pulse modulation and current sampling to a medium level is 1, the corresponding multiple groups of parallel NMOS tubes are turned on, so that VCC_M outputs a high level; when the controller signal of pulse modulation and current sampling to a medium level is 0, the corresponding multiple groups of parallel NMOS tubes are turned off, so that VCC_M outputs a low level. Finally, when the pulse modulation and current sampling to the low-level controller signal is 1, the corresponding multiple sets of parallel NMOS tubes are turned on. At this time, if the medium-level controller signal and the high-level controller signal are also 0, L+ is pulled down to a low level. The current returned from the slave flows through the sampling resistor, forming a voltage at the + input terminal of the operational amplifier OPA, and the output voltage sampling value is output after the impedance conversion and low-pass filtering of the operational amplifier. In this way, effective control and management of controller signals of different levels can be achieved. Specifically, the circuit structure, such as Fig.11 As shown, this structure is the core component for realizing long-distance power transmission in this scheme. Through this group of independently designed pulse-adjusted charging current sampling circuits, multiple groups of level-independent analog circuit control and output can be realized, and the output can be output between the same L+ and L-, so as to realize the verification and analysis of long-distance communication circuits and complete the effective isolation of analog and digital signals.

[0127] According to a second aspect of an embodiment of the present invention, a long distance communication and calibration system of a power line host communication core chip architecture is provided.

[0128] Figure 8 It is a structural diagram of a long-distance communication and calibration system of a power line host communication core chip architecture according to an embodiment of the present invention.

[0129] In one or more embodiments, preferably, the long distance communication and verification system of the power line host communication core chip architecture includes:

[0130] Link setting module 801, used to set up four communication links for parallel data calculation and processing;

[0131] The receiving setting module 802 is used to set a noise elimination and signal shaping module in the receiving link, process the acquired data, decode it and store it in the receiving buffer module;

[0132] The sending setting module 803 is used to generate high, medium and low level controller signals and send them to the pulse width modulation module;

[0133] The quality analysis module 804 is used to collect the voltage sampling value and L+ voltage sampling value of the slave sampling current in real time, and complete the quality control after low-pass filtering and AD conversion;

[0134] The soft analysis module 805 is used to read data from the cache module and decode and analyze it through the single chip microcomputer;

[0135] The pulse width modulation control module 806 is used to generate L+ power supplies and transmission signals of three voltage sources of high, medium and low online according to the controller signals of high, medium and low levels (BUS_H, BUS_M, BUS_L).

[0136] In the embodiment of the present invention, a system suitable for different structures is realized through a series of modular designs. The system can achieve closed-loop, reliable and efficient execution through collection, analysis and control.

[0137] According to a third aspect of an embodiment of the present invention, there is provided a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method as described in any one of the first aspect of the embodiment of the present invention is implemented.

[0138] According to a fourth aspect of an embodiment of the present invention, an electronic device is provided. Fig. 9 It is a structural diagram of an electronic device in one embodiment of the present invention. Fig. 9 The electronic device shown is a long distance communication and calibration device with a universal power line host communication core chip architecture. Fig. 9 As shown, the electronic device 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 902 or computer program instructions loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the electronic device 900 can also be stored. The CPU 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0139] Multiple components in the electronic device 900 are connected to the I / O interface 905, including: an input unit 906, an output unit 907, a storage unit 908, and the processing unit 901 performs the various methods and processes described above, such as the method described in the first aspect of the embodiment of the present invention. For example, in some embodiments, the method described in the first aspect of the embodiment of the present invention may be implemented as a computer software program, which is stored in a machine-readable medium, such as the storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the CPU 901, one or more operations of the method described in the first aspect of the embodiment of the present invention may be performed. Alternatively, in other embodiments, the CPU 901 may be configured as one or more actions of the method described in the first aspect of the embodiment of the present invention by any other appropriate means (e.g., by means of firmware).

[0140] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0141] In the solution of the present invention, a power host communication core chip architecture, equipment and device are provided, which adopts technical means such as high-speed parallel processing of four links, real-time noise elimination, and real-time quality monitoring and analysis of vector processing engine.

[0142] In the solution of the present invention, through real-time signal shaping, real-time receiving decoding and real-time encoding, the quality of the communication channel is analyzed and monitored in real time, while also greatly reducing the requirements on the MCU computing power performance, freeing up the MCU performance to handle more complex applications.

[0143] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0144] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0147] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A long distance communication and verification method for a power line host communication core chip architecture, characterized in that: The method includes: Setting four links, which are communication links for parallel data computing and processing, namely a sending link, a receiving link, a quality link and a software link; The transmission link is responsible for filling the data to be transmitted into the transmission buffer module, generating high, medium and low level controller signals in the transmission link and sending them to the pulse width modulation module; The pulse width modulation module generates L+ power supply signals of three voltage sources, high, medium and low, online according to the controller signals (BUS_H, BUS_M, BUS_L) of three levels; The voltage sampling value of the slave sampling current and the voltage sampling value between the L+ terminal and the L- terminal are collected in real time, and are transmitted to the local ADC data cache module after low-pass filtering and AD conversion are completed by the low-pass filter module and the high-speed and high-precision ADC module in turn, and quality control is completed by the quality link; The receiving link is responsible for receiving the data collected by the high-speed and high-precision ADC. A noise elimination module and a signal shaping module are set in the receiving link to process the acquired data and decode and store it in the receiving buffer module; The data is read in the cache module and decoded and analyzed by the single-chip microcomputer, specifically including: the MCU subsystem module uses a software program to process and decode the data in the receiving cache module and the local ADC data cache module; when the software decoding is inconsistent with the hardware result of the receiving link, the data is deleted; The quality link is responsible for analyzing the original ADC data in the local ADC data cache module. The quality control specifically includes: Collect the voltage sampling value of the slave sampling current in real time, calculate the noise density, time domain transformation, frequency domain transformation, spectrum analysis and signal distortion curve; Collect the voltage sampling values ​​of the L+ and L- terminals in real time, monitor and calculate the amplitudes of the high, medium and low level signals actually sent, and whether there are any abnormalities in the communication link; The quality levels of different channels are obtained and stored in the local ADC data cache module.

2. The long distance communication and verification method of the power line host communication core chip architecture as claimed in claim 1, characterized in that: The pulse width modulation module generates L+ power supply signals of three voltage sources, high, medium and low, online according to the controller signals of three levels (BUS_H, BUS_M, BUS_L), specifically including: When the controller signal (BUS_H) of pulse modulation and current sampling to a high level is 1, the corresponding multiple sets of parallel NMOS tubes are turned on to enable the high-level voltage source VCC_H to be output to the L+ power line, wherein the multiple sets of parallel NMOS tubes are part of the pulse width modulation module; When the high-level controller signal (BUS_H) of pulse modulation and current sampling is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the high-level voltage source VCC_H is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the medium-level and low-level controller signals; When the controller signal (BUS_M) of the pulse modulation and current sampling is 1, the corresponding multiple sets of parallel NMOS tubes are turned on to enable the output of the medium-level voltage source VCC_M to the L+ power line; When the pulse modulation and current sampling controller signal (BUS_M) of the middle level is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the middle level voltage source VCC_M is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high level and low level controller signals; When the pulse modulation and current sampling controller signal (BUS_L) of the low level is 1, the corresponding multiple groups of parallel NMOS tubes are turned on to enable the low level voltage source to be output to the L+ power line, wherein the low level voltage source is the ground potential; When the pulse modulation and current sampling low-level controller signal (BUS_L) is 0, the corresponding multiple sets of parallel NMOS tubes are turned off, and the low-level voltage source is prohibited from being output to the L+ power line. At this time, the L+ power signal is determined by the high-level and medium-level controller signals.

3. The long distance communication and verification method of the power line host communication core chip architecture as claimed in claim 1, characterized in that: The receiving link is provided with a noise elimination module and a signal shaping module, which processes the acquired data and decodes and stores them in the receiving buffer module, specifically including: A noise elimination module is provided in the receiving link, and the noise elimination module suppresses and eliminates the interference of electromagnetic radiation in the external harsh environment in real time; Use signal shaping and equalization technology to determine whether the signal frequency is distorted. If it is distorted, it will automatically compensate for the information. Determine whether the signal waveform is distorted. If it is distorted, it will automatically compensate for the signal. The signal after signal shaping is decoded and stored in the receiving buffer module.

4. The long distance communication and verification method of the power line host communication core chip architecture as claimed in claim 1, characterized in that: The controller signals of three levels, high, medium and low, are generated in the transmission link and sent to the pulse width modulation module, specifically including: After being unpacked by the Frame packet module, CRC check is inserted and converted into a serial bit code stream; Manchester encoding is performed on the serial bit code stream through a pulse encoding module and a frame start and frame end mark is inserted; A basic pulse width generating module is set to generate high, medium and low level controller signals according to the internal timer and the control signal received from the pulse encoding module.

5. A long distance communication and verification system based on a power line host communication core chip architecture, characterized in that: The system is used to implement the method according to any one of claims 1 to 4, and the system comprises: A link setting module, used to set four links, wherein the four links are communication links used for parallel data calculation and processing; A receiving setting module is used to set a noise elimination module and a signal shaping module in the receiving link, process the acquired data, decode it and store it in the receiving buffer module; A transmission setting module is used to generate high, medium and low level controller signals in the transmission link and send them to the pulse width modulation module; The quality analysis module is used to collect the voltage sampling value of the slave sampling current and the voltage sampling value between the L+ terminal and the L- terminal in real time, and transmit it to the quality link after low-pass filtering and AD conversion to complete quality control; A soft analysis module, used to read data in the cache module and decode and analyze it through the microcontroller; The pulse width modulation module is used to generate L+ power supply signals of high, medium and low voltage sources online according to the controller signals of high, medium and low levels (BUS_H, BUS_M, BUS_L).

6. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: The computer program instructions implement the method according to any one of claims 1 to 4 when executed by a processor.

7. An electronic device comprising a memory and a processor, characterized in that: The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1-4.

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