Printed circuit board and electronic device

Abstract

The present disclosure provides a printed circuit board and an electronic device. The printed circuit board comprises at least two pad regions; at least two fan-out regions, each of which corresponds to one of the pad regions, and the fan-out region is arranged adjacent to the corresponding pad region; for each pad region, a row of first pads is arranged in the pad region on a first surface of the printed circuit board; wherein each row of first pads is fixedly connected to a row of pins of a connector; the connector comprises at least one row of pins; each fan-out region comprises a plurality of rows of through holes and a plurality of lead channels, and a plurality of through holes in each row of through holes are arranged in a first direction; the plurality of rows of through holes comprise a first through hole corresponding to each first pad; for each first pad, the first pad and the corresponding first through hole are connected by a first lead, and the first lead passes through a target lead channel corresponding to the pad; the first lead is arranged on the first surface, and the first lead is a curve.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the technical field of network equipment, in particular to a printed circuit board and an electronic device. BACKGROUND

[0002] In an electronic device (for example, an electronic device for network communication), different signal modules can be integrated using a printed circuit board. A connector can be used to connect the signal module with the printed circuit board, for example, pins are arranged on the connector, pads are arranged in the printed circuit board, the pins of the connector are fixedly connected with the pads of the printed circuit board, and the signal module can be plugged into the connector, so as to realize signal connection between the signal module and the printed circuit board. SUMMARY

[0003] The embodiment of the present disclosure provides a printed circuit board and an electronic device.

[0004] In a first aspect, the embodiment of the present disclosure provides a printed circuit board method, comprising: at least two pad areas, each of the pad areas extending along a first direction; at least two fan-out areas, each of the fan-out areas corresponding to one of the pad areas, and the fan-out area being arranged adjacent to the corresponding pad area; for each of the pad areas, a row of first pads is arranged in the pad area on a first surface of the printed circuit board, and a plurality of first pads in each row of the first pads are arranged along the first direction; wherein each row of the first pads is fixedly connected with a row of pins of a connector; the connector comprises at least one row of pins; each of the fan-out areas comprises a plurality of rows of through holes and a plurality of lead channels, a plurality of through holes in each row of through holes are arranged along the first direction; the plurality of rows of through holes comprise a first through hole corresponding to each of the first pads; for each of the first pads, the first pad and the corresponding first through hole are connected by a first lead, and the first lead passes through a target lead channel corresponding to the first pad; the first lead is arranged on the first surface, and the first lead is a curve; wherein the target lead channel is one of the plurality of lead channels.

[0005] In a second aspect, the embodiment of the present disclosure provides an electronic device, comprising: a printed circuit board and a connector, wherein the printed circuit board is as described in the first aspect and various possible designs of the first aspect.

[0006] The printed circuit board and electronic device provided by the embodiment include at least two pad areas, each of the pad areas extending along a first direction; at least two fan-out areas, each of the fan-out areas corresponding to one of the pad areas, and the fan-out area being arranged adjacent to the corresponding pad area; for each of the pad areas, a row of first pads is arranged in the pad area on a first surface of the printed circuit board, and a plurality of first pads in each row of the first pads are arranged along the first direction; wherein each row of the first pads is fixedly connected to a row of pins of a connector; the connector includes at least one row of pins; each of the fan-out areas includes a plurality of rows of through holes and a plurality of lead channels, a plurality of through holes in each row of through holes are arranged along the first direction; the plurality of rows of through holes include a first through hole corresponding to each of the first pads; for each of the first pads, the first pad and the corresponding first through hole are connected by a first lead, and the first lead passes through a target lead channel corresponding to the first pad; the first lead is arranged on the first surface, and the first lead is a curve; wherein the target lead channel is one of the plurality of lead channels. Through the above scheme, in the fan-out area corresponding to each pad area, the through holes corresponding to the plurality of pads of the pad area are arranged in a plurality of rows, so as to reduce the density of the through holes arranged along the first direction. A plurality of lead channels can be arranged in the fan-out area, and the fan-out lead is drawn out from the corresponding target lead channel. Since the density of the through holes distributed along the first direction is reduced, an internal signal line area extending along a second direction can be formed inside the plurality of rows of through holes, which helps to reduce the crosstalk between the signals transmitted on the signal lines. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0008] Figure 1 A top view of the printed circuit board provided by the embodiment of the present disclosure;

[0009] Figure 2 A schematic diagram of lead fan-out for a pad area and a corresponding fan-out area;

[0010] Figure 3 A schematic diagram of a first fan-out sub-area;

[0011] Figure 4 A schematic diagram of a second surface of the printed circuit board;

[0012] Figure 5A schematic view of a third fan-out sub-region;

[0013] Figure 6 A schematic view of a projection of the third pad sub-region and the third fan-out sub-region onto the first surface;

[0014] Figure 7 A schematic view of a partial structure of a fan-out region with a shielding hole;

[0015] Figure 8 A schematic view of a corresponding lead fan-out of a row of pads close to a positioning hole;

[0016] Figure 9 A schematic view of a structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0018] With the increase in the number of signal modules integrated in a printed circuit board, signal modules can be integrated on the upper surface and the lower surface of the printed circuit board, respectively. The upper surface and the lower surface of the printed circuit board can be provided with pads, respectively. The pads need to be connected to vias by fan-out leads, and the vias can be connected to signal lines in the printed circuit board. In this way, the pads and the pads are connected to the fan-out leads, the vias connected to the fan-out leads, and the signal lines connected to the vias form a signal transmission path.

[0019] In some embodiments, blind holes can be used for fan-out of the pads on the upper surface and the lower surface, respectively. That is, for the pads on the upper surface and the lower surface, one or more layers of printed circuit boards can be used to set blind holes, respectively. Fan-out leads are used to connect the pads and the blind holes, and the blind holes can be connected to signal lines, thereby forming respective signal transmission paths of the pads on the upper surface and the lower surface. Such an implementation can prevent interference between the fan-out leads on the upper surface and the lower surface.

[0020] However, because the blind hole process is complex, it increases the processing difficulty and manufacturing cost of the printed circuit board. In order to reduce the processing difficulty and manufacturing cost of the printed circuit board, the inventors hope to use through holes to complete the fan-out of leads.

[0021] However, with the increase of the connection points of the signal module, the number of pads and through holes of the pads also increases. If two surfaces corresponding to the through holes are arranged on one side of the pad in a straight-out punching manner to perform the fan-out of the lead, one or more rows of pads corresponding to the signal lines cannot pass through the internal area of the pad. Therefore, the signal lines can only be arranged on the side of each row of pads. However, for multiple rows of pads, the wiring area of the line number line is very narrow, which may cause signal crosstalk in the signal line or the problem that the signal line cannot be arranged.

[0022] To solve the above problems, the scheme provided by the embodiments of the present disclosure sets a corresponding fan-out area for each first row of pads, sets multiple rows of through holes and multiple lead channels in the fan-out area, and the fan-out leads corresponding to the multiple rows of through holes are led out through the target channels. Thus, the density of the through holes arranged in the first direction is reduced. Multiple lead channels can be arranged in the fan-out area, and the fan-out leads are led out from the corresponding target lead channels. Since the density of the through holes distributed along the first direction is reduced, the internal signal line area can be formed in the multiple rows of through holes, which helps to reduce the crosstalk between the signals transmitted on the signal lines.

[0023] Please refer to Figure 1 and Figure 2 , Figure 1 for a top view of a printed circuit board provided by the embodiments of the present disclosure. Figure 2 for a schematic diagram of the fan-out of the leads of a pad area and a corresponding fan-out area. As Figure 1 indicated, the printed circuit board 10 includes:

[0024] at least two pad areas 101, each of which extends along a first direction;

[0025] at least two fan-out areas 102, each of which corresponds to one pad area 101, and the fan-out area 102 is arranged adjacent to the corresponding pad area 101;

[0026] for each pad area 101, a row of first pads is arranged in the pad area on the first surface of the printed circuit board 10, and multiple first pads 1011 in each row of first pads are arranged along the first direction; wherein each row of first pads is fixedly connected to a row of pins of a connector; the connector includes at least one row of pins;

[0027] each fan-out area 102 includes multiple rows of through hole areas (such as row 1, row 2, and row 3 in Figure 2 ) and multiple lead channels, multiple through holes in each row of through hole areas are arranged along the first direction; the through holes in the multiple rows of through hole areas include first through holes 1012 corresponding to each first pad 1011;

[0028] For each first pad 1011, the first pad 1011 is connected with a corresponding first via 1012 by a first lead 1013, the first lead 1013 passing through a target lead channel corresponding to the first pad; the first lead 1013 is disposed on the first surface, and the first lead 1013 is a curve; the target lead channel is one of the plurality of lead channels 105.

[0029] In the embodiment, the printed circuit board can be divided into at least two pad regions 101 and at least two fan-out regions 102. The pad regions are used to dispose a plurality of pads. The pads can be rectangular pads extending along the second direction, for example. A plurality of rows of first vias 1012 can be disposed in the fan-out regions 102.

[0030] The printed circuit board can include a first surface, a second surface, and a plurality of layers of printed circuit boards disposed between the first surface and the second surface. The different layers of printed circuit boards can bury signal lines.

[0031] The pad regions of the printed circuit board can be provided with pads for connecting with any connectors. The connectors include one of the following types of connectors: radio frequency connectors, fiber interface connectors, power connectors, etc. In some application scenarios, the connectors can be fiber interface connectors. The fiber interface connectors are used to connect optical modules with the printed circuit board.

[0032] In some embodiments, the at least two pad regions 101 are arranged along the second direction, and the first direction is perpendicular to the second direction.

[0033] Each pad region 101 includes a row of first pads 1011 disposed on the first surface.

[0034] In these embodiments, the printed circuit board can be provided with at least two pad regions 101 arranged along the second direction, and each pad region 101 can include a plurality of pads 1011 arranged along the first direction.

[0035] The first pads 1011 of each pad region 101 of the at least two pad regions arranged along the second direction are used to connect with pins of the connectors. The connectors can include at least one row of pins. The printed circuit board can be provided with pads for connecting with the pins of the plurality of connectors.

[0036] The connectors can be four-channel connectors, eight-channel connectors (Octagon Small Form-factor Pluggable, OSFP).

[0037] In the embodiment, at least two pad areas 101 can be provided in the first surface of the printed circuit board, and each of the pad areas 101 is provided with a row of first pads. The first vias 1012 provided in the fan-out area 102 of the first surface correspond to the first pads 1011 one by one. For each first pad 1011, a first lead 1013 between the first pad 1011 and the corresponding first via 1012 is provided in the first surface. The first lead can be provided as a curve. Providing the first lead as a curve can reduce the interference between the first lead and the signals transmitted by other signal lines.

[0038] In the embodiment, in order to use the vias as lead fan-out vias to reduce the manufacturing complexity of the printed circuit board and reduce the cost, and in order to enable the signal lines inside the multiple rows of first pads to be led out from the pad inner area, in the scheme, in the fan-out area corresponding to each pad area, the vias corresponding to the multiple pads of the pad area are provided in multiple rows, and the density of the vias arranged in the first direction is reduced. Multiple lead channels can be provided in the fan-out area, and the fan-out leads are led out from the corresponding target lead channels. Due to the reduced density of the vias distributed along the first direction, the internal signal line area extending along the second direction can be formed inside the multiple rows of vias, which helps to reduce the crosstalk between the signals transmitted by the signal lines.

[0039] In some embodiments, please continue to combine Figure 1 and Figure 2 For each pad area 101, the pad area 101 includes a first pad sub-area 1010 and a second pad sub-area 1010', and the fan-out area 102 corresponding to the pad area 101 includes a first fan-out sub-area 103 and a second fan-out sub-area 104, wherein,

[0040] The distribution of the first pads in the first pad sub-area 1010 is mirror-symmetric to the distribution of the first pads in the second pad sub-area 1010'.

[0041] The distribution of the lead channels in the first fan-out sub-area 103 and the first leads 1013 in the lead channels are mirror-symmetric to the distribution of the lead channels in the second fan-out sub-area 104 and the first leads 1013 in the lead channels.

[0042] For each pad area 101, the first pad sub-area 1010 and the second pad sub-area 1010' in the pad area 101 are symmetric about the center line of the pad area 101. The distribution of the first pads in the first pad sub-area 1010 is mirror-symmetric to the distribution of the first pads in the second pad sub-area 1010', for example, mirror-symmetric about the center line of the pad area.

[0043] In the embodiments, by arranging the first pad sub-area and the second pad sub-area through the pad area, mirroring the distribution of the first pads in the first pad sub-area and the distribution of the first pads in the second pad sub-area, and mirroring the first leads in the first fan-out sub-area and the second fan-out sub-area, the process complexity of the printed circuit board can be further simplified, and the manufacturing cost of the printed circuit board can be reduced.

[0044] In some embodiments, the first fan-out sub-area includes a first lead channel, a second lead channel, and a third lead channel, wherein,

[0045] The first lead channel is located at the center of the first area, and the second lead channel and the third lead channel are located at two edge areas of the first area;

[0046] The width of the second lead channel and the width of the third lead channel are smaller than the width of the first lead channel.

[0047] Please continue to refer to Figure 3 , Figure 3 The first fan-out sub-area is shown in FIG. 10. The first fan-out sub-area 103 includes a first lead channel 1051 located at the center area of the first fan-out sub-area 103, and a second lead channel 1052 and a third lead channel 1053 located at two edge areas of the first fan-out sub-area 103 extending in the second direction. The width of the second lead channel 1052 and the third lead channel 1053 is smaller than the width of the first lead channel 1051.

[0048] In the embodiments, since the width of the first lead channel is greater than the width of the second lead channel and the third lead channel, no via hole is arranged in the first lead channel, so that the fan-out lead can be arranged in the first lead channel, and the signal line, such as the signal line arranged in different printed circuit board layers, etc. can also be arranged in the first lead channel. The interference between the fan-out leads and the interference between the signal lines can be reduced.

[0049] In some embodiments, the first pad sub-area includes a first group of first pads, a second group of first pads, a third group of first pads, and a fourth group of first pads arranged in the first direction;

[0050] The second lead channel 1052 includes a first sub-channel 10521, a second sub-channel 10522, and a third sub-channel 10523, wherein the first sub-channel 10521 is composed of a blank area between the first group of first pads group 1 and the area 10121 where the row of first vias adjacent to the first pad sub-area;

[0051] The second sub-channel 10522 is composed of the first edge area of the first fan-out sub-area extending in the second direction;

[0052] The third sub-channel 10523 is composed of the blank area between the first via area 10123 corresponding to the first pad group 1 and the via area 10122 adjacent to the first via group corresponding to the first pad group 1, wherein the first sub-channel and the third sub-channel extend along the first direction.

[0053] The first pads in the first pad sub-area 1010 are divided into groups, such as the first pad group 1, the second pad group 2, the third pad group 3, and the fourth pad group 4 arranged along the first direction. Each group of pads is used to connect with a pair of differential signal pins of the connector. The first vias corresponding to each group of first pads include a group of first vias. The groups of first vias can be located in different rows. The groups of first vias are staggered.

[0054] In these embodiments, the first edge area of the first fan-out sub-area can be used to form the second lead channel, the fan-out leads corresponding to the first pad group 1 can be arranged in the first edge area, the density of the fan-out leads can be reduced, and the interference between signals can be reduced.

[0055] In some embodiments, the first lead channel is used to arrange the first leads corresponding to the second pad group 2.

[0056] In these embodiments, the first lead channel 1051 is located at the center of the first fan-out sub-area, and the first lead channel 1051 is used to arrange two first leads corresponding to the second pad group 2. In addition, the first lead channel 1051 can also be used to arrange the fan-out leads on the first surface.

[0057] In some embodiments, the third lead channel 1053 includes a fourth sub-channel 10531, a fifth sub-channel 10532, and a sixth sub-channel 10533, wherein,

[0058] The fourth sub-channel 10531 is composed of the blank area between the fourth pad group 4 and the via area 10121 adjacent to the first pad sub-area;

[0059] The fifth sub-channel is composed of the second edge area of the first fan-out sub-area extending along the second direction; here, the second edge area is the right edge area of the first fan-out sub-area.

[0060] The sixth sub-channel 10533 is composed of the blank area between the via area 10122 corresponding to the fourth pad group 4 and the via area 10121 adjacent to the first via group corresponding to the fourth pad group 4.

[0061] In the embodiments, the third lead channel can be formed by using the second edge region of the first fan-out sub-region, the fourth group of first pads can be connected to the fan-out leads in the second edge region, the density of the fan-out leads can be reduced, and the interference between signals can be reduced.

[0062] In some embodiments, the plurality of rows of through holes arranged on one side of the first pad sub-region includes a first row of through holes (row 1), a second row of through holes (row 2), and a third row of through holes (row 3) arranged in the first fan-out sub-region 103, wherein the distances between the first row of through holes (row 1), the second row of through holes (row 2), and the third row of through holes (row 3) and the pad region increase in turn.

[0063] The first through hole corresponding to the first group of pads 1 is located in the third row of through holes (row 3) and adjacent to the first edge region.

[0064] The first lead connecting the first group of first pads (group 1) and the corresponding first through hole is a first curve, and the first curve is located in the second lead channel. The first through hole corresponding to the first group of first pads (group 1) is located in the third row of through holes and adjacent to the first edge region.

[0065] For each pad region 101, a corresponding fan-out region 102 can be arranged on one side of the pad region. The plurality of rows of through holes arranged in the fan-out region 102 in the second direction includes a first row of through holes (row 1), a second row of through holes (row 2), and a third row of through holes (row 3).

[0066] The first through hole corresponding to the second group of first pads group 2 is located in the third row of through holes (row 3).

[0067] The first lead connecting the second group of first pads group 2 and the corresponding first through hole is a second curve, and the second curve is located in the first lead channel.

[0068] The first through hole corresponding to the third group of first pads group 3 is located in the first row of through holes (row 1), and the first lead between the third group of first pads group 3 and the corresponding first through hole is arranged in the region between the first row of through holes and the third group of first pads.

[0069] The first through hole corresponding to the fourth group of first pads group 4 is located in the second row of through holes (row 2).

[0070] The first lead connecting the fourth group of first pads group 4 and the corresponding first through hole is a third curve, and the third curve is located in the third lead channel.

[0071] The first curve, the second curve, and the third curve are not parallel to each other.

[0072] In the embodiments, the plurality of first pads in the first pad sub-area are divided into a plurality of groups, and each group of first pads is arranged with a group of first through holes. Each first pad in each group of first pads can be connected with the corresponding first through hole through a first lead. The first leads corresponding to each first pad in each group of first pads can be parallel to each other.

[0073] The first leads between different groups of first pads and the corresponding first through holes are not parallel to each other. The interference of signals transmitted on the first leads corresponding to different groups of first pads can be reduced.

[0074] By arranging the corresponding positions of the first through holes corresponding to each group of first pads and arranging the lead channels of the first leads connected between each group of first pads and the corresponding first through holes, the lead fan-out of each group of first pads can be reasonably configured, the number of through holes distributed along the first direction can be reduced, the internal transmission of the signal lines through each row of pads can be realized, the lead fan-out through the through holes in the printed circuit board can be realized, the manufacturing process complexity of the printed circuit board can be reduced, and the cost of the printed circuit board can be reduced.

[0075] The following will be described in conjunction with Figure 1 , Figure 4 , Figure 4 A schematic view of the second surface of the printed circuit board is shown. The second surface of the printed circuit board 10 includes a plurality of pad areas 201 arranged along a first direction, and each pad area 201 is arranged with a fan-out area 202 on one side of the pad area. Each pad area 201 corresponds to a fan-out area 202 including a plurality of lead channels and a plurality of rows of through holes. On the first surface of the printed circuit board, each pad area is arranged with a row of a plurality of first pads arranged along the first direction.

[0076] The plurality of rows of through holes of the printed circuit board include a plurality of first through holes corresponding one-to-one to the first pads. The plurality of first through holes are located in different rows. The first through holes are connected with the corresponding first pads through first leads to complete the fan-out of the first pads.

[0077] The plurality of rows of pads on the first surface can be used to connect with a plurality of connectors.

[0078] In order to improve the carrying capacity of the connector, so as to connect more signal modules to the printed circuit board.

[0079] On the second surface of the printed circuit board, for each pad area 201, a row of second pads 2011 is arranged in the pad area on the second surface of the printed circuit board, and a plurality of second pads in each row of second pads are arranged along the first direction; wherein each row of second pads 2011 is fixedly connected with a row of pins of a connector; and the connector includes at least two rows of pins.

[0080] Each fan-out region 202 includes a plurality of second vias in the plurality of rows of through holes, and each second via corresponds to each second pad;

[0081] Each fan-out region includes a plurality of lead channels on the second surface, and for each second pad, the second pad is connected with a corresponding second via by a second lead, and the second lead passes through a target lead channel in the corresponding second surface of the second pad; the second lead is arranged on the second surface, and the second lead is a curve; wherein each lead channel in the second surface corresponds to a lead channel on the first surface, and the projection of the lead channel in the second surface on the first surface coincides with the corresponding lead channel on the first surface.

[0082] In the embodiment, each row of second pads is used for fixed connection with a row of pins of a connector. The fixed connection can be welding, for example.

[0083] For each pad region 201, a fan-out region 202 is arranged on the second surface on the side of the pad region 201. The fan-out region 202 includes a third fan-out sub-region 203 and a fourth fan-out sub-region 204 which are symmetrical. The projections of the third fan-out sub-region 203 and the fourth fan-out sub-region 204 on the first surface respectively coincide with the first fan-out sub-region 103 and the second fan-out sub-region 104.

[0084] Each pad region 201 can include a third pad sub-region 2010 and a fourth pad sub-region 2010' which are symmetrical on the second surface. The projection of the third pad sub-region on the first surface coincides with the first pad sub-region 1010 in the pad region, and the projection of each second pad in the third pad sub-region on the first surface coincides with the corresponding first pad in the first pad sub-region. The projection of the fourth pad sub-region 2010' on the first surface coincides with the second pad sub-region 1010' in the pad region, and each second pad in the fourth pad sub-region coincides with the corresponding first pad in the second pad sub-region 1010'.

[0085] For each pad region 201, the corresponding fan-out region 202 in the second surface of the pad region 201 includes a third fan-out sub-region 203 and a fourth fan-out sub-region 204 which are symmetrical, and the projections of the third fan-out sub-region 203 and the fourth fan-out sub-region 204 on the first surface respectively coincide with the first fan-out sub-region 103 and the second fan-out sub-region 104. Since the third fan-out sub-region and the fourth fan-out sub-region are symmetrical, the third fan-out sub-region can be used for description. As shown in Figure 5 , Figure 5 a schematic view of the third fan-out sub-region is shown. The third fan-out sub-region 203 includes a plurality of rows of through holes, such as a first row of through holes row 1, a second row of through holes row 2 and a third row of through holes row 3, and each row of through holes includes a plurality of second vias 2012.

[0086] In the second surface, for each third fan-out sub-region 203, the third fan-out sub-region 203 comprises a fourth lead channel, a fifth lead channel and a sixth lead channel, wherein the fourth lead channel, the fifth lead channel and the sixth lead channel correspond to the first lead channel, the second lead channel and the third lead channel in the first fan-out sub-region of the first surface respectively. Accordingly, the fourth lead channel is located at the center of the third fan-out sub-region. The fifth lead channel is located at the first edge of the third fan-out sub-region, and the sixth lead channel is located at the second edge of the third fan-out sub-region. The lead channels are arranged in the same region on different surfaces, which on one hand can simplify the manufacturing process of the printed circuit board, and on the other hand the same region is used as the lead channel on the first surface and the second surface, so that there is no via hole in these regions, which is beneficial to arranging signal lines and fan-out leads in these regions.

[0087] In some embodiments, each pad region comprises a third pad sub-region 2010 and a fourth pad sub-region 2010’ which are symmetrical in the second surface;

[0088] The plurality of second pads in each third pad sub-region 2010 are divided into a first group of second pads, a second group of second pads, a third group of second pads and a fourth group of second pads arranged along a first direction, wherein,

[0089] The projection of the second lead connected between the first group of second pads and the corresponding second via hole to the first surface is mirror-symmetrical to the first lead connected between the fourth group of first pads and the corresponding first via hole;

[0090] The projection of the second lead connected between the fourth group of second pads and the corresponding second via hole to the first surface is mirror-symmetrical to the first lead connected between the first group of first pads and the corresponding first via hole.

[0091] In each row of vias, the first vias and the second vias are arranged alternately. As Figure 6 shown, Figure 6 is a schematic view of the projection of the third pad sub-region and the third fan-out sub-region to the first surface. The shaded ones are the first vias, and the unshaded ones are the second vias. In each row of vias, each group of first vias and each group of second vias are arranged alternately. This can avoid signal crosstalk in the leads in the same surface.

[0092] As Figure 5 shown, the first group of second pads, the second group of second pads, the third group of second pads and the fourth group of second pads are Figure 5 group 5, group 6, group 7 and group 8 respectively. Each group of second pads can comprise at least one second pad. For example, it comprises 2 second pads.

[0093] The projections of the first group of second pads (group 5), the second group of second pads (group 6), the third group of second pads (group 7) and the fourth group of second pads (group 8) on the first surface coincide with the first group of first pads (group 1), the second group of second pads (group 2), the third group of second pads (group 3) and the fourth group of first pads (group 4) respectively, as shown in FIG. 10. Figure 6 That is, the first pads on the first surface and the second pads on the second surface in the pad area can be arranged at the same position of the pad area.

[0094] The projection 2061 of the second leads between the first group of second pads (group 5) and the corresponding second vias on the first surface is mirror-symmetrical to the first leads 1063 between the fourth group of first pads (group 4) and the corresponding first vias.

[0095] The projection 2063 of the second leads between the fourth group of second pads (group 8) and the corresponding second vias on the first surface is mirror-symmetrical to the first leads 1061 between the first group of first pads (group 1) and the corresponding first vias.

[0096] By mirror-symmetrical arrangement of the second leads corresponding to the first group of second pads and the first leads corresponding to the fourth group of first pads, and mirror-symmetrical arrangement of the second leads corresponding to the fourth group of second pads and the first leads corresponding to the first group of first pads, the manufacturing process complexity of the printed circuit board can be further reduced.

[0097] In addition, the second leads between the third group of second pads (group 7) and the corresponding second vias are fourth curves, and the fourth curves are located in the fourth lead channel,

[0098] The projection 2062 of the fourth curves on the first surface is not coincident with the second curve 1062, and has a different extension direction from the second curve.

[0099] That is, the fourth curves and the second curve 1062 are both arranged in the center of the fan-out area. In order to avoid signal interference, the fourth curves and the second curve can be arranged in different extension directions.

[0100] In some embodiments, each row of multiple vias includes multiple groups of first vias and multiple groups of second vias, each group of first vias and each group of second vias, and different groups of first vias and different groups of second vias are shielded by multiple ground holes.

[0101] Please refer to Figure 7 , Figure 7 for a partial structure diagram of the fan-out area with shielded holes. Figure 7 It can be a structure diagram of the first fan-out sub-area, and the other fan-out sub-areas are similar. In Figure 7 , a ground shield hole 107 can be used for two adjacent groups of vias 1012 or 2012 in the first fan-out area.

[0102] In order to save the area occupied by the ground shielding hole 107, in the first row of through holes (row 1) and the second row of through holes (row 2), a plurality of ground shielding holes 107 arranged in a C shape are arranged for each group of through holes.

[0103] In the third row of through holes, a plurality of rows of ground shielding holes 107 arranged in the vertical direction can be used to achieve better shielding effect.

[0104] In some embodiments, each group of first through holes and each group of second through holes respectively include 2 differential lead through holes for transmitting differential signals.

[0105] In these embodiments, a group of first pads corresponding to each group of first through holes can include 2 first pads, and a group of second pads corresponding to each group of second through holes can include 2 second pads. Each group of first pads is connected to a pair of differential signal output pins of a connector. Each group of second pads is respectively connected to a pair of differential signal output pins of a connector. It can be understood that the two pads in each group of first pads respectively correspond to first leads transmitting differential signals, and the two first leads can be parallel to each other to achieve better differential signal transmission effect. Similarly, the two pads in each group of second pads respectively correspond to second leads which are parallel to each other.

[0106] In some embodiments, please refer to Figure 8 , Figure 8 The lead fan-out diagram corresponding to the row of pads close to the positioning hole.

[0107] For the row of first pads close to the positioning hole 30, the lead channel and the plurality of rows of through holes can be set by using the shape of the positioning hole and the fan-out area of the row of pads.

[0108] The pad area can include a symmetrical first pad sub-area and a second pad sub-area. Take the first pad sub-area 1010 as an example for illustration.

[0109] The plurality of first pads in the first pad sub-area 1010 are divided into a first group of first pad group 1, a second group of first pad group 2, a third group of first pad group 3, and a fourth group of first pad group 4. The first fan-out sub-area 103 corresponding to the first pad sub-area is arranged on the side of the row of first pads away from other rows of pads.

[0110] The corresponding first fan-out sub-area 103 can be provided with a plurality of rows of through holes (such as the through holes shown in row 1, row 2, and row 3), and the plurality of rows of through holes include first through holes. The lead channel in the fan-out area 102 can include a seventh lead channel 108 close to the positioning hole, and an eighth lead channel 109 arranged in the middle of the first fan-out sub-area 103.

[0111] The first group of first pads (group 1) in the row of first pads correspond to first leads that use the blank area between the row of pads and the positioning hole for routing.

[0112] The second group of first pads (group 2) can set first leads through the seventh lead channel 108, and the first via corresponding to the second group of first pads can be arranged in the third row of vias (row 3).

[0113] The third group of first pads (group 3) in the row of first pads correspond to first leads that use the blank area between the row of pads and the via area for routing.

[0114] The fourth group of first pads (group 4) can set first leads through the eighth lead channel 109, and the first via corresponding to the fourth group of first pads can be arranged in the third row of vias (row 3).

[0115] Please refer to Figure 9 , Figure 9 The schematic structural diagram of an electronic device provided by the embodiments of the present disclosure is shown. The electronic device includes a printed circuit board 91 and a connector 92. Wherein, the printed circuit board 91 can be a printed circuit board as shown in the embodiment shown in Figures 1-8 . Wherein, the connector 92 can be a multi-channel connector. A plurality of first pads 1011 can be arranged in the first surface 911 of the printed circuit board 91, and a second pad 2011 can be arranged in the second surface 912 of the printed circuit board 91. The first pad 1011 can be connected with the pin of the connector 92 corresponding to the first surface, and the second pad 2011 can be connected with the pin of the connector 92 corresponding to the second surface. The technical solutions of the present scheme are described as follows:

[0116] In a first aspect, according to one or more embodiments of the present disclosure, a printed circuit board is provided, comprising:

[0117] At least two pad regions, each pad region extending along a first direction;

[0118] At least two fan-out regions, each fan-out region corresponding to one pad region, and the fan-out region being arranged adjacent to the corresponding pad region;

[0119] For each pad region, a row of first pads is arranged in the pad region of the first surface of the printed circuit board, and a plurality of first pads in each row of first pads are arranged along the first direction; wherein each row of first pads is fixedly connected with a row of pins of a connector; the connector includes at least one row of pins;

[0120] Each fan-out region includes a plurality of rows of vias and a plurality of lead channels, a plurality of vias of each row of vias are arranged along the first direction; the plurality of rows of vias include a first via corresponding to each first pad;

[0121] For each first pad, the first pad is connected with a corresponding first via by a first lead, the first lead passing through a target lead via corresponding to the first pad; the first lead is arranged on the first surface, and the first lead is a curve; wherein the target lead via is one of the plurality of lead vias.

[0122] According to one or more embodiments of the present disclosure, the at least one pad region comprises a plurality of pad regions arranged along a second direction, the first direction being perpendicular to the second direction;

[0123] Each pad region comprises a row of first pads arranged on the first surface.

[0124] According to one or more embodiments of the present disclosure, for each pad region, the pad region comprises a first pad sub-region and a second pad sub-region, the fan-out region corresponding to the pad region comprises a first fan-out sub-region and a second fan-out sub-region, wherein,

[0125] The distribution of the first pads in the first pad sub-region is mirror-symmetric to the distribution of the first pads in the second pad sub-region; and

[0126] The distribution of the lead vias in the first fan-out sub-region and the first lead in the lead vias is mirror-symmetric to the distribution of the lead vias in the second fan-out sub-region and the first lead in the lead vias.

[0127] According to one or more embodiments of the present disclosure, the first fan-out sub-region comprises a first lead via, a second lead via and a third lead via, wherein,

[0128] The first lead via is located at the center of the first fan-out sub-region, and the second lead via and the third lead via are located at two edge regions of the first fan-out sub-region;

[0129] The width of the second lead via and the width of the third lead via are smaller than the width of the first lead via.

[0130] According to one or more embodiments of the present disclosure, the first pad sub-region comprises a first group of first pads, a second group of first pads, a third group of first pads and a fourth group of first pads arranged along the first direction;

[0131] The second lead via comprises a first sub-via, a second sub-via and a third sub-via, wherein the first sub-via is composed of a blank area between the first group of first pads and the area where a row of vias adjacent to the first pad sub-region are located;

[0132] The second sub-via is composed of a first edge region of the first fan-out sub-region extending along the second direction;

[0133] The third sub-channel is composed of a blank area between a region where a first group of first vias corresponding to the first group of first pads is located and a region where a row of vias adjacent to the first group of first vias is located; the first sub-channel and the third sub-channel extend along the first direction.

[0134] According to one or more embodiments of the present disclosure, the third lead channel includes a fourth sub-channel, a fifth sub-channel, and a sixth sub-channel, wherein,

[0135] The fourth sub-channel is composed of a blank area between the fourth group of first pads and a region where a row of vias adjacent to the first pad sub-region is located;

[0136] The fifth sub-channel is composed of a second edge region of the first fan-out sub-region extending along the second direction;

[0137] The sixth sub-channel is composed of a blank area between a region where a first group of first vias corresponding to the fourth group of first pads is located and a region where a row of vias adjacent to the first group of first vias is located.

[0138] According to one or more embodiments of the present disclosure, the first lead channel is used to set a first lead corresponding to the second group of first pads.

[0139] According to one or more embodiments of the present disclosure, the multiple rows of vias arranged on one side of the first pad sub-region include a first row of vias, a second row of vias, and a third row of vias arranged in the first fan-out sub-region, wherein the distances between the first row of vias, the second row of vias, and the third row of vias and the pad region increase in turn;

[0140] The first via corresponding to the first group of first pads is located in the third row of vias and adjacent to the first edge region,

[0141] The first lead connecting the first group of first pads and the corresponding first via is a first curve, and the first curve is located in the second lead channel.

[0142] According to one or more embodiments of the present disclosure, the first via corresponding to the second group of first pads is located in the third row of vias;

[0143] The first lead connecting the second group of first pads and the corresponding first via is a second curve, and the second curve is located in the first lead channel.

[0144] According to one or more embodiments of the present disclosure, the first via corresponding to the third group of first pads is located in the first row of vias, and the first lead between the third group of first pads and the corresponding first via is arranged in a region between the first row of vias and the third group of first pads.

[0145] According to one or more embodiments of the present disclosure, the first via corresponding to the fourth group of first pads is located in the second row of vias;

[0146] The first lead wire connecting the fourth group of first pads and the corresponding first through hole is a third curve, and the third curve is located in the third lead wire channel.

[0147] According to one or more embodiments of the present disclosure, further comprising:

[0148] For each pad area, a plurality of second pads arranged in the pad area of the second surface of the printed circuit board, the plurality of second pads in each row of second pads arranged along a first direction; wherein each row of second pads is fixedly connected with a row of pins of the connector;

[0149] The plurality of rows of through holes in each fan-out area includes a second through hole corresponding to each second pad;

[0150] Each fan-out area includes a plurality of lead wire channels on the second surface, for each second pad, the second pad and the corresponding second through hole are connected by a second lead wire, and the second lead wire passes through the target lead wire channel in the second surface corresponding to the second pad; the second lead wire is arranged on the second surface, and the second lead wire is a curve; wherein each lead wire channel in the second surface corresponds to a lead wire channel in the first surface, and the projection of the lead wire channel in the second surface on the first surface coincides with the corresponding lead wire channel in the first surface.

[0151] According to one or more embodiments of the present disclosure, the projection of each second pad in each row of second pads on the first surface overlaps with the corresponding first pad in the row of first pads.

[0152] According to one or more embodiments of the present disclosure, the fan-out area in the second surface includes a third fan-out sub-area and a fourth fan-out sub-area, and the projections of the third fan-out sub-area and the fourth fan-out sub-area on the first surface respectively coincide with the first fan-out sub-area and the second fan-out sub-area.

[0153] For each third fan-out sub-area, the third fan-out sub-area includes a fourth lead wire channel, a fifth lead wire channel and a sixth lead wire channel, wherein,

[0154] The fourth lead wire channel, the fifth lead wire channel and the sixth lead wire channel respectively correspond to the first lead wire channel, the second lead wire channel and the third lead wire channel in the first fan-out sub-area of the first surface.

[0155] According to one or more embodiments of the present disclosure, each pad area includes a third pad sub-area and a fourth pad sub-area in the second surface;

[0156] The plurality of second pads in each third pad sub-area are divided into a first group of second pads, a second group of second pads, a third group of second pads and a fourth group of second pads arranged along a first direction, wherein,

[0157] The projection of the second lead connected between the second pad of the fourth group and the corresponding second via to the first surface is mirror-symmetrical to the first lead connected between the first pad of the fourth group and the corresponding first via;

[0158] The projection of the second lead connected between the second pad of the fourth group and the corresponding second via to the first surface is mirror-symmetrical to the first lead connected between the first pad of the fourth group and the corresponding first via;

[0159] The second lead connected between the second pad of the third group and the corresponding second via is a fourth curve, and the fourth curve is located in the fourth lead channel,

[0160] The projection of the fourth curve to the first surface is not coincided with the second curve, and the projection of the fourth curve to the first surface is different from the extension direction of the second curve.

[0161] According to one or more embodiments of the present disclosure, each row of the plurality of vias includes a plurality of groups of first vias and a plurality of groups of second vias, each group of first vias and each group of second vias, and different groups of first vias and different groups of second vias are shielded by a plurality of ground holes.

[0162] According to one or more embodiments of the present disclosure, each group of first vias and each group of second vias respectively includes two differential lead vias for transmitting differential signals.

[0163] In a second aspect, according to one or more embodiments of the present disclosure, an electronic device is provided, including a printed circuit board and a connector, wherein the printed circuit board is the printed circuit board of the first aspect and various possible designs.

[0164] The above description is merely preferred embodiments of the present disclosure and a description of the principles of the technology used. Those skilled in the art should understand that the disclosed scope of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combinations of the above technical features or equivalent features without departing from the above disclosed concept. For example, the above features are replaced with each other to form technical solutions with similar functions disclosed in the present disclosure (but not limited to).

[0165] Moreover, while operations are depicted in a particular order, this should not be understood as requiring such an order nor infringing on the scope of the disclosure. Certain of the operations described in the discussion are combinable into a single operation, and certain operations can be separated into several operations. In some embodiments, the operations described in the discussion can be performed in an order different than presented in the discussion. In some embodiments, the operations described in the discussion can be performed concurrently. Also, while several specific implementation details are discussed in the discussion, these should not be interpreted as limiting the scope of the disclosure. Rather, certain features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination.

[0166] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A printed circuit board, characterized by, The printed circuit board comprises: at least two pad regions, each of the pad regions extending along a first direction; at least two fan-out regions, each of the fan-out regions corresponding to one of the pad regions, and the fan-out region being arranged adjacent to the corresponding pad region; for each of the pad regions, a row of first pads is arranged in the pad region on the first surface of the printed circuit board, and a plurality of first pads in each row of the first pads are arranged along the first direction; wherein each row of the first pads is fixedly connected to a row of pins of a connector; and the connector comprises at least one row of pins; each of the fan-out regions comprises a plurality of rows of through holes and a plurality of lead channels, and a plurality of through holes in each row of the through holes are arranged along the first direction; the plurality of rows of through holes comprises a first through hole corresponding to each of the first pads; for each of the first pads, a first lead is connected between the first pad and the corresponding first through hole, and the first lead passes through a target lead channel corresponding to the first pad; the first lead is arranged on the first surface, and the first lead is a curve; wherein the target lead channel is one of the plurality of lead channels; for each of the pad regions, the pad region comprises a first pad sub-region and a second pad sub-region which are symmetrical, and the corresponding fan-out region comprises a first fan-out sub-region and a second fan-out sub-region which are symmetrical; the first fan-out sub-region comprises a first lead channel, a second lead channel and a third lead channel, wherein the first lead channel is located at the center of the first fan-out sub-region, and the second lead channel and the third lead channel are located at two edge regions of the first fan-out sub-region; the width of the second lead channel and the width of the third lead channel are smaller than the width of the first lead channel.

2. The printed circuit board of claim 1, wherein, the at least two pad regions are arranged along a second direction, and the first direction and the second direction are perpendicular to each other; each of the pad regions comprises a row of the first pads arranged on the first surface.

3. The printed circuit board of claim 1, wherein, the distribution of the first pads in the first pad sub-region is mirror-symmetrical to the distribution of the first pads in the second pad sub-region; and the distribution of the lead channels in the first fan-out sub-region is mirror-symmetrical to the distribution of the lead channels in the second fan-out sub-region; the distribution of the first leads in the lead channels in the first fan-out sub-region is mirror-symmetrical to the distribution of the first leads in the lead channels in the second fan-out sub-region.

4. The printed circuit board of claim 2, wherein, the first pad sub-region comprises a first group of first pads, a second group of first pads, a third group of first pads and a fourth group of first pads which are arranged along the first direction; the second lead channel comprises a first sub-channel, a second sub-channel and a third sub-channel, wherein the first sub-channel is composed of a blank area between the first group of first pads and an area where a row of through holes adjacent to the first pad sub-region is located; the second sub-channel is composed of a first edge region of the first fan-out sub-region extending along the second direction; and the third sub-channel is composed of a second edge region of the first fan-out sub-region extending along the second direction. The third sub-channel is composed of a blank area between a group of first via hole areas corresponding to the first group of first pads and a row of via hole areas adjacent to the group of first via holes; the first sub-channel and the third sub-channel extend along the first direction.

5. The printed circuit board of claim 4, wherein, The third lead channel includes a fourth sub-channel, a fifth sub-channel, and a sixth sub-channel, wherein, The fourth sub-channel is composed of a blank area between the fourth group of first pads and a row of via hole areas adjacent to the first pad sub-area; The fifth sub-channel is composed of a second edge area of the first fan-out sub-area extending along the second direction; The sixth sub-channel is composed of a blank area between a group of first via hole areas corresponding to the fourth group of first pads and a row of via hole areas adjacent to the group of first via holes.

6. The printed circuit board of claim 4, wherein, The first lead channel is used to set the first lead corresponding to the second group of first pads.

7. The printed circuit board of claim 6, wherein, The multiple rows of via holes arranged on one side of the first pad sub-area include a first row of via holes, a second row of via holes, and a third row of via holes arranged in the first fan-out sub-area, wherein the distances between the first row of via holes, the second row of via holes, and the third row of via holes and the pad area respectively increase in turn; The first via hole corresponding to the first group of first pads is located in the third row of via holes and is adjacent to the first edge area, The first lead connecting the first group of first pads and the corresponding first via hole is a first curve, and the first curve is located in the second lead channel.

8. The printed circuit board of claim 7, wherein, The first via hole corresponding to the second group of first pads is located in the third row of via holes; The first lead connecting the second group of first pads and the corresponding first via hole is a second curve, and the second curve is located in the first lead channel.

9. The printed circuit board of claim 7, wherein, The first via hole corresponding to the third group of first pads is located in the first row of via holes, and the first lead between the third group of first pads and the corresponding first via hole is arranged in the area between the first row of via holes and the third group of first pads.

10. The printed circuit board of claim 8, wherein, The first via hole corresponding to the fourth group of first pads is located in the second row of via holes; The first lead connecting the fourth group of first pads and the corresponding first via hole is a third curve, and the third curve is located in the third lead channel.

11. The printed circuit board according to claim 8, characterized in that, Further comprising: For each of the pad areas, a row of second pads is arranged in the pad area on the second surface of the printed circuit board, and multiple second pads in each row of second pads are arranged along the first direction; wherein each row of second pads is fixedly connected with a row of pins of the connector; Each of the fan-out areas includes multiple rows of via holes, each of which corresponds to one of the second pads; Each of the fan-out areas includes multiple lead channels on the second surface, and for each second pad, the second pad and the corresponding second via hole are connected by a second lead, and the second lead passes through a target lead channel in the second surface corresponding to the second pad; the second lead is arranged on the second surface, and the second lead is a curve; wherein each lead channel in the second surface corresponds to one lead channel in the first surface.

12. The printed circuit board of claim 11, wherein, The projection of each second pad in each row of second pads onto the first surface overlaps with a corresponding first pad in a row of first pads.

13. The printed circuit board of claim 12, wherein, The fan-out region in the second surface includes a third fan-out sub-region and a fourth fan-out sub-region which are symmetrical, and the projections of the third fan-out sub-region and the fourth fan-out sub-region onto the first surface respectively coincide with the first fan-out sub-region and the second fan-out sub-region; For each third fan-out sub-region, the third fan-out sub-region includes a fourth lead channel, a fifth lead channel and a sixth lead channel, wherein, The fourth lead channel, the fifth lead channel and the sixth lead channel respectively correspond to the first lead channel, the second lead channel and the third lead channel in the first fan-out sub-region of the first surface.

14. The printed circuit board of claim 12, wherein, Each pad region includes a third pad sub-region and a fourth pad sub-region which are symmetrical in the second surface; The second pads in each third pad sub-region are divided into a first group of second pads, a second group of second pads, a third group of second pads and a fourth group of second pads arranged along a first direction, wherein, The projection of the second lead connected between the first group of second pads and the corresponding second via onto the first surface is mirror-symmetrical to the first lead connected between the fourth group of first pads and the corresponding first via; The projection of the second lead connected between the fourth group of second pads and the corresponding second via onto the first surface is mirror-symmetrical to the first lead connected between the first group of first pads and the corresponding first via; The second lead connected between the third group of second pads and the corresponding second via is a fourth curve, and the fourth curve is located in the fourth lead channel, The projection of the fourth curve onto the first surface does not overlap with the second curve, and the projection direction of the fourth curve is different from the projection direction of the second curve.

15. The printed circuit board according to any one of claims 1-14, wherein, Each row of vias includes a plurality of groups of first vias and a plurality of groups of second vias, and each group of first vias and each group of second vias are shielded by a plurality of ground holes from each other and from different groups of first vias and different groups of second vias.

16. The printed circuit board of claim 15, wherein, Each group of first vias and each group of second vias respectively include two differential lead vias for transmitting differential signals.

17. An electronic device comprising a printed circuit board and a connector, wherein, The printed circuit board is the printed circuit board according to any one of claims 1-16.

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