Semiconductor device including channel layer

Abstract

A semiconductor device includes: a bit line extending in a first direction; a word line extending in a second direction crossing the first direction, the word line being at a higher level than a level of the bit line; a channel layer on the bit line, the channel layer including a vertical portion at least partially at the same level as the word line and an extension portion extending from an upper region of the vertical portion; a gate dielectric layer at least partially between the vertical portion and the word line; and an upper conductive pattern on the extended portion, in which the extended portion includes a first region vertically overlapping the vertical portion and a second region not vertically overlapping the vertical portion, and the upper conductive pattern has a side surface vertically aligned with a side surface of the extended portion.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device including a channel layer. Background Art

[0002] Consideration has been given to reducing the size of elements constituting semiconductor devices and improving the performance thereof. Summary of the invention

[0003] An embodiment can be achieved by providing a semiconductor device comprising: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction, the word line being at a level higher than that of the bit line; a channel layer on the bit line, the channel layer comprising a vertical portion and an extension portion, the vertical portion being at least partially at the same level as the word line, the extension portion extending from an upper region of the vertical portion; a gate dielectric layer at least partially between the vertical portion and the word line; and an upper conductive pattern on the extension portion, wherein the extension portion comprises a first region vertically overlapping with the vertical portion and a second region not vertically overlapping with the vertical portion, and the upper conductive pattern has a side surface vertically aligned with a side surface of the extension portion.

[0004] An embodiment can be achieved by providing a semiconductor device including: a bit line; a first channel layer and a second channel layer, which are spaced apart from each other on the bit line; a first word line and a second word line, which are spaced apart from each other on the bit line and respectively include portions between the first channel layer and the second channel layer; an intermediate layer, which is connected to the first channel layer and the second channel layer and the bit line; a first gate dielectric layer, which is at least partially between the first channel layer and the first word line; a second gate dielectric layer, which is at least partially between the second channel layer and the second word line; a first upper conductive pattern, which is on the first channel layer and connected to the first channel layer; and a second upper conductive pattern, which is on the second channel layer and connected to the second channel layer.

[0005] Embodiments may be implemented by providing a semiconductor device, the semiconductor device comprising: a bit line; an insulating structure on the bit line and having an opening exposing the bit line; a structure at least partially in the opening; and an upper conductive pattern on the structure, wherein the structure comprises: a first channel layer and a second channel layer spaced apart from each other in the opening; a first word line and a second word line spaced apart from each other in the opening and respectively including a portion between the first channel layer and the second channel layer; an intermediate insulating pattern in the opening and between the first word line and the second word line and covering an upper surface of the first word line and an upper surface of the second word line; a first gate dielectric layer, at least partially between the first channel layer and the first word line; and a second gate dielectric layer, at least partially between the second channel layer and the second word line, each of the first channel layer and the second channel layer includes a vertical portion in the opening and an extension portion extending from an upper region of the vertical portion, the upper conductive pattern includes a first upper conductive pattern on the extension portion of the first channel layer and a second upper conductive pattern on the extension portion of the second channel layer, the first upper conductive pattern has a side surface vertically aligned with a side surface of the extension portion of the first channel layer, and the second upper conductive pattern has a side surface vertically aligned with a side surface of the extension portion of the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will be apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 , Figure 2A , Figure 2B and Figure 2C is a diagram schematically illustrating a semiconductor device according to an example embodiment;

[0008] Figure 3 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0009] Figure 4 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0010] Figure 5 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0011] Figure 6 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0012] Figure 7 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0013] Figure 8is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0014] Fig. 9 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0015] Fig.10 is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0016] Fig.11A is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0017] Fig. 11B is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0018] Fig. 11C is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0019] Fig.11D is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0020] Fig. 12A is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0021] Fig. 12B is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment;

[0022] Fig. 12C is a cross-sectional view schematically illustrating a modified example of the semiconductor device according to the example embodiment; and

[0023] Figures 13 to 23C are diagrams illustrating stages in a method of forming a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, terms such as "upper", "middle", "lower", etc. may be replaced with other terms such as "first", "second", "third", etc. to describe elements of the specification. Terms such as "first", "second", "third", etc. may be used to describe various elements, but the elements are not limited by the terms, for example, the terms are not intended to imply or require sequential inclusion, and the "first element" may be referred to as the "second element". As used herein, the term "or" is not necessarily an exclusive term, for example, "A or B" will include A, B, or A and B.

[0025] First, refer to Figure 1 , Figure 2A , Figure 2B and Figure 2C Illustrative examples of semiconductor devices according to example embodiments are described. Figures 1 to 2C middle, Figure 1 is a top view schematically illustrating a semiconductor device according to an example embodiment, Figure 2A is schematically shown along Figure 1 A cross-sectional view of the area cut by line II', Figure 2B is schematically shown along Figure 1 A cross-sectional view of the area cut by line II-II', Figure 2C is schematically shown along Figure 1 A cross-sectional view of the area cut off by line III-III'.

[0026] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C , a semiconductor device 1 according to example embodiments may include a lower structure 3 and a first conductive line 6 on the lower structure 3 .

[0027] The lower structure 3 may include an insulating layer.

[0028] The lower structure 3 may include a peripheral circuit structure including a peripheral circuit.

[0029] Each of the first conductive lines 6 may have a line shape extending in the first direction Y. The first conductive lines 6 may be spaced apart from each other in a second direction X perpendicular to the first direction Y.

[0030] The first direction (Y) and the second direction (X) may be parallel to the upper surface of the lower structure (3).

[0031] The first conductive line 6 may be a bit line BL.

[0032] Each of the first conductive lines 6 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube or a combination thereof. In an implementation, each of the first conductive lines 6 may include, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube or a combination thereof. Each of the first conductive lines 6 may include a single layer or multiple layers of the above materials.

[0033] The semiconductor device 1 may further include a shielding structure 8 between the first conductive lines 6. The first conductive lines 6 and the shielding structure 8 may be alternately and repeatedly arranged in the second direction (X).

[0034] Each of the shielding structures 8 may include a conductive shielding pattern 15. Each of the conductive shielding patterns 15 may have a line shape extending in a first direction Y (eg, longitudinally). The conductive shielding pattern 15 may be parallel to the first conductive line 6. The conductive shielding pattern 15 may be spaced apart from the first conductive line 6.

[0035] Each of the shielding structures 8 may further include a first insulating layer 9 covering side and bottom surfaces of the conductive shield pattern 15 , a second insulating layer 12 between the first insulating layer 9 and the conductive shield pattern 15 , and a third insulating layer 18 on the conductive shield pattern 15 .

[0036] The semiconductor device 1 may include an insulating structure 25 having an opening 27 on the first conductive line 6 and the shielding structure 8 .

[0037] The insulating structure 25 may include an etch stop layer 21 and an interlayer insulating layer 24 stacked in sequence. The etch stop layer 21 may have a thickness that is smaller or thinner than that of the interlayer insulating layer 24. The etch stop layer 21 may include a material different from that of the interlayer insulating layer 24. In an implementation, the interlayer insulating layer 24 may be formed of silicon oxide or a low-κ dielectric, and the etch stop layer 21 may be formed of silicon nitride or a high-κ dielectric.

[0038] In an implementation, a "low-κ dielectric" may be a dielectric having a dielectric constant smaller than that of silicon oxide, and a "high-κ dielectric" may be a dielectric having a dielectric constant larger than that of silicon oxide. The opening 27 may have a linear shape extending in the second direction (X). The first conductive line 6 and the shielding structure 8 may be exposed through the opening 27.

[0039] The semiconductor device 1 may further include a structure ST. At least a portion of the structure ST may be in the opening 27 .

[0040] Each of the first conductive lines 6 may include a first region 6a vertically overlapping the structure ST and a second region 6b vertically overlapping the insulating structure 25. In each of the first conductive lines 6, the first region 6a may contact the structure ST, and the second region 6b may contact the insulating structure 25. In each of the first conductive lines 6, the thickness of the second region 6b may be greater than the thickness of the first region 6a. In each of the first conductive lines 6, the upper surface of the second region 6b may be at a higher level than the upper surface of the first region 6a.

[0041] The structure ST may further include a channel layer 49 , a second conductive line 39 , a gate dielectric layer 36 , an intermediate layer 31 , and an intermediate insulating pattern 42 .

[0042] The channel layers 49 may include a material that may function as a channel of a transistor, such as a semiconductor material. In an implementation, each of the channel layers 49 may include an oxide semiconductor layer or a two-dimensional (2D) material layer that may function as a channel region of a transistor.

[0043] In an implementation, the oxide semiconductor layer may include, for example, indium gallium zinc oxide (IGZO). In an implementation, the oxide semiconductor layer may include, for example, indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium silicon oxide (IGSiO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc nitride oxide (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (IZO), Indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) or indium gallium silicon oxide (InGaSiO).

[0044] The 2D material layer may include a transition metal dichalcogenide material layer (TMD material layer), a black phosphorus material layer, or a hexagonal boron nitride material layer (h-BN material layer). In an implementation, the two-dimensional material layer may include, for example, BiOSe, CrI 3 ,WSe 2 ,CuSe 2 、MoS 2 、TaS、WS、CuS 2 , SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene or Janus 2D materials.

[0045] The channel layer 49 is a material that can be used as a channel of a transistor. In an implementation, the channel layer 49 can be formed of single crystal silicon or polycrystalline silicon.

[0046] When from Figure 1 When viewed from the top view shown, the vertical portion of the channel layer 49 ( Figure 2A 49V) can be arranged sequentially while being spaced apart from each other along the first direction Y. Figure 1 When viewed from above, the vertical portion of the channel layer 49 ( Figure 2A Each of the 49V) in the second direction X can have a strip shape extending in the second direction X.

[0047] The lower end of the channel layer 49 may be at a higher level than the lower end of the second conductive line 39. The channel layer 49 may include a first channel layer 49_1 and a second channel layer 49_2 spaced apart from each other. Each of the first channel layer 49_1 and the second channel layer 49_2 may include a vertical portion 49V extending in the vertical direction Z and an extension portion 49H extending from an upper region of the vertical portion 49V.

[0048] In each of the first and second channel layers 49_1 and 49_2 , the extension portion 49H may include a region vertically overlapping with the vertical portion 49V and a region not vertically overlapping with the vertical portion 49V.

[0049] The second conductive lines 39 may be on the first conductive lines 6 and the shielding structure 8 . A portion of each of the second conductive lines 39 may be at the same level as a portion of each of the vertical portions 49V of the channel layer 49 .

[0050] Each of the second conductive lines 39 may extend in a second direction X crossing the first direction Y. The second direction X may be perpendicular to the first direction Y. The second conductive lines 39 may be parallel to each other.

[0051] The second conductive line 39 may be a word line WL. The second conductive line 39 may include, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or a combination thereof. Each of the second conductive lines 39 may include a single layer or multiple layers of the above materials.

[0052] Hereinafter, the first conductive line 6 will be referred to as a bit line and described, and the second conductive line 39 will be referred to as a word line. Furthermore, hereinafter, one of the bit lines 6 will be mainly described.

[0053] The word line 39 may include a first word line 39a and a second word line 39b that are spaced apart from and adjacent to each other. The first word line 39a and the second word line 39b may include portions between the first channel layer 49_1 and the second channel layer 49_2, respectively.

[0054] Upper ends of the first and second word lines 39 a and 39 b may be at a lower level than upper ends of the vertical portions 49V of the first and second channel layers 49_1 and 49_2 .

[0055] In an implementation, lower ends of the first and second word lines 39 a and 39 b may be at a lower level than lower ends of the vertical portions 49V of the first and second channel layers 49_1 and 49_2 .

[0056] In an implementation, lower ends of the first word line 39 a and the second word line 39 b may be at the same level as or higher than an upper surface of the second region 6 b of the bit line 6 .

[0057] In an implementation, lower ends of the first word line 39 a and the second word line 39 b may be at a lower level than an upper surface of the second region 6 b of the bit line 6 .

[0058] In an implementation, lower ends of the first word line 39 a and the second word line 39 b may be at a lower level than an upper surface of the etch stop layer 21 .

[0059] The intermediate insulating pattern 42 may be between the first word line 39a and the second word line 39b and cover the upper portions of the first word line 39a and the second word line 39b. The first word line 39a and the second word line 39b may be spaced apart from each other with the intermediate insulating pattern 42 therebetween. The intermediate insulating pattern 42 may be between the vertical portions 49V of the first channel layer 49_1 and the second channel layer 49_2, and the first channel layer 49_1 and the second channel layer 49_2 may be at a lower level than the extension portion 49H. The intermediate insulating pattern 42 may include silicon oxide or a low-κ dielectric having a dielectric constant smaller than that of silicon oxide.

[0060] The intermediate layer 31 may include a first intermediate portion 31V1 vertically overlapping the vertical portion 49V of the first channel layer 49_1 and a second intermediate portion 31V2 vertically overlapping the vertical portion 49V of the second channel layer 49_2. The intermediate layer 31 may further include a connection portion 31H extending from lower regions of the first and second intermediate portions 31V1 and 31V2.

[0061] The intermediate layer 31 may contact the first channel layer 49_1 and the second channel layer 49_2 and the bit line 6. The upper ends of the first intermediate portion 31V1 and the second intermediate portion 31V2 of the intermediate layer 31 may contact (e.g., directly contact) the lower surfaces of the first channel layer 49_1 and the second channel layer 49_2. The upper ends of the first intermediate portion 31V1 and the second intermediate portion 31V2 of the intermediate layer 31 may be at a higher level than the lower ends of the first word line 39a and the second word line 39b. The first channel layer 49_1 and the second channel layer 49_2 may be spaced apart from the bit line 6 with the intermediate layer 31 therebetween.

[0062] The lower surface of the intermediate layer 31 may contact the upper surface of the first region 6a of the bit line 6. It may be at a lower level than the upper surface of the second region 6b of the bit line 6.

[0063] The intermediate layer 31 may include a conductive material layer. In an implementation, the intermediate layer 31 may include a metal nitride, such as TiN. In an implementation, the intermediate layer 31 may include another conductive material that may replace TiN, such as WN or TaN.

[0064] The gate dielectric layer 36 may include a first gate dielectric layer 36 a and a second gate dielectric layer 36 b .

[0065] At least a portion of the first gate dielectric layer 36a may be between the first channel layer 49_1 and the first word line 39a. The first gate dielectric layer 36a may include a portion extending upward from a portion between the first channel layer 49_1 and the first word line 39a and a portion extending downward.

[0066] The first gate dielectric layer 36a may extend from a portion between the first channel layer 49_1 and the first word line 39a, between the first word line 39a and the intermediate layer 31. A portion of the first gate dielectric layer 36a may be between a lower surface of the first word line 39a and the connection portion 31H of the intermediate layer 31. The first gate dielectric layer 36a may extend from a portion between the first channel layer 49_1 and the first word line 39a, to between the intermediate insulating pattern 42 and the vertical portion 49V of the first channel layer 49_1.

[0067] The second gate dielectric layer 36b may extend from a portion between the second channel layer 49_2 and the second word line 39b, between the second word line 39b and the intermediate layer 31. A portion of the second gate dielectric layer 36b may be between a lower surface of the second word line 39b and the connection portion 31H of the intermediate layer 31. The second gate dielectric layer 36b may extend from a portion between the second channel layer 49_2 and the second word line 39b, between the intermediate insulating pattern 42 and the vertical portion 49V of the second channel layer 49_2.

[0068] Each of the extension portions 49H of the first and second channel layers 49_1 and 49_2 may include a first extension region 49H1 and a second extension region 49H2 .

[0069] The first extension region 49H1 of the extension portion 49H of the first channel layer 49_1 may contact the upper surface of the insulating structure 25, and the second extension region 49H2 of the extension portion 49H of the first channel layer 49_1 may contact the upper surface of the first gate dielectric layer 36a and the upper surface of the intermediate insulating pattern 42. The first extension region 49H1 of the extension portion 49H of the second channel layer 49_2 may contact the upper surface of the insulating structure 25, and the second extension region 49H2 of the extension portion 49H of the second channel layer 49_2 may contact the upper surface of the second gate dielectric layer 36b and the upper surface of the intermediate insulating pattern 42.

[0070] The second extension region 49H2 of the extension portion 49H of the first channel layer 49_1 may vertically overlap the first word line 39 a , and the second extension region 49H2 of the extension portion 49H of the second channel layer 49_2 may vertically overlap the second word line 39 b .

[0071] Each of the gate dielectric layers 36 may include silicon oxide or a high-κ dielectric. The high-κ dielectric may be a dielectric having a higher dielectric constant than that of silicon oxide. The high-κ dielectric may include a metal oxide or a metal oxynitride. In an implementation, the high-κ dielectric may be composed of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 Each of the gate dielectric layers 36 may be formed of a single layer or multiple layers of the above materials.

[0072] The semiconductor device 1 may further include an upper conductive pattern 52 on the channel layer 49. The upper conductive pattern 52 may contact the channel layer 49. The upper conductive pattern 52 may contact an upper surface of an extension portion 49H of the channel layer 49. The upper conductive pattern 52 may be vertically aligned with the extension portion 49H of the channel layer 49. The upper conductive pattern 52 may have a side surface vertically aligned with a side surface of the extension portion 49H of the channel layer 49.

[0073] The extension portion 49H of the channel layer 49 may increase the contact area between the channel layer 49 and the upper conductive pattern 52. In an implementation, by increasing the contact area between the upper conductive pattern 52 and the channel layer 49, the contact resistance between the upper conductive pattern 52 and the channel layer 49 may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0074] The upper conductive pattern 52 may include a first upper conductive pattern 52a on the extension portion 49H of the first channel layer 49_1 and a second upper conductive pattern 52b on the extension portion 49H of the second channel layer 49_2. The first upper conductive pattern 52a may have a side surface vertically aligned with the side surface of the extension portion 49H of the first channel layer 49_1. The second upper conductive pattern 52b may have a side surface vertically aligned with the side surface of the extension portion 49H of the second channel layer 49_2.

[0075] The semiconductor device 1 may further include an insulating separation pattern 55 on the side surfaces of the extension portion 49H and the upper conductive pattern 52, which are sequentially stacked and vertically aligned. The insulating separation pattern 55 may pass between the upper conductive patterns 52 and extend downward. The insulating separation pattern 55 may include a portion extending into the interlayer insulating layer 24 and a portion extending into the middle insulating pattern 42. The lower end of the insulating separation pattern 55 may be at a lower level than the extension portion 49H of the channel layer 49. The upper surface of the insulating separation pattern 55 may be coplanar with the upper surface of the upper conductive pattern 52.

[0076] The semiconductor device 1 may further include an etch stop layer 60 on the upper conductive pattern 52 and the insulating separation pattern 55. The etch stop layer 60 may include an insulating material, such as silicon nitride, SiBN, SiCN, or an insulating metal oxide.

[0077] The semiconductor device 1 may further include a data storage structure DS. The data storage structure DS may include a first electrode 63 penetrating the etch stop layer 60 and electrically connected to the upper conductive pattern 52 , a dielectric layer 65 covering the first electrode 63 and the etch stop layer 60 , and a second electrode 67 covering the dielectric layer 65 .

[0078] In an implementation, the data storage structure DS may be a capacitor for storing data in a DRAM. In an implementation, the dielectric layer 65 of the data storage structure DS may be a capacitor dielectric layer of the DRAM. The dielectric layer 65 may include a high-κ dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0079] In an implementation, the data storage structure DS may be a capacitor structure for storing DRAM and other memory information. In an implementation, the data storage structure DS may be between the first electrode 63 and the second electrode 67, and may be a capacitor of a ferroelectric memory (FeRAM) including a dielectric layer 65, the dielectric layer 65 including a ferroelectric layer or an antiferroelectric layer.

[0080] Various modified examples of the elements of the above-described embodiments will be described. The various modified examples of the elements of the above-described embodiments described below will focus on the modified or replaced elements. In this case, the above-described elements may be directly referenced without a separate detailed description, or the description may be omitted. In addition, the elements described below that may be modified or replaced will be described with reference to the accompanying drawings, and the elements that may be modified or replaced may be combined with each other or with the above-described elements to form a semiconductor device according to an example embodiment. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B and Fig. 12C It is along Figure 1 sectional views taken along line II' in FIG. 1 to describe various modifications according to example embodiments.

[0081] In the implementation, refer to Figure 3 , Figure 2A The channel layer 49 in the embodiment may alternatively be a channel layer 49a having a lower end at a level lower than the lower surface of the interlayer insulating layer 24. In an implementation, Figure 2A The vertical portion 49V of the channel layer 49 in the embodiment may be a vertical portion 49Va having a lower end disposed at a level lower than the lower surface of the interlayer insulating layer 24. Therefore, the channel layer 49a may include the vertical portion 49Va and the vertical portion 49Va. Figure 2A The extension 49H is shown.

[0082] Figure 2A The intermediate layer 31 in the embodiment may alternatively be an intermediate layer 31a having an upper end at a level lower than the lower surface of the interlayer insulating layer 24. In an implementation, Figure 2A The first middle portion 31V1 and the second middle portion 31V2 of the middle layer 31 in the embodiment may be the first middle portion 31V1a and the second middle portion 31V2 having upper ends at a level lower than the lower surface of the interlayer insulating layer 24. Therefore, the middle layer 31a may include the first middle portion 31V1a and the second middle portion 31V2 and the like. Figure 2A The connecting portion 31H is shown.

[0083] In an implementation, a lower end of the vertical portion 49Va may be at a lower level than a lower surface of the etch stop layer 21. Thus, the vertical portion 49Va of the channel layer 49a may contact the intermediate layer 31 and the bit line 6.

[0084] In an implementation, a lower end of the vertical portion 49Va may be at substantially the same level as a lower end of the word line 39 .

[0085] In an implementation, a lower end of the vertical portion 49Va may be at a lower level than a lower end of the word line 39 .

[0086] In the implementation, refer to Figure 4 , Figure 2A The channel layer 49 in φ may instead be a channel layer 49 b having a lower end located at a lower level than the lower end of the word line 39 . Figure 2A The vertical portion 49V in the channel layer 49b may be a vertical portion 49Vb extending downward and contacting the bit line 6. Each of the channel layers 49b may further include a lower extension portion 49E extending while bending from the vertical portion 49Vb. Therefore, each of the channel layers 49b may include the vertical portion 49Vb and the lower extension portion 49E and Figure 2A The channel layer 49b may include a first channel layer 49_1 and a second channel layer 49_2 spaced apart from each other.

[0087] Figure 2A The intermediate layer 31 in the embodiment may alternatively be an intermediate layer 31 b between the lower extension portion 49E of the first channel layer 49_1 and the lower extension portion 49E of the second channel layer 49_2 . The intermediate layer 31 b may vertically overlap the word line 39 .

[0088] In an implementation, the intermediate layer 31 may include a conductive material layer.

[0089] In an implementation, the intermediate layer 31 may include an insulating material layer.

[0090] In an implementation, the intermediate layer 31 may be an empty space, such as an air gap.

[0091] In the implementation, refer to Figure 5 , Figure 2A The intermediate layer 31 in the embodiment may alternatively be an intermediate layer 31c including a first intermediate material layer 31c_1 and a second intermediate material layer 31c_2 on the first intermediate material layer 31c_1. The first intermediate material layer 31c_1 may include a conductive material layer, such as TiN, WN, or TaN. The second intermediate material layer 31c_2 may include an oxide of the conductive material of the first intermediate material layer 31c_1, such as TiON. In an implementation, the second intermediate material layer 31c_2 may be an insulating material layer. The first intermediate material layer 31c_1 may include Figure 2A The first middle portion 31V1, the second middle portion 31V2, and the first middle portion 31V1c, the second middle portion 31V2c, and the connecting portion 31Hc described in FIG.

[0092] In the implementation, refer to Figure 6 , Figure 3 The intermediate layer 31a in the embodiment may alternatively be an intermediate layer 31d including a first intermediate material layer 31d_1 and a second intermediate material layer 31d_2 on the first intermediate material layer 31d_1. Figure 6 As shown, the intermediate layer 31d may include a first intermediate material layer 31d_1 and a second intermediate material layer 31d_2 on the first intermediate material layer 31d_1. The first intermediate material layer 31d_1 and the second intermediate material layer 31d_2 may be made of Figure 5 The first intermediate material layer 31c_1 and the second intermediate material layer 31c_2 are formed of the same material.

[0093] The first intermediate material layer 31d_1 may include Figure 3 The first middle portion 31V1a, the second middle portion 31V2a, and the first middle portion 31V1d, the second middle portion 31V2d, and the connecting portion 31H described in FIG.

[0094] In the implementation, refer to Figure 7 , Figure 2A The channel layers 49 in may alternatively be channel layers 49c having the inner region 51. Each of the channel layers 49c may include a vertical portion 49Vc covering a lower surface and both side surfaces of the inner region 51 and an extension region 49Hc extending from the vertical portion 49Vc.

[0095] In each of the channel layers 49c, the extension regions 49Hc may include Figure 2A The first extension region 49H1c and the second extension region 49H2c are located at positions corresponding to the first extension region 49H1 and the second extension region 49H2.

[0096] In an implementation, the inner region 51 may include an insulating material, such as silicon oxide or a low-κ dielectric material.

[0097] In implementations, the interior region 51 may be an empty space, such as a void or an air gap.

[0098] Refer to above Figure 2A The depicted upper conductive pattern 52 may cover an upper surface of the channel layer 49 c and an upper portion of the inner region 51 .

[0099] In the implementation, refer to Figure 8 , Figure 3The channel layer 49a in the embodiment may be alternatively a channel layer 49d having an inner region 51a. Each of the channel layers 49d may include a vertical portion 49Vd covering the lower surface and both side surfaces of the inner region 51a and an extension region 49Hc extending from the vertical portion 49Vd. In each of the channel layers 49d, the extension region 49Hc may be connected to the inner region 51a. Figure 7 The extension region 49Hc is the same as in FIG. Figure 7 The inner region 51a in the structure may be an insulating material (such as silicon oxide) or a low-κ dielectric material, or an empty space (such as a void).

[0100] In the implementation, refer to Fig. 9 , Figure 8 Each of the upper conductive patterns 52 in the embodiment may alternatively be an upper conductive pattern 52 a including a horizontal portion 52H covering the upper surface of the extension region 49Hc of the channel layer 49 c and an extension portion 52E extending from the horizontal portion 52H into the inner region 51 .

[0101] In each of the upper conductive patterns 52 a , a lower end of the extension portion 52E may be at a lower level than upper ends of the vertical portion 49Vc and the extension portion 49Hc.

[0102] In each of the upper conductive patterns 52a, the side surface of the extension portion 52E may contact the vertical portion 49Vc of the channel layer 49c. In an implementation, by increasing the contact area between the upper conductive pattern 52a and the channel layer 49c, the contact resistance between the upper conductive pattern 52a and the channel layer 49c may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0103] In the implementation, refer to Fig.10 , Fig. 9 Each of the upper conductive patterns 52 in the embodiment may alternatively be an upper conductive pattern 52 a including a horizontal portion 52H covering the upper surface of the extension region 49Hc of the channel layer 49 d and an extension portion 52E extending from the horizontal portion 52H into the inner region 51 .

[0104] In each of the upper conductive patterns 52 a , a lower end of the extension portion 52E may be at a lower level than upper ends of the vertical portion 49Vd and the extension portion 49Hc.

[0105] In each of the upper conductive patterns 52a, the side surface of the extension portion 52E may contact the vertical portion 49Vd of the channel layer 49d. In an implementation, by increasing the contact area between the upper conductive pattern 52a and the channel layer 49d, the contact resistance between the upper conductive pattern 52a and the channel layer 49d may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0106] In the implementation, refer to Fig.11A , above Figures 1 to 10 The intermediate layer in the example embodiment described in the embodiment may alternatively be an intermediate layer 31e having a curved surface. In an implementation, Figure 2A The surface of the intermediate layer 31 in contact with the channel layer 49 may be deformed into a concave shape. In an implementation, Figure 2A The upper surface of the intermediate layer 31 in contact with the channel layer 49 may alternatively be a curved upper surface 31U. Figure 2A The intermediate layer 31 in may alternatively be an intermediate layer 31 e having a curved upper surface 31U.

[0107] On the upper surface 31U of the intermediate layer 31 e , the edge region 31E may be at a higher level than the intermediate region 31C.

[0108] In an implementation, the upper surface 31U of the intermediate layer 31e may have a curved shape, and the contact area between the intermediate layer 31e and the channel layer 49 may be increased. In an implementation, by increasing the contact area between the intermediate layer 31e and the channel layer 49c, the contact resistance between the intermediate layer 31e and the channel layer 49c may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0109] In the implementation, refer to Fig. 11B ,exist Figures 1 to 11A In the channel layers 49, 49a, 49b, 49c, 49d of the example embodiment, the extension regions 49H and 49Hc may be omitted, and the upper ends of the vertical portions 49V, 49Va, 49Vb, 49Vc, and 49Vd may be lower than the top surface of the insulating structure 25. In an implementation, Figure 2A The channel layer 49 of φ may alternatively be a channel layer 49 e having an upper end at a level lower than the upper surface of the insulation structure 25 .

[0110] Figures 1 to 11A Each of the upper conductive patterns 52 and 52a of the exemplary embodiment may alternatively be an upper conductive pattern 52a′ including a horizontal portion 52H′ on the upper surface of the insulating structure 25 and a conductive pattern extending downward from the horizontal portion 52H′ and contacting the insulating structure 25. Figures 1 to 11A The example embodiment of the channel layers 49, 49a, 49b, 49c, and 49d of the embodiment of the invention includes an extension portion 52E' at an upper end of the deformed channel layer. In an implementation, an upper surface 49U of the channel layer 49e may be at a lower level than an upper surface of the insulating structure 25, the extension portion 52E' may be between the interlayer insulating layer 24 and the gate dielectric layer 36 of the insulating structure 25, and the extension portion 52E' may contact the top surface 49U of the channel layer 49e.

[0111] The upper surface 49U of the channel layer 49e may have a curved shape. The upper surface 49U of the channel layer 49e may have a concave shape. On the upper surface 49U of the channel layer 49e, the edge region 49G may be at a higher level than the middle region 49C. In an implementation, the upper surface 49U of the channel layer 49e may have a curved shape, and the contact area between the upper conductive pattern 52a' and the channel layer 49e may be increased. In an implementation, by increasing the contact area between the upper conductive pattern 52a' and the channel layer 49e, the contact resistance between the upper conductive pattern 52a' and the channel layer 49e may be reduced. Therefore, the electrical characteristics of the semiconductor device may be improved.

[0112] In the implementation, refer to Fig. 11C ,exist Figures 1 to 11B In the example embodiment of FIG. 1 , the middle insulating pattern 42 may extend downward, and may alternatively be Figures 1 to 11B In the example embodiment of the present invention, the intermediate insulating pattern 42a separates the intermediate layers 31, 31a, 31b, 31c, 31d and 31e in the first direction Y. In an implementation, Figure 2A The intermediate layer 31 in FIG. 4 may alternatively be an intermediate layer 31 f including portions 31 f 1 and 31 f 2 separated from each other by the intermediate insulating pattern 42 a .

[0113] In the implementation, refer to Fig.11D ,exist Figures 1 to 3 and Figures 5 to 11C In the example embodiment, in the portion where the channel layers (49a, 49b, 49c, 49d, 49e) and the intermediate layers (31, 31a, 31c, 31d, 31e) contact each other, the channel layers 49a, 49b, 49c, 49d, and 49e may alternatively be channel layers having a width greater than that of the intermediate layers 31, 31a, 31c, 31d, and 31e. In an implementation, Figure 2A The vertical portion 49V of the channel layer 49 in the embodiment may be transformed into a vertical portion 49Vf having a width greater than that of the intermediate layer 31. Figure 2A The channel layer 49 in 49Vf may be transformed into a channel layer 49f including a vertical portion 49Vf.

[0114] In the implementation, refer to Fig. 12A ,exist Figures 1 to 11D In the example embodiment, the lower structure 3 may alternatively be a peripheral circuit structure LR including a peripheral circuit. Fig. 12A The upper area indicated by "UR" in the figure may have Figures 1 to 11D The structure on the lower structure 3 in any of the example embodiments of the same structure, and can be referred to as a memory structure (UR). In an implementation, Fig. 12AThe upper area indicated by "UR" in the Figure 2A The lower structure 3 has the same structure as the structure on top.

[0115] The peripheral circuit structure LR may include a semiconductor substrate 105, an active region 110a on the semiconductor substrate 105, an isolation region 110b on the semiconductor substrate 105 that defines the active region 110a, a peripheral gate (Gox, GE) on the active region 110a, and a peripheral source / drain (SD) in the active region 110a on both sides of the peripheral gate (Gox, GE). The peripheral gates Gox and GE and the peripheral source / drain SD may constitute a peripheral transistor PTRa. The peripheral gates Gox and GE may include a peripheral gate dielectric layer Gox and a peripheral gate electrode GE sequentially stacked on the active region 110a. The peripheral transistor PTRa may constitute a peripheral circuit.

[0116] The peripheral circuit structure LR may further include a peripheral wiring structure 115 electrically connected to the peripheral transistor PTRa and a peripheral insulation structure 120 on the semiconductor substrate 105 covering the peripheral transistor PTRa and the peripheral wiring structure 115. The peripheral wiring structure 115 may include a vertical portion and a horizontal portion. The peripheral wiring structure 115 may electrically connect the bit line 6 and the peripheral transistor PTRa.

[0117] In an implementation, a semiconductor device 100 a including a peripheral wiring structure 115 and a memory structure UR may be provided.

[0118] In the implementation, refer to Fig. 12B , Figures 1 to 11D The semiconductor device in the example embodiment may alternatively be a semiconductor device 100b, which further includes an upper insulating structure 80, an upper wiring structure 83 buried in the upper insulating structure 80, a lower bonding pad 86 electrically connected to the upper wiring structure 83 and having an upper surface coplanar with the upper surface of the upper insulating structure 80, and an upper chip structure CH2 bonded to the lower bonding pad 86 and the upper insulating structure 80.

[0119] exist Figures 1 to 11D In an example embodiment of FIG. 8 , the upper insulating structure 80 may be on the data storage structure DS. A structure from the lower structure 3 to the upper insulating structure 80 and the lower bonding pad 86 may be defined as a lower chip structure CH1 .

[0120] The upper chip structure CH2 may include a semiconductor substrate 205, an active region 210a below the semiconductor substrate 205, an isolation region 210b defining the active region 210a below the semiconductor substrate 205, a peripheral gate (Gox, GE) below the active region 210a, and a peripheral source / drain SD in the active region 210a on both sides of the peripheral gate Gox and GE. The peripheral gates Gox and GE and the peripheral source / drain SD may constitute a peripheral transistor PTRb. The peripheral gate (Gox, GE) may include a peripheral gate electrode (GE) below the active region 210a and a peripheral gate dielectric layer (Gox) between the active region 210a and the peripheral gate electrode (GE). The peripheral transistor PTRb may constitute a peripheral circuit.

[0121] The upper chip structure CH2 may further include a peripheral wiring structure 215 electrically connected to the peripheral transistor PTRb under the semiconductor substrate 205 and a peripheral insulation structure 220 covering the peripheral transistor PTRb and the peripheral wiring structure 215 under the semiconductor substrate 205. The peripheral wiring structure 215 may include a vertical portion and a horizontal portion. The peripheral wiring structure 215 may electrically connect the bit line 6 and the peripheral transistor PTRb.

[0122] The upper chip structure CH2 may further include an upper bonding pad 230 electrically connected to the peripheral wiring structure 215 , and a side surface of the upper bonding pad 230 is covered by the peripheral insulation structure 220 .

[0123] The peripheral insulating structure 220 may contact the upper insulating structure 80, and the upper bonding pad 230 may contact and bond to the lower bonding pad 86. The upper bonding pad 230 and the lower bonding pad 86 may include the same metal material as each other, for example, copper (Cu).

[0124] In the implementation, refer to Fig. 12C ,exist Figures 1 to 12B In the example embodiment of the present invention, the data storage structure DS may be omitted, and the gate dielectric layer 36 may instead be a data storage layer 36 capable of storing information. Each of the data storage layers 36 may include a ferroelectric layer capable of storing information. The ferroelectric layer capable of storing information may have a polarization characteristic according to an electric field applied by the word line 39, and may have a residual polarization due to a dipole even in the absence of an external electric field. The polarization state in the ferroelectric layer of the data storage layer 36 may be used to record data.

[0125] The ferroelectric layer of the data storage layer 36 may include an Hf compound, a Zr compound, or an Hf-Zr compound. In an implementation, the Hf compound may include an HfO ferroelectric material, the Zr compound may include a ZrO ferroelectric material, and the Hf-Zr compound may include a hafnium zirconium oxide (HZO) ferroelectric material. The ferroelectric layer of the data storage layer 36 may include impurities, such as a ferroelectric material doped with C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, or Sr. In the data storage layer 36, the ferroelectric layer may be a ferroelectric material in which HfO 2 、ZrO 2 Or HZO doped with C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc or Sr. In an implementation, the ferroelectric layer of the data storage layer 36 may include a suitable material having ferroelectric properties capable of storing information.

[0126] Each of the data storage layers 36 may have a structure in which a lower dielectric layer and a ferroelectric layer are alternately laminated. In an implementation, the lower dielectric layer may include silicon oxide, silicon oxynitride, silicon nitride, or a high-κ dielectric. The high-κ dielectric may include a metal oxide or a metal oxynitride. In an implementation, the high-κ dielectric may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 or a combination thereof.

[0127] In an implementation, a semiconductor device 100 c including a data storage layer 36 may be provided.

[0128] The semiconductor device 100c may further include an upper conductive pattern (eg, Figures 1 to 12B In an example implementation of Figure 2A The upper conductive line 370 may be electrically connected to the upper conductive pattern 52. The upper conductive line 370 may vertically overlap the bit line 6. The upper conductive line 370 may be a source line.

[0129] In the following, reference will be made to Figures 13 to 23C An illustrative example of a method of forming a semiconductor device according to an embodiment is described. Figures 13 to 23C middle, Fig.13 , Fig.15 , Fig.17 and Fig.19 is a plan view of a stage in a method of forming a semiconductor device according to an example embodiment, Fig.14A , Fig.16A , Fig.18A , Fig. 20 , Fig.21 , Fig. 22 and Fig.23A is schematically shown along Figure 1 A cross-sectional view of the area cut by line II', Fig. 14B , Fig. 16B , Fig.18B and Fig. 23B is schematically shown along Figure 1 A cross-sectional view of the area cut by line II-II', Fig. 14C , Fig. 16C , Fig.18C and Fig.23C is schematically shown along Figure 1 A cross-sectional view of the area cut off by line III-III'.

[0130] exist Fig.13 , Fig.14A , Fig. 14B and Fig. 14C In the embodiment of the present invention, a lower structure 3 may be formed. A first conductive line 6 may be formed on the lower structure 3. Each of the first conductive lines 6 may have a linear shape extending in a first direction Y. The first conductive lines 6 may be spaced apart from each other in a second direction X perpendicular to the first direction Y. The first conductive lines 6 may be bit lines BL.

[0131] The shielding structures 8 may be formed between the first conductive lines 6. Each of the shielding structures 8 may include a conductive shielding pattern 15, a first insulating layer 9 covering side and bottom surfaces of the conductive shielding pattern 15, a second insulating layer 12 between the first insulating layer 9 and the conductive shielding pattern 15, and a third insulating layer 18 on the conductive shielding pattern 15.

[0132] An insulating structure 25 having an opening 27 may be formed on the conductive line 6 and the shielding structure 8. The insulating structure 25 may include an etch stop layer 21 and an interlayer insulating layer 24 that are sequentially stacked.

[0133] Forming the insulating structure 25 may include forming an etch stop layer 21 and an interlayer insulating layer 24 stacked in sequence and patterning the etch stop layer 21 and the interlayer insulating layer 24 to form an opening 27. While the opening 27 is formed, the thickness of the first conductive line 6 exposed by the opening 27 may be reduced. In an implementation, each of the first conductive lines 6 may include a first region 6a having a thickness reduced by the opening 27 and a second region 6b vertically overlapping the insulating structure 25.

[0134] Reference Fig.15 , Fig.16A , Fig. 16B and Fig. 16C , a preliminary intermediate layer 30 conformally covering the sidewalls and bottom surfaces of the opening 27 and the top surface of the insulation structure 25 may be formed.

[0135] In an implementation, the preliminary intermediate layer 30 may be formed of a conductive material.

[0136] In an implementation, the preliminary intermediate layer 30 may be formed of an insulating material.

[0137] In an implementation, the preliminary intermediate layer 30 may be formed of a conductive material layer and an insulating material layer stacked sequentially.

[0138] Reference Fig.17 , Fig.18A , Fig.18B and Fig.18C , mask patterns 33 may be formed on the preliminary intermediate layer 30. Each of the mask patterns 33 may have a line shape extending in the first direction Y.

[0139] The preliminary intermediate layer 30 may be etched in an etching process using the mask pattern 33 as an etching mask to form preliminary intermediate patterns 30a. The preliminary intermediate patterns 30a may be spaced apart from each other in the second direction X.

[0140] Reference Fig.19 and Fig. 20 , the mask pattern 33 may be removed. A gate dielectric layer 36 may be formed to cover the preliminary intermediate pattern 30a.

[0141] A conformal conductive layer may be formed on the gate dielectric layer 36, and the conductive layer may be etched to form a second conductive line 39. The second conductive line 39 may be a word line WL.

[0142] The second conductive line 39 may be formed in the opening 27 , and may have an upper surface located at a lower level than an upper surface of the insulating structure 25 .

[0143] An insulating material layer is formed and then planarized until the upper surface of the insulating structure 25 is exposed. In an implementation, an intermediate insulating pattern 42 that remains in the opening 27 and covers the second conductive line 39 may be formed, and the preliminary intermediate pattern 30a may remain in the opening 27. The upper surface of the preliminary intermediate pattern 30a remaining in the opening 27 may be exposed.

[0144] Reference Fig.21 The intermediate layer 31 may be formed by etching at least a portion of the preliminary intermediate pattern 30a. The preliminary intermediate pattern 30a may be formed of any one of the intermediate layers 31, 31a, 31c, 31d, and 31e of the various embodiments described above, depending on the amount by which the preliminary intermediate pattern 30a is etched. Fig.21 It shows that Figure 2A The middle layer 31 in.

[0145] The empty space 45 may be formed by etching the preliminary intermediate pattern 30a. Figure 2A When the intermediate layer 31 is formed in the gate dielectric layer 36 , an empty space 45 may be formed between the gate dielectric layer 36 and the insulating structure 25 .

[0146] Reference Fig. 22 , a preliminary channel layer 48 may be formed to cover the upper surface of the insulating structure 25 while filling the empty space 45 .

[0147] In an implementation, in the case of the preliminary channel layer 48, in order to form Figures 7 to 10 In the embodiment of the present invention, the preliminary channel layer 48 may be formed to partially fill the empty spaces 45 while conformally covering the bottom surface and side surfaces of each empty space 45. The remaining space of the empty space 45 not filled with the preliminary channel layer 48 may be filled with an insulating material or may be left as an empty space.

[0148] Reference Fig.23A , Fig. 23B and Fig.23C , by forming a conductive layer on the preliminary channel layer 48 and patterning the conductive layer and the preliminary channel layer 48, an upper conductive pattern 52 and a channel layer 49 may be formed. Thus, the upper conductive pattern 52 may be vertically aligned with the remaining channel layer 49 on the upper surface of the insulating structure 25. The channel layer 49 remaining on the upper surface of the insulating structure 25 may be referred to as an extension portion ( Figure 2A 49H), such as Figure 2A As described in.

[0149] Then, an insulating material layer covering the upper and side surfaces of the upper conductive pattern 52 may be formed, and the insulating material layer may be planarized until the top surface of the upper conductive pattern 52 is exposed, thereby forming the insulating separation pattern 55 .

[0150] Refer again Figure 1 , Figure 2A , Figure 2B and Figure 2C , an etch stop layer 60 may be formed on the upper conductive pattern 52 and the insulating separation pattern 55. The etch stop layer 60 may be formed of an insulating material, such as silicon nitride, SiBN, SiCN, or an insulating metal oxide. A data storage structure DS electrically connected to the upper conductive pattern 52 may be formed. The data storage structure DS may include a first electrode 63 penetrating the etch stop layer 60 and electrically connected to the upper conductive pattern 52, a dielectric layer 65 covering the first electrode 63 and the etch stop layer 60, and a second electrode 67 covering the dielectric layer 65.

[0151] By way of summary and review, in DRAM, consideration has been given to reliably and stably forming components with reduced size. Distribution characteristics of semiconductor devices may deteriorate as the size of components is reduced.

[0152] As described above, according to an example embodiment, a method for forming an upper conductive pattern and a channel layer can be provided by the following steps: forming a "U"-shaped preliminary intermediate pattern in an opening of an insulating structure; etching at least a portion of the preliminary intermediate pattern to form an empty space; forming a preliminary channel layer that covers the upper surface of the insulating structure while being formed in the empty space; forming a conductive layer on the preliminary channel layer; and patterning the conductive layer and the preliminary channel layer at the same time. The channel layer formed by the method may include a vertical portion remaining in the empty space in the opening and an extension portion remaining on the upper surface of the insulating structure. The extension portion and the upper conductive pattern may be vertically aligned. The preliminary intermediate pattern may remain in the opening and be formed as an intermediate layer. The preliminary intermediate patterns may be spaced apart from each other in the longitudinal direction of the opening. Therefore, the channel layer may be spaced apart in the longitudinal direction of the opening.

[0153] According to example embodiments, vertical portions of the channel layer spaced apart in the longitudinal direction of the opening can be formed within the opening by filling the empty space without a separate etching process. Therefore, in the case of forming the channel layer using an oxide semiconductor, since vertical portions of the channel layer spaced apart in the longitudinal direction of the opening can be formed without etching the oxide semiconductor layer located on the side surface of the opening, a reliable channel layer can be provided.

[0154] One or more embodiments may provide a semiconductor device that may improve reliability.

[0155] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art when filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0156] This application claims the benefit of Korean Patent Application No. 10-2023-0076329 filed in the Korean Intellectual Property Office on June 14, 2023, the disclosure of which is incorporated herein by reference for all purposes.

Claims

1. A semiconductor device, include: A bit line extending in a first direction; a word line extending in a second direction intersecting the first direction, the word line being at a higher level than that of the bit line; a channel layer on the bit line, the channel layer comprising a vertical portion and an extension portion, the vertical portion being at least partially at the same level as the word line, the extension portion extending from an upper region of the vertical portion; a gate dielectric layer at least partially between the vertical portion and the word line; as well as an upper conductive pattern on the extending portion, in: The extension portion includes a first area vertically overlapping with the vertical portion and a second area not vertically overlapping with the vertical portion, and The upper conductive pattern has a side surface vertically aligned with a side surface of the extending portion.

2. The semiconductor device according to claim 1, further comprising an intermediate layer between the channel layer and the bit line, The intermediate layer is in contact with the bit line and the channel layer. 3 . The semiconductor device according to claim 2 , wherein an upper end of the intermediate layer is at a level higher than that of a lower end of the word line.

4. The semiconductor device according to claim 2, in: The middle layer includes a middle portion vertically overlapping the vertical portion and a connecting portion extending from a lower region of the middle portion and not overlapping the vertical portion, and The connection portion contacts the bit line.

5. The semiconductor device according to claim 4, in: The bit line has a first upper surface and a second upper surface at a lower level than the first upper surface, and The second upper surface of the bit line is in contact with the connection portion of the intermediate layer. The semiconductor device according to claim 2 , wherein the intermediate layer comprises a conductive material layer or an insulating material layer.

7. The semiconductor device according to claim 2, in: The intermediate layer comprises a conductive material layer and an insulating material layer on the conductive material layer, The conductive material layer contacts the bit line and the channel layer, and The insulating material layer contacts the gate dielectric layer. 8 . The semiconductor device according to claim 1 , wherein the extending portion of the channel layer includes a region vertically overlapping the gate dielectric layer and the word line. 9 . The semiconductor device according to claim 8 , wherein the extending portion of the channel layer is in contact with the gate dielectric layer. 10 . The semiconductor device according to claim 1 , wherein the channel layer is in contact with the bit line.

11. The semiconductor device according to claim 1 , further comprising an intermediate layer at least partially between a lower surface of the word line and the bit line, The gate dielectric layer extends from a portion disposed between the vertical portion and the word line between the lower surface of the word line and the intermediate layer.

12. A semiconductor device, include: bit line; a first channel layer and a second channel layer spaced apart from each other on the bit line; a first word line and a second word line spaced apart from each other on the bit line and respectively including portions between the first channel layer and the second channel layer; an intermediate layer connected to the first channel layer, the second channel layer and the bit line; a first gate dielectric layer at least partially between the first channel layer and the first word line; a second gate dielectric layer at least partially between the second channel layer and the second word line; a first upper conductive pattern on and connected to the first channel layer; as well as A second upper conductive pattern is on and connected to the second channel layer.

13. The semiconductor device according to claim 12, wherein the intermediate layer include: a first middle portion vertically overlapping the first channel layer; a second middle portion vertically overlapping the second channel layer; as well as A connection portion extends from a lower region of the first middle portion and a lower region of the second middle portion and contacts the bit line. 14 . The semiconductor device according to claim 13 , wherein the connection portion vertically overlaps the first word line and the second word line. The semiconductor device according to claim 12 , wherein the intermediate layer comprises a conductive material layer.

16. The semiconductor device according to claim 12, in: An upper end of the intermediate layer is at a level higher than that of a lower end of the first word line, and The upper end of the intermediate layer is at a level higher than that of a lower end of the second word line.

17. The semiconductor device according to claim 12, in: Each of the first channel layer and the second channel layer includes a vertical portion and an extension portion extending from an upper region of the vertical portion, The extending portion of the first channel layer vertically overlaps the first word line, and The extending portion of the second channel layer vertically overlaps the second word line.

18. A semiconductor device, include: bit line; an insulating structure on the bit line and having an opening exposing the bit line; a structure at least partially within said opening; as well as an upper conductive pattern on the structure, in: The structure comprises: a first channel layer and a second channel layer spaced apart from each other in the opening; a first word line and a second word line spaced apart from each other in the opening and respectively including portions between the first channel layer and the second channel layer; an intermediate insulating pattern in the opening and between the first word line and the second word line and covering an upper surface of the first word line and an upper surface of the second word line; a first gate dielectric layer at least partially between the first channel layer and the first word line; and a second gate dielectric layer at least partially between the second channel layer and the second word line, Each of the first channel layer and the second channel layer includes a vertical portion in the opening and an extension portion extending from an upper region of the vertical portion, The upper conductive pattern includes a first upper conductive pattern on the extending portion of the first channel layer and a second upper conductive pattern on the extending portion of the second channel layer, The first upper conductive pattern has a side surface vertically aligned with a side surface of the extending portion of the first channel layer, and The second upper conductive pattern has a side surface vertically aligned with a side surface of the extending portion of the second channel layer.

19. The semiconductor device according to claim 18, further comprising an intermediate material layer contacting the first channel layer, the second channel layer and the bit line, in: The intermediate material layer includes a middle portion vertically overlapping the vertical portion of the first channel layer and the vertical portion of the second channel layer and a connecting portion extending from a lower region of the middle portion, and The connection portion of the intermediate material layer vertically overlaps the first word line and the second word line.

20. The semiconductor device according to claim 19, in: The first channel layer and the second channel layer each include an oxide semiconductor, and The intermediate material layer includes TiN.

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