Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a first word line; a second word line, the second word line being spaced apart from the first word line; the back gate electrode is positioned between the first word line and the second word line; a first channel pattern located between the first word line and the back gate electrode; the second channel pattern is positioned between the second word line and the back gate electrode; a first gate insulating film located between the first word line and the first channel pattern; a second gate insulating film located between the second word line and the second channel pattern; a first bit line on the first channel pattern and the second channel pattern, where the first bit line is connected to the first channel pattern; and a second bit line on the first channel pattern and the second channel pattern, where the second bit line is connected to the second channel pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0002] In order to meet the excellent performance and low price of semiconductor memory devices required by consumers, it is desirable to increase the integration of semiconductor memory devices. Since the integration of semiconductor memory devices is an important factor in determining product prices, increased integration is particularly desirable.

[0003] Since the integration of a two-dimensional or planar semiconductor memory device is mainly determined by the area occupied by a unit memory cell, it is significantly affected by the technical level used to form fine patterns. However, since ultra-expensive equipment may be required to form fine patterns, the integration of two-dimensional semiconductor memory devices is constantly increasing, but still limited. Therefore, a semiconductor memory device including a vertical channel transistor having a channel extending in a vertical direction is proposed. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor memory device whose integration degree and electrical characteristics can be improved.

[0005] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0006] According to one aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a first word line, the first word line extending in a first direction; a second word line, the second word line being spaced apart from the first word line in a second direction intersecting the first direction, wherein the second word line extends in the first direction; a back gate electrode, the back gate electrode being located between the first word line and the second word line, wherein the back gate electrode extends in the first direction; a first channel pattern, the first channel pattern being located between the first word line and the back gate electrode; a second channel pattern, the second channel pattern being located between the second word line and the back gate electrode; a first gate insulating film, the first gate insulating film being located between the first word line and the back gate electrode; and the first channel pattern, wherein the first gate insulating film includes a first ferroelectric material film; a second gate insulating film, the second gate insulating film is located between the second word line and the second channel pattern, wherein the second gate insulating film includes a second ferroelectric material film; a first bit line, the first bit line is located on the first channel pattern and the second channel pattern, wherein the first bit line extends in the second direction and is connected to the first channel pattern; and a second bit line, the second bit line is located on the first channel pattern and the second channel pattern, wherein the second bit line is spaced apart from the first bit line in the first direction, and wherein the second bit line extends in the second direction and is connected to the second channel pattern.

[0007] According to another aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a first source line, the first source line extending in a first direction; a second source line, the second source line extending in the first direction, wherein the second source line is spaced apart from the first source line in a second direction intersecting the first orientation; a first word line, the first word line is located between the first source line and the second source line, wherein the first word line extends in the second direction; a second word line, the second word line is located between the first source line and the second source line, wherein the second word line is spaced apart from the first word line in the first direction and extends in the second direction; a first channel pattern, the first channel pattern is located between the first word line and the second word line, wherein the first channel pattern is connected to the first source line; a second channel pattern, the second channel pattern is located between the first word line and the second word line, wherein the first channel pattern is connected to the first source line; and a second channel pattern, the second channel pattern is located between the first word line and the second word line. between a word line and a second word line, wherein the second channel pattern is connected to the second source line; a first gate insulating film, wherein the first gate insulating film is located between the first word line and the first channel pattern, wherein the first gate insulating film includes a first ferroelectric material film; a second gate insulating film, wherein the second gate insulating film is located between the second word line and the second channel pattern, wherein the second gate insulating film includes a second ferroelectric material film; a first bit line, wherein the first bit line is located on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern and extends in the first direction; and a second bit line, wherein the second bit line is located on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern and is spaced apart from the first bit line in the second direction, and wherein the second bit line extends in the first direction.

[0008] According to another aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a peripheral gate structure, the peripheral gate structure being located on a substrate; a back gate electrode, the back gate electrode being located on the peripheral gate structure, wherein the back gate electrode extends in a first direction; a first word line, the first word line being located between a first back gate electrode and a second back gate electrode among the back gate electrodes, wherein the first back gate electrode and the second back gate electrode are adjacent to each other in a second direction intersecting the first direction, and wherein the first word line extends in the first direction; a second word line, the second word line being located between the first back gate electrode and the second back gate electrode, wherein the second word line extends in the first direction; a first channel pattern, the first channel pattern being located between the first back gate electrode and the first word line; a second channel pattern, the second channel pattern being located between the second back gate electrode and the second word line; a gate separation pattern, the gate separation pattern being located between the first word line and the second word line, wherein the gate separation pattern comprises a horizontal portion and a protrusion, wherein the protrusion of the gate separation pattern is parallel to the first direction and the second direction. protruding from the horizontal portion of the gate separation pattern in an intersecting third direction, wherein the width of the horizontal portion of the gate separation pattern in the second direction is greater than the width of the protrusion of the gate separation pattern in the second direction, and wherein the protrusion of the gate separation pattern is closer to the peripheral gate structure in the third direction than the horizontal portion of the gate separation pattern; a first gate insulating film, the first gate insulating film is located between the first word line and the first channel pattern, wherein the first gate insulating film includes a first ferroelectric material film; a second gate insulating film, the second gate insulating film is located between the second word line and the second channel pattern, wherein the second gate insulating film includes a second ferroelectric material film; a first bit line, the first bit line is located on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern and extends in the second direction; and a second bit line, the second bit line is located on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern, is spaced apart from the first bit line in the first direction, and extends in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a top view layout diagram for describing a semiconductor memory device according to some example embodiments;

[0011] Figure 2 Picture shows Figure 1 A semiconductor memory device without a bit line;

[0012] Figure 3 , Figure 4 and Figure 5 Along the Figure 1 sectional views taken along lines AA', BB' and CC';

[0013] Figure 6 yes Figure 3 An enlarged view of a portion P;

[0014] Figure 7 Is used to describe Figure 1 A top view of a channel pattern;

[0015] Figures 8 to 11 are cross-sectional views each for describing a semiconductor device according to some example embodiments;

[0016] Fig.12 is a top view for describing a semiconductor memory device according to some example embodiments;

[0017] Fig.13 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments;

[0018] Fig.14 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments;

[0019] Fig.15 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments;

[0020] Figures 16 to 32 are views for describing a method of manufacturing a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0021] The terms "first", "second", etc. are used in this article to describe various elements or components, but these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the scope of the present disclosure, the first element or component mentioned below can be referred to as the second element or component.

[0022] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0023] Figure 1 is a top-down layout diagram for describing a semiconductor memory device according to some example embodiments. Figure 2 Picture shows Figure 1 A semiconductor memory device without bit lines. Figure 3 , Figure 4 and Figure 5 Along the Figure 1 Cross-sectional views taken along lines AA', BB' and CC'. Figure 6 yes Figure 3 An enlarged view of part P. Figure 7 Is used to describe Figure 1 Top view of the channel pattern.

[0024] For reference, in Figure 2 1 and 2 (each of the first gate insulating film GI_1 and the second gate insulating film GI_2) is illustrated as a single film, but this is only for convenience of explanation, and the present disclosure is not limited thereto. For example, each of the first gate insulating film GI_1 and the second gate insulating film GI_2 may include a plurality of layers.

[0025] A semiconductor memory device according to some example embodiments of the present disclosure may include a memory cell having a vertical channel transistor (VCT).

[0026] refer to Figures 1 to 7 , a semiconductor memory device according to some example embodiments may include a first source line SL1, a second source line SL2, a first bit line BL1, a second bit line BL2, a first word line WL1, a second word line WL2, a back gate electrode BG, a first channel pattern AP1, and a second channel pattern AP2.

[0027] The substrate 100 may include, for example, silicon, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide.

[0028] The first lower insulating film 121 may be disposed on the substrate 100. The first lower insulating film 121 may include an insulating material.

[0029] The first source line SL1 and the second source line SL2 may be disposed on the substrate 100. For example, the first source line SL1 and the second source line SL2 may be disposed on the first lower insulating film 121.

[0030] Each of the first source line SL1 and the second source line SL2 may include a portion (e.g., a source line extension portion SLe) extending in the first direction D1. The first direction D1 may be a horizontal direction parallel to the upper surface of the substrate 100. The first source line SL1 and the second source line SL2 may be alternately arranged along the second direction D2. The second direction D2 may be a horizontal direction parallel to the upper surface of the substrate 100. The first direction D1 may intersect with the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. In some embodiments, one of the first source lines SL1 may be disposed between the second source lines SL2 adjacent to each other along the second direction D2. In some embodiments, one of the second source lines SL2 may be disposed between the first source lines SL1 adjacent to each other along the second direction D2.

[0031] Each of the first source line SL1 and the second source line SL2 may include a source line extension SLe and a source line protrusion SLp. The source line protrusion SLp is connected to the source line extension SLe.

[0032] The source line extension portion SLe may have a line shape extending in the first direction D1. The source line protrusion SLp may protrude from the source line extension portion SLe in the third direction D3. The third direction D3 may be a vertical direction perpendicular to the upper surface of the substrate 100. The third direction D3 may intersect the first direction D1 and the second direction D2. In each of the first source line SL1 and the second source line SL2, a plurality of source line protrusions SLp may be arranged along the first direction D1.

[0033] In the plurality of first source lines SL1 arranged along the second direction D2, the corresponding source line protrusions SLp may be aligned in the second direction D2. For example, adjacent first source lines SL1 among the plurality of first source lines SL1 may include source line protrusions SLp aligned in the second direction D2. One of the second source lines SL2 may be disposed between adjacent first source lines SL1. In the plurality of second source lines SL2 arranged along the second direction D2, the corresponding source line protrusions SLp may be aligned in the second direction D2. For example, adjacent second source lines SL2 among the plurality of second source lines SL2 may include source line protrusions SLp aligned in the second direction D2. One of the first source lines SL1 may be disposed between adjacent second source lines SL2.

[0034] In the first source line SL1 and the second source line SL2 adjacent to (eg, closest to) each other in the second direction D2, the source line protrusion SLp included in the first source line SL1 may not be aligned with the source line protrusion SLp included in the second source line SL2 in the second direction D2. Fig.16, in a plan view, the source line protrusion SLp included in the first source line SL1 and the source line protrusion SLp included in the second source line SL2 may be arranged in a zigzag pattern along the second direction D2.

[0035] The first and second source lines SL1 and SL2 may include, for example, a conductive material such as a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, and / or a metal alloy.

[0036] In a semiconductor memory device, according to some example embodiments, the two-dimensional material may include a metal material and / or a semiconductor material. The 2D material may include, for example, a two-dimensional allotrope or a two-dimensional compound. For example, the 2D material may include graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and / or tungsten disulfide (WS 2 That is, since the above-mentioned 2D materials are listed only as examples, the 2D materials that can be included in the semiconductor memory device of the present disclosure are not limited to the above-mentioned materials.

[0037] The source line protrusion SLp and the source line extension SLe may form a single structure. A single structure herein may refer to a structure having no visible boundary between at least two of its sub-elements. For example, the boundary between the source line protrusion SLp and the source line extension SLe may not be distinguished, but this is only for ease of explanation, and the present disclosure is not limited thereto. As an example, the source line protrusion SLp and the source line extension SLe may include the same material. As another example, the source line protrusion SLp may include a material different from that of the source line extension SLe.

[0038] The second lower insulating film 122 may be disposed on the first lower insulating film 121. The first source line SL1 and the second source line SL2 may be disposed on the second lower insulating film 122. The source line extensions SLe adjacent to each other in the second direction D2 may be separated by the second lower insulating film 122.

[0039] The second lower insulating film 122 may include an upper portion and a lower portion. The source line extension SLe may be disposed in the lower portion of the second lower insulating film 122. The source line protrusion SLp may be disposed in the upper portion of the second lower insulating film 122. For example, the source line protrusion SLp may be farther from the upper surface of the substrate 100 than the source line extension SLe in the third direction D3.

[0040] The second lower insulating film 122 may include an insulating material. The lower portion of the second lower insulating film 122 and the upper portion of the second lower insulating film 122 may include the same insulating material or different insulating materials. The upper portion of the second lower insulating film 122 and the lower portion of the second lower insulating film 122 may form a single structure. For example, there is no boundary between the lower portion of the second lower insulating film 122 and the upper portion of the second lower insulating film 122, but the present disclosure is not limited thereto.

[0041] The first channel pattern AP1 may be disposed on the first source line SL1 and the second source line SL2 . The second channel pattern AP2 may be disposed on the first source line SL1 and the second source line SL2 . The first channel pattern AP1 and the second channel pattern AP2 may be disposed on the second lower insulating film 122 .

[0042] The first channel pattern AP1 and the second channel pattern AP2 may be alternately disposed along the first direction D1. The first channel pattern AP1 and the second channel pattern AP2 may be disposed on the pair of first source lines SL1 and the second source line SL2. For example, one of the first channel patterns AP1 and one of the second channel patterns AP2 may be disposed on one of the first source lines SL1 and one of the second source lines SL2 adjacent to each other. For example, the pair of adjacent first channel patterns AP1 and the second channel pattern AP2 may overlap with the pair of adjacent first source lines SL1 and the second source line SL in the third direction D3.

[0043] The first channel patterns AP1 may be spaced apart from each other in the second direction D2. The first channel patterns AP1 may be spaced apart from each other at regular intervals. The second channel patterns AP2 may be spaced apart from each other in the second direction D2. The second channel patterns AP2 may be spaced apart from each other at regular intervals. The first channel patterns AP1 and the second channel patterns AP2 may be two-dimensionally arranged along the first direction D1 and the second direction D2 intersecting each other.

[0044] The first channel pattern AP1 may be connected (e.g., electrically connected) to the first source line SL1, and may not be connected to the second source line SL2 (e.g., may be spaced apart from the second source line SL2). The second channel pattern AP2 may be connected (e.g., electrically connected) to the second source line SL2, and may not be connected to the first source line SL1 (e.g., may be spaced apart from the first source line SL1). It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on another element or layer, connected to or coupled to another element or layer, or there may be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly coupled" to another element, "directly connected" to another element, or "directly responsive to" another element, or "directly on" another element, there is no intermediate element. When an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may refer to a physical connection or physical coupling. In addition, "electrical connection" conceptually includes physical connection and physical disconnection. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0045] In some embodiments, each first source line SL1 may be electrically connected to a plurality of first channel patterns AP1 arranged along the first direction D1, and may not be electrically connected to a plurality of second channel patterns AP2 arranged along the first direction D1. Each second source line SL2 may be electrically connected to a plurality of second channel patterns AP2 arranged along the first direction D1, and may not be electrically connected to a plurality of first channel patterns AP1 arranged along the first direction D1.

[0046] The first channel pattern AP1 may be in contact with the source line protrusion SLp of the first source line SL1 The second channel pattern AP2 may be in contact with the source line protrusion SLp of the second source line SL2 .

[0047] exist Figure 6 and Figure 7 In the embodiment, the first channel pattern AP1 and the second channel pattern AP2 may be separated from each other. The first channel pattern AP1 and the second channel pattern AP2 may not be connected.

[0048] The first channel pattern AP1 may include a horizontal portion AP1_H and vertical portions AP1_V1 and AP1_V2 (first and second vertical portions AP1_V1 and AP1_V2 of the first channel pattern AP1). The vertical portions AP1_V1 and AP1_V2 of the first channel pattern AP1 may protrude from the horizontal portion AP1_H of the first channel pattern AP1 in the third direction D3.

[0049] The horizontal portion AP1_H of the first channel pattern AP1 may be connected to the first source line SL1. The horizontal portion AP1_H of the first channel pattern AP1 may be in contact with the source line protrusion SLp of the first source line SL1. The horizontal portion AP1_H of the first channel pattern AP1 may be disposed on a plane formed along the first direction D1 and the second direction D2. In a cross-sectional view, the horizontal portion AP1_H of the first channel pattern AP1 may extend in the first direction D1 and / or the second direction D2.

[0050] The vertical portions AP1_V1 and AP1_V2 of the first channel pattern AP1 may include a first vertical portion AP1_V1 and a second vertical portion AP1_V2. The first vertical portion AP1_V1 of the first channel pattern AP1 and the second vertical portion AP1_V2 of the first channel pattern AP1 may protrude from the horizontal portion AP1_H of the first channel pattern AP1 in the third direction D3. The first vertical portion AP1_V1 of the first channel pattern AP1 may be directly connected to the second vertical portion AP1_V2 of the first channel pattern AP1. In a top view, the first vertical portion AP1_V1 of the first channel pattern AP1 may extend in the second direction D2. The second vertical portion AP1_V2 of the first channel pattern AP1 may protrude from the first vertical portion AP1_V1 of the first channel pattern AP1 in the first direction D1. For example, the shape of the first channel pattern AP1 in a top view may be a shape such as “[”.

[0051] The second channel pattern AP2 may include a horizontal portion AP2_H and vertical portions AP2_V1 and AP2_V2 (first and second vertical portions AP2_V1 and AP2_V2 of the second channel pattern AP2). The vertical portions AP2_V1 and AP2_V2 of the second channel pattern AP2 may protrude from the horizontal portion AP2_H of the second channel pattern AP2 in the third direction D3.

[0052] Although not shown, the horizontal portion AP2_H of the second channel pattern AP2 may be connected to the second source line SL2. The horizontal portion AP2_H of the second channel pattern AP2 may be in contact with the source line protrusion SLp of the second source line SL2. The horizontal portion AP2_H of the second channel pattern AP2 may be disposed on a plane formed along the first direction D1 and the second direction D2. In a cross-sectional view, the horizontal portion AP2_H of the second channel pattern AP2 may extend in the first direction D1 and / or the second direction D2.

[0053] The vertical portions AP2_V1 and AP2_V2 of the second channel pattern AP2 may include a first vertical portion AP2_V1 and a second vertical portion AP2_V2. The first vertical portion AP2_V1 of the second channel pattern AP2 and the second vertical portion AP2_V2 of the second channel pattern AP2 may protrude from the horizontal portion AP2_H of the second channel pattern AP2 in the third direction D3. The first vertical portion AP2_V1 of the second channel pattern AP2 may be directly connected to the second vertical portion AP2_V2 of the second channel pattern AP2. In a top view, the first vertical portion AP2_V1 of the second channel pattern AP2 may extend in the second direction D2. The second vertical portion AP2_V2 of the second channel pattern AP2 may protrude from the first vertical portion AP2_V1 of the second channel pattern AP2 in the first direction D1. For example, the shape of the second channel pattern AP2 in a top view may be a shape such as “]”. In some embodiments, the first channel pattern AP1 may be a mirror image of the second channel pattern AP2 in a top view and / or in a cross-sectional view.

[0054] The first vertical portion AP1_V1 of the first channel pattern AP1 and the first vertical portion AP2_V1 of the second channel pattern AP2 may include a first side wall AP_SW1 and a second side wall AP_SW2 that are opposite in the first direction D1, respectively. For example, the first side wall AP_SW1 may be an outer side wall of the first channel pattern AP1 and / or the second channel pattern AP2. The second side wall AP_SW2 may be an inner side wall of the first channel pattern AP1 and / or the second channel pattern AP2. The second side wall AP_SW2 of the first vertical portion AP1_V1 of the first channel pattern AP1 may face the second side wall AP_SW2 of the first vertical portion AP2_V1 of the second channel pattern AP2.

[0055] The first channel pattern AP1 and / or the second channel pattern AP2 may include, for example, polycrystalline silicon (poly-Si), poly-crystalline silicon germanium, and / or poly-crystalline germanium.

[0056] The first channel pattern AP1 and / or the second channel pattern AP2 may include, for example, an oxide semiconductor material. The first channel pattern AP1 and / or the second channel pattern AP2 may include, for example, a metal oxide. In some embodiments, the first channel pattern AP1 and / or the second channel pattern AP2 may include an amorphous metal oxide film. In some embodiments, the first channel pattern AP1 and / or the second channel pattern AP2 may include a polycrystalline metal oxide film. The first channel pattern AP1 and / or the second channel pattern AP2 may include a combination of an amorphous metal oxide film and a polycrystalline metal oxide film. The first channel pattern AP1 and / or the second channel pattern AP2 may include a c-axis oriented crystallization (CAAC) metal oxide film.

[0057] The first channel pattern AP1 and / or the second channel pattern AP2 may include, for example, indium oxide, tin oxide, zinc oxide, indium zinc oxide (IZO), tin zinc oxide, aluminum zinc oxide, zinc magnesium oxide, tin magnesium oxide, indium magnesium oxide, indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, tin aluminum zinc oxide, indium hafnium zinc oxide, indium lanthanum zinc oxide, indium cerium zinc oxide, indium praseodymium zinc oxide, indium neodymium zinc oxide, indium samarium zinc oxide, indium europium zinc oxide, indium gadolinium zinc oxide, indium terbium zinc oxide, indium dysprosium zinc oxide, indium holmium zinc oxide, indium erbium zinc oxide, indium thulium zinc oxide, indium ytterbium zinc oxide, indium lutetium zinc oxide, indium tin gallium zinc oxide, indium hafnium gallium zinc oxide, indium aluminum gallium zinc oxide, indium tin aluminum zinc oxide, indium tin hafnium zinc oxide and / or indium hafnium aluminum zinc oxide, but is not limited thereto.

[0058] Here, indium gallium zinc oxide may refer to an oxide having In, Ga, and Zn as main components, but does not indicate the ratio of In, Ga, and Zn. That is, taking indium gallium zinc oxide (IGZO) as an example, the first channel pattern AP1 and / or the second channel pattern AP2 may include indium gallium zinc oxide (IGZO, In x Ga y Zn z O). IGZO containing indium, gallium and zinc in the same ratio (In:Ga:Zn=1:1:1) may be indium gallium zinc oxide. Ga-rich IGZO may have a higher gallium ratio than IGZO (In:Ga:Zn=1:1:1), and may have a lower indium ratio than IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO may also be indium gallium zinc oxide. In addition, In-rich IGZO may have a higher indium ratio than IGZO (In:Ga:Zn=1:1:1), and may have a lower gallium ratio than IGZO (In:Ga:Zn=1:1:1). In-rich IGZO may also be indium gallium zinc oxide.

[0059] The first word line WL1 and the second word line WL2 may be disposed on the first source line SL1 and the second source line SL2. For example, the first word line WL1 may be disposed on the first source line SL1 and the second source line SL2. The second word line WL2 may be disposed on the first source line SL1 and the second source line SL2. Each of the first word line WL1 and the second word line WL2 may extend in the second direction D2.

[0060] The first and second word lines WL1 and WL2 may be spaced apart from the first and second source lines SL1 and SL2 in the third direction D3. Each of the first and second word lines WL1 and WL2 may intersect the first and second source lines SL1 and SL2.

[0061] The first word lines WL1 and the second word lines WL2 may be alternately arranged in the first direction D1. The first word lines WL1 may be spaced apart from the second word lines WL2 in the first direction D1.

[0062] The first word line WL1 may be disposed on the first channel pattern AP1. The first word line WL1 may be disposed on a plurality of first channel patterns AP1 arranged along the second direction D2. The first word line WL1 may be disposed on a horizontal portion AP1_H of the first channel pattern AP1. The first word line WL1 may be disposed on a second sidewall AP_SW2 of a first vertical portion AP1_V1 of the first channel pattern AP1.

[0063] The second word line WL2 may be disposed on the second channel pattern AP2. The second word line WL2 may be disposed on a plurality of second channel patterns AP2 arranged along the second direction D2. The second word line WL2 may be disposed on a horizontal portion AP2_H of the second channel pattern AP2. The second word line WL2 may be disposed on a second side wall AP_SW2 of a first vertical portion AP2_V1 of the second channel pattern AP2.

[0064] The first channel pattern AP1 may be closer to the first word line WL1 than to the second word line WL2. The second channel pattern AP2 may be closer to the second word line WL2 than to the first word line WL1.

[0065] The first word line WL1 and the second word line WL2 may be disposed between the first channel pattern AP1 and the second channel pattern AP2. For example, the first word line WL1 and the second word line WL2 may be disposed between adjacent (e.g., paired) first channel patterns AP1 and second channel patterns AP2. Since the first word line WL1 and the second word line WL2 are alternately disposed along the first direction D1, and the first channel pattern AP1 and the second channel pattern AP2 are alternately disposed along the first direction D1, the first channel pattern AP1 and the second channel pattern AP2 may be disposed between the first word line WL1 and the second word line WL2.

[0066] The first word line WL1 may include a horizontal portion WL1_H and a vertical portion WL1_V. The vertical portion WL1_V of the first word line WL1 may protrude from the horizontal portion WL1_H of the first word line WL1 in the third direction D3.

[0067] The second word line WL2 may include a horizontal portion WL2_H and a vertical portion WL2_V. The vertical portion WL2_V of the second word line WL2 may protrude from the horizontal portion WL2_H of the second word line WL2 in the third direction D3. Figure 3 and Figure 4In the cross-sectional view of FIG. 1 , the first word line WL1 and the second word line WL2 may be in an “L” shape. In some embodiments, the first word line WL1 may be a mirror image of the second word line WL2 in the cross-sectional view.

[0068] Each of the first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 opposite to each other in the third direction D3. The second surface WL_S2 of the first word line WL1 may face the horizontal portion AP1_H of the first channel pattern AP1. The second surface WL_S2 of the second word line WL2 may face the horizontal portion AP2_H of the second channel pattern AP2.

[0069] Each of the vertical portions WL1_V and WL2_V of the first and second word lines WL1 and WL2 may include a first surface WL_S1 of the corresponding word line. Each of the horizontal portions WL1_H and WL2_H of the first and second word lines WL1 and WL2 may include a second surface WL_S2 of the corresponding word line.

[0070] The first surface WL_S1 of the first word line WL1 and the second word line WL2 may be lower than the uppermost portion of the first vertical portion AP1_V1 of the first channel pattern AP1 and the uppermost portion of the first vertical portion AP2_V1 of the second channel pattern AP2 with respect to the upper surface of the second lower insulating film 122. The uppermost portion of the first channel pattern AP1 may be the uppermost portion of the first vertical portion AP1_V1 of the first channel pattern AP1, and the uppermost portion of the second channel pattern AP2 may be the uppermost portion of the first vertical portion AP2_V1 of the second channel pattern AP2.

[0071] exist Figure 6 1 and 2 illustrate that the first surface WL1 of the first word line WL1 and the second word line WL2 is flat, but the present disclosure is not limited thereto. Different from the illustration, as an example, the first surface WL_S1 of the first word line WL1 and the second word line WL2 may be convex. As another example, the first surface WL_S1 of the first word line WL1 and the second word line WL2 may be concave.

[0072] The first word line WL1 and the second word line WL2 may include a conductive material, such as doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal.

[0073] The first gate insulating film GI_1 may be disposed between the first word line WL1 and the first channel pattern AP1. The first gate insulating film GI_1 may extend along the horizontal portion AP1_H of the first channel pattern AP1, the first vertical portion AP1_V1 of the first channel pattern AP1, and the second vertical portion AP1_V2 of the first channel pattern AP1.

[0074] The second gate insulating film GI_2 may be disposed between the second word line WL2 and the second channel pattern AP2. The second gate insulating film GI_2 may extend along the horizontal portion AP2_H of the second channel pattern AP2, the first vertical portion AP2_V1 of the second channel pattern AP2, and the second vertical portion AP2_V2 of the second channel pattern AP2. In some embodiments, the first gate insulating film GI_1 may be separated from the second gate insulating film GI_2.

[0075] A portion of the first gate insulating film GI_1 and a portion of the second gate insulating film GI_2 may protrude further than the first surfaces WL_S1 of the word lines WL1 and WL2 in the third direction D3. For example, the upper surfaces of the first gate insulating film GI_1 and the second gate insulating film GI_2 may be disposed higher than the first surfaces WL_S1 of the first word lines WL1 and WL2 relative to the upper surface of the second lower insulating film 122.

[0076] The first gate insulating film GI_1 may include a first gate insulating oxide film GOX1 and a first ferroelectric material film FE1. The first gate insulating oxide film GOX1 may be disposed between the first channel pattern AP1 and the first ferroelectric material film FE1. The second gate insulating film GI_2 may include a second gate insulating oxide film GOX2 and a second ferroelectric material film FE2. The second gate insulating oxide film GOX2 may be disposed between the second channel pattern AP2 and the second ferroelectric material film FE2.

[0077] exist Figure 2 In some example embodiments, a semiconductor memory device may include a first sub memory cell region MC_SB1 and a second sub memory cell region MC_SB2 spaced apart from each other in a second direction D2. Each of the first sub memory cell region MC_SB1 and the second sub memory cell region MC_SB2 may be defined between a pair of first and second word lines WL1 and WL2 and a pair of first and second channel patterns AP1 and AP2. The first sub memory cell region MC_SB1 and the second sub memory cell region MC_SB2 may be disposed between back gate electrodes BG adjacent to each other.

[0078] In a semiconductor memory device according to some example embodiments, the first gate insulating film GI_1 included in the first sub memory cell region MC_SB1 may not be connected to the first gate insulating film GI_1 included in the second sub memory cell region MC_SB2. The second gate insulating film GI_2 included in the first sub memory cell region MC_SB1 may not be connected to the second gate insulating film GI_2 included in the second sub memory cell region MC_SB2.

[0079] The first gate insulating film GI_1 included in the first sub memory cell region MC_SB1 may be separated from the first gate insulating film GI_1 included in the second sub memory cell region MC_SB2. The second gate insulating film GI_2 included in the first sub memory cell region MC_SB1 may be separated from the second gate insulating film GI_2 included in the second sub memory cell region MC_SB2.

[0080] The first gate insulating oxide film GOX1 and the second gate insulating oxide film GOX2 may include silicon oxide. For example, the first gate insulating oxide film GOX1 and the second gate insulating oxide film GOX2 may include silicon oxide films.

[0081] The first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include a ferroelectric material. For example, the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may be formed of a ferroelectric material.

[0082] The first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, hafnium oxide, zirconium hafnium oxide, strontium barium titanium oxide, barium titanium oxide and / or lead zirconium titanium oxide. Here, as an example, zirconium hafnium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). Hafnium zirconium oxide may also be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O). The above-mentioned ferroelectric materials are merely examples, and the technical scope of the present disclosure is not limited thereto.

[0083] The first ferroelectric material film FE1 and the second ferroelectric material film FE2 may also include doped dopants. For example, the dopants may include, for example, aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). Depending on which ferroelectric material the first ferroelectric material film FE1 and the second ferroelectric material film FE2 include, the types of dopants included in the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may be different.

[0084] When the first ferroelectric material film FE1 and the second ferroelectric material film FE2 include hafnium oxide, dopants included in the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and / or yttrium (Y).

[0085] When the dopant is aluminum (Al), the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, 3 to 8 at% (atomic percentage) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, 2 to 10 at% of silicon. When the dopant is yttrium (Y), the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, 2 to 10 at% of yttrium. When the dopant is gadolinium (Gd), the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may include, for example, 50 to 80 at% of zirconium.

[0086] The first ferroelectric material film FE1 and the second ferroelectric material film FE2 may have a thickness that exhibits ferroelectric properties. The thickness of the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness that exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the first ferroelectric material film FE1 and the second ferroelectric material film FE2 may vary depending on the ferroelectric material thereof.

[0087] The gate separation pattern GSS may be disposed on the second lower insulating film 122, the first source line SL1, and the second source line SL2. The gate separation pattern GSS may be disposed on the first channel pattern AP1, the second channel pattern AP2, the first word line WL1, and the second word line WL2.

[0088] In a semiconductor memory device according to some example embodiments, a gate separation pattern GSS may contact the first channel pattern AP1 and the second channel pattern AP2. The gate separation pattern GSS may contact the horizontal portion AP1_H of the first channel pattern AP1 and the horizontal portion AP2_H of the second channel pattern AP2. The gate separation pattern GSS may separate the first channel pattern AP1 and the second channel pattern AP2.

[0089] The gate separation pattern GSS may be disposed between the first and second word lines WL1 and WL2 adjacent to each other in the first direction D1. The first and second word lines WL1 and WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend in the second direction D2 between the first and second word lines WL1 and WL2.

[0090] The first word line WL1 may be disposed between the gate separation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second channel pattern AP2.

[0091] The gate separation pattern GSS may include a horizontal portion GSS_H and a protrusion GSS_P. The horizontal portion GSS_H of the gate separation pattern GSS may be disposed on the first surfaces WL_S1 of the word lines WL1 and WL2. The horizontal portion GSS_H of the gate separation pattern GSS may overlap with (eg, cover) the first surfaces WL_S1 of the word lines WL1 and WL2.

[0092] The protrusion GSS_P of the gate separation pattern GSS may protrude from the horizontal portion GSS_H of the gate separation pattern GSS toward the source line SL1 or SL2 in the third direction D3. The width of the horizontal portion GSS_H of the gate separation pattern GSS in the first direction D1 may be greater than the width of the protrusion GSS_P of the gate separation pattern GSS in the first direction D1. In a cross-sectional view, the gate separation pattern GSS may have a "T" shape.

[0093] The protrusion GSS_P of the gate separation pattern GSS may be disposed between the first word line WL1 and the second word line WL2 adjacent to each other in the first direction D1. In the semiconductor memory device according to some example embodiments, the first channel pattern AP1 and the second channel pattern AP2 may be separated by the protrusion GSS_P of the gate separation pattern GSS. The horizontal portion AP1_H of the first channel pattern AP1 and the horizontal portion AP2_H of the second channel pattern AP2 may contact the protrusion GSS_P of the gate separation pattern GSS.

[0094] The gate separation pattern GSS may include an insulating material. The gate separation pattern GSS is illustrated as a single film, but this is only for convenience of explanation, and the present disclosure is not limited thereto.

[0095] The back gate electrode BG may be disposed on the first source line SL1 and the second source line SL2. The back gate electrode BG may extend in the second direction D2. The back gate electrodes BG may be spaced apart from each other in the first direction D1. The back gate electrodes BG may be spaced apart from each other at regular intervals.

[0096] Each back gate electrode BG may be disposed between first and second channel patterns AP1 and AP2 adjacent to each other in the first direction D1. In the first direction D1, the first channel pattern AP1 may be disposed on one side of each back gate electrode BG, and the second channel pattern AP2 may be disposed on the other side of each back gate electrode BG.

[0097] Each back gate electrode BG may be disposed between first and second word lines WL1 and WL2 adjacent to each other in the first direction D1. In the first direction D1, the first word line WL1 may be disposed on one side of each back gate electrode BG, and the second word line WL2 may be disposed on the other side of each back gate electrode BG.

[0098] In other words, a pair of first and second word lines WL1 and WL2 may be disposed between back gate electrodes BG adjacent to each other along the first direction D1. First and second channel patterns AP1 and AP2 (eg, a pair of first and second channel patterns AP1 and AP2) may be disposed between back gate electrodes BG adjacent to each other along the first direction D1.

[0099] A plurality of first channel patterns AP1 aligned in the second direction D2 may be disposed between the first word line WL1 (e.g., the closest first word line WL1 in the first direction D1) and the back gate electrode BG (e.g., the closest back gate electrode BG in the first direction D1). A plurality of second channel patterns AP2 aligned in the second direction D2 may be disposed between the second word line WL2 (e.g., the closest second word line WL2 in the first direction D1) and the back gate electrode BG (e.g., the closest back gate electrode BG in the first direction D1).

[0100] The back gate electrode BG may be disposed on the first side wall AP_SW1 of the first vertical portion AP1_V1 of the first channel pattern AP1. The back gate electrode BG may be disposed on the first side wall AP_SW1 of the first vertical portion AP2_V1 of the second channel pattern AP2. The first side wall AP_SW1 of the first vertical portion AP1_V1 of the first channel pattern AP1 and the first side wall AP_SW1 of the first vertical portion AP2_V1 of the second channel pattern AP2 may face the back gate electrode BG.

[0101] The back gate electrode BG may be disposed on the first sidewall AP_SW1 of the first vertical portions AP1_V1 and AP2_V1 of the channel patterns AP1 and AP2. The word lines WL1 and WL2 may be disposed on the second sidewall AP_SW2 of the first vertical portions AP1_V1 and AP2_V1 of the channel patterns AP1 and AP2.

[0102] The back gate electrode BG may include a conductive material, such as doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material and / or metal. During operation of the semiconductor memory device, a voltage may be applied to the back gate electrode BG to adjust the threshold voltage of the vertical channel transistor. As the threshold voltage of the vertical channel transistor is adjusted, degradation of the leakage current characteristic may be improved (e.g., reduced or prevented).

[0103] The back gate insulating film 113 may be disposed between the back gate electrode BG and the first channel pattern AP1 and between the back gate electrode BG and the second channel pattern AP2. The back gate insulating film 113 may be disposed between the back gate electrode BG and the second lower insulating film 122. The back gate insulating film 113 may extend along the sidewall and lower surface of the back gate electrode BG.

[0104] The back gate insulating film 113 may include, for example, silicon oxide. For example, the back gate insulating film 113 may include a silicon oxide film.

[0105] The thickness t1 of the back gate insulating film 113 in the first direction D1 may be different from the thickness t2 of the first gate insulating oxide film GOX1 in the first direction D1 and the thickness t2 of the second gate insulating oxide film GOX2 in the first direction D1. For example, the thickness t1 of the back gate insulating film 113 in the first direction D1 may be greater than the thickness t2 of the first gate insulating oxide film GOX1 in the first direction D1 and / or the thickness t2 of the second gate insulating oxide film GOX2 in the first direction D1.

[0106] Here, the thickness t1 of the back gate insulating film 113 in the first direction D1 may be the thickness between the back gate electrode BG and the first channel pattern AP1 and / or the thickness between the back gate electrode BG and the second channel pattern AP2 in the first direction D1. The thickness t2 of the first gate insulating oxide film GOX1 in the first direction D1 may be the thickness between the first ferroelectric material film FE1 and the first vertical portion AP1_V1 of the first channel pattern AP1. The thickness t2 of the second gate insulating oxide film GOX2 in the first direction D1 may be the thickness between the second ferroelectric material film FE2 and the first vertical portion AP2_V1 of the second channel pattern AP2.

[0107] Since the thickness t1 is greater than the thickness t2 , a memory window between a read operation and a write operation of the semiconductor memory device may be increased.

[0108] The first and second bit lines BL1 and BL2 may be disposed on the first and second channel patterns AP1 and AP2. The first and second bit lines BL1 and BL2 may be disposed on the first and second word lines WL1 and WL2.

[0109] Each of the first bit line BL1 and the second bit line BL2 may extend in the first direction D1. The first bit line BL1 and the second bit line BL2 may be alternately arranged along the second direction D2. The first bit line BL1 may be disposed between the second bit lines BL2 adjacent to each other along the second direction D2. The second bit line BL2 may be disposed between the first bit lines BL1 adjacent to each other along the second direction D2.

[0110] Each first bit line BL1 may be disposed on a corresponding first source line SL1. Each second bit line BL2 may be disposed on a corresponding second source line SL2.

[0111] Each of the first and second bit lines BL1 and BL2 may include a bit line extension BLe and a plurality of bit line protrusions BLp. Each of the bit line protrusions BLp may be connected to the bit line extension BLe.

[0112] The bit line extension BLe may be in a line shape extending in the first direction D1. Each bit line protrusion BLp may protrude from the bit line extension BLe in the third direction D3. In each of the first bit line BL1 and the second bit line BL2, a plurality of bit line protrusions BLp may be arranged along the first direction D1. For example, the first bit line BL1 may include a plurality of bit line protrusions BLp arranged along the first direction D1. For example, the second bit line BL2 may include a plurality of bit line protrusions BLp arranged along the first direction D1.

[0113] Among the plurality of first bit lines BL1 arranged along the second direction D2, the corresponding bit line protrusions BLp may be aligned in the second direction D2. For example, adjacent first bit lines BL1 among the plurality of first bit lines BL1 may include bit line protrusions BLp aligned in the second direction D2. One of the second bit lines BL2 may be disposed between the adjacent first bit lines BL1. Among the plurality of second bit lines BL2 arranged along the second direction D2, the corresponding bit line protrusions BLp may be aligned in the second direction D2. For example, adjacent second bit lines BL2 among the plurality of second bit lines BL2 may include bit line protrusions BLp aligned in the second direction D2. One of the first bit lines BL1 may be disposed between the adjacent second bit lines BL2.

[0114] In the first bit line BL1 and the second bit line BL2 that are closest to each other in the second direction D2, the bit line protrusion BLp included in the first bit line BL1 may not be aligned with the bit line protrusion BLp included in the second bit line BL2 in the second direction D2. In a top view, the bit line protrusion BLp included in the first bit line BL1 and the bit line protrusion BLp included in the second bit line BL2 may be arranged in a zigzag shape in the second direction D2.

[0115] The first channel pattern AP1 may be connected (e.g., electrically connected) to the first bit line BL1, and may not be connected to the second bit line BL2 (e.g., may be spaced apart from the second bit line BL2). The second channel pattern AP2 may be connected (e.g., electrically connected) to the second bit line BL2, and may not be connected to the first bit line BL1 (e.g., may be spaced apart from the first bit line BL1).

[0116] In other words, each first bit line BL1 may be electrically connected to the plurality of first channel patterns AP1 arranged along the first direction D1, and may not be electrically connected to the plurality of second channel patterns AP2 arranged along the first direction D1. Each second bit line BL2 may be electrically connected to the plurality of second channel patterns AP2 arranged along the first direction D1, and may not be electrically connected to the plurality of first channel patterns AP1 arranged along the first direction D1.

[0117] The first channel pattern AP1 may be in contact with and connected to the bit line protrusion BLp of the first bit line BL1. The second channel pattern AP2 may be in contact with and connected to the bit line protrusion BLp of the second bit line BL2.

[0118] The first bit line BL1 and the second bit line BL2 may include a conductive material, such as a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal and / or a metal alloy. The bit line protrusion BLp and the bit line extension BLe may form a single structure. For example, the boundary between the bit line protrusion BLp and the bit line extension BLe may not be distinguished, but this is only for ease of description and the present disclosure is not limited thereto.

[0119] Unlike the above, the first bit line BL1 may be connected to the second channel pattern AP2 and may not be connected to the first channel pattern AP1. The second bit line BL2 may be connected to the first channel pattern AP1 and may not be connected to the second channel pattern AP2.

[0120] The third lower insulating film 123 may be disposed on the channel patterns AP1 and AP2, the back gate electrode BG, and the word lines WL1 and WL2. The first bit line BL1 and the second bit line BL2 may be disposed in the third lower insulating film 123. The bit line extensions BLe adjacent to each other in the second direction D2 may be separated by the third lower insulating film 123. The third lower insulating film 123 may include an insulating material.

[0121] Figures 8 to 11 are cross-sectional views each for describing a semiconductor device according to some example embodiments. Fig.12 is a top view for describing a semiconductor memory device according to some example embodiments. Fig.13 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments. Figures 1 to 7 The points described are different.

[0122] For reference, Figures 8 to 11 yes Figure 3 An enlarged view of part P. Fig.12 A top view of a semiconductor memory device without bit lines is shown.

[0123] refer to Figures 8 to 10 In a semiconductor memory device according to some example embodiments, first and second channel patterns AP1 and AP2 that are closest to (eg, adjacent to) each other (eg, a pair of first and second channel patterns AP1 and AP2 ) may be connected by a connecting channel pattern AP_CP.

[0124] The connection channel pattern AP_CP may be directly connected to the first and second channel patterns AP1 and AP2. The connection channel pattern AP_CP may be disposed on the second lower insulating film 122. The connection channel pattern AP_CP may include the same material as the first and second channel patterns AP1 and AP2.

[0125] With respect to the first word line WL1 and the second word line WL2, a first channel pattern AP1, a second channel pattern AP2, and a connecting channel pattern AP_CP may be distinguished. The first word line WL1 will be described as an example. The first word line WL1 may include an inner sidewall of a first vertical portion AP1_V1 facing the first channel pattern AP1 and an outer sidewall in an "L" shape. The boundary between the first channel pattern AP1 and the connecting channel pattern AP_CP may be an extension line of the outer sidewall of the first word line WL1 included in the horizontal portion WL1_H of the first word line WL1 extending in the third direction D3. For example, the boundary between the first channel pattern AP1 and the connecting channel pattern AP_CP may be aligned with the outer sidewall of the horizontal portion WL1_H of the first word line WL1 in the third direction D3.

[0126] The gate separation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate separation pattern GSS may not separate the first channel pattern AP1 and the second channel pattern AP2.

[0127] exist Figure 8 In the embodiment, the first gate insulating film GI_1 may not be connected to the second gate insulating film GI_2. The first gate insulating film GI_1 and the second gate insulating film GI_2 may be separated by the gate separation pattern GSS.

[0128] exist Fig. 9 and Fig.10 In the embodiment, the first gate insulating film GI_1 may be connected to the second gate insulating film GI_2.

[0129] exist Fig. 9In the embodiment, the first gate insulating oxide film GOX1 included in the first gate insulating film GI_1 can be connected to the second gate separating oxide film GOX2 included in the second gate insulating film GI_2. However, the first ferroelectric material film FE1 included in the first gate insulating film GI_1 can be separated from the second ferroelectric material film FE2 included in the second gate insulating film GI_2.

[0130] exist Fig.10 In the embodiment, the first gate insulating oxide film GOX1 and the first ferroelectric material film FE1 may be connected to the second gate insulating oxide film GOX2 and the second ferroelectric material film FE2, respectively. The gate separation pattern GSS may not separate the first gate insulating film GI_1 and the second gate insulating film GI_2.

[0131] refer to Fig.11 , in a semiconductor memory device according to some example embodiments, the first word line WL1 and the second word line WL2 may not have an “L” shape in a cross-sectional view.

[0132] For example, the first word line WL1 and the second word line WL2 may have an “I” shape.

[0133] refer to Fig.12 , in the semiconductor memory device according to some example embodiments, the first gate insulating film GI_1 included in the first sub memory cell region MC_SB1 may be connected to the first gate insulating film GI_1 included in the second sub memory cell region MC_SB2 .

[0134] The second gate insulating film GI_2 included in the first sub memory cell region MC_SB1 may be connected to the second gate insulating film GI_2 included in the second sub memory cell region MC_SB2.

[0135] In some embodiments, the first gate insulating film GI_1 included in the first sub-memory cell region MC_SB1 may be formed by a first ferroelectric material film ( Figure 3 and Figure 4 FE1 in the memory cell region MC_SB2 is connected to the second gate insulation film GI_2 included in the second sub-memory cell region MC_SB2.

[0136] In some embodiments, the first gate insulating film GI_1 included in the first sub memory cell region MC_SB1 may be connected to the second gate insulating film GI_2 included in the second sub memory cell region MC_SB2 through the first gate insulating oxide film GOX1 and the first ferroelectric material film FE1.

[0137] refer to Fig.13, in the semiconductor memory device according to some example embodiments, the first bit line BL1 may be disposed between the substrate 100 and the first channel pattern AP1 and between the substrate 100 and the second channel pattern AP2 .

[0138] The first bit line BL2 may be disposed in the second lower insulating film 122. The first source line SL1 may be disposed in the third lower insulating film 123.

[0139] Fig.14 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments. Figures 1 to 7 The points described are different.

[0140] refer to Fig.14 , the semiconductor memory device according to some example embodiments may further include a peripheral gate structure PG.

[0141] The peripheral gate structure PG may be disposed on the substrate 100. The peripheral gate structure PG may be included in a readout transistor, a transfer transistor, a driving transistor, etc. The type of transistor disposed in the peripheral gate structure PG may vary depending on the design arrangement of the semiconductor memory device.

[0142] The peripheral gate structure PG may include a peripheral gate insulating film 215, a lower peripheral conductive pattern 223, and an upper peripheral conductive pattern 225. The peripheral gate insulating film 215 may include, for example, a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a dielectric constant higher than that of the silicon oxide film, and / or a combination thereof. The high-k insulating film may include, for example, a metal oxide, a metal oxynitride, a metal silicon oxide, and / or a metal silicon oxynitride, but is not limited thereto.

[0143] Each of the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may include a conductive material. For example, each of the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may include a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and / or a metal. The peripheral gate structure PG is illustrated to include a plurality of conductive patterns (e.g., a lower peripheral conductive pattern 223 and an upper peripheral conductive pattern 225), but the present disclosure is not limited thereto.

[0144] The first and second lower peripheral insulating films 227 and 228 may be disposed on the substrate 100. Each of the first and second lower peripheral insulating films 227 and 228 may include an insulating material.

[0145] The first peripheral wiring line 241a and the peripheral contact plug 241b may be disposed in the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. It is illustrated that the first peripheral wiring line 241a and the peripheral contact plug 241b are disposed in different films, but the present disclosure is not limited thereto. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b may not be distinguished. Each of the first peripheral wiring line 241a and the peripheral contact plug 241b may include, for example, a conductive material.

[0146] The first and second peripheral upper insulating films 261 and 262 may be disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The second peripheral upper insulating film 262 may be located on the first peripheral upper insulating film 261. Each of the first and second peripheral upper insulating films 261 and 262 may include, for example, an insulating material.

[0147] The second peripheral wiring line 243 and the peripheral via plug 242 may be disposed on the first peripheral wiring line 241 a. The peripheral via plug 242 may be disposed in the first upper peripheral insulating film 261. The second peripheral wiring line 243 may be disposed in the second upper peripheral insulating film 262.

[0148] The second peripheral wiring line 243 and the peripheral via plug 242 can be connected to the first peripheral wiring line 241a. The peripheral via plug 242 can connect the first peripheral wiring line 241a and the second peripheral wiring line 243. Each of the second peripheral wiring line 243 and the peripheral via plug 242 may include, for example, a conductive material. It is illustrated that the second peripheral wiring line 243 and the peripheral via plug 242 are different films, but the present disclosure is not limited to this. For example, the peripheral via plug 242 and the second peripheral wiring line 243 can form a single structure. The boundary between the second peripheral wiring line 243 and the peripheral via plug 242 may not be distinguished.

[0149] The first source line SL1 , the second source line SL2 , the first bit line BL1 , the second bit line BL2 , the first word line WL1 , the second word line WL2 , the back gate electrode BG, the first channel pattern AP1 , and the second channel pattern AP2 may be disposed on the peripheral gate structure PG.

[0150] The cell connection plug 244 may be disposed in the first lower insulating film 121. The cell connection plug 244 may be connected to the second peripheral wiring line 243. The cell connection plug 244 may include, for example, a conductive material.

[0151] The first bit line BL1 may be disposed on the cell connection plug 244. The first bit line BL1 may be connected to the cell connection plug 244. Although not shown, the second bit line ( Figure 1The BL2 in FIG. 2 may be disposed on the cell connection plug 244 and connected to the cell connection plug 244 .

[0152] The description of the first source line SL1, the second source line SL2, the first bit line BL1, the second bit line BL2, the first word line WL1, the second word line WL2, the back gate electrode BG, the first channel pattern AP1 and the second channel pattern AP2 may be the same as that of the reference Figures 1 to 13 Those described are substantially the same and thus may be omitted below.

[0153] The protruding portion GSS_P (reference Figure 6 The GSS_P in the third direction D3 can be separated from the horizontal portion GSS_H (reference Figure 6 The protrusion GSS_P of the gate separation pattern GSS may protrude from the horizontal portion GSS_H of the gate separation pattern GSS toward the peripheral gate structure PG in the third direction D3. The protrusion GSS_P of the gate separation pattern GSS may be closer to the peripheral gate structure PG than the horizontal portion GSS_H of the gate separation pattern GSS.

[0154] Fig.15 is a cross-sectional view for describing a semiconductor memory device according to some example embodiments. Fig.14 Those parts that are described are different.

[0155] refer to Fig.15 , the semiconductor memory device according to some example embodiments may further include a first bonding pad BP1 and a second bonding pad BP2 .

[0156] The first bonding pad BP1 and the first pad plug 281 may be disposed on the second peripheral wiring line 243. The third peripheral upper insulating film 263 may be disposed on the second peripheral upper insulating film 262. The first bonding pad BP1 and the first pad plug 281 may be disposed in the third peripheral upper insulating film 263.

[0157] The first pad plug 281 may be disposed between the first bonding pad BP1 and the second peripheral wiring line 243. The first pad plug 281 may connect the first bonding pad BP1 and the second peripheral wiring line 243.

[0158] The second bonding pad BP2 and the second pad plug 282 may be disposed on the first bonding pad BP1. The fourth lower insulating film 124 may be disposed on the third peripheral upper insulating film 263. The second bonding pad BP2 and the second pad plug 282 may be disposed in the fourth lower insulating film 124.

[0159] The second bonding pad BP2 may be connected (e.g., electrically connected) to the first bonding pad BP1. For example, the second bonding pad BP2 may be in contact with the first bonding pad BP1. Since the second bonding pad BP2 is electrically connected to the first bonding pad BP1, the second bonding pad BP2 may be connected (e.g., electrically connected) to the first peripheral wiring line 241a and the second peripheral wiring line 243.

[0160] The first bit line BL1 may be disposed on the second bonding pad BP2. Although not shown, the second bit line ( Figure 1 The BL2) in the embodiment may be disposed on the second bonding pad BP2.

[0161] The second pad plug 282 may be disposed between the first bit line BL1 and the second bonding pad BP2. The second pad plug 282 may connect (eg, electrically connect) the first bit line BL1 and the second bonding pad BP2.

[0162] Since the second bonding pad BP2 is connected (eg, electrically connected) to the first bonding pad BP1 , the first and second peripheral wiring lines 241 a and 243 may be connected (eg, electrically connected) to the first and second bit lines BL1 and BL2 .

[0163] The first pad plug 281 and the second pad plug 282 may include, for example, a conductive material including a metal. Each of the first bonding pad BP1 and the second bonding pad BP2 may include a conductive material including a metal. It is illustrated that each of the first pad BP1 and the second pad BP2 is a single film, but this is only for convenience of explanation, and the present disclosure is not limited thereto.

[0164] Each of the fourth lower insulating film 124 and the third peripheral upper insulating film 263 may include, for example, an insulating material. It is illustrated that the boundary between the fourth lower insulating film 124 and the third peripheral upper insulating film 263 is distinguished, but this is only for ease of explanation, and the present disclosure is not limited thereto. For example, the fourth lower insulating film 124 and the third peripheral upper insulating film 263 may form a single structure. When the fourth lower insulating film 124 and the third peripheral upper insulating film 263 include the same material, the boundary between the fourth lower insulating film 124 and the third peripheral upper insulating film 263 may not be distinguished. In this case, the boundary between the first bonding pad BP1 and the second bonding pad BP2 may be used to distinguish the boundary between the fourth lower insulating film 124 and the third peripheral upper insulating film 263.

[0165] Although not shown, a bonding insulating film may be further provided between the fourth lower insulating film 124 and the third upper peripheral insulating film 263. For example, the bonding insulating film may include SiCN, but is not limited thereto.

[0166] A first source line SL1 , a second source line SL2 , a first word line WL1 , a second word line WL2 , a back gate electrode BG, a first channel pattern AP1 , and a second channel pattern AP2 may be disposed on the first bit line BL1 and the second bit line BL2 .

[0167] Figures 16 to 32 are views for describing a method of manufacturing a semiconductor memory device according to some example embodiments.

[0168] refer to Fig.16 and Fig.17 , a first lower insulating film 121 may be formed on the substrate 100 .

[0169] The first source line SL1 and the second source line SL2 may be formed on the first lower insulating film 121. Each of the first source line SL1 and the second source line SL2 may include a source line extension portion SLe and a source line protrusion SLp. The second lower insulating film 122 may be formed on the first lower insulating film 121. The second lower insulating film 122 may be formed around the first source line SL1 and the second source line SL2. The second lower insulating film 122 may not cover the upper surface of the source line protrusion SLp of the first source line SL1 and the upper surface of the source line protrusion SLp of the second source line SL2, or may not overlap with the upper surface of the source line protrusion SLp of the first source line SL1 and the upper surface of the source line protrusion SLp of the second source line SL2.

[0170] For example, source line extensions SLe of the first and second source lines SL1 and SL2 may be formed on the first lower insulating film 121 . Source line extensions SLe of the first and second source lines SL1 and SL2 and a portion of the second lower insulating film 122 may be formed on the first lower insulating film 121 .

[0171] Then, the source line protrusion SLp of the first source line SL1 and the source line protrusion SLp of the second source line SL2 may be formed. The remaining portion of the second lower insulating film 122 may be formed around the source line protrusion SLp of the first source line SL1 and the second source line SL2.

[0172] refer to Fig.18 and Fig.19 , a sacrificial film 50 may be formed on the second lower insulating film 122 .

[0173] The sacrificial film 50 may include a plurality of channel trenches CH_T. The plurality of channel trenches CH_T may be arranged in a grid shape along the first direction D1 and the second direction D2.

[0174] Each channel trench CH_T may have, for example, a quadrangular shape in a plan view. Each channel trench CH_T may expose one source line protrusion SLp included in the first source line SL1 and one source line protrusion SLp included in the second source line SL2.

[0175] The sacrificial film 50 may include, for example, an insulating material. The sacrificial film 50 may include a material having an etching selectivity with respect to the second lower insulating film 122. For example, when the second lower insulating film 122 includes silicon oxide, the sacrificial film 50 may include silicon nitride, but is not limited thereto.

[0176] refer to Fig. 20 and Fig.21 , a pre-channel pattern AP_P may be formed in each channel trench CH_T.

[0177] A pre-channel pattern AP_P may be formed along the sidewall and lower surface of the channel trench CH_T. The pre-channel pattern AP_P may be connected to the exposed source line protrusion SLp of the first source line SL1. The pre-channel pattern AP_P may be connected to the exposed source line protrusion SLp of the second source line SL2.

[0178] A pre-gate insulating film GI_P may be formed on the pre-channel pattern AP_P. A pre-gate insulating film GI_P may be formed in each channel trench CH_T. The pre-gate insulating film GI_P may be formed along the sidewalls and lower surface of the channel trench CH_T. The pre-gate insulating film GI_P may be formed along the sidewalls and lower surface of the pre-channel pattern AP_P. The pre-gate insulating film GI_P may include a pre-gate insulating oxide film GOX_P and a pre-ferroelectric material film PE_P.

[0179] A sacrificial filling pattern 55 may be formed on the pre-gate insulating film GI_P. The sacrificial filling pattern 55 may fill the channel trench CH_T remaining after the pre-channel pattern AP_P and the pre-gate insulating film GI_P are formed. The sacrificial filling pattern 55 may include the same material as the sacrificial film 50 .

[0180] refer to Fig. 22 and Fig.24 , a word line trench WL_T may be formed on the second lower insulating film 122 .

[0181] The word line trench WL_T may be formed by removing a portion of the sacrificial film 50 (and / or the sacrificial filling pattern 55), a portion of the pre-channel pattern AP_P, and a portion of the pre-gate insulating film GI_P. When the word line trench WL_T is formed, the sacrificial filling pattern 55 may be removed. The word line trench WL_T may extend in the second direction D2.

[0182] When the word line trench WL_T is formed, the pre-channel pattern AP_P and the pre-gate insulating film GI_P may not be divided into two parts. Fig.24 In the embodiment, a lower surface of the word line trench WL_T may be defined by the sacrificial film 50 , the pre-channel pattern AP_P, and the pre-gate insulating film GI_P.

[0183] refer to Fig.25 and Fig.26 , a pre-word line WL_P may be formed in the word line trench WL_T.

[0184] The pre-word line WL_P may be formed along the sidewall and the lower surface of the word line trench WL_T. The pre-word line WL_P may extend in the second direction D2.

[0185] The pre-word line WL_P may not extend to the upper surface of the sacrificial film 50. For example, the uppermost portion of the pre-word line WL_P may be lower than the upper surface of the sacrificial film 50 in the third direction D3 relative to the upper surface of the substrate 100. The uppermost portion of the pre-word line WL_P may be closer to the upper surface of the substrate 100 than the upper surface of the sacrificial film 10.

[0186] Unlike what is shown in the figure, the pre-word line WL_P may extend to the upper surface of the sacrificial film 50 .

[0187] Different from the above, as an example, after the word line trench WL_T is formed, a pre-gate insulating film GI_P may be formed. The pre-gate insulating film GI_P may extend in the second direction D2 along the word line trench WL_T. In some embodiments, before the word line trench WL_T is formed, a pre-gate insulating oxide film GOX_P of the pre-gate insulating film GI_P may be formed. In addition, after the word line trench WL_T is formed, a pre-ferroelectric material film PE_P may be formed.

[0188] refer to Fig. 27 and Fig.28 , the first word line WL1 and the second word line WL2 may be formed in the word line trench WL_T by separating the pre-word line WL_P.

[0189] The first and second channel patterns AP1 and AP2 may be formed by separating the pre-channel pattern AP_P. The first and second gate insulating films GI_1 and GI_2 may be formed by separating the pre-gate insulating film GI_P.

[0190] A gate separation pattern GSS may be formed on the first word line WL1 and the second word line WL2 . The gate separation pattern GSS may extend along the second direction D2 . An upper surface of the gate separation pattern GSS may be coplanar with an upper surface of the sacrificial film 50 .

[0191] refer to Fig.29 and Fig.30 , the second lower insulating film 122 may be exposed by removing the sacrificial film 50 .

[0192] A back gate trench extending in the second direction D2 may be formed between the gate separation patterns GSS adjacent to each other in the first direction D1. Sidewalls of the back gate trench may be defined by the first and second channel patterns AP1 and AP2, and the gate separation pattern GSS.

[0193] refer to Fig.31 and Fig.32 , a back gate electrode BG may be formed between the gate separation patterns GSS adjacent to each other along the first direction D1.

[0194] For example, the back gate insulating film 113 may be formed along the sidewall and the lower surface of the back gate trench. A back gate recess may be defined by the back gate insulating film 113. Subsequently, the back gate electrode BG may fill the back gate recess.

[0195] Then, refer to Figure 3 and Figure 4 , a first bit line BL1 and a second bit line BL2 may be formed on the back gate electrode BG, the first word line WL1 , the second word line WL2 , the first channel pattern AP1 and the second channel pattern AP2 .

[0196] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the scope of the inventive concept. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor memory device, the semiconductor memory device include: a first word line extending in a first direction; a second word line spaced apart from the first word line in a second direction intersecting the first direction, wherein the second word line extends in the first direction; a back gate electrode, the back gate electrode being located between the first word line and the second word line, wherein the back gate electrode extends in the first direction; a first channel pattern, wherein the first channel pattern is located between the first word line and the back gate electrode; a second channel pattern, the second channel pattern being located between the second word line and the back gate electrode; a first gate insulating film, the first gate insulating film being located between the first word line and the first channel pattern, wherein the first gate insulating film comprises a first ferroelectric material film; a second gate insulating film, the second gate insulating film being located between the second word line and the second channel pattern, wherein the second gate insulating film comprises a second ferroelectric material film; a first bit line located on the first channel pattern and the second channel pattern, wherein the first bit line extends in the second direction and is connected to the first channel pattern; and a second bit line, the second bit line being located on the first channel pattern and the second channel pattern, wherein the second bit line is spaced apart from the first bit line in the first direction, and The second bit line extends in the second direction and is connected to the second channel pattern. 2 . The semiconductor memory device according to claim 1 , further comprising a back gate insulating film between the back gate electrode and the first channel pattern and between the back gate electrode and the second channel pattern.

3. The semiconductor memory device according to claim 2, in, The first gate insulating film includes a gate insulating oxide film between the first ferroelectric material film and the first channel pattern, and A thickness of the gate insulating oxide film in the second direction is different from a thickness of the back gate insulating film in the second direction.

4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: include: a first source line connected to the first channel pattern and spaced apart from the second channel pattern; as well as A second source line connected to the second channel pattern and spaced apart from the first channel pattern.

5. The semiconductor memory device according to claim 1, in, The first bit line includes a line extension portion extending in the second direction and a line protrusion portion protruding from the line extension portion in a third direction intersecting the first direction and the second direction, and Wherein, the first channel pattern is in contact with the wire protrusion.

6. The semiconductor memory device according to claim 1, in, The first channel pattern includes a vertical portion extending in a third direction and a horizontal portion extending in the second direction.

7. The semiconductor memory device according to claim 6, in, The vertical portion of the first channel pattern includes a first vertical portion and a second vertical portion, wherein the first vertical portion of the first channel pattern and the second vertical portion of the first channel pattern are directly connected to each other, wherein the first vertical portion of the first channel pattern includes a first sidewall and a second sidewall opposite to each other in the second direction, and Wherein, the first sidewall of the first vertical portion of the first channel pattern faces the back gate electrode.

8. The semiconductor memory device according to claim 1, in, The first word line includes a vertical portion extending in the third direction and a horizontal portion extending in the second direction in a cross-sectional view.

9. The semiconductor memory device according to claim 1, in, The first channel pattern and the second channel pattern each include polysilicon and / or metal oxide.

10. A semiconductor memory device, the semiconductor memory device include: a first source line extending in a first direction; a second source line extending in the first direction, wherein the second source line is spaced apart from the first source line in a second direction intersecting the first direction; a first word line, the first word line being located on the first source line and the second source line, wherein the first word line extends in the second direction; a second word line located on the first source line and the second source line, wherein the second word line is spaced apart from the first word line in the first direction and extends in the second direction; a first channel pattern, the first channel pattern being located between the first word line and the second word line, wherein the first channel pattern is connected to the first source line; a second channel pattern, the second channel pattern being located between the first word line and the second word line, wherein the second channel pattern is connected to the second source line; a first gate insulating film, the first gate insulating film being located between the first word line and the first channel pattern, wherein the first gate insulating film comprises a first ferroelectric material film; a second gate insulating film, the second gate insulating film being located between the second word line and the second channel pattern, wherein the second gate insulating film comprises a second ferroelectric material film; a first bit line located on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern and extends in the first direction; and a second bit line located on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern and is spaced apart from the first bit line in the second direction, and Wherein, the second bit line extends in the first direction.

11. The semiconductor memory device according to claim 10, in, The first source line and the first bit line each include a line extension portion extending in the first direction and a line protrusion portion protruding from the line extension portion in a third direction intersecting the first direction and the second direction, and The first channel pattern is in contact with the line protrusion of the first source line and the line protrusion of the first bit line.

12. The semiconductor memory device according to claim 10, further comprising a back gate electrode located on the first source line and the second source line, in, The back gate electrode is located between the first word line and the second word line.

13. The semiconductor memory device according to claim 12, further comprising a back gate insulating film between the back gate electrode and the first channel pattern, in, The first gate insulating film includes a gate insulating oxide film between the first ferroelectric material film and the first channel pattern, and The thickness of the gate insulating oxide film in the first direction is smaller than the thickness of the back gate insulating film in the first direction.

14. The semiconductor memory device according to claim 10, in, The first channel pattern includes a vertical portion extending in a third direction and a horizontal portion extending in the second direction.

15. The semiconductor memory device according to claim 10, in, The first channel pattern and the second channel pattern each include polysilicon and / or metal oxide.

16. A semiconductor memory device, the semiconductor memory device include: A peripheral gate structure, the peripheral gate structure is located on the substrate; a back-gate electrode, the back-gate electrode being located on the peripheral gate structure, wherein the back-gate electrode extends in a first direction; a first word line, the first word line being located between a first back-gate electrode and a second back-gate electrode among the back-gate electrodes, wherein the first back-gate electrode and the second back-gate electrode are adjacent to each other in a second direction intersecting the first direction, and wherein the first word line extends in the first direction; a second word line, the second word line being located between the first back-gate electrode and the second back-gate electrode, wherein the second word line extends in the first direction; a first channel pattern, wherein the first channel pattern is located between the first back gate electrode and the first word line; a second channel pattern, wherein the second channel pattern is located between the second back gate electrode and the second word line; a gate separation pattern, the gate separation pattern being located between the first word line and the second word line, wherein the gate separation pattern comprises a horizontal portion and a protrusion, wherein the protrusion of the gate separation pattern protrudes from the horizontal portion of the gate separation pattern in a third direction intersecting the first direction and the second direction, wherein a width of the horizontal portion of the gate separation pattern in the second direction is greater than a width of the protrusion of the gate separation pattern in the second direction, and wherein the protrusion of the gate separation pattern is closer to the peripheral gate structure in the third direction than the horizontal portion of the gate separation pattern; a first gate insulating film, the first gate insulating film being located between the first word line and the first channel pattern, wherein the first gate insulating film comprises a first ferroelectric material film; a second gate insulating film, the second gate insulating film being located between the second word line and the second channel pattern, wherein the second gate insulating film comprises a second ferroelectric material film; a first bit line located on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern and extends in the second direction; and A second bit line is located on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern, is spaced apart from the first bit line in the first direction, and extends in the second direction.

17. The semiconductor memory device according to claim 16, further comprising a back gate insulating film between the first back gate electrode and the first channel pattern, in, The first gate insulating film includes a gate insulating oxide film between the first ferroelectric material film and the first channel pattern, and The thickness of the gate insulating oxide film in the second direction is smaller than the thickness of the back gate insulating film in the second direction.

18. The semiconductor memory device according to claim 16, further comprising a first source line and a second source line, wherein the first source line and the second source line are located on the peripheral gate structure and each extend in the second direction, in, The first source line is connected to the first channel pattern and is spaced apart from the second channel pattern, and The second source line is connected to the second channel pattern and is spaced apart from the first channel pattern.

19. The semiconductor memory device according to claim 16, in, The first channel pattern and the second channel pattern are separated by the protrusion of the gate separation pattern.

20. The semiconductor memory device according to claim 16, in, The first channel pattern and the second channel pattern are connected by a connecting channel pattern, and Wherein, the gate separation pattern is located on the connection channel pattern.

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