A multi-functional SOC chip aging system of DFT vector

Abstract

The application discloses a kind of multifunctional SOC chip aging systems of DFT vector, the system includes rack, host computer, excitation board, aging board and SOC chip to be aged;Rack adopts multi-layer equidistant structure, including indicator light, switch, intelligent controller, power socket and universal wheel;Host computer includes system configuration module, pretreatment module, data query module, fault processing module;Excitation board uses FPGA and control chip to control multiple SOC chips to carry out aging test.The application uses FPGA and control chip on excitation board to control multiple SOC chips to carry out aging test, improves the same test quantity of SOC chip, and further improves the efficiency of SOC chip automatic aging test;At the same time, each device in excitation board is conventional device, cost is greatly reduced and excitation board universality is higher, suitable for multiple scenarios;In addition, FPGA, MCU and control chip are used to control test process, timely warning and processing when abnormality is found, further optimize test process, improve test efficiency and accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor design, in particular to a multi-functional SOC chip aging system of DFT vector. BACKGROUND

[0002] DFT is generally integrated in SOC chip, and DFT is a design for testability, which is specially designed for chip production test, can check the defects in chip production and manufacturing process, detect the reliability and stability of the chip, and has a wide range of application scenarios.

[0003] Aging test is a link in the chip screening process, and the purpose of aging test is to stimulate the defects that may be hidden in chip manufacturing in advance, and to eliminate such failed chips, thereby improving the reliability and stability of the mass-produced chips.

[0004] However, the existing SOC chip aging method has three ways of static aging, functional aging and DFT vector to make the chip run to age. The first way cannot cover the internal circuit work of the chip, and cannot effectively age; the second way has the problem of low coverage rate of internal circuit work of SOC chip, and cannot effectively age; the third way of DFT vector cannot be directly used by embedded system, and needs special aging machine and other DFT test equipment, which greatly increases the cost, especially when the test demand is large, more time and cost are needed. SUMMARY

[0005] In view of the above problems, the present application aims to provide a multi-functional SOC chip aging system of DFT vector, which uses FPGA and control chip on the excitation board to control multiple SOC chips for aging test at the same time, greatly improves the efficiency of SOC chip aging test under the premise of ensuring the test efficiency of single SOC chip, and can be applied to simultaneous test of a large number of SOC chips; at the same time, all devices used in the excitation board are conventional mature devices, the cost is greatly reduced compared with professional test equipment, and the excitation board has higher universality and can be applied to various test scenes; in addition, FPGA, MCU and control chip are used to control the test process before and after aging test, and timely warning and processing are carried out when abnormality is found in the test, which further optimizes the test process and improves the efficiency and accuracy of the test.

[0006] The following technical solutions are realized:

[0007] The application discloses a multifunctional SOC chip aging system of DFT vector, which comprises a rack, an upper computer, a switch, a plurality of excitation boards, a plurality of aging boards, a plurality of SOC chips to be aged, a switching power supply and an intelligent controller; wherein the rack adopts a multi-layer equidistant structure, a series of indicator lights and a buzzer are installed on the top of the rack, the indicator lights and the buzzer are controlled by the intelligent controller, a plurality of universal wheels are installed on the bottom of the rack, the universal wheels are used for controlling the movement of the rack, and a corresponding excitation board and a corresponding aging board are arranged on each layer of the equidistant side plate of the rack; the upper computer is connected to each excitation board through the switch, and each aging board is connected to the switch through a serial port; each excitation board is provided with a power switch and a power socket in series, the switching power supply is connected to the power socket of each excitation board through the intelligent controller for power supply control; a plurality of Socket bases are arranged on each aging board, and each Socket base is used for mounting each SOC chip to be aged; the upper computer comprises a system configuration module, a pretreatment module, a data query module and a fault processing module, the system configuration module is used for checking in each SOC chip to be aged and each corresponding aging board, the pretreatment module is used for pretreatment, the pretreatment comprises transmitting the information of each aging board to be checked in and each corresponding Socket base as input information to the upper computer, the data query module is used for obtaining the pretreatment software version corresponding to each aging board according to the input information and loading the pretreatment software version into the FPGA on the excitation board, and the fault processing module is used for informing the operator to handle the fault and positioning the abnormal reason when the fault occurs; a control chip and an FPGA are installed on each excitation board, the FPGA is used for transmitting the output signal of each SOC chip to be aged, the control chip is used for obtaining the pretreatment software version matched with the input information from the upper computer and downloading the pretreatment program, the control chip is also used for loading the FPGA logic version of the excitation board according to the pretreatment program and verifying the output signal, if the verification is passed, the output signal is normally transmitted to the upper computer, and if the verification is not passed, a warning signal is transmitted to the upper computer to remind the user; each aging board is also provided with an MCU chip, the MCU chip contains burning information, the burning information comprises the number of each aging board, the signal information of each SOC chip to be aged and the version information of each aging program, and the MCU chip is used for transmitting the burning information to the upper computer, the upper computer obtains the aging program according to the burning information and transmits the aging program to the control chip, the control chip loads the FPGA by using the aging program, and the FPGA and the control chip perform the aging test on each SOC chip to be aged; wherein the aging test comprises power-on aging, temperature monitoring and voltage monitoring.

[0008] The FPGA and the control chip are used for simultaneously controlling multiple SOC chips to perform the aging test, the efficiency of the aging test of the SOC chips is greatly improved, and the test demand of a large number of SOC chips can be met. Meanwhile, all the devices used in the excitation board are conventional mature devices, the cost is greatly reduced compared with professional test equipment, and the excitation board has higher universality and can be applied to multiple test scenes. In addition, the FPGA, the MCU and the control chip are used for controlling the test before and after the aging test, and an abnormality can be timely warned, the test process is optimized, and the accuracy of the test is improved.

[0009] Preferably, each aging board is further provided with a voltage detection unit, a heating rod and a temperature sensor, and the side plate of the rack is further provided with multiple fan boxes; wherein the temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the fan box is used for air cooling when the temperature monitoring finds overheating; the voltage detection unit is used for voltage monitoring and sends a voltage abnormality to the upper computer for warning when the voltage abnormality is found. Monitoring the temperature and the voltage can effectively find whether there is an abnormal condition during the aging test, so as to ensure the safe test.

[0010] Preferably, the method for any one excitation board to perform the verification and judgment on the corresponding SOC chip to be aged is that: the FPGA in the excitation board is used to send a scan vector to the SOC chip to be aged, the SOC chip to be aged is scanned by the scan vector, the scanning result is taken as an output signal and output from the output pin of the SOC chip to be aged, and the control chip is used to verify and judge the output signal. The JTAG scanning can cover most of the logic and interfaces in the chip, and the current state of the SOC chip can be comprehensively obtained.

[0011] Preferably, after the aging test is completed, each SOC chip subjected to the aging test needs to be subjected to chip detection and electrical parameter measurement; wherein the chip detection includes: taking each SOC chip subjected to the aging test from the corresponding Socket base, and then scanning and recording each SOC chip subjected to the aging test and performing visual inspection; the electrical parameter measurement includes: performing electrical parameter test on each SOC chip subjected to the chip detection, checking whether there is an abnormality, packaging and storing each SOC chip without abnormality, and discarding each SOC chip with abnormality. The chip detection and the electrical parameter measurement can exclude the SOC chips with problems, and facilitate the smooth performance of the next test.

[0012] Preferably, the same connector is arranged on each excitation plate and each aging plate for corresponding connection; for any one excitation plate and the corresponding aging plate, the control chip is connected with the connector of the excitation plate through a UART interface, the MCU is connected with the connector of the aging plate and a serial port through a UART interface respectively, and the MCU is also connected with an indicator light through a GPIO interface. The UART interface has the advantages of low cost and stable transmission, and the GPIO interface has high flexibility and universality.

[0013] Preferably, each universal wheel is a height-adjustable universal wheel, the height of each universal wheel is kept consistent, and the plurality of universal wheels form a triangular plane or a rectangular plane. The height of the universal wheel is adjustable, which is convenient for actual use, and the triangular plane or the rectangular plane is beneficial to improve stability.

[0014] Preferably, when any one of the aging plates is used to perform aging test on any one of the SOC chips to be aged, the method for using the aging system comprises the following steps: S1, chip check-in and aging plate check-in: the SOC chip to be aged is packaged, unpacked, code scanned and visually inspected; the aging plate is visually inspected and code scanned, and the Socket base to be used on the aging plate is code scanned; S2, pretreatment: S21, the information of the aging plate and the Socket base in step S1 is transmitted to the upper computer as input information, the SOC chip to be aged is loaded into the Socket base, and the aging plate is powered; S22, after the power supply in step S21 is completed, the control chip is used to obtain the pretreatment software version corresponding to the input information from the upper computer and download the pretreatment program, and then the pretreatment program is used to load the FPGA, so that the FPGA is initialized and configured; S23, after the FPGA initialization and configuration in step S22 are completed, the FPGA and the control chip are used to judge the output signal of the SOC chip to be aged, if the judgment is passed, the pretreatment is completed; if the judgment is not passed, the step S21 is returned to cycle until the pretreatment is completed; S3, aging test: the SOC chip to be tested is powered and aged, and temperature monitoring and voltage monitoring are performed simultaneously, until the output signal of the SOC chip appears abnormal, the control chip is used to warn the upper computer, and the aging test is stopped; S4, chip check-out: the SOC chip after the aging test is taken out from the Socket base, and then the SOC chip after the aging test is code scanned and visually inspected; S5, electrical parameter measurement: the SOC chip after the chip check-out is tested for electrical parameters, and whether there is an abnormality is checked, if there is no abnormality, the SOC chip is packaged and stored, and if there is an abnormality, the SOC chip is discarded. Each SOC chip is aged according to the method, which can effectively improve the test efficiency and accuracy.

[0015] Compared with the prior art, the present application has the following advantages:

[0016] The technical scheme of the present application uses an FPGA and a control chip on an excitation board to simultaneously control multiple SOC chips for aging test, greatly improves the efficiency of SOC chip aging test under the premise of ensuring that the test efficiency of a single SOC chip is not affected, and can be suitable for simultaneous test of a large number of SOC chips; at the same time, all devices used in the excitation board are conventional mature devices, the cost is greatly reduced compared with professional test equipment, and the excitation board has higher universality and can be suitable for multiple test scenarios; in addition, the FPGA, MCU and control chip are used to control the test process before and after the aging test, and timely warning and processing are performed when an abnormality is found in the test, which further optimizes the test process and improves the test efficiency and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a structure schematic diagram of a host computer connecting an aging board through an excitation board.

[0018] Figure 2 It is a hardware architecture schematic diagram of a multifunctional SOC chip aging system of a DFT vector.

[0019] Figure 3 It is a rack schematic diagram.

[0020] Figure 4 It is a running flowchart when a SOC chip is subjected to aging test.

[0021] Figure 5 It is a pretreatment flowchart.

[0022] Figure 6 It is a flowchart of SOC chip aging test. DETAILED DESCRIPTION

[0023] The technical scheme in the embodiments of the present application will be described in detail below with reference to the accompanying drawings in the embodiments of the present application.

[0024] As shown in Figure 1 , it is a structure schematic diagram of a host computer connecting an aging board through an excitation board, as shown in Figure 2 , it is a hardware architecture schematic diagram of a multifunctional SOC chip aging system of a DFT vector, in combination with Figure 1 and Figure 2As shown, the aging system mainly comprises a rack, an upper computer, a switch, a plurality of excitation boards, a plurality of aging boards, a plurality of SOC chips to be aged, a switching power supply and an intelligent controller. The upper computer is a computer system, which is connected with the excitation boards through respective corresponding host interfaces, the excitation boards are connected with the aging boards through two connectors, the excitation boards have two power supply interfaces, one power supply interface is used for receiving power supply and connecting to the other power supply interface through a DC / DC circuit and a relay, and the other power supply interface is used for connecting the power supply interface of the aging board, thereby supplying power for the aging board.

[0025] The rack adopts a multi-layer equidistant structure, and the equidistance of each layer is 3U. The rack is provided with a series of indicator lights and a buzzer at the top, and the indicator lights and the buzzer are controlled by the intelligent controller. When the intelligent controller receives a warning from the excitation board, the indicator lights and the buzzer will give a warning. The rack is provided with a plurality of universal wheels at the bottom, and the universal wheels are used to control the movement of the rack. The side plates of the rack, i.e. four vertical side panels, are provided with corresponding aging cabinets and corresponding aging boards in each equidistant layer. The aging cabinets are used to install the aging boards. Each aging board is provided with a plurality of Socket seats, and each Socket seat is used to install each SOC chip to be aged. The upper computer is connected to each excitation board through the switch, and each aging board can be connected to the switch through a serial port. Each excitation board is provided with a series of power switches and power sockets. The switching power supply is connected to the power socket of each excitation board through the intelligent controller, and then the power supply of each SOC chip tested by the excitation board can be controlled in combination with the power switch.

[0026] The upper computer comprises a system configuration module, a preprocessing module, a data query module and a fault processing module. The four modules are in parallel relationship. The system configuration module is used to check in each SOC chip to be aged and each corresponding aging board. The preprocessing module is used for preprocessing. When preprocessing, the information of each aging board to be checked in and each corresponding Socket seat is transmitted to the upper computer as input information. The data query module is used to obtain the preprocessing software version corresponding to each aging board and load it into the FPGA on the excitation board. The FPGA can obtain the program corresponding to the preprocessing software version. The fault processing module is used to notify the operator to handle the fault and locate the abnormal reason when a fault occurs.

[0027] In this embodiment, each universal wheel is a height-adjustable universal wheel, and the heights of each universal wheel are consistent and the plurality of universal wheels form a triangular face or a rectangular face. The height of the universal wheel can be adjusted to facilitate height adjustment during actual use. The universal wheel is actually a kind of roller, and there are many rollers with height adjustment function and have been disclosed. Here, no limitation is made as long as the height can be adjusted. In addition, the plurality of rollers form a triangular face or a rectangular face, which is also beneficial to improve the stability of the whole and reduce the possibility of tilting.

[0028] Each excitation board is installed with a control chip and an FPGA, the FPGA can generate a DFT vector for the aging test of the SOC chip, and can also be used to transmit the output signal of each SOC chip to be aged during the test and analyze it, the control chip is used to obtain the pre-processing software version matched with the input information from the host computer and download the pre-processing program, and the control chip is also used to load the FPGA logic version of the excitation board according to the pre-processing program and check the output signal of the output pin of the chip, if the check is passed, the output signal is normally transmitted to the host computer, if the check is not passed, a warning signal is transmitted to the host computer to remind the user.

[0029] Each aging board is also provided with an MCU chip, the MCU chip contains burned information, the burned information includes the number of each aging board, the signal information of each SOC chip to be aged and the version information of each aging program; the MCU chip is used to transmit the burned information to the host computer, the host computer obtains the aging program according to the burned information and transmits it to the control chip, the control chip loads the FPGA with the aging program, and the FPGA and the control chip perform the aging test of each SOC chip to be aged; wherein the aging test includes power-on aging, temperature monitoring and voltage monitoring.

[0030] In this embodiment, the same connectors are provided on each excitation board and each aging board for corresponding connection, so that the devices in the excitation board and the aging board can interact with each other. For any excitation board and the corresponding aging board, the control chip is connected to the connector of the excitation board through the UART interface, the MCU is connected to the connector of the aging board and the serial port through the UART interface respectively, and the MCU is also connected to the indicator light through the GPIO interface. The UART interface has the advantages of low cost and stable transmission, and the GPIO interface has high flexibility and universality.

[0031] As shown in FIG. 1, it is a flow chart of the aging test of the SOC chip, the flow of the operation of the aging system includes the following steps S1 to S5: Figure 4

[0032] Step S1, when a plurality of SOC chips are prepared for aging test, the SOC chips to be aged and the aging boards to be used are checked in. Here, there are multiple Socket seats on one aging board, and multiple SOC chips to be aged can be simultaneously aged and tested, if the number of SOC chips to be aged does not exceed the upper limit of the test of one aging board, one aging board can be directly used, if the number exceeds the upper limit, multiple aging boards can be simultaneously used.

[0033] ​Specifically, the inspection process for SOC chips to be tested generally includes the following steps: first, unpacking the SOC chips; second, scanning and recording the barcodes on the chips to be tested; and finally, visual inspection. The inspection process for aging boards to be used generally includes the following steps: first, visual inspection of the aging board to check if all components are present; second, scanning and recording the barcodes on the aging board; and third, scanning and recording the barcodes on each socket on the aging board.

[0034] It should be noted that a socket is a device used for testing chips. It provides a reliable and repeatable testing environment to ensure that the chip's functionality and performance meet requirements. It can also be used for reliability testing and burn-in testing. Each burn-in board can have one socket or at least two, depending on actual needs.

[0035] In addition, the socket base and aging board are usually equipped with QR codes or other codes that can be scanned for information retrieval, which is also common in current electronic devices.

[0036] Step S2: When preparing the SOC chip for aging test, pre-processing for aging test is required.

[0037] like Figure 5 The diagram shows a preprocessing flowchart, which includes steps S11 to S17. The preprocessing flow mainly includes:

[0038] Step S11: Input the information of the detected aging board and Socket base into the host computer system as input information;

[0039] Specifically, users log in on the host computer and then enter their information there.

[0040] Step S12: Each SOC chip to be aged is loaded into its corresponding socket and entered into the host computer system.

[0041] Specifically, each detected SOC chip is installed into its corresponding socket, and the SOC chip information is simultaneously recorded into the host computer system.

[0042] Step S13: Insert the prepared aging board into the aging cabinet and perform power-on initialization. The excitation board is part of the backplane, and the aging board is plugged into the excitation board via two corresponding connectors. The aging cabinet can accommodate both the excitation board and the aging board.

[0043] Specifically, the prepared aging board is inserted into the aging cabinet, and power-on is manually performed to enable the control chip on the excitation board to initialize the MCU and the SOC chip to be aged on the aging board.

[0044] In step S14, the control chip on the excitation board obtains the pre-processing software version matching the input information from the host computer through the corresponding host interface.

[0045] Specifically, the control chip in the excitation board on the aging cabinet obtains the corresponding pre-processed software version in the host computer system according to the input information of the SOC chip, loads the software version into the control chip of the excitation board, and uses the UART interface, which is easy to use, highly compatible, and relatively inexpensive.

[0046] In step S15, the control chip loads the FPGA logic version in the pre-processed software version obtained in step S14 online.

[0047] Specifically, the FPGA logic version in the pre-processed software version loaded in step S14 is loaded online into the FPGA on the excitation board. Since the PIN definition of each SOC chip is different and the scan vector is also different, the pre-processing program is also different, and the corresponding FPGA logic version is also different. The way of obtaining the pre-processing program from the host computer greatly improves the compatibility.

[0048] In step S16, after the FPGA configuration is completed, the scan vector is sent through the corresponding connector by the FPGA, the scan vector is in the form of a DFT vector, the JTAG scan can be performed on the SOC chip to be tested, and then the control chip judges the output signal of the SOC chip output pin.

[0049] Specifically, after the configuration of the FPGA chip is completed, the scan vector is sent through the connector by the FPGA, the output pin of the SOC chip on the aging board is connected to the IO pin of the FPGA on the excitation board through the connector, and then the FPGA transmits the output signal to the control chip through the bus for verification.

[0050] If the output signal verification fails, the control chip on the excitation board reports the corresponding alarm to the host computer through the host interface, notifies the operator to process the corresponding alarm, and then checks the test chip and the Socket base to locate the abnormal reason, and then returns to S11 to start the operation again.

[0051] If the output signal verification passes, the control chip outputs the normal state to the host computer through the host interface, and continues to step S17.

[0052] Step S17: After the aging board pretreatment is completed, place the aging board in the transfer station and wait for the aging process to begin.

[0053] Specifically, the aging pretreatment steps have all been completed, and the treated aging boards can be placed in the transfer station to await the start of the aging test, preparing for the next step, S3. The transfer station here is a temporary storage facility or area for the aging boards, and staff can choose the transfer station themselves during testing.

[0054] It should be noted that preprocessing is very important. Identifying the quality of the burn-in board, socket base, and SOC chip in advance ensures that the chips entering the burn-in test are those that have passed the initial selection, and avoids discovering related problems after the burn-in test has started, thus saving testing time and effort.

[0055] Step S3: The SOC chip aging test officially begins.

[0056] like Figure 6 The diagram shows a flowchart of an aging test for a SOC chip. The aging test includes steps S21 to S33, describing the overall process from inserting the aging board into the aging chamber to the final aging process.

[0057] Step S21: Insert the pre-treated aging board into the aging cabinet and turn on the main switch of the aging cabinet.

[0058] Specifically, take the pre-treated aging board from the transfer station and insert it into the aging cabinet. After it is fully inserted, turn on the main switch of the aging cabinet to power on and initialize the common parts of the aging cabinet.

[0059] Step S22: Turn on the switching power supply of the corresponding slot to power on the corresponding excitation board.

[0060] Specifically, when the switch of the power supply corresponding to the slot inserted into the aging board is turned on, the power chip on the excitation board will start working, outputting various voltages required by the chip, such as 3.3V, 1.8V and 0.8V, and also outputting the power required by the aging board; after the power chip outputs normal voltage, the control chip also begins to initialize; the control chip is mainly responsible for functions such as communicating with the host computer, communicating with the MCU, loading the FPGA and verifying the output signal.

[0061] Step S23: The control chip on the excitation board completes initialization, communicates with the host computer, and completes registration.

[0062] Specifically, after the control chip is initialized, it communicates with the host computer through the main control interface. After the communication is normal, the registration process begins and is completed. The initialization of the excitation board is then complete.

[0063] Step S24, the control chip on the excitation board determines whether to power on the MCU on the aging board according to the plug-stable signal on the aging board.

[0064] It should be noted that the plug-stable determination is very important. If the plug-stable determination is not performed when the debugging is initially performed, the MCU may be in an abnormal state, the temperature and voltage detection may not work normally, and finally the aging chip cannot perform the aging operation under the specified conditions, thereby wasting the test time and effort.

[0065] Specifically, after the control chip is initialized, whether to power on the MCU on the aging board is determined according to the plug-stable signal on the aging board.

[0066] If the plug-stable signal is abnormal, the control chip on the excitation board reports the corresponding alarm to the host computer through the host port, notifies the operator to process the corresponding alarm, and then checks the related link on the aging board to locate the abnormal reason, and then returns to step S21 to start the operation again.

[0067] If the plug-stable signal is normal, the control chip on the excitation board powers on the MCU on the aging board through the corresponding connector, and continues to step S25.

[0068] Step S25, the MCU chip on the aging board starts chip initialization.

[0069] Specifically, after the determination in step S24 is normal, the control chip on the excitation board provides the power supply voltage of the MCU through the connector, so that the MCU chip on the aging board can be normally initialized. The MCU chip is a core device on the aging board, and the information and monitoring during the operation of the aging board are completed by the MCU chip.

[0070] Step S26, the control chip on the excitation board reads the burning information in the MCU chip on the aging board through the UART interface.

[0071] Specifically, after the MCU on the aging board is normally initialized, the control chip on the excitation board reads the burning information in the MCU chip on the aging board through the UART interface. The burning information includes the aging board number, the SOC chip model information, and the aging program version information. The aging board number is mainly used for comparison with the information recorded in step S11 to determine whether they are consistent. If they are not consistent, an exception needs to be reported to the operator for processing. The SOC chip model information is mainly used for checking whether the aging test information is correct and whether the selected aging board meets the requirements. Different types of chips need to be matched with specific aging boards. The aging program version information is used to find the corresponding aging program and the correct version information on the host computer, so as to ensure the correctness of the aging program. Multiple verifications ensure the performance of the aging test. After all, the aging test takes a long time, and if an error occurs in the early stage, a lot of test time and effort will be wasted.

[0072] Step S27, the control chip on the excitation board obtains the software version matching the burning information from the host computer through the host interface.

[0073] Specifically, the burning information in the MCU chip on the aging board obtained in step S26 is saved in the control chip on the excitation board, and then the burning information is transmitted to the host computer through the host interface, and the host computer matches the corresponding aging software program, and finally the correct aging program is loaded into the control chip on the excitation board.

[0074] Step S28, the control chip loads the FPGA logic version on the excitation board according to the downloaded aging program;

[0075] Specifically, the correct FPGA logic version in the correct aging program obtained in step S27 is loaded into the FPGA on the excitation board online. Since the PIN definition of each SOC chip is different and the DFT vector is also different, the aging program is also different, and the logic version of the corresponding FPGA is also different. The way of obtaining the aging program from the host computer greatly improves the compatibility and greatly reduces the risk of aging program error.

[0076] Step S29, after the FPGA is loaded, the control chip determines whether to power on the aging board according to the chip state.

[0077] It should be noted that the chip state judgment of FPGA and MCU is very important. The FPGA undertakes the DFT vector sending and checking, which is an important link of aging. The importance of the normal work of the MCU chip has been explained, and it is necessary to ensure that the FPGA and MCU can work normally before the aging board is powered on.

[0078] Specifically, after the FPGA logic is loaded, the control chip determines whether to power on the aging board according to whether the specific pin output of the FPGA and MCU is normal. If the specific pin output of the FPGA and MCU is abnormal signal, the control chip on the excitation board will report the corresponding alarm to the host computer through the host interface, notify the operator to process the corresponding alarm, then check the related link on the aging board, locate the abnormal reason, and then return to step S21 to start the operation again. If the specific pin output of the FPGA and MCU is normal signal, the control chip on the excitation board will open the relay to allow the power supply chip to power on the aging board, and continue to step S30.

[0079] Step S30, the SOC chip to be tested on the aging board is powered on to enter the aging state.

[0080] Specifically, after determining normality in step S29, the power supply on the excitation board ages the power supply chip on the aging board through the power supply connector, outputs various voltages required by the chip, such as 3.3V, 1.8V, 0.8V, etc., and enables the SOC chip to start power-on initialization and enter the aging state.

[0081] In step S31, the control chip on the excitation board determines whether to continue aging according to the output signal of the SOC chip.

[0082] Specifically, after the aging configuration of the aging SOC chip is completed, that is, after completing a test, the output pin of the SOC chip on the aging board is connected to the IO pin of the FPGA on the excitation board through the connector, and then the FPGA transmits the output signal to the control chip through the bus for verification to determine whether the output signal can pass the verification:

[0083] If the output signal verification fails, the control chip on the excitation board reports the corresponding alarm to the host computer through the host interface, notifies the operator to process the corresponding alarm, and then checks the aging chip and Socket to locate the abnormal reason, and then returns to S21 to start the operation again. If the output signal verification passes, the control chip outputs the normal state to the host computer through the host interface, and continues to step S32 to continue aging.

[0084] In step S32, the chip starts aging test, and the temperature and voltage states are monitored and processed in real time.

[0085] It should be noted that temperature and voltage monitoring is the most important part of the system, which is related to whether the aging test is running normally. It can monitor the global state and report problems in the first time. According to the actual situation, the test activity is provided with integrity and protection.

[0086] Each aging board is also provided with a voltage detection unit, a heating rod and a temperature sensor, and the side plate of the rack is also provided with a plurality of fan boxes. The temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the voltage detection unit is used for voltage monitoring and sending voltage abnormalities to the host computer for warning when voltage abnormalities are found.

[0087] Specifically, we can divide it into two parts, the first part is the temperature monitoring part, and the second part is the voltage monitoring part. The temperature monitoring includes judgment logic and processing scheme for various conditions: in the case of over-temperature, the fan will be started at a corresponding speed and the heating rod will be heated off; in the case of low temperature, the heating rod will be turned on and the fan will be turned off, etc. The voltage monitoring is also the same. In the case of high or low voltage, the chip aging is interrupted while uploading the warning.

[0088] For example, Figure 3As shown, a rack schematic view is shown, and a plurality of fan boxes are further arranged on two symmetrical side plates of the rack, and the fan boxes can be blown by the fan to achieve cooling.

[0089] Step S33, the chip aging test is ended, the excitation board stops excitation input, and the upper computer notifies the operator to perform the next operation.

[0090] Specifically, after all the aging tests are completed, the control chip on the excitation board reports to the upper computer to remind the operator that the aging test has been completed, and all related data are uploaded to the upper computer, and the FPGA is controlled not to generate DFT vectors, and the MCU does not perform temperature and voltage monitoring operations.

[0091] Step S4, after the SOC chip aging test is completed, the detection of the aging SOC chip needs to be performed.

[0092] Specifically, the detection operation of the aging SOC chip generally includes the following operations, first, the aging test chip is taken out from the socket, then the aging completed chip needs to be scanned and recorded, and finally, visual inspection needs to be performed.

[0093] Step S5, after the SOC chip is detected, electrical parameter measurement, that is, electrical parameter measurement, needs to be performed.

[0094] Specifically, after the aging SOC chip is detected, the electrical parameters of the SOC chip need to be tested to see if there is an abnormal chip, and if there is no abnormal chip, the SOC chip is packaged and stored.

[0095] In summary, the present application uses FPGA and control chips on the excitation board to control multiple SOC chips for aging test, which greatly improves the efficiency of SOC chip aging test without affecting the test efficiency of a single SOC chip, and can be applied to simultaneous testing of a large number of SOC chips.

[0096] The above embodiments only illustrate the technical idea of the present application, and cannot limit the protection scope of the present application, and any modification made according to the technical idea of the present application on the basis of the technical solution falls within the protection scope of the present application.

Claims

1. A multifunctional SOC chip aging system with DFT vector, characterized in that, The system includes a rack, a host computer, a switch, multiple excitation boards, multiple aging boards, multiple SOC chips to be aged, a switching power supply, and an intelligent controller. The rack employs a multi-layered, equally spaced structure. The top of the rack is equipped with a series of indicator lights and buzzers, both controlled by an intelligent controller. The bottom of the rack has multiple casters for movement. Each layer of the rack's side panels contains a corresponding excitation board and a corresponding aging board. A host computer connects to each excitation board via a switch, and each aging board connects to the switch via a serial port. Each excitation board has a series-connected power switch and power socket. The switching power supply is connected to the power socket of each excitation board via the intelligent controller for power control. Each aging board has multiple socket bases, each used to mount a specific SOC chip to be aged. The host computer includes a system configuration module, a preprocessing module, a data query module, and a fault handling module. The system configuration module is used to check each SOC chip to be aged and its corresponding aging board. The preprocessing module is used to perform preprocessing, which includes transmitting the information of each aging board to be checked and its corresponding socket base as input information to the host computer. The data query module is used to obtain the preprocessing software version corresponding to each aging board based on the input information and load it into the FPGA on the excitation board. The fault handling module is used to notify the operator to handle the fault and locate the cause of the abnormality when a fault occurs. Each excitation board is equipped with a control chip and an FPGA. The FPGA is used to transmit the output signals of each SOC chip to be aged. The control chip is used to obtain the preprocessing software version that matches the entered information from the host computer and download the preprocessing program. The control chip is also used to load the FPGA logic version of the excitation board according to the preprocessing program and to verify and judge the output signal. If the verification passes, the output signal is transmitted normally to the host computer. If the verification fails, a warning signal is transmitted to the host computer to remind the user. Each aging board is also equipped with an MCU chip, which contains programming information, including the aging board number, signal information of each SOC chip to be aged, and version information of each aging program. The MCU chip is used to transmit the programming information to the host computer. The host computer obtains the aging program based on the programming information and transmits it to the control chip. The control chip uses the aging program to load the FPGA. The FPGA and the control chip perform aging tests on each SOC chip to be aged. The aging tests include power-on aging, temperature monitoring, and voltage monitoring.

2. The multifunctional SOC chip aging system with DFT vector according to claim 1, characterized in that, Each aging board is also equipped with a voltage detection unit, a heating rod, and a temperature sensor. The side panel of the rack is also equipped with multiple fan boxes. The temperature sensor is used for temperature monitoring, the heating rod is used for heating during power-on aging, and the fan boxes are used to cool down the board by blowing air when the temperature monitoring detects overheating. The voltage detection unit is used for voltage monitoring and sends a warning to the host computer when an abnormal voltage is detected.

3. The multifunctional SOC chip aging system with DFT vector according to claim 1, characterized in that, The method for any excitation board to verify and judge the corresponding SOC chip to be aged is as follows: First, the FPGA in the excitation board sends a scan vector to the SOC chip to be aged. The scan vector is used to perform a JTAG scan on the SOC chip to be aged, and the scan result is output as an output signal from the output pin of the SOC chip to be aged. Then, the control chip is used to verify and judge the output signal.

4. The multifunctional SOC chip aging system based on DFT vectors according to claim 1, characterized in that, After the aging test is completed, chip detection and electrical parameter measurement are also required for each SOC chip that has undergone the aging test. The chip detection process includes: first, removing each SOC chip that has undergone aging testing from its corresponding socket, and then scanning and visually inspecting each SOC chip that has undergone aging testing; the electrical parameter measurement process includes: performing electrical parameter tests on each SOC chip that has passed chip detection to check for any abnormalities, packaging and storing each SOC chip without abnormalities, and discarding each SOC chip with abnormalities.

5. The multifunctional SOC chip aging system based on DFT vectors according to claim 1, characterized in that, Each excitation board and each aging board is equipped with the same connector for corresponding connection; for any excitation board and its corresponding aging board, the control chip is connected to the connector of the excitation board through the UART interface, and the MCU is connected to the connector and serial port of the aging board through the UART interface respectively. The MCU is also connected to indicator lights through the GPIO interface.

6. The multifunctional SOC chip aging system with DFT vector according to claim 1, characterized in that, Each caster wheel is height-adjustable, and the height of each caster wheel is consistent. Multiple casters are arranged in a triangular or rectangular shape.

7. The multifunctional SOC chip aging system with DFT vector according to claim 1, characterized in that, When using any aging board to perform aging tests on any SOC chip to be aged, the method of using the aging system includes the following steps: S1. Chip Inspection and Burn-in Board Inspection: Packaging, unpacking, barcode scanning, and visual inspection of the SOC chips to be burned-in; visual inspection and barcode scanning of the burn-in boards; barcode scanning of the socket bases to be used on the burn-in boards. S2, Pretreatment: S21. Transmit the information of the aging board and Socket base in step S1 as input information to the host computer, load the SOC chip to be aged into the Socket base, and power the aging board. S22. After powering on in step S21, the control chip first obtains the preprocessing software version corresponding to the entered information from the host computer and downloads the preprocessing program. Then, the preprocessing program is used to load the FPGA and initialize the FPGA. S23. After completing the FPGA initialization configuration in step S22, the FPGA and control chip are used to judge the output signal of the SOC chip to be aged. If the judgment passes, the preprocessing is completed; if the judgment fails, the process returns to step S21 and repeats until the preprocessing is completed. S3. Aging test: Power on the SOC chip under test for aging, while monitoring the temperature and voltage. When the output signal of the SOC chip becomes abnormal, the control chip will send a warning to the host computer and stop the aging test. S4. Chip detection: First, remove the SOC chip that has undergone aging test from the socket base, and then scan and record the SOC chip that has undergone aging test and visually inspect it. S5. Electrical parameter measurement: Perform electrical parameter testing on the SOC chip that has passed the chip detection to check for any abnormalities. If there are no abnormalities, the SOC chip will be packaged and stored. If there are abnormalities, the SOC chip will be discarded.

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