Storage chip integration method, integrated storage chip, server and storage medium

Abstract

The invention provides a storage chip integration method, an integrated storage chip, a server and a storage medium, and relates to the technical field of computers, by screening out redundant function modules between at least two to-be-integrated storage chips, the to-be-integrated storage chips storing the redundant function modules are judged, and the integrated storage chips are integrated. Reserving the redundant function module in the to-be-integrated storage chip storing the redundant function module, and deleting the redundant function modules in other to-be-integrated storage chips; simplifying the code program of the to-be-integrated storage chip to obtain an independent code of the to-be-integrated storage chip; defining a starting address corresponding to the independent code according to the starting time sequence of each to-be-integrated storage chip, and synthesizing the independent codes corresponding to the at least two to-be-integrated storage chips to obtain an integrated code; the integrated code is burnt to the integrated storage chip, so that independent storage chips can be reduced, the hardware cost is reduced, the hardware architecture of the system is more compact and efficient, the integration level of the system is improved, and the maintenance cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a storage chip integration method, an integrated storage chip, a server and a storage medium. Background Art

[0002] The server motherboard is equipped with a chip that stores the Basic Input Output System (BIOS) program and a chip that stores the Baseboard Management Controller (BMC) program. The two chips are independent of each other and are located in different locations on the motherboard. BIOS is the underlying operating program under the operating system (OS). It is an abstract layer between computer hardware and OS. It is used to set up hardware and prepare for OS operation. Its main functions are power-on self-test, detection of input and output devices and bootable devices. BMC is a core component used to deploy, diagnose and manage servers. It is responsible for monitoring the operating status of the server, fault warning and remote management. With the rapid development of servers, the complexity and integration of server systems are constantly improving. The separate storage of BIOS and BMC programs not only increases hardware costs, but also occupies more motherboard space. In addition, the two chips need to be processed separately during system upgrades and maintenance, which reduces processing efficiency. Summary of the invention

[0003] The present invention provides a storage chip integration method, an integrated storage chip, a server and a storage medium, which are used to solve the problem that the method of using two storage chips to separately store a BIOS program and a BMC program not only increases the hardware cost, but also occupies more mainboard space, and also requires the two chips to be processed separately during system upgrade and maintenance, thereby reducing the processing efficiency.

[0004] The present invention provides a memory chip integration method, comprising: Screening out redundant functional modules between at least two storage chips to be integrated, determining the storage chip to be integrated that stores the redundant functional modules, retaining the redundant functional modules in the storage chip to be integrated that stores the redundant functional modules, and deleting redundant functional modules in other storage chips to be integrated; Simplifying the code program of each memory chip to be integrated to obtain independent code of each memory chip to be integrated; Defining a startup address of a corresponding independent code according to the startup timing of each memory chip to be integrated, synthesizing the independent codes corresponding to at least two memory chips to be integrated to obtain an integrated code; The integrated code is burned into the integrated memory chip.

[0005] According to the memory chip integration method provided by the present invention, the step of screening out redundant functional modules between at least two memory chips to be integrated and determining the memory chip to be integrated that stores the redundant functional modules comprises: Determine the core function and auxiliary function of each storage chip to be integrated, and use the auxiliary function module shared by at least two storage chips to be integrated with data interaction as a redundant function module; The startup sequence of at least two storage chips to be integrated is determined, and the storage chip to be integrated with a later startup sequence is used as the storage chip to be integrated for storing the redundant functional module.

[0006] The memory chip integration method provided by the present invention further includes: An error recovery mechanism is added to the integrated code. When an error occurs in the integrated storage chip during loading or running, the integrated storage chip is repaired through the error recovery mechanism. The error recovery mechanism includes skipping the current error and restarting the device.

[0007] According to the memory chip integration method provided by the present invention, the at least two memory chips to be integrated include a basic input-output system chip and a baseboard management controller chip, and the redundant functional modules between the basic input-output system chip and the baseboard management controller chip include a hardware configuration module and a user interface configuration module related to remote management. The hardware configuration module and the user interface configuration module related to remote management are retained in the baseboard management controller chip, and the hardware configuration module and the user interface configuration module related to remote management in the basic input-output system chip are deleted.

[0008] According to the memory chip integration method provided by the present invention, the code program of each memory chip to be integrated is simplified, including: Retaining the boot loader module, the hardware initialization module, the core interrupt service module and the hardware inspection module in the basic input and output system chip; Delete the functional module that interacts with the baseboard management controller chip; Delete or modify the non-core interrupt service module in the basic input and output system chip.

[0009] According to the memory chip integration method provided by the present invention, the code program of each memory chip to be integrated is simplified, including: Retain the hardware status monitoring module, key remote management function module, event recording and alarm module, energy consumption management module, security management module and specific model hardware support module in the baseboard management controller chip; Delete auxiliary model hardware support modules, non-critical remote management functions, detailed logging function modules, and function modules that interact with the basic input and output system chip.

[0010] According to the memory chip integration method provided by the present invention, the startup address corresponding to the independent code is defined according to the startup timing of each memory chip to be integrated, including: The startup sequence of the basic input and output system chip is earlier than that of the baseboard management controller chip, and the startup address of the independent code of the basic input and output system chip is set before the startup address of the independent code of the baseboard management controller chip.

[0011] The memory chip integration method provided by the present invention further includes: A switching mechanism is set in the integration code, and the switching mechanism is used to switch between the external main control devices corresponding to each storage chip to be integrated according to the switching strategy; Use event-driven or polling monitoring to obtain current environment data, and when the current environment data meets the switching strategy, use shared memory and / or interrupt mechanism to switch to the communication interface or communication protocol of the corresponding main control device; The switching strategy includes whether the central controller has a demand and a system status detection result, and whether the central controller has a demand has a higher priority than the system status detection result; The central controller needs to be acquired according to business needs, user configuration or preset control strategy, and when the central controller has a need, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; The system status detection result includes the utilization rate of the central controller, the temperature of the central controller, the system power consumption and the system load; when the utilization rate of the central controller reaches a first preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the temperature of the central controller reaches a second preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the system power consumption is lower than a third preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; when the system load is lower than a fourth preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip.

[0012] The memory chip integration method provided by the present invention further includes: After the integration code is compiled, a verification code is generated, and before the integrated storage chip is started or a key operation is performed, the integrity and authenticity of the integration code are verified using the verification code; The integration code is digitally signed using a public key encryption method, and when the device is upgraded or maintained, the security of the integration code is verified using the private key corresponding to the digital signature; Different user roles are defined, and different user permissions are assigned to the integrated storage chip according to different user roles; the user roles include administrators and ordinary users, the administrator has the permission to modify the integrated storage chip, and the ordinary user has the permission to view the integrated storage chip, and when receiving a user's access request, the user's access is restricted according to the corresponding permissions of the user.

[0013] The present invention also provides an integrated storage chip, comprising: The memory chip is obtained by integrating at least two memory chips to be integrated according to any of the memory chip integration methods described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the above-mentioned methods for integrating a memory chip.

[0015] The storage chip integration method, integrated storage chip, server and storage medium provided by the present invention screen out redundant functional modules between at least two storage chips to be integrated, determine the storage chip to be integrated that stores the redundant functional modules, retain the redundant functional modules in the storage chip to be integrated that stores the redundant functional modules, and delete the redundant functional modules in other storage chips to be integrated; streamline the code program of each storage chip to be integrated to obtain independent code for each storage chip to be integrated; define the startup address corresponding to the independent code according to the startup timing of each storage chip to be integrated, synthesize the independent codes corresponding to at least two storage chips to be integrated to obtain an integrated code; burn the integrated code to the integrated storage chip, and optimize multiple chip programs and store them in the same storage chip, thereby reducing independent storage chips, reducing hardware costs, and releasing motherboard space, making the hardware architecture of the system more compact and efficient, improving system integration, reducing upgrade and update time, and reducing maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is one of the flow diagrams of the memory chip integration method provided by an embodiment of the present invention; Figure 2 This is a second flow chart of the memory chip integration method provided by an embodiment of the present invention; Figure 3It is a functional structure diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Figure 1 A flowchart of a memory chip integration method provided by an embodiment of the present invention, such as Figure 1 As shown, the memory chip integration method provided by the embodiment of the present invention is applied to a baseboard management controller, the baseboard management controller is serially connected to each level of cascade expanders through a 485 bus, and the method includes: Step 101, screening out redundant functional modules between at least two storage chips to be integrated, determining the storage chip to be integrated storing the redundant functional module, retaining the redundant functional module in the storage chip to be integrated storing the redundant functional module, and deleting redundant functional modules in other storage chips to be integrated; Step 102: simplify the code program of each memory chip to be integrated to obtain independent code of each memory chip to be integrated; Step 103, defining a startup address of a corresponding independent code according to the startup timing of each memory chip to be integrated, synthesizing the independent codes corresponding to at least two memory chips to be integrated to obtain an integrated code; Step 104: Burn the integration code into the integrated storage chip.

[0019] Traditional server motherboards are equipped with BIOS and BMC chips for storing BIOS and BMC programs respectively. The separate storage of BIOS and BMC programs not only increases hardware costs, but also takes up more motherboard space. In addition, the two chips need to be processed separately during system upgrades and maintenance, which reduces processing efficiency.

[0020] The memory chip integration method provided by the embodiment of the present invention screens out redundant functional modules between at least two memory chips to be integrated, determines the memory chip to be integrated that stores the redundant functional modules, retains the redundant functional modules in the memory chip to be integrated that stores the redundant functional modules, and deletes the redundant functional modules in other memory chips to be integrated; simplifies the code program of each memory chip to be integrated to obtain independent code for each memory chip to be integrated; defines the startup address corresponding to the independent code according to the startup timing of each memory chip to be integrated, synthesizes the independent codes corresponding to at least two memory chips to be integrated, and obtains an integrated code; burns the integrated code to the integrated memory chip, and stores multiple chip programs in the same memory chip after optimization, thereby reducing independent memory chips, reducing hardware costs, and releasing motherboard space, making the hardware architecture of the system more compact and efficient, improving system integration, reducing upgrade and update time, and reducing maintenance costs.

[0021] Based on any of the above embodiments, the step of screening out redundant functional modules between at least two storage chips to be integrated includes: The core function and auxiliary function of each storage chip to be integrated are determined, and the auxiliary function module shared by at least two storage chips to be integrated with data interaction is used as a redundant function module.

[0022] In an embodiment of the present invention, determining the storage chip to be integrated to store the redundant functional module includes: determining the startup sequence of at least two storage chips to be integrated, and using the storage chip to be integrated with a later startup sequence as the storage chip to be integrated to store the redundant functional module.

[0023] Based on any of the above embodiments, the memory chip integration method provided by the embodiment of the present invention further includes: An error recovery mechanism is added to the integrated code. When an error occurs in the integrated storage chip during loading or running, the integrated storage chip is repaired through the error recovery mechanism. The error recovery mechanism includes skipping the current error and restarting the device.

[0024] System startup and program running: When the server starts, the BIOS program first loads and runs its own core code to complete basic hardware initialization, system configuration and system startup. If the startup fails, it will try to start again. After the startup is completed, the BMC code part will be executed. The BMC is responsible for hardware management functions during system operation, including system monitoring, fault handling, device monitoring and remote management. When an error occurs during the loading or running of the firmware, the error recovery mechanism can automatically load the running code again from the integrated storage chip to ensure the stable operation of the system.

[0025] Based on any of the above embodiments, the at least two storage chips to be integrated include a basic input / output system chip and a baseboard management controller chip, and the redundant functional modules between the basic input / output system chip and the baseboard management controller chip include a hardware configuration module and a user interface configuration module related to remote management. The hardware configuration module and the user interface configuration module related to remote management are retained in the baseboard management controller chip, and the hardware configuration module and the user interface configuration module related to remote management in the basic input / output system chip are deleted.

[0026] In an embodiment of the present invention, the streamlining of the code program of each storage chip to be integrated includes: Retaining the boot loader module, the hardware initialization module, the core interrupt service module and the hardware inspection module in the basic input and output system chip; In an embodiment of the present invention, BIOS is responsible for initializing hardware devices such as CPU, memory, storage devices, I / O devices, etc. at startup. This is the core function of BIOS, and the hardware initialization module needs to be retained to ensure that the system can start and run normally. BIOS provides a series of interrupt service routines for handling various hardware interrupt requests. These interrupt service routines are the key to communication between the operating system and the hardware, so the core interrupt service module needs to be retained. The hardware check module (Power-On Self-Test, POST) is a series of hardware checks performed by BIOS at system startup. This process can ensure that the hardware devices work properly, which is crucial to the stability and reliability of the server, so it needs to be retained. BIOS is responsible for loading the boot loader (Boot Loader) from a predetermined startup device (such as a hard disk, USB drive, network, etc.), and handing over its control to the boot loader to load the operating system.

[0027] Delete the functional module that interacts with the baseboard management controller chip; Delete or modify the non-core interrupt service module in the basic input and output system chip.

[0028] In an embodiment of the present invention, although BIOS is responsible for initializing hardware devices, after integration with the BMC code, some hardware configuration settings are taken over by the BMC. BMC is responsible for remotely setting the server's boot sequence, power management, etc. Therefore, these hardware configuration functions related to remote management need to be deleted. BIOS has a user configuration interface (usually text mode or graphical interface) that allows users to make some configurations and settings during the startup process. However, after integration with the BMC code, these configuration user interface functions can be replaced by the remote management tools provided by the BMC. Therefore, the user configuration interface function can be deleted to adapt to the new management method. Although BIOS provides many interrupt service routines, some of them are not required for server operation. After integration with the BMC code, the importance of these non-core interrupt service routines can be evaluated and a decision can be made whether to delete or modify them.

[0029] In the embodiment of the present invention, the source code of BIOS is simplified and optimized, and the core code function modules of BIOS that need to be retained are mainly hardware initialization, interrupt service, POST, boot loading and other function modules. When deleting BIOS function modules, it is necessary to consider whether there is redundancy with the functions of BMC. Redundant functions can be implemented by BMC, such as some hardware configurations, user configuration interfaces, and non-core interrupt service modules can all be deleted.

[0030] In an embodiment of the present invention, the streamlining of the code program of each storage chip to be integrated includes: Retain the hardware status monitoring module, key remote management function module, event recording and alarm module, energy consumption management module, security management module and specific model hardware support module in the baseboard management controller chip; In an embodiment of the present invention, one of the core functions of BMC is to monitor the hardware status of the server, such as CPU temperature, fan speed, power status, etc., which is the key to ensure the stable operation of the server and therefore needs to be retained. The remote management function of BMC allows administrators to remotely monitor, configure and maintain the server. This is crucial for remote management of the server: BMC can record events and errors that occur during the operation of the server and generate alarms when the hardware status exceeds the preset threshold. This is very important for troubleshooting and early warning. BMC helps reduce the operating costs of the server by managing the energy consumption of the server, including power management, energy-saving strategies, etc. The security management functions of BMC, such as access control, encrypted communication, etc., can ensure the security of the remote management interface.

[0031] Delete auxiliary model hardware support modules, non-critical remote management functions, detailed logging function modules, and function modules that interact with the basic input and output system chip.

[0032] In an embodiment of the present invention, the source code of the BMC is streamlined and optimized, and the BMC functional modules that need to be retained are mainly those modules related to server hardware status monitoring, remote management, event recording and alarm, energy consumption management, and security management. When deleting the BMC functional modules, we should consider the functional importance of the module, the frequency of use, and the redundancy with other functions. Specific hardware support modules, non-critical remote management functions, detailed logging functions, and functional modules that interact with BIOS are modules that need to be deleted. Only the code that supports a specific model of server or hardware platform is retained, and the support modules of other hardware platforms need to be deleted. For example, if it is only for servers with Intel X86 architecture, then the hardware support modules for ARM or other non-X86 architectures can be deleted. Some remote management functions may not be required by every user or application scenario. For example, the function of remotely installing an operating system is normally implemented through network boot, so this module can be deleted. Although event recording and alarm functions are very important for server troubleshooting and monitoring, overly detailed logging may take up a lot of storage space and is relatively complicated to handle. Therefore, it can be considered to delete some non-critical logging modules and only retain necessary log information. After integration with the BIOS code, the functional modules that interact with the BIOS need to be deleted. There is no need for the BIOS to obtain information and then send it to the BMC, or for the BMC to obtain information and then send it to the BIOS. The integrated code is a set of codes that can be directly processed by the code without the need for interaction.

[0033] In an embodiment of the present invention, the step of defining a startup address corresponding to an independent code according to a startup timing of each memory chip to be integrated includes: The startup sequence of the basic input and output system chip is earlier than that of the baseboard management controller chip, and the startup address of the independent code of the basic input and output system chip is set before the startup address of the independent code of the baseboard management controller chip.

[0034] In an embodiment of the present invention, the startup address of BIOS is defined as FFFFFFF0H, which ensures that the BIOS program can be started first to perform POST, initialize hardware devices, load boot programs, etc. when the system starts, and the BMC program is placed after the BIOS program. BMC will assume more responsibilities after the BIOS startup is completed, including hardware status monitoring, remote management, event recording and alarming, energy consumption management, security management, asset information management, and interaction with the operating system. These functions will ensure the stable operation and efficient management of the server. At the same time, BMC also needs to have the ability of self-recovery to cope with possible serious problems or crashes. Finally, the BIOS and BMC codes are integrated into a set of codes so that the integrated code can be directly stored in the storage chip through a refresh tool or a burner.

[0035] Based on any of the above embodiments, the memory chip integration method provided by the embodiment of the present invention further includes: Step 201: setting a switching mechanism in the integration code, wherein the switching mechanism is used to switch between external main control devices corresponding to each storage chip to be integrated according to a switching strategy; Step 202: Use event-driven or polling monitoring to obtain current environment data, and when the current environment data meets the switching strategy, use shared memory and / or interrupt mechanism to switch to the communication interface or communication protocol of the corresponding main control device; The switching strategy includes whether the central controller has a demand and a system status detection result, and whether the central controller has a demand has a higher priority than the system status detection result; The central controller needs to be acquired according to business needs, user configuration or preset control strategy, and when the central controller has a need, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; The system status detection result includes the utilization rate of the central controller, the temperature of the central controller, the system power consumption and the system load; when the utilization rate of the central controller reaches a first preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the temperature of the central controller reaches a second preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the system power consumption is lower than a third preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; when the system load is lower than a fourth preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip.

[0036] In the embodiment of the present invention, the main control device externally connected to the baseboard management controller chip is a BMC control chip, and the main control device externally connected to the basic input and output system chip is a CPU. Figure 2 As shown, in order to ensure smooth switching between the BMC control chip and the CPU, corresponding modules are added to the integrated code, including: Communication module: responsible for realizing the communication functions with the CPU and BMC control chip, including data sending, receiving, and parsing.

[0037] Status monitoring module: monitors the system status of the server in real time, such as temperature, voltage, fan speed, etc., and provides this information to the decision module.

[0038] Decision-making module: Dynamically adjusts the communication strategy between the CPU and BMC control chip according to system status and requirements.

[0039] The status monitoring module detects the system status of the server in real time, such as CPU utilization, temperature, power consumption, etc. According to business needs, user configuration or preset policies, the current demand for CPU and BMC control chips is evaluated. The decision module dynamically adjusts the communication strategy with the CPU and BMC control chips based on the results of status detection and demand evaluation. For example, when the CPU temperature is too high, the communication frequency with the BMC chip can be increased to obtain more detailed temperature data and trigger the corresponding cooling strategy. When the server load is low, the communication frequency with the CPU can be reduced to save system resources. When the status monitoring module detects that the overall power consumption of the server is high and the current business needs do not require all hardware resources to be active, the communication frequency with currently unused hardware (such as CPU cores with no tasks assigned and unconnected storage devices) is reduced to reduce energy consumption. Send instructions to the BMC chip through the communication module to request it to adjust the power management strategy of the server, such as enabling low power mode, shutting down unnecessary hardware components, etc. The communication module implements smooth switching between the CPU and BMC control chips according to the communication strategy given by the decision module. Use event-driven or polling methods to ensure that the corresponding communication interface or protocol can be switched to in time when needed. Use technologies such as shared memory and interrupt mechanism to improve communication efficiency and response speed.

[0040] During the communication process, possible errors are detected, such as communication timeout, data verification failure, etc. When an error is detected, an appropriate recovery strategy is adopted, and the retry mechanism is set to 3 times. If it cannot be recovered after 3 times, it is restored to the previous state to ensure the stability and reliability of communication. For data verification failure, sufficient redundant information can be added to the sent data so that the receiver can detect and correct a certain number of errors without retransmission.

[0041] Based on any of the above embodiments, the memory chip integration method provided by the embodiment of the present invention further includes: After the integration code is compiled, a verification code is generated, and before the integrated storage chip is started or a key operation is performed, the integrity and authenticity of the integration code are verified using the verification code; The integration code is digitally signed using a public key encryption method, and when the device is upgraded or maintained, the security of the integration code is verified using the private key corresponding to the digital signature; Different user roles are defined, and different user permissions are assigned to the integrated storage chip according to different user roles; the user roles include administrators and ordinary users, the administrator has the permission to modify the integrated storage chip, and the ordinary user has the permission to view the integrated storage chip, and when receiving a user's access request, the user's access is restricted according to the corresponding permissions of the user.

[0042] In an embodiment of the present invention, the integrated code program is set with an encryption algorithm, access rights, verification code, and code signature to ensure that only authorized code can be executed, and an integrity check is performed when the program is started. This can prevent malicious code from being injected or replaced, ensure that the program has not been tampered with, and ensure the security and integrity of the program.

[0043] The storage chip integration method provided by the embodiment of the present invention optimizes the BIOS and BMC programs and stores them in the same storage chip, simplifies and optimizes the source code of the BIOS, and the core code functional modules of the BIOS that need to be retained are mainly hardware initialization, interrupt service, POST, boot loading and other functional modules. When deleting the BIOS functional module, it is necessary to consider whether there is redundancy with the BMC function. The redundant functions can be implemented by the BMC, such as some hardware configurations, user configuration interfaces, and non-core interrupt service modules can all be deleted. The source code of the BMC is simplified and optimized. The BMC functional modules that need to be retained are mainly those related to server hardware status monitoring, remote management, event recording and alarm, energy consumption management, and security management. When deleting the BMC functional module, we should consider the functional importance of the module, the frequency of use, and the redundancy with other functions. Specific hardware support modules, non-critical remote management functions, detailed logging functions, and functional modules that interact with BIOS are modules that need to be deleted; the integrated code realizes smooth switching between the CPU and BMC control chips. Through a unified storage interface, only one firmware version needs to be updated, which can greatly reduce update time and maintenance costs. It optimizes the firmware communication protocol and reasonably arranges chip storage space, reducing the loading time at system startup and improving the startup speed.

[0044] The integrated memory chip provided by the present invention is described below. The integrated memory chip described below and the memory chip integration method described above can be referred to each other.

[0045] An integrated memory chip provided by an embodiment of the present invention comprises: at least two memory chips to be integrated are integrated according to the memory chip integration method described in the above embodiment.

[0046] The present invention optimizes BIOS and BMC programs and stores them in the same storage chip, thereby reducing independent BIOS and BMC storage chips, and can solve the problem of high hardware cost; makes the hardware architecture of the system more compact and efficient, and can solve the problem of occupying more motherboard space; through a unified storage interface, only one firmware version needs to be updated, and can solve the problems of long update time and high maintenance cost; optimizes the firmware communication protocol and reasonably arranges the chip storage space, reduces the loading time when the system starts, and can solve the problem of slow startup speed.

[0047] Figure 3 An example of a server physical structure diagram is shown below: Figure 3 As shown, the server may include: a processor 310, a communication interface 320, an integrated memory chip 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the integrated memory chip 330 communicate with each other through the communication bus 340. The integrated memory chip 330 includes a computer program, an operating system and acquired data, and the processor 310 may call the logic instructions in the integrated memory chip 330 to execute the memory chip integration method, which includes: screening out redundant functional modules between at least two memory chips to be integrated, determining the memory chip to be integrated storing the redundant functional modules, retaining the redundant functional modules in the memory chip to be integrated storing the redundant functional modules, and deleting the redundant functional modules in other memory chips to be integrated; streamlining the code program of each memory chip to be integrated to obtain independent codes of each memory chip to be integrated; defining the startup address of the corresponding independent codes according to the startup timing of each memory chip to be integrated, synthesizing the independent codes corresponding to at least two memory chips to be integrated to obtain integrated codes; and burning the integrated codes to the integrated memory chip.

[0048] In addition, the logic instructions in the above-mentioned integrated storage chip 330 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only integrated storage chip (ROM, Read-Only Memory), random access integrated storage chip (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0049] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the storage chip integration method provided by the above-mentioned methods, the method comprising: screening out redundant functional modules between at least two storage chips to be integrated, determining the storage chip to be integrated that stores the redundant functional module, retaining the redundant functional module in the storage chip to be integrated that stores the redundant functional module, and deleting the redundant functional modules in other storage chips to be integrated; streamlining the code program of each storage chip to be integrated to obtain independent code for each storage chip to be integrated; defining the startup address corresponding to the independent code according to the startup timing of each storage chip to be integrated, synthesizing the independent codes corresponding to at least two storage chips to be integrated to obtain an integrated code; and burning the integrated code to the integrated storage chip.

[0050] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0051] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory chip integration method, It is characterized in that include: Screening out redundant functional modules between at least two storage chips to be integrated, determining the storage chip to be integrated that stores the redundant functional modules, retaining the redundant functional modules in the storage chip to be integrated that stores the redundant functional modules, and deleting redundant functional modules in other storage chips to be integrated; Simplifying the code program of each memory chip to be integrated to obtain independent code of each memory chip to be integrated; Defining a startup address of a corresponding independent code according to the startup timing of each memory chip to be integrated, synthesizing the independent codes corresponding to at least two memory chips to be integrated to obtain an integrated code; The integrated code is burned into the integrated memory chip.

2. The memory chip integration method according to claim 1, It is characterized in that The step of screening out redundant functional modules between at least two storage chips to be integrated and determining the storage chip to be integrated that stores the redundant functional modules comprises: Determine the core function and auxiliary function of each storage chip to be integrated, and use the auxiliary function module shared by at least two storage chips to be integrated with data interaction as a redundant function module; The startup sequence of at least two storage chips to be integrated is determined, and the storage chip to be integrated with a later startup sequence is used as the storage chip to be integrated for storing the redundant functional module.

3. The memory chip integration method according to claim 1, It is characterized in that Also includes: An error recovery mechanism is added to the integrated code. When an error occurs in the integrated storage chip during loading or running, the integrated storage chip is repaired through the error recovery mechanism. The error recovery mechanism includes skipping the current error and restarting the device.

4. The memory chip integration method according to claim 1, It is characterized in that The at least two storage chips to be integrated include a basic input / output system chip and a baseboard management controller chip. The redundant functional modules between the basic input / output system chip and the baseboard management controller chip include a hardware configuration module and a user interface configuration module related to remote management. The hardware configuration module and the user interface configuration module related to remote management are retained in the baseboard management controller chip, and the hardware configuration module and the user interface configuration module related to remote management in the basic input / output system chip are deleted.

5. The memory chip integration method according to claim 4, It is characterized in that The streamlining of the code program of each storage chip to be integrated includes: Retaining the boot loader module, the hardware initialization module, the core interrupt service module and the hardware inspection module in the basic input and output system chip; Delete the functional module that interacts with the baseboard management controller chip; Delete or modify the non-core interrupt service module in the basic input and output system chip.

6. The memory chip integration method according to claim 4, It is characterized in that The streamlining of the code program of each storage chip to be integrated includes: Retain the hardware status monitoring module, key remote management function module, event recording and alarm module, energy consumption management module, security management module and specific model hardware support module in the baseboard management controller chip; Delete auxiliary model hardware support modules, non-critical remote management functions, detailed logging function modules, and function modules that interact with the basic input and output system chip.

7. The memory chip integration method according to claim 4, It is characterized in that The step of defining the startup address of the corresponding independent code according to the startup timing of each memory chip to be integrated includes: The startup sequence of the basic input and output system chip is earlier than that of the baseboard management controller chip, and the startup address of the independent code of the basic input and output system chip is set before the startup address of the independent code of the baseboard management controller chip.

8. The memory chip integration method according to claim 4, It is characterized in that Also includes: A switching mechanism is set in the integration code, and the switching mechanism is used to switch between the external main control devices corresponding to each storage chip to be integrated according to the switching strategy; Use event-driven or polling monitoring to obtain current environment data, and when the current environment data meets the switching strategy, use shared memory and / or interrupt mechanism to switch to the communication interface or communication protocol of the corresponding main control device; The switching strategy includes whether the central controller has a demand and a system status detection result, and whether the central controller has a demand has a higher priority than the system status detection result; The central controller needs to be acquired according to business needs, user configuration or preset control strategy, and when the central controller has a need, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; The system status detection result includes the utilization rate of the central controller, the temperature of the central controller, the system power consumption and the system load; when the utilization rate of the central controller reaches a first preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the temperature of the central controller reaches a second preset value, the master control device of the integrated storage chip is switched to the master control device external to the baseboard management controller chip; when the system power consumption is lower than a third preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip; when the system load is lower than a fourth preset value, the master control device of the integrated storage chip is switched to the master control device external to the basic input and output system chip.

9. The memory chip integration method according to claim 1, It is characterized in that Also includes: After the integration code is compiled, a verification code is generated, and before the integrated storage chip is started or a key operation is performed, the integrity and authenticity of the integration code are verified using the verification code; The integration code is digitally signed using a public key encryption method, and when the device is upgraded or maintained, the security of the integration code is verified using the private key corresponding to the digital signature; Defining different user roles, and assigning different user permissions to the integrated storage chip for different user roles; The user roles include administrators and common users. The administrator has the authority to modify the integrated storage chip, and the common user has the authority to view the integrated storage chip. When receiving a user's access request, the user's access is restricted according to the corresponding authority of the user.

10. An integrated memory chip, It is characterized in that include: The memory chip integration method according to any one of claims 1 to 9 is obtained by integrating at least two memory chips to be integrated.

11. A non-transitory readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the memory chip integration method according to any one of claims 1 to 9 is implemented.

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