Dynamic adaptive precision switching method and device for voice recognition NPU

Abstract

The invention discloses a dynamic self-adaptive precision switching method for a voice recognition NPU, and aims to solve the core problems that precision and energy efficiency of an end-side voice recognition NPU in multiple scenes cannot be considered at the same time, fixed-precision hardware resources are seriously wasted, software switching efficiency is low, and errors are accumulated. A hardware architecture of a 4 * 4 reconfigurable MAC subunit array and a switch matrix is constructed, and a task-driven adaptive scheduling mechanism, an operation period synchronous control technology (single-period hardware reconfiguration is realized by utilizing idle gap latch configuration) and a direction-sensitive error compensation algorithm (historical data interpolation extension or correction truncation) are combined; hardware-level dynamic lossless switching of the MAC unit between 8bit / 16bit / 32bit precision is realized, so that different voice tasks achieve the highest necessary computing power with the lowest necessary power consumption, no data is lost in the switching process, and finally, the energy efficiency rigidity of a fixed-precision framework is oppositely converted into the precision on-demand supply capability capable of being deployed in an engineering manner.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of speech recognition, and particularly relates to a dynamic adaptive precision switching method and device for speech recognition NPU. BACKGROUND

[0002] NPU (Neural Processing Unit) is a domain-specific accelerator specially designed for neural network calculation, which is complementary to CPU (general-purpose processing) and GPU (parallel computing) in computing power: CPU: good at logical control and serial tasks, but low in computing energy efficiency ratio (<1 TOPS / W); GPU: accelerates matrix operation through SIMT architecture, but is high in power consumption and large in delay, and resources are idle; NPU: customized for three characteristics of neural network calculation, high data reuse and precision tolerance, and can reach 10-100 TOPS / W in energy efficiency ratio, and is low to milliseconds in delay.

[0003] The core computing array of NPU is composed of hundreds to thousands of processing elements (PE) in a 2D array, and each PE includes a MAC (multiplier-accumulator) and a local register.

[0004] At present, there are the following: Fixed precision NPU MAC unit: belongs to a special hardware structure composed of a multiplier, an accumulator and a register, and only supports single precision (such as 8bit or 16bit) calculation. Taking 8bit fixed precision MAC as an example, the multiplier can only process 8bit×8bit operation, the accumulator outputs 32bit intermediate result, the register stores operation data, and all modules are bound to 8bit data bit width without precision adjustment interface.

[0005] Software configurable precision MAC scheme: no hardware level precision switching capability, and precision adaptation is realized by relying on software tool chain. The steps are: 1) quantizing input neural network model data at the software layer (such as 32bit→8bit); 2) transmitting the quantized data into the fixed precision MAC unit for calculation; and 3) outputting the calculation result after software dequantization. The core relies on CPU or NPU software driver, and the hardware MAC unit itself has no precision switching logic.

[0006] Double-precision hardware switching MAC scheme: the hardware structure includes two independent MAC subunits of 8bit and 16bit, and the activated subunit is selected by a hardware switch. The switching steps are: 1) externally configuring a switch signal; 2) turning on the target precision subunit (such as the 8bit subunit) and turning off the other subunit; 3) the target subunit performs multiplication and addition operation. The two subunits are independent in structure, without multiplexing logic, and only support two precision switching.

[0007] The above schemes have some shortcomings: Fixed-precision MAC unit: unable to adapt to multi-scenario precision requirements, such as 8bit low precision (low power consumption) for voice wake-up and 16bit medium precision (high accuracy) for semantic recognition. Fixed precision leads to surplus computing power (high power consumption) in low-precision scenarios or insufficient precision (low accuracy) in high-precision scenarios; Software-configurable precision scheme: the quantization / dequantization process occupies CPU bandwidth, and the switching delay is high (usually > 10 clock cycles), which cannot meet the real-time requirements of voice processing (such as < 100ms for wake-up response). Moreover, quantization error easily leads to a decrease in recognition accuracy (usually > 5%); Double-precision hardware switching scheme: large hardware overhead (more than 60% increase in area of two subunits), only supports 2 precision, cannot cover 32bit high-precision scenarios (such as complex voice noise reduction), and needs to interrupt the current operation when switching, which has the risk of data loss. SUMMARY

[0008] The purpose of the present application is to provide a dynamic adaptive precision switching method and device for voice recognition NPU, to realize dynamic precision adaptive capability, to improve voice recognition accuracy with minimal area overhead, and to break through the energy efficiency bottleneck of traditional fixed-precision architecture.

[0009] To solve the above problems, the technical scheme of the present application is: A dynamic adaptive precision switching method for voice recognition NPU, comprising: Receiving a voice processing task and identifying the task type, and inputting the task type signal into an adaptive scheduling module; When it is determined to switch to a new task, the adaptive scheduling module queries a pre-stored precision-parallelism-power mapping table, determines the target precision and parallelism parameters according to the task type and power consumption constraints, and generates corresponding bit width configuration signals and parallelism enable signals; The switching synchronization module interacts with the MAC unit main controller, enters an idle gap after the current multiplication and addition operation period ends, and latches the configuration signals and enable signals; The bit width configuration module controls a switch matrix among 4*4 8bit MAC subunits according to the bit width configuration signal, and selectively splices the subunits into 8bit, 16bit or 32bit operation modes; The parallelism control module selectively activates 1*1, 2*2 or 4*4 scale subunits according to the parallelism enable signal; The error compensation module corrects historical data according to a corresponding compensation algorithm according to the precision switching direction; The MAC unit performs multiplication and addition operation of target precision to complete voice processing in the reconfigured hardware state.

[0010] According to an embodiment of the present application, the precision-parallelism-power consumption mapping table comprises a corresponding relationship of voice task type, target precision, parallelism and typical power consumption value, wherein voice wake-up corresponds to 8bit+1*1 parallelism, semantic recognition corresponds to 16bit+2*2 parallelism, and voice noise reduction corresponds to 32bit+4*4 parallelism.

[0011] According to an embodiment of the present application, the compensation algorithm of the error compensation module comprises: when switching from low precision to high precision, using adjacent data interpolation expansion algorithm to take the average value of current data and previous period data for bit width expansion; when switching from high precision to low precision, using a correction factor truncation algorithm to truncate the data.

[0012] According to an embodiment of the present application, the switching synchronization module completes configuration latching and hardware reconfiguration in 1 clock cycle after the current operation period ends, ensuring no data loss.

[0013] According to an embodiment of the present application, the bit width configuration module is configured to: when the target precision is 8bit, disconnect all splicing switches to make the subunits work independently; when the target precision is 16bit, close the splicing switches between 2*2 subunits; and when the target precision is 32bit, close the splicing switches of all 4*4 subunits.

[0014] A dynamic adaptive precision switching device for a voice recognition NPU, comprising: An adaptive scheduling module is configured to receive a voice task type signal, query a precision-parallelism-power consumption mapping table, and generate a bit width configuration signal and a parallelism enable signal; 8bit MAC subunits in a 4*4 array are interconnected by a programmable switch matrix; A bit width configuration module is connected to the switch matrix and controls the subunit splicing into 8bit, 16bit or 32bit operation modes according to the bit width configuration signal; A parallelism control module is connected to the subunit enable terminals and activates 1*1, 2*2 or 4*4 scale subunit arrays according to the parallelism enable signal. The switching synchronization module is connected with the MAC unit main controller and the bit width configuration module and the parallelism control module, and is used for latching the configuration signal and triggering hardware reconfiguration after the current operation period ends. The error compensation module is used for executing a corresponding compensation algorithm to correct historical data according to a switching direction in the precision switching process.

[0015] According to an embodiment of the present application, the switch matrix comprises controllable splicing switches arranged between adjacent subunits, and the bit width configuration module realizes dynamic reconstruction of the subunit array by controlling the on-off of the controllable splicing switches.

[0016] According to an embodiment of the present application, the error compensation module comprises: The interpolation expansion unit is used for executing adjacent data average value calculation when switching from low precision to high precision; The correction factor truncation unit is used for executing data truncation and error correction when switching from high precision to low precision.

[0017] According to an embodiment of the present application, the switching synchronization module comprises an idle gap detection unit and a configuration latch unit. The idle gap detection unit is used for capturing a safe time window of MAC unit hardware reconfiguration, so as to ensure that the precision switching process does not interfere with the ongoing multiply-add operation and avoids data loss or timing conflict. The configuration latch unit completes signal latching within 1 clock cycle after the current operation period ends.

[0018] The present application has the following advantages and positive effects compared with the prior art due to the use of the above technical solutions: The dynamic adaptive precision switching method for the speech recognition NPU in an embodiment of the present application aims at the core problems of the end-side speech recognition NPU in multiple scenes (wakeup, semantics, noise reduction), such as the inability to balance precision and energy efficiency, the serious waste of fixed precision hardware resources, the low software switching efficiency and error accumulation. By constructing a hardware architecture of a 4*4 reconfigurable MAC subunit array and a switch matrix, combining a task-driven adaptive scheduling mechanism (generating a configuration signal according to a precision-parallelism-power mapping table according to a task type), an operation period synchronization control technology (using idle gap latching configuration to realize single-period hardware reconfiguration) and a direction-sensitive error compensation algorithm (interpolating and expanding or correcting truncation of historical data), the present application realizes hardware-level dynamic lossless switching of the MAC unit between 8bit / 16bit / 32bit precisions, so that different speech tasks achieve the highest necessary computing power with the lowest necessary power consumption, and there is no data loss in the switching process. Finally, the energy efficiency rigidity of the fixed precision architecture is converted into the precision on-demand supply ability that can be deployed in engineering. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Figure 1 is a flow chart of a dynamic adaptive precision switching method for a speech recognition NPU according to an embodiment of the present application; Figure 2 Figure 2 is a block diagram of a dynamic adaptive precision switching device for a speech recognition NPU according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description and claims.

[0021] The following are several NPU MAC schemes: A fixed precision NPU MAC unit has fixed hardware module (multiplier, accumulator) bit width, no flexible adaptation logic, resulting in a contradiction that one precision is used for multiple scenarios, and power consumption and accuracy cannot be balanced; A software configurable precision MAC scheme relies on software layer data processing for precision switching, requires additional CPU resources to execute quantization / dequantization instructions, and has pipeline delay in software instruction execution, resulting in low switching efficiency and error accumulation; A double precision hardware switching scheme uses independent subunit + switch design, has no module reuse logic, has large hardware area redundancy, and only supports limited precision combinations, and cannot be extended to high precision scenarios such as 32 bits.

[0022] The industry's conventional solution is as follows: For the fixed precision defect: increase the number of hardware subunits (such as 8bit + 16bit + 32bit three sets of subunits), but this will increase the hardware area by more than 100%, which does not meet the lightweight terminal requirements; For the software scheme delay defect: optimize the software quantization algorithm (such as quantization parameter pre-computation), but only reduces the delay by 20%-30%, still cannot achieve hardware-level real-time performance; For the double precision hardware overhead defect: simplify the subunit circuit (such as sharing the accumulator), but this will cause data conflicts during precision switching, reducing the operation stability.

[0023] The industry generally believes that multi-precision switching needs to rely on multiple hardware or software quantization, but the present application breaks this recognition, realizes multi-precision (8bit / 16bit / 32bit) switching through single hardware subunit splicing + dynamic configuration, and integrates hardware-level error compensation and fast synchronization control, avoiding the area redundancy of multiple subunits, eliminating the delay and error of software quantization, and belonging to the innovative combination of hardware reuse + precise compensation, which is significantly different from the conventional idea of increasing hardware or optimizing software.

[0024] Referring to Figure 1 The embodiment provides a dynamic adaptive precision switching method for a speech recognition NPU, comprising: Receiving a speech processing task and identifying the task type, and inputting a task type signal into an adaptive scheduling module; When it is judged to switch to a new task, the adaptive scheduling module queries a pre-stored precision-parallelism-power consumption mapping table, determines target precision and parallelism parameters according to the task type and power consumption constraints, and generates corresponding bit width configuration signals and parallelism enable signals; The switching synchronization module interacts with a MAC unit main controller, enters an idle gap after the end of the current multiplication and addition operation period, and latches the configuration signals and enable signals; The bit width configuration module controls the switch matrix between 4x4 8bit MAC subunits according to the bit width configuration signals, and selectively splices the subunits into 8bit, 16bit or 32bit operation modes; The parallelism control module selectively activates 1x1, 2x2 or 4x4 scale subunits according to the parallelism enable signals; The error compensation module executes a corresponding compensation algorithm according to the precision switching direction and corrects historical data; The MAC unit performs multiplication and addition operation of target precision under the reconfigured hardware state to complete speech processing.

[0025] The method supports 8bit / 16bit / 32bit switching, adapts to all scenarios of speech wake-up (8bit), semantic recognition (16bit) and noise reduction (32bit), adopts hardware-level switching, the delay is ≤1 clock cycle, and the real-time requirement of speech is met.

[0026] Specifically, the dynamic adaptive precision switching method for the speech recognition NPU comprises the following steps: Step 1: The NPU receives a speech task (such as wake-up word detection and semantic recognition), and transmits a task type signal into an adaptive scheduling module; Step 2: Task feature analysis is performed to determine whether it is a new task: if it is a current execution task (such as continuous wake-up monitoring), the current precision operation is continued; if it is a new task (such as switching from wake-up to semantic recognition), step 3 is entered; Step 3: The adaptive scheduling module queries a pre-stored precision-parallelism-power consumption mapping table (Table 1 example), and determines target precision and parallelism parameters according to the task type (such as 16bit corresponding to semantic recognition) and current power consumption constraints (such as selecting a low parallelism when the battery power is low); Table 1 Step 4: Determine if precision switching is needed: If the target precision is consistent with the current precision (e.g., continuous semantic recognition), continue the current operation; if they are inconsistent (e.g., 8-bit → 16-bit), proceed to step 5; Step 5: Initialize the error compensation module and select the compensation algorithm according to the switching direction (low precision → high precision / high precision → low precision): if low → high, the interpolation expansion algorithm is enabled; if high → low, the correction factor truncation algorithm is enabled. Step 6: Switch the synchronization module to interact with the MAC unit main controller, wait for the current multiplication-accumulation operation cycle to end (ensure no data loss), and enter the idle interval; Step 7: The bit width configuration module controls the switch matrix according to the target precision: 8 bits will disconnect all splicing switches (independent sub-units), 16 bits will close the 2×2 sub-unit splicing switches, and 32 bits will close the 4×4 sub-unit splicing switches; Step 8: The parallelism control module outputs an enable signal according to the target parallelism: 1×1 enables 1 sub-unit, 2×2 enables 4 sub-units, and 4×4 enables 16 sub-units. Step 9: The error compensation module performs error correction: Taking 8bit→16bit as an example, the zero-expansion error is reduced by using an adjacent data interpolation algorithm (such as taking the average of the current 8 bits of data and the previous period's data, and expanding it to 16 bits); Step 10: The MAC unit performs target precision multiplication and addition operations: the multiplier processes the target precision data (e.g., 16bit × 16bit), the accumulator accumulates 32 bits of intermediate results, and the register stores the operation data; Step 11: Determine if the task is completed: If not completed (e.g., continuous semantic recognition), return to Step 2 to continue monitoring the task type; if completed, output the calculation result and the process ends.

[0027] The switching synchronization module includes an idle gap detection unit and a configuration latch unit. The idle gap detection unit is used to capture the safe time window for MAC unit hardware reconfiguration to ensure that the precision switching process does not interfere with the ongoing multiplication-accumulation operation and avoids data loss or timing conflicts. The configuration latch unit completes signal latching within one clock cycle after the end of the current operation cycle.

[0028] This idle gap detection unit is a key sub-module in the switching synchronization module, and it specifically implements the following functions: The system monitors the status signals of the MAC unit's main controller in real time (such as the operation completion flag and pipeline empty / full status) to identify the exact end point of the current multiply-accumulate operation cycle; it also determines whether the MAC array has entered an idle interval, which is a short interval in which all sub-units have completed effective calculations and new data has not yet been loaded.

[0029] Only after an idle gap is detected is the configuration latch unit allowed to capture and fix the new bit width / parallelism configuration signal; this prevents the configuration signal from being incorrectly latched during the operation, which could cause the sub-unit splicing / splitting action to destroy the pipeline data integrity.

[0030] The handshake mechanism of waiting before switching ensures that historical calculation results have been stably written to registers or the next level cache; it also provides a clear processing time boundary for the error compensation module, enabling it to complete the correction of historical data before hardware reconfiguration.

[0031] Once the idle gap detection is successful, the configuration latch unit is immediately triggered to complete the entire hardware reconfiguration process within one clock cycle. This synchronization mechanism is the core of achieving seamless switching, making precision adjustment transparent to upper-layer tasks.

[0032] This idle gap detection unit transforms the uncertainty of software-layer task switching into deterministic timing control at the hardware layer, fundamentally solving the problems of low switching efficiency and error susceptibility caused by CPU intervention delays or interrupt response lags in traditional solutions.

[0033] In this embodiment, the error compensation module, as a data preprocessing unit for precision switching, is embedded in the data path of the MAC array and includes the following core sub-units: Historical data buffer: Stores 8-bit / 16-bit input data from the last two operation cycles and intermediate accumulation results from one cycle, with a capacity equal to the data width of a 4×4 sub-cell array; Switching direction detector: Receives bit width configuration signal and parses the current switching mode (8→16bit, 16→8bit, 16→32bit, etc.). Interpolation extension unit: performs data bit width extension operations during low-to-high precision switching; Truncation correction unit: performs data compression and error correction during high-to-low precision switching; Dynamic correction factor register group: stores the compensation coefficient α corresponding to different speech tasks, and supports real-time updates.

[0034] Interface relationship: The input end is connected to the data input bus and intermediate result register of the MAC unit, and the output end is connected to the reconfigured MAC sub-unit array; the control end receives the compensation enable signal and direction detection signal from the switching synchronization module.

[0035] The interpolation extension algorithm is executed in two steps: 1. Data alignment and symbol extension: For 8-bit unsigned speech feature data (such as MFCC coefficients), perform high-bit zero padding to extend to 16 bits to obtain the base value D_base = {8'b0, original_8bit}; for 8-bit signed data (such as quantization weights), perform symbol extension D_base = {{8{original_8bit[7]}}, original_8bit}.

[0036] 2. Information Compensation Interpolation: Read the data D_prev from the previous cycle at the same position from the buffer, calculate the linear interpolation component: D_comp = (D_base + D_prev) >> 1; output the final 16-bit data: D_out = D_base + α × D_comp, where α is a task-related dynamic correction factor (0.01≤α≤0.05) used to control the fusion strength of historical data; its hardware implementation uses one 16-bit adder, one right shifter, and one multiplier (α×D_comp), with a delay of 2 clock cycles. Essentially, it compensates for the loss of high-frequency information due to insufficient quantization bit width by using first-order momentum estimation, reducing quantization noise energy by approximately 40%.

[0037] The correction factor truncation algorithm performs the following steps: 1. Truncation preprocessing: For the 16-bit data D_16, truncate the high 8 bits as the base value: D_trunc = D_16[15:8]; calculate the truncation error: E_trunc = D_16[7:0] (the low 8 bits that are discarded).

[0038] 2. Error Correction: Query the dynamic correction factor α (α=0.02 for semantic recognition, α=0.03 for noise reduction), calculate the correction amount: Δ = (α × E_trunc) >> 4 (right shift by 4 bits to map 256 levels of error to 16 levels); output 8-bit data: D_out = D_trunc + Δ, where Δ∈[0,15] is a small compensation value to prevent systematic bias caused by truncation. If D_trunc + Δ > 255, then saturate the output to 8'hFF.

[0039] Compared to direct truncation, the modified correction factor truncation algorithm can reduce the mean square error (MSE) by more than 60%, avoiding auditory distortion caused by sudden changes in the amplitude of the speech signal.

[0040] This embodiment presents a dynamic adaptive precision switching method for speech recognition NPUs. Addressing the core issues faced by edge-side speech recognition NPUs in various scenarios (wake-up, semantics, noise reduction), including the inability to balance precision and energy efficiency, significant waste of fixed-precision hardware resources, low software switching efficiency, and error accumulation, this method constructs a 4×4 reconfigurable MAC sub-unit array and switching matrix hardware architecture. Combined with a task-driven adaptive scheduling mechanism (generating configuration signals by querying a precision-parallelism-power consumption mapping table based on task type), computation cycle synchronization control technology (utilizing idle gaps to latch configurations for single-cycle hardware reconfiguration), and a direction-sensitive error compensation algorithm (interpolating and expanding or correcting truncation of historical data), it achieves hardware-level dynamic lossless switching of MAC units between 8-bit / 16-bit / 32-bit precision. This allows different speech tasks to achieve the highest necessary computing power with the lowest necessary power consumption, and the switching process is data-free. Ultimately, it transforms the rigid energy efficiency contradiction of fixed-precision architecture into an engineerable, deployable, on-demand precision supply capability.

[0041] Based on the same concept, this embodiment also provides a dynamic adaptive precision switching device for a speech recognition NPU, used to implement the above-described dynamic adaptive precision switching method for a speech recognition NPU. Please refer to... Figure 2 The device includes: The adaptive scheduling module receives the voice task type signal, queries the precision-parallelism-power consumption mapping table to generate the bit width configuration signal and the parallelism enable signal; The 4×4 array consists of 8-bit MAC sub-units, which are interconnected by a programmable switch matrix. The bit width configuration module is connected to a programmable switch matrix and controls the sub-units to be spliced ​​into 8-bit, 16-bit or 32-bit working modes according to the bit width configuration signal. The parallelism control module connects to the enable terminals of each sub-unit and activates the sub-unit array of 1×1, 2×2 or 4×4 scale according to the parallelism enable signal. The switching synchronization module is connected to the MAC unit main controller, bit width configuration module, and parallelism control module. It is used to latch the configuration signal and trigger hardware reconfiguration after the current operation cycle ends. The error compensation module is used to correct historical data by executing the corresponding compensation algorithm according to the switching direction during the precision switching process.

[0042] The switch matrix includes controllable splicing switches set between adjacent sub-units. The bit-width configuration module realizes dynamic reconstruction of the sub-unit array by controlling the on / off state of the controllable splicing switches.

[0043] The error compensation module includes: an interpolation expansion unit, used to calculate the average value of adjacent data when switching from low precision to high precision; and a correction factor truncation unit, used to perform data truncation and error correction when switching from high precision to low precision.

[0044] The switching synchronization module includes an idle gap detection unit and a configuration latch unit. The idle gap detection unit is used to capture the safe time window for MAC unit hardware reconfiguration to ensure that the precision switching process does not interfere with the ongoing multiplication and addition operations and avoid data loss or timing conflicts. The configuration latch unit completes signal latching within one clock cycle after the end of the current operation cycle.

[0045] The above-mentioned device is used to implement a dynamic adaptive precision switching method for speech recognition NPU. Its implementation method is similar and will not be described in detail here.

[0046] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A method for dynamic adaptive precision switching for a speech recognition NPU, characterized in that, include: Receive voice processing tasks and identify task types, then input the task type signal into the adaptive scheduling module; When it is determined that the task is to switch to a new task, the adaptive scheduling module queries the pre-stored precision-parallelism-power consumption mapping table, determines the target precision and parallelism parameters according to the task type and power consumption constraints, and generates the corresponding bit width configuration signal and parallelism enable signal. The switching synchronization module interacts with the MAC unit main controller, and enters an idle interval after the current multiply-accumulate operation cycle ends, latching the configuration signal and the enable signal; The bit width configuration module controls the switching matrix between 4×4 8-bit MAC sub-units according to the bit width configuration signal, and selectively splices the sub-units into 8-bit, 16-bit or 32-bit working modes. The parallelism control module selectively activates the sub-units of 1×1, 2×2, or 4×4 scale according to the parallelism enable signal; The error compensation module executes the corresponding compensation algorithm according to the precision switching direction to correct historical data; In the reconfigured hardware state, the MAC unit performs multiply-accumulate operations to achieve the target precision to complete voice processing.

2. The dynamic adaptive precision switching method for a speech recognition NPU as described in claim 1, characterized in that, The precision-parallelism-power consumption mapping table contains the correspondence between voice task types and target precision, parallelism, and typical power consumption values. Voice wake-up corresponds to 8 bits + 1 × 1 parallelism, semantic recognition corresponds to 16 bits + 2 × 2 parallelism, and voice noise reduction corresponds to 32 bits + 4 × 4 parallelism.

3. The dynamic adaptive precision switching method for a speech recognition NPU as described in claim 1, characterized in that, The error compensation module's compensation algorithm includes: when switching from low precision to high precision, an adjacent data interpolation expansion algorithm is used to expand the bit width by taking the average value of the current data and the previous period's data; when switching from high precision to low precision, a correction factor truncation algorithm is used to truncate the data.

4. The dynamic adaptive precision switching method for a speech recognition NPU as described in claim 1, characterized in that, The switching synchronization module completes configuration latching and hardware reconfiguration within one clock cycle after the end of the current operation cycle to ensure no data loss.

5. The dynamic adaptive precision switching method for a speech recognition NPU as described in claim 1, characterized in that, The bit width configuration module is configured to: disconnect all splicing switches to allow sub-units to work independently when the target precision is 8 bits; close the splicing switches between 2×2 sub-units when the target precision is 16 bits; and close the splicing switches of all 4×4 sub-units when the target precision is 32 bits.

6. A dynamic adaptive precision switching device for a speech recognition NPU, characterized in that, include: The adaptive scheduling module receives the voice task type signal, queries the precision-parallelism-power consumption mapping table to generate the bit width configuration signal and the parallelism enable signal; The 4×4 array consists of 8-bit MAC sub-units, which are interconnected by a programmable switch matrix. The bit width configuration module is connected to the switch matrix and controls the sub-units to be spliced ​​into 8-bit, 16-bit or 32-bit working modes according to the bit width configuration signal. The parallelism control module connects to the enable terminals of each sub-unit and activates the sub-unit array of 1×1, 2×2 or 4×4 scale according to the parallelism enable signal. The switching synchronization module is connected to the MAC unit main controller and the bit width configuration module and parallelism control module, and is used to latch the configuration signal and trigger hardware reconfiguration after the current operation cycle ends. The error compensation module is used to correct historical data by executing the corresponding compensation algorithm according to the switching direction during the precision switching process.

7. The dynamic adaptive precision switching device for a speech recognition NPU as described in claim 6, characterized in that, The switch matrix includes controllable splicing switches disposed between adjacent sub-units, and the bit width configuration module realizes dynamic reconstruction of the sub-unit array by controlling the on / off state of the controllable splicing switches.

8. The dynamic adaptive precision switching device for a speech recognition NPU as described in claim 6, characterized in that, The error compensation module includes: The interpolation extension unit is used to calculate the average value of adjacent data when switching from low precision to high precision. The correction factor truncation unit is used to perform data truncation and error correction when switching from high precision to low precision.

9. The dynamic adaptive precision switching device for a speech recognition NPU as described in claim 6, characterized in that, The switching synchronization module includes an idle gap detection unit and a configuration latch unit; The idle gap detection unit is used to capture the safe time window for MAC unit hardware reconfiguration to ensure that the precision switching process does not interfere with the ongoing multiplication and addition operations, and to avoid data loss or timing conflicts. The configuration latch unit completes signal latching within one clock cycle after the end of the current operation cycle.

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