System and method for tone mapping high dynamic range images for high quality deep learning based processing

Abstract

Systems and methods for tone mapping high dynamic range (HDR) images for high quality deep learning based processing are disclosed. In one embodiment, a graphics processor comprises: a media pipeline to generate media requests for processing images; and an execution unit to receive a media request from the media pipeline. The execution unit is configured to: calculate an automatic exposure ratio of the image to efficiently tone map the image; scaling the image using the calculated automatic exposure ratio; and applying a tone mapping operator comprising a logarithmic function to the image and scaling the logarithmic function to generate a tone-mapped image.

Description

This invention patent application is a divisional application of the invention patent application with application number 202010227257.6 filed on March 27, 2020, and named “System and method for tone mapping high dynamic range images for high-quality deep learning-based processing”. Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to tone mapping of high dynamic range (HDR) images for high quality deep learning based processing. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations to process vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to increase processing efficiency. A general overview of software and hardware for the SIMT architecture can be found in Shane Cook's "CUDA Programming", Chapter 3, pages 37-51 (2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Therefore, in order that the manner in which the features of the present embodiments set out above may be understood in detail, a more particular description of the embodiments briefly outlined above may be made with reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments and, therefore, should not be considered to limit the scope of the embodiments.

[0005] Figure 1 is a block diagram of a processing system 100 according to an embodiment;

[0006] Figures 2A-2D illustrates a computing system and a graphics processor according to an embodiment;

[0007] Figure 3A-3C is a block diagram of an additional graphics processor and computing accelerator architecture according to an embodiment;

[0008] Figure 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments;

[0009] Figure 5A-5B illustrates thread execution logic 500 including an array of processing elements employed in a graphics processor core according to an embodiment;

[0010] Figure 6 illustrates an additional execution unit 600 according to an embodiment;

[0011] Figure 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments;

[0012] Figure 8 is a block diagram of another embodiment of a graphics processor 800 according to an embodiment;

[0013] Fig. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments;

[0014] Fig. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment.

[0015] Fig.10 illustrates an exemplary graphical software architecture of data processing system 1000 according to some embodiments;

[0016] Fig.11A is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit to perform operations according to an embodiment;

[0017] Fig. 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 in accordance with some embodiments;

[0018] Fig. 11C A package assembly 1190 is shown that includes multiple units of hardware logic chiplets connected to a substrate 1180 (eg, a base die).

[0019] Fig.11D A package assembly 1194 including interchangeable chiplets 1195 is illustrated in accordance with an embodiment.

[0020] Fig.12 An exemplary integrated circuit is shown, and Figures 13A-13B illustrates an associated graphics processor that may be manufactured using one or more IP cores according to various embodiments;

[0021] Fig.14 Illustrated is a machine learning software stack according to an embodiment.

[0022] Figures 15A-15B Illustration of the layers of an exemplary deep neural network.

[0023] Fig.16 An exemplary recurrent neural network is shown.

[0024] Fig.17 Illustration of the training and deployment of a deep neural network.

[0025] Fig.18 is a block diagram illustrating distributed learning.

[0026] Fig.19 A method 1900 is illustrated having an exemplary sequence of operations for image processing an HDR image using a graphics processing unit, a graphics multiprocessor, a graphics processor, or a CPU, according to one embodiment.

[0027] Fig. 20 A method 2000 is illustrated having an exemplary sequence of operations for performing image processing (eg, anti-aliasing, super-resolution, demosaicing, noise reduction) on an HDR image using a graphics processing unit, a graphics multiprocessor, a graphics processor, or a CPU, according to one embodiment. DETAILED DESCRIPTION

[0028] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0029] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments. System Overview

[0030] Figure 11 is a block diagram of a processing system 100 according to an embodiment. System 100 may be used in a single processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device, such as for use within an Internet of Things (IoT) device having wired or wireless connectivity to a local area network or a wide area network.

[0031] In one embodiment, the system 100 may include, be coupled with, or be incorporated into a server-based gaming platform, a gaming console including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile phone, a smart phone, a tablet computing device, or a mobile Internet-connected device such as a notebook with low internal storage capacity. The processing system 100 may also include, be coupled with, or be integrated into a wearable device such as a smart watch wearable device; smart glasses or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, the processing system 100 includes a television or set-top box device, or is part of a television or set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated into an autonomous vehicle, such as a bus, a tractor trailer, an automobile, an electric or electrical cycle, an airplane, or a glider (or any combination thereof). The autonomous vehicle may use system 100 to process the environment sensed around the vehicle.

[0032] In some embodiments, one or more processors 102 each include one or more processor cores 107 for processor instructions that, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, the instruction set 109 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). One or more processor cores 107 may process different instruction sets 109, which may include instructions for facilitating emulation of other instruction sets. The processor core 107 may also include other processing devices, such as a digital signal processor (DSP).

[0033] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared between the processor cores 107 using known cache coherence techniques. A register file 106 may additionally be included in the processor 102, and the register file 106 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0034] In some embodiments, one or more processors 102 are coupled to one or more interface buses 110 to transmit communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 can be a processor bus, such as a version of a direct media interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCIexpress), memory buses, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connections to I / O devices via a local I / O bus.

[0035] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with appropriate performance to act as a process memory. In one embodiment, the memory device 120 may operate as a system memory for the system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute applications or processes. The memory controller 116 is also coupled to an optional external graphics processor 118, which may communicate with one or more graphics processors 108 in the processor 102 to perform graphics operations and media operations. In some embodiments, graphics operations, media operations, or computing operations may be assisted by an accelerator 112, which is a coprocessor that can be configured to perform a collection of specialized graphics operations, media operations, or computing operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator for optimizing machine learning or computing operations. In one embodiment, the accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in concert with the graphics processor 108. In one embodiment, external accelerator 119 may be used instead of accelerator 112 , or may be used in conjunction with accelerator 112 .

[0036] In some embodiments, display device 111 may be connected to processor(s) 102. Display device 111 may be one or more of: an internal display device, such as in a mobile electronic device or laptop device; or an external display device attached via a display interface (e.g., display port, etc.). In one embodiment, display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0037] In some embodiments, the platform controller hub 130 enables peripheral devices to be connected to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI express). The touch sensor 125 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G or long term evolution (LTE) transceiver. The firmware interface 128 enables communication with the system firmware and may be, for example, a unified extensible firmware interface (UEFI). The network controller 134 may enable a network connection to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to the interface bus 110. In one embodiment, the audio controller 146 is a multi-channel high definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 130 may also be connected to one or more Universal Serial Bus (USB) controllers 142 to connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

[0038] It will be appreciated that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 116 and the platform controller hub 130 may be integrated into a discrete external graphics processor, such as the external graphics processor 118. In one embodiment, the platform controller hub 130 and / or the memory controller 116 may be external to one or more processors 102. For example, the system 100 may include the external memory controller 116 and the platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 102.

[0039] For example, a circuit board ("sled") may be used on which components (such as CPUs, memory and other components) are placed, designed to achieve improved thermal performance. In some examples, processing components such as processors are located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by the design, the components can operate at higher frequencies and power levels than typical systems, thereby increasing performance. In addition, the sled is configured to blindly mate power and data communication cables in the rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled and / or replaced. Similarly, the various components (such as processors, accelerators, memory and data storage devices) located on the sled are configured to be easily upgraded due to their increased spacing relative to each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

[0040] The data center may utilize a single network fabric ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds may be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center may, in use, concentrate physically disaggregated resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.) and data storage drives, and provide them to computing resources (e.g., processors) as needed, thereby enabling the computing resources to access these concentrated resources as if the concentrated resources were local.

[0041] A power supply or power source may provide voltage and / or current to the system 100 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current-direct current) adapter for plugging into a wall socket. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging by approaching a charging field. In one example, the power source may include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

[0042] Figure 2A-2D Illustrated is a computing system and graphics processor provided by embodiments described herein. Figure 2A-2D Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0043] Figure 2A 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. The processor 200 may include additional cores up to and including the additional core 202N represented by the dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache unit 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between each cache unit 206 and 204A-204N.

[0044] In some embodiments, the processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI buses or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0045] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreaded processing. The system agent core 210 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 202A-202N and the graphics processor 208.

[0046] In some embodiments, the processor 200 additionally includes a graphics processor 208 for performing graphics processing operations. In some embodiments, the graphics processor 208 is coupled to the set of shared cache units 206 and to a system agent core 210, which includes one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 for driving the graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208.

[0047] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of the processor 200. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 212 via an I / O link 213.

[0048] Exemplary I / O link 213 represents at least one of a plurality of various I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of processor cores 202A-202N and graphics processor 208 may use embedded memory module 218 as a shared last-level cache.

[0049] In some embodiments, the processor cores 202A-202N are isomorphic cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 202A-202N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In one fact, the processor cores 202A-202N are heterogeneous in terms of computing power. In addition, the processor 200 may be implemented on one or more chips, or may be implemented as a SoC integrated circuit having the illustrated components in addition to other components.

[0050] Figure 2B is a block diagram of the hardware logic of graphics processor core 219 according to some embodiments described herein. Figure 2BThose elements having the same reference numerals (or names) as elements of any other figure in this document can operate or function in any manner similar to, but not limited to, those described elsewhere in this document. A graphics processor core 219 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. An example of a graphics processor core 219 is a graphics core slice, and based on a target power envelope and performance envelope, a graphics processor as described herein may include multiple graphics core slices. Each graphics processor core 219 may include a fixed function block 230 that is coupled to a plurality of sub-cores 221A-221F (also referred to as sub-slices), and the plurality of sub-cores 221A-221F include blocks of modular general-purpose and fixed-function logic.

[0051] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231, which may be shared by all sub-cores of graphics processor core 219, for example, in a lower performance and / or lower power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., as described in FIGS. 3 and 4 below). Figure 4 ), a video front end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that unifies the return buffers (e.g., as described below in Figure 4 The unified return buffer 418 in .

[0052] In one embodiment, fixed function block 230 also includes graphics SoC interface 232, graphics microcontroller 233, and media pipeline 234. Graphics SoC interface 232 provides an interface between graphics processor core 219 and other processor cores within the system on chip integrated circuit. Graphics microcontroller 233 is a programmable subprocessor that can be configured to manage various functions of graphics processor core 219, including thread dispatching, scheduling, and preemption. Media pipeline 234 (e.g., FIG. 3 and FIG. 4 ) Figure 4 The media pipeline 316 of the embodiment includes logic for facilitating decoding, encoding, pre-processing and / or post-processing of multimedia data including image data and video data. The media pipeline 234 implements media operations via requests to computational or sampling logic within the sub-cores 221A-221F.

[0053] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomicity, which may be shared between the graphics processor core 219 and the CPU within the SoC. The SoC interface 232 may also implement power management control for the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains within the SoC. In one embodiment, the SoC interface 232 enables receiving a command buffer from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of the one or more graphics cores within the graphics processor. These commands and instructions may be dispatched to media pipeline 234 when media operations are to be performed, or to geometry and fixed function pipelines (eg, geometry and fixed function pipeline 231, geometry and fixed function pipeline 237) when graphics processing operations are to be performed.

[0054] The graphics microcontroller 233 may be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment, the graphics microcontroller 233 may perform graphics and / or computational workload scheduling for each graphics parallel engine within the execution unit (EU) arrays 222A-222F, 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of a SoC including the graphics processor core 219 may submit a workload via one of a plurality of graphics processor doorbells, which invokes a scheduling operation to the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to the command stream converter, preempting an existing workload running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, graphics microcontroller 233 may also facilitate a low power or idle state for graphics processor core 219, thereby providing graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0055] The graphics processor core 219 may have more or fewer sub-cores 221A-221F than those shown, up to N modular sub-cores. For each set of N sub-cores, the graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipelines 237, and additional fixed function logic 238 for accelerating various graphics and compute processing operations. The shared function logic 235 may include logic that is shared by each of the N sub-cores within the graphics processor core 219, and logic that is shared by each of the N sub-cores within the graphics processor core 219. Figure 4 The shared function logic 420 (e.g., sampler logic, math logic, and / or inter-thread communication logic) of the graphics processor core 219 may be associated with the shared function logic 420 (e.g., sampler logic, math logic, and / or inter-thread communication logic). The shared and / or cache memory 236 may be a last-level cache for the set 221A-221F of N sub-cores within the graphics processor core 219, and may also serve as a shared memory accessible by multiple sub-cores. A geometry / fixed function pipeline 237 may be included within the fixed function block 230 instead of the geometry / fixed function pipeline 231, and the geometry / fixed function pipeline 237 may include the same or similar logic units.

[0056] In one embodiment, the graphics processor core 219 includes additional fixed function logic 238, which may include various fixed function acceleration logic for use by the graphics processor core 219. In one embodiment, the additional fixed function logic 238 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline within the geometry / fixed function pipelines 238, 231; and a culling pipeline, which is an additional geometry pipeline that may be included in the additional fixed function logic 238. In one embodiment, the culling pipeline is a streamlined version of the full geometry pipeline. The full pipeline and the culling pipeline can execute different instances of the same application, each with a separate context. Position-only shading can hide long culling runs for discarded triangles, thereby enabling shading to be completed earlier in some instances. For example and in one embodiment, the culling pipeline logic within the additional fixed function logic 238 can execute the position shader in parallel with the main application and generally generate key results faster than the full pipeline because the culling pipeline only takes the position attributes of the vertices and shades them without performing rasterization and rendering of the pixels to the frame buffer. The culling pipeline can use the generated key results to calculate visibility information for all triangles, regardless of whether those triangles are culled. The full pipeline (which in this example may be referred to as a replay pipeline) can consume this visibility information to skip culled triangles, thereby only shading visible triangles that are ultimately passed to the rasterization stage.

[0057] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, which is used to include an optimized implementation for machine learning training or inference.

[0058] Included within each graphics sub-core 221A-221F is a collection of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests made by a graphics pipeline, a media pipeline, or a shader program. Graphics sub-cores 221A-221F include: multiple EU arrays 222A-222F, 224A-224F; thread dispatch and inter-thread communication (TD / IC) logic 223A-223F; 3D (e.g., texture) samplers 225A-225F; media samplers 206A-206F; shader processors 227A-227F; and shared local memory (SLM) 228A-228F. EU arrays 222A-222F, 224A-224F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics operations, media operations, or computing operations (including graphics programs, media programs, or computing shader programs). TD / IC logic 223A-223F performs local thread dispatch and thread control operations for execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. 3D samplers 225A-225F can read textures or other 3D graphics-related data into memory. 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. Media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F can alternately include unified 3D and media samplers. Threads executing on execution units within each of the sub-cores 221A-221F may utilize shared local memory 228A-228F within each sub-core, such that threads executing within a thread group can execute using a common pool of on-chip memory.

[0059] Figure 2C A graphics processing unit (GPU) 239 is illustrated that includes a dedicated set of graphics processing resources arranged as multi-core groups 240A - 240N. While details of only a single multi-core group 240A are provided, it will be understood that other multi-core groups 240B - 240N may be equipped with the same or similar set of graphics processing resources.

[0060] As illustrated, multi-core group 240A may include a set 243 of graphics cores, a set 244 of tensor cores, and a set 245 of ray tracing cores. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set 242 of register files stores operand values ​​used by cores 243, 244, 245 when executing graphics threads. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and slice registers for storing tensor / matrix values. In one embodiment, the slice registers are implemented as a combined set of vector registers.

[0061] One or more combined first level (L1) caches and shared memory units 247 store graphics data locally within each multi-core group 240A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 247 may also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 253 shared by all multi-core groups 240A-240N or a subset of multi-core groups 240A-240N stores graphics data and / or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across multiple multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to a memory 249, which may be a system memory (e.g., DRAM) and / or a dedicated graphics memory (e.g., GDDR6 memory).

[0062] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O devices 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O devices 252 to system memory 249. In one embodiment, IOMMU 251 manages page tables for mapping virtual addresses to multiple sets of physical addresses in system memory 249. In this embodiment, I / O devices 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

[0063] In one implementation, the IOMMU 251 supports virtualization. In this case, the IOMMU 251 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 249). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out at context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Although not described in detail in the prior art, the IOMMU 251 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 249). Figure 2C 240A-240N, but each of the cores 243, 244, 245 and / or multi-core groups 240A-240N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0064] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated on a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip, or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the underlying principles of the invention are not limited to this particular implementation.

[0065] In one embodiment, the tensor core 244 includes multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations can be used for neural network training and inference. The tensor core 244 can perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0066] In a deep learning implementation, parallel matrix multiplication work can be scheduled for execution on the tensor core 244. The training of neural networks in particular requires a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the tensor core 244 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the slice register, and for each of the N cycles, at least one column of the second matrix is ​​loaded. For each cycle, there are N dot products that are processed.

[0067] Depending on the specific implementation, matrix elements can be stored in different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and to nibbles).

[0068] In one embodiment, the ray tracing core 245 accelerates ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, the ray tracing core 245 includes a ray traversal / intersection circuit that uses a bounding volume hierarchy (BVH) to perform ray traversals and identify intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 245 may also include circuits for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 245 performs traversal operations and intersection operations in conjunction with the image processing techniques 244A (e.g., image denoising, anti-aliasing, super-resolution, demosaicing, etc.) described herein (e.g., methods 1900 and 2000), at least a portion of which may be executed on the tensor core 244. For example, in one embodiment, the tensor core 244 implements a deep learning neural network to perform denoising on frames generated by the ray tracing core 245. However, CPU(s) 246, graphics core 243, and / or ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0069] In addition, as described above, a distributed approach to denoising may be employed in which the GPU 239 is in a computing device coupled to other computing devices via a network or high-speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0070] In one embodiment, the ray tracing core 245 handles all BVH traversals and ray-primitive intersections, thereby preventing the graphics core 243 from being overloaded with thousands of instructions for each ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuits for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuits for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, in one embodiment, the multi-core group 240A can simply initiate ray detection, and the ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 245 performs traversal and intersection operations, the other cores 243, 244 are freed up to perform other graphics or computational work.

[0071] In one embodiment, each ray tracing core 245 includes a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed up to perform other forms of graphics work.

[0072] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between graphics core 243 and ray tracing core 245.

[0073] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable the assignment of a unique set of shaders and textures to each object. Another ray tracing platform that can be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it is noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0074] In general, each core 245, 244, 243 may support a ray tracing instruction set including instructions / functions for: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0075] Ray Generation - Executes ray generation instructions for each pixel, sample, or other user-defined work distribution.

[0076] Closest Hit - A nearest hit command may be executed to locate the closest intersection of a ray with a primitive within the scene.

[0077] Any Hit - Any hit instruction identifies multiple intersections between rays and primitives within the scene, thereby potentially identifying new closest intersection points.

[0078] Intersection ——The intersection instruction performs a ray-primitive intersection test and outputs the result.

[0079] Per-primitive Bounding box Construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0080] Miss - Indicates that the ray missed the scene or any geometry within the specified region of the scene.

[0081] Visit ——Indicates the subvolume that the ray will traverse.

[0082] Exceptions - Includes various types of exception handlers (e.g., called for various error conditions).

[0083] Figure 2D 2 is a block diagram of a general purpose graphics processor unit (GPGPU) 270 according to an embodiment described herein, which GPGPU 270 can be configured as a graphics processor and / or a computing accelerator. GPGPU 270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that can be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 can be mapped to memory addresses accessible by one or more CPUs 246. Access to memories 271 and 272 can be facilitated via a memory controller 268. In one embodiment, memory controller 268 includes an internal direct memory access (DMA) controller 269, or can include logic for performing operations that would otherwise be performed by a DMA controller.

[0084] GPGPU 270 includes a plurality of cache memories, including an L2 cache 253, an L1 cache 254, an instruction cache 255, and a shared memory 256, at least a portion of which may also be partitioned as cache memories. GPGPU 270 also includes a plurality of compute units 260A-260N. Each compute unit 260A-260N includes a set 261 of vector registers, a set 262 of scalar registers, a set 263 of vector logic units, and a set 264 of scalar logic units. Computing units 260A-260N may also include a local shared memory 265 and a program counter 266. Computing units 260A-260N may be coupled to a constant cache 267, which may be used to store constant data, which is data that will not change during the execution of a kernel program or a shader program executed on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data may be fetched directly into scalar registers 262 .

[0085] During operation, one or more CPUs 246 may write commands to registers in GPGPU 270, or to memory in GPGPU 270 that has been mapped to an accessible address space. Command processor 257 may read commands from registers or memory and determine how to process those commands within GPGPU 270. Thread dispatcher 258 may then be used to dispatch threads to computing units 260A-260N to execute those commands. Each computing unit 260A-260N may execute threads independently of other computing units. In addition, each computing unit 260A-260N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. Command processor 257 may interrupt one or more CPUs 246 when the submitted commands are completed.

[0086] Figure 3A-3C Block diagram illustrating additional graphics processor and computing accelerator architectures provided by embodiments described herein. Figure 3A-3C Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0087] Figure 3A3 is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0088] In some embodiments, the graphics processor 300 also includes a display controller 302 for driving display output data to a display device 318. The display controller 302 includes hardware for compositing one or more overlay planes and multiple layers of video or user interface elements for a display. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as, MPEG-2), Advanced Video Coding (AVC) formats (such as, H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as, JPEG, and Motion JPEG (MJPEG) formats).

[0089] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0090] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed-function elements that perform various tasks within elements and / or generated execution threads of 3D / media subsystem 315. Although 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0091] In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of the video codec engine 306. In some embodiments, the media pipeline 316 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 315. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0092] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D threads and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes a shared memory for sharing data between threads and for storing output data, which includes registers and addressable memory.

[0093] Figure 3B A graphics processor 320 having a tiled architecture is shown in accordance with an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having graphics engine slices 310A-310D. Figure 3A310D. Each graphics engine slice 310A-310D may be interconnected via a set 323A-323F of slice interconnects. Each graphics engine slice 310A-310D may also be connected to a memory module or memory device 326A-326D via a memory interconnect 325A-325D. The memory device 326A-326D may use any graphics memory technology. For example, the memory device 326A-326D may be a graphics double data rate (GDDR) memory. In one embodiment, the memory device 326A-326D is a high bandwidth memory (HBM) module that may be on a die with its corresponding graphics engine slice 310A-310D. In one embodiment, the memory device 326A-326D is a stacked memory device that may be stacked on top of their corresponding graphics engine slice 310A-310D. In one embodiment, each graphics engine slice 310A-310D and associated memory 326A-326D resides on a separate chiplet that is bonded to a base die or substrate, such as in Figure 11B-Figure 11D As described in further detail in .

[0094] The graphics processing engine cluster 322 may be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 may enable communication between the graphics engine slices 310A-310D and components such as the video codec 306 and one or more replica engines 304. The replica engines 304 may be used to move data out of the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory), move data into the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory), and move data between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine slices 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor may also be configured as a graphics accelerator or a computing accelerator. In an accelerometer configuration, display controller 302 and display device 318 may be omitted.

[0095] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or system components. Host interface 328 may be, for example, a PCI express bus or another type of host system interface.

[0096] Figure 3CFIG. 3 shows a computing accelerator 330 according to an embodiment described herein. The computing accelerator 330 may include Figure 3B The computing engine cluster 332 may include a set 340A-340D of computing engine slices, which include execution logic optimized for parallel or vector-based general computing operations. In some embodiments, the computing engine slices 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computing engine slices 340A-340D may include logic for performing media acceleration. The computing engine slices 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and the memory interconnects 325A-325D may be technologies similar to those in the graphics processor 320, or may be different technologies. The graphics compute engine slices 340A-340D may also be interconnected via a set of slice interconnects 323A-323F and may be connected to and / or interconnected by a fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336 that may be configured as a device-wide cache. The compute accelerator 330 may also be configured to communicate with the CPU 324. Figure 3B The graphics processor 320 in FIG. 1 is connected to a host processor and memory via a host interface 328 in a similar manner.

[0097] Graphics processing engine

[0098] Figure 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is Figure 3A A version of the GPE 310 shown in FIG. Figure 3B The graphics engine slices 310A-310D in FIG. Figure 4 Those elements having the same reference numerals (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Figure 3A 410. The 3D pipeline 312 and the media pipeline 316 of the GPE 410. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included in the GPE 410. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 410.

[0099] In some embodiments, GPE 410 is coupled to or includes a command stream converter 403, which provides a command stream to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command stream converter 403 is coupled to a memory, which can be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 403 receives commands from the memory and sends these commands to 3D pipeline 312 and / or media pipeline 316. These commands are instructions taken from a circular buffer that stores commands for 3D pipeline 312 and media pipeline 316. In one embodiment, the circular buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. 3D pipeline 312 and media pipeline 316 process commands and data by executing operations via logic within the respective pipelines or by dispatching one or more execution threads to graphics core array 414. In one embodiment, graphics core array 414 includes blocks of one or more graphics cores (e.g., (multiple) graphics cores 415A, (multiple) graphics cores 415B), each block including one or more graphics cores. Each graphics core includes a collection of graphics execution resources, including: general execution logic and graphics-specific execution logic for performing graphics operations and computing operations; and fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0100] In various embodiments, the 3D pipeline 312 may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified execution resource block for use in processing these shader programs. The multi-function execution logic (e.g., execution unit) within the (multiple) graphics cores 415A-415B of the graphics core array 414 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0101] In some embodiments, graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution units include general purpose logic that can be programmed to perform parallel general purpose computing operations in addition to performing graphics processing operations. The general purpose logic can be used with Figure 1 (multiple) processor cores 107 or Figure 2A The general logic within the cores 202A-202N in the process performs processing operations in parallel or in combination.

[0102] Output data generated by threads executing on graphics core array 414 may output data to memory in unified return buffer (URB) 418. URB 418 may store data for multiple threads. In some embodiments, URB 418 may be used to send data between different threads executing on graphics core array 414. In some embodiments, URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 420.

[0103] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0104] The graphics core array 414 is coupled to shared function logic 420, which includes a plurality of resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide specialized, complementary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler logic 421, math logic 422, and inter-thread communication (ITC) logic 423. In addition, some embodiments implement one or more caches 425 within the shared function logic 420.

[0105] Shared functionality is implemented at least in cases where demand for a given specialized functionality is insufficient to be included in the graphics core array 414. Instead, a single instantiation of that specialized functionality is implemented as an independent entity in the shared functionality logic 420 and is shared between execution resources within the graphics core array 414. The exact set of functions that are shared between the graphics core array 414 and included within the graphics core array 414 varies from embodiment to embodiment. In some embodiments, specific shared functionality within the shared functionality logic 420 that is widely used by the graphics core array 414 may be included within the shared functionality logic 416 within the graphics core array 414. In various embodiments, the shared functionality logic 416 within the graphics core array 414 may include some or all of the logic within the shared functionality logic 420. In one embodiment, all logic elements within the shared functionality logic 420 may be replicated within the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared functionality logic 420 is excluded in favor of the shared functionality logic 416 within the graphics core array 414.

[0107] Execution Unit

[0108] Figure 5A-Figure 5B Thread execution logic 500 is illustrated including an array of processing elements employed in a graphics processor core, according to embodiments described herein. Figure 5A-Figure 5B Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Figure 5A-Figure 5B An overview of thread execution logic 500 is shown, which may represent a Figure 2B The hardware logic of each sub-core 221A-221F is shown in FIG. Figure 5A represents an execution unit within a general-purpose graphics processor, and Figure 5B Represents an execution unit that can be used within a computing accelerator.

[0109] As in Figure 5A As shown in FIG. 5 , in some embodiments, thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including a plurality of execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 508A, 508B, 508C, 508D, up to any one of 508N-1 and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 500 includes one or more connections to a memory (such as a system memory or a cache memory) through the instruction cache 506, the data port 514, the sampler 510, and one or more of the execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a self-contained programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of separate execution units.

[0110] In some embodiments, execution units 508A-508N are primarily used to execute shader programs. Shader processor 502 can process various shader programs and can dispatch execution threads associated with shader programs via thread dispatcher 504. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics pipelines and media pipelines and instantiating the requested threads on one or more execution units in execution units 508A-508N. For example, a geometry pipeline can dispatch vertex shaders, tessellation shaders, or geometry shaders to thread execution logic for processing. In some embodiments, thread dispatcher 504 can also process runtime thread generation requests from executed shader programs.

[0111] In some embodiments, execution units 508A-508N support an instruction set including native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each execution unit in execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations enable efficient execution environments in the face of high latency memory accesses. Each hardware thread in each execution unit has a dedicated high-bandwidth register file and associated independent thread states. For pipelines capable of integer operations, single-precision floating-point operations, and double-precision floating-point operations, capable of SIMD branching capabilities, capable of logical operations, capable of transcendental operations, and capable of other miscellaneous operations, execution is multi-issued for each clock. While waiting for data from a shared function in memory or a shared function, dependency logic within execution units 508A-508N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including different vertex shaders. Embodiments may be applied to use execution utilizing single instruction multiple threads (SIMT) as an alternative to, or in addition to, a SIMD use case. References to SIMD cores or operations may also be applied to SIMT, or applied to SIMD in conjunction with SIMT.

[0112] Each execution unit in execution units 508A-508N operates on arrays of data elements. The number of data elements is the "execution size," or number of lanes for an instruction. An execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) used for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0113] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process each element based on the data size of the element. For example, when a 256-bit wide vector is operated, 256 bits of the vector are stored in registers, and the execution unit operates the vector as four independent 64-bit compact data elements (quad word (QW) size data elements), eight independent 32-bit compact data elements (double word (DW) size data elements), sixteen independent 16-bit compact data elements (data elements of word (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0114] In one embodiment, one or more execution units may be combined into a fused execution unit 509A-509N having a thread control logic (507A-507N) common to the fused EU. Multiple EUs may be fused into a EU group. Each EU in a fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group may vary according to the embodiment. In addition, various SIMD widths may be executed EU by EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, a fused execution unit 509A includes a first EU 508A, a second EU 508B, and a thread control logic 507A common to the first EU 508A and the second EU 508B. Thread control logic 507A controls threads executing on fused graphics execution unit 509A, allowing each EU within fused execution units 509A-509N to execute using a common instruction pointer register.

[0115] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executed on the execution logic 500 may also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 510 includes specialized texture or media sampling functions to process texture data or media data during the sampling process before providing the sampled data to the execution unit.

[0116] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 500 via thread generation and dispatch logic. Once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, and the value of each vertex attribute is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 502 then executes the pixel shader program or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 502 dispatches the thread to the execution unit (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses the texture sampling logic in the sampler 510 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0117] In some embodiments, data port 514 provides a memory access mechanism for thread execution logic 500 to output processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

[0118] In one embodiment, the execution logic 500 may also include a ray tracer 505 that can provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be used with Figure 2C The ray tracing instruction set supported by the ray tracing core 245 in may be similar or different.

[0119] Figure 5B Illustrated are exemplary internal details of an execution unit 508 according to an embodiment. Graphics execution unit 508 may include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, an issue unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and a set of dedicated integer SIMD ALUs 535 in one embodiment. GRF 524 and ARF 526 include a set of general register files and architectural register files associated with each simultaneous hardware thread that may be active in graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in ARF 526, while data used during thread execution is stored in GRF 524. The execution state of each thread, including the instruction pointer for each thread, may be maintained in thread-specific registers in ARF 526.

[0120] In one embodiment, graphics execution unit 508 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are divided across logic for executing multiple simultaneous threads. The number of logical threads that can be executed by graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0121] In one embodiment, the graphics execution unit 508 may issue multiple instructions in coordination, which may each be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 may dispatch the instruction to one of the following for execution: the send unit 530, the branch unit 532, or (multiple) SIMD FPUs 534. Each execution thread may access 128 general registers within the GRF 524, wherein each register may store 32 bytes accessible as a SIMD 8 element vector with 32-bit data elements. In one embodiment, each execution unit thread has access to 4 kilobytes within the GRF 524, but the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. In one embodiment, the graphics execution unit 508 is partitioned into seven hardware threads that may independently perform computing operations, but the number of threads of each execution unit may also vary according to the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment in which seven threads may access 4 kilobytes, the GRF 524 may store a total of 28 kilobytes. With 16 threads accessing 4 kilobytes, a total of 64 kilobytes can be stored by GRF 524. Flexible addressing modes may permit multiple registers to be addressed together, creating effectively wider registers or representing strided rectangular block data structures.

[0122] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed through message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

[0123] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 for performing floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 534 can SIMD perform up to a number M of 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capabilities that support high throughput transcendental math functions and double precision 64-bit floating points. In some embodiments, a set 535 of 8-bit integer SIMD ALUs also exists and can be specifically optimized to perform operations associated with machine learning calculations.

[0124] In one embodiment, an array of multiple instances of graphics execution unit 508 may be instantiated in graphics sub-core groupings (e.g., sub-slices). For scalability, product architects may choose the exact number of execution units per sub-core grouping. In one embodiment, execution unit 508 may execute instructions across multiple execution lanes. In further embodiments, each thread executed on graphics execution unit 508 is executed on a different lane.

[0125] Figure 6 An additional execution unit 600 according to an embodiment is shown. The execution unit 600 may be a processor for executing, for example, Figure 3C The execution unit 600 may be a computationally optimized execution unit used in the computing engine slices 340A-340D in the embodiment of the present invention, but is not limited thereto. A variation of the execution unit 600 may also be used in the embodiment of the present invention. Figure 3B In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 additionally includes a register file 606, which stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a dispatch unit 607 and a branch unit 608. In one embodiment, the dispatch unit 607 and the branch unit 608 can be used in conjunction with Figure 5B The dispatch unit 530 and the branch unit 532 of the graphics execution unit 508 in FIG. 5 operate in a similar manner.

[0126] The execution unit 600 also includes a computing unit 610, which includes a plurality of functional units of different types. In one embodiment, the computing unit 610 includes an ALU unit 611, which includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations can be performed simultaneously. The computing unit 610 may also include a systolic array 612 and a mathematical unit 613. The systolic array 612 includes a network of width W and depth D of a data processing unit, which can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, the systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, the systolic array 612 supports 16-bit floating-point operations and 8-bit and 4-bit integer operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, the systolic array 612 can be configured with support for the bfloat 16-bit floating-point format. In one embodiment, math unit 613 may be included to perform a specific subset of math operations in an efficient and lower power manner than ALU unit 611. Math unit 613 may include shared functional logic that may be used in graphics processing engines provided by other embodiments (e.g., Figure 4 In one embodiment, math unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0127] Thread control unit 601 includes logic for controlling the execution of threads within execution units. Thread control unit 601 may include thread arbitration logic for starting, stopping, and preempting the execution of threads within execution unit 600. Thread state unit 602 may be used to store thread states for threads assigned to execute on execution unit 600. Storing thread states in execution unit 600 enables fast preemption of threads when they become locked or idle. Instruction fetch / prefetch unit 603 may fetch instructions from an instruction cache of higher level execution logic (e.g., Figure 5A The instruction fetch / prefetch unit 603 also issues prefetch requests for instructions to be loaded into the execution cache based on an analysis of the current execution thread. The instruction decode unit 604 may be used to decode instructions to be executed by the computational unit. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0128] Execution unit 600 additionally includes a register file 606 that can be used by hardware threads executing on execution unit 600. Registers in register file 606 can be divided across logic used to execute multiple simultaneous threads within compute unit 610 of execution unit 600. The number of logical threads that can be executed by graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 606 can vary from embodiment to embodiment based on the number of hardware threads supported. In one embodiment, register renaming can be used to dynamically assign registers to hardware threads.

[0129] Figure 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes illustrate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to microinstructions that result from instruction decoding that occurs once the instruction is processed.

[0130] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 710. Based on the selected instructions, instruction options, and number of operands, 64-bit compact instruction format 730 can be used for some instructions. Native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited in 64-bit format 730. The native instructions available in 64-bit format 730 vary from embodiment to embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in index field 713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions of 128-bit instruction format 710. Other sizes and formats of instructions can be used.

[0131] For each format, the instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 enables control of certain execution options, such as channel selection (e.g., assertion) and data channel order (e.g., mixing). For instructions of the 128-bit instruction format 710, the execution size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compact instruction format 730.

[0132] Some execution unit instructions have up to three operands, including two source operands src0 720, src1 722, and one destination operand 718. In some embodiments, the execution unit supports dual destination instructions, where one of the dual destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0133] In some embodiments, the 128-bit instruction format 710 includes an access / addressing mode field 726 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0134] In some embodiments, the 128-bit instruction format 710 includes an access / addressing mode field 726 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0135] In one embodiment, the addressing mode portion of the access / addressing mode field 726 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0136] In some embodiments, instructions are grouped based on the opcode 712 bit field to simplify opcode decoding 740. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares five most significant bits (MSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 744 (e.g., call (call), jump (jmp)) includes the instruction of 0010xxxxb (e.g., 0x7) form. The miscellaneous instruction group 746 includes a mixture of instructions, including the synchronization instruction (e.g., wait (wait), send (send)) of 0011xxxxb (e.g., 0x30) form. The parallel math instruction group 748 includes component-by-component arithmetic instructions (e.g., add, multiply (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, the illustrated opcode decode 740 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0137] Graphics Pipeline

[0138] Figure 8 is a block diagram of another embodiment of a graphics processor 800 . Figure 8 Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0139] In some embodiments, the graphics processor 800 includes a graphics pipeline 820, a media pipeline 830, a display engine 840, a thread execution logic 850, and a rendering output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 800 through the ring interconnect 802. In some embodiments, the ring interconnect 802 couples the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command stream converter 803, which supplies instructions to various components of the geometry pipeline 820 or the media pipeline 830.

[0140] In some embodiments, the command stream converter 803 directs the operation of the vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 803. In some embodiments, the vertex fetcher 805 provides the vertex data to the vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 805 and the vertex shader 807 execute the vertex processing instructions by dispatching execution threads to the execution units 852A-852B via the thread dispatcher 831.

[0141] In some embodiments, execution units 852A-852B are arrays of vector processors with instruction sets for performing graphics operations and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851 that is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0142] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable shell shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation 813 operates under the direction of the shell shader 811 and includes dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, the tessellation components (e.g., the shell shader 811, the tessellation 813, and the domain shader 817) can be bypassed.

[0143] In some embodiments, the complete geometric object may be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0144] Before rasterization, the clipper 829 processes the vertex data. The clipper 829 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches a pixel shader to convert the geometric object into a pixel-by-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the unrasterized vertex data via the outflow unit 823.

[0145] The graphics processor 800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data ports 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 can also be configured as a sampler cache.

[0146] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 878 and depth cache 879 are also available in some embodiments. The pixel operation component 877 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 841, or replaced by the display controller 843 using an overlay display plane when displaying. In some embodiments, a shared L3 cache 875 can be used for all graphics components, allowing data to be shared without using main system memory.

[0147] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front end 834 processes the media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function for generating threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0148] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via the ring interconnect 802, or some other interconnect bus or structure. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0149] In some embodiments, geometry pipeline 820 and media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not dedicated to any application programming interface (API). In some embodiments, the driver software of the graphics processor converts the API call dedicated to a specific graphics or media library into a command that can be processed by the graphics processor. In some embodiments, all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group are provided with support. In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, the combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If the mapping from the pipeline of the future API to the pipeline of the graphics processor can be carried out, the future API with compatible 3D pipelines will also be supported.

[0150] Graphics pipeline programming

[0151] Fig. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Fig. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. Fig. 9A The solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig. 9A An exemplary graphics processor command format 900 includes data fields for identifying the client 902 of the command, a command operation code (opcode) 904, and data 906. A subopcode 905 and a command size 908 are also included in some commands.

[0152] In some embodiments, client 902 specifies the client unit of processing command data of graphics device. In some embodiments, graphics processor command parser checks the client field of each command to adjust the further processing of command and route command data to appropriate client unit. In some embodiments, graphics processor client unit includes memory interface unit, rendering unit, 2D unit, 3D unit and media unit. Each client unit has corresponding processing pipeline for processing command. Once command is received by client unit, client unit reads opcode 904 and sub-opcode 905 (if exists) to determine the operation to be performed. Client unit uses information in data field 906 to execute command. For some commands, explicit command size 908 is expected to specify the size of command. In some embodiments, command parser automatically determines the size of at least some commands in command based on command opcode. In some embodiments, command is aligned via multiples of double word. Other command formats can be used.

[0153] Fig. 9B 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as the embodiments are not limited to these particular commands or command sequences. Moreover, the commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0154] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline dump clear command 912 to cause any active graphics pipeline to complete the currently pending commands of the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active painting engine completes the pending operation and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 912 can be used for pipeline synchronization, or before placing the graphics processor in a low power state.

[0155] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 913 is used. In some embodiments, a pipeline select command 913 is only required once in an execution context before issuing pipeline commands unless the context will issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via a pipeline select command 913.

[0156] In some embodiments, pipeline control commands 914 configure the graphics pipeline for operation and are used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0157] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to be used for the set of pipeline operations.

[0158] The remaining commands in the command sequence differ based on the active pipeline for operation.Based on pipeline decision 920 , the command sequence is tailored for either 3D pipeline 922 starting at 3D pipeline state 930 , or media pipeline 924 starting at media pipeline state 940 .

[0159] The commands for configuring the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, if certain pipeline elements will not be used, the 3D pipeline state 930 commands can also selectively disable or bypass those elements.

[0160] In some embodiments, 3D primitive 932 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 932 commands are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 932 command data to generate multiple vertex data structures. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 932 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 922 dispatches the shader execution thread to the graphics processor execution unit.

[0161] In some embodiments, the 3D pipeline 922 is triggered via an execution 934 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a "go" or "kick" command in the command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0162] In some embodiments, when performing media operations, the graphics processor command sequence 910 follows the media pipeline 924 path. Generally, the specific purpose and manner of programming for the media pipeline 924 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be transferred to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the resources provided by one or more general processing cores can be used to perform media decoding in whole or in part. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs, which are not explicitly related to the rendering of graphics primitives.

[0163] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands for configuring the media pipeline state 940 is dispatched or placed into a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain batches of state settings.

[0164] In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 942. Once the pipeline state is configured and media object commands 942 are queued, media pipeline 924 is triggered via an execution command 944 or an equivalent execution event (e.g., a register write). The output from media pipeline 924 can then be post-processed by operations provided by 3D pipeline 922 or media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0165] Graphics software architecture

[0166] Fig.10 An exemplary graphics software architecture for data processing system 1000 according to some embodiments is illustrated. In some embodiments, the software architecture includes 3D graphics application 1010, operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes graphics processor 1032 and one or more general purpose processor cores 1034. Graphics application 1010 and operating system 1020 are each executed in system memory 1050 of the data processing system.

[0167] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by the general purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0168] In some embodiments, operating system 1020 is from Microsoft Corporation Operating system 1020 may be a graphics API 1022, such as Direct3D API, OpenGL API or Vulkan API. When Direct3D API is in use, operating system 1020 uses front-end shader compiler 1024 to compile any shader instruction 1012 using HLSL into a lower-level shader language. Compilation may be just-in-time (JIT) compilation, or application executable shader precompilation. In some embodiments, during the compilation of 3D graphics application 1010, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 1012 are provided in an intermediate form, such as a certain version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0169] In some embodiments, the user mode graphics driver 1026 includes a backend shader compiler 1027 for converting shader instructions 1012 into hardware-specific representations. When the OpenGL API is in use, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses the operating system kernel mode function 1028 to communicate with the kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

[0170] IP Core Implementation

[0171] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0172] Fig.11A1 is a block diagram illustrating an IP core development system 1100 according to an embodiment, which can be used to manufacture integrated circuits to perform operations. The IP core development system 1100 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 1130 can generate a software simulation 1110 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 can include functional simulation, behavioral simulation and / or timing simulation. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 1115, a lower level design at the logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can be different.

[0173] The RTL design 1115 or an equivalent solution can be further synthesized into a hardware model 1120 by the design facility, which can adopt a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored using a non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design can be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0174] Fig. 11BA cross-sectional side view of an integrated circuit package assembly 21170 according to some embodiments described herein is illustrated. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 1170 includes a plurality of hardware logic units 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least in part in configurable logic or fixed-function logic hardware, and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein (multiple) processor cores, (multiple) graphics processors, or other accelerator devices. Each logic unit 1172, 1174 may be implemented within a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 can be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is a laminate substrate based on epoxy resin. In other embodiments, the package substrate 1180 may include other suitable types of substrates. The package assembly 1170 can be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 can be coupled to the surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0175] In some embodiments, logic units 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between logic 1172 and logic 1174. Bridge 1182 may be a dense interconnect structure that provides routing for electrical signals. Bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between logic 1172 and logic 1174.

[0176] Although two logic cells 1172, 1174 and bridge 1182 are illustrated, the embodiments described herein may include more or fewer logic cells on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 1182 may be excluded when the logic is included on a single die. Alternatively, multiple dies or logic cells may be connected by one or more bridges. Additionally, multiple logic cells, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0177] Fig. 11CThe illustrated package assembly 1190 includes a hardware logic chiplet (e.g., a base die) of multiple units connected to a substrate 1180. A graphics processing unit, parallel processor, and / or computing accelerator as described herein may be composed of various silicon chiplets manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged and includes different logic units that can be assembled into a larger package with other chiplets. Various collections of chiplets with different IP core logic can be assembled into a single device. In addition, active interposer technology can be used to integrate chiplets into a base die or base chiplet. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and assembled during manufacturing, which avoids the complexity of aggregating multiple IPs into the same manufacturing process, especially for large SoCs with several styles of IP. Allowing the use of multiple process technologies improves time to market and provides a cost-effective method to create multiple product SKUs. Additionally, disaggregated IP is more amenable to being independently power-gated, shutting down components that are not used on a given workload, thereby reducing overall power consumption.

[0178] The hardware logic chiplets may include dedicated hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented at least in part in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplet 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0179] Each chiplet may be fabricated as a separate semiconductor die and coupled to substrate 1180 via interconnect structure 1173. Interconnect structure 1173 may be configured to route electrical signals between various chiplets and logic within substrate 1180. Interconnect structure 1173 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structure 1173 may be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of logic chiplets, I / O chiplets, and memory chiplets.

[0180] In some embodiments, substrate 1180 is an epoxy-based laminate substrate. In other embodiments, substrate 1180 may include other suitable types of substrates. Package assembly 1190 may be connected to other electrical devices via package interconnect 1183. Package interconnect 1183 may be coupled to the surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0181] In some embodiments, the logic or I / O chiplet 1174 and the memory chiplet 1175 may be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplet 1174 and the memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides routing for electrical signals. The bridge 1187 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I / O chiplet 1174 and the memory chiplet 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, in some embodiments, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB). In some embodiments, the bridge 1187 may be just a direct connection from one chiplet to another chiplet.

[0182] The substrate 1180 may include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 may be embedded in the substrate 1180 to enable communication between various logic chiplets within the substrate 1180 and the logic 1191, 1193. In one embodiment, the I / O 1191, fabric 1185, cache, bridge, and other hardware logic 1193 may be integrated in a base die stacked on top of the substrate 1180.

[0183] In various embodiments, the package assembly 1190 may include a fewer or greater number of components and bridges interconnected by the structure 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 can be arranged in a 3D arrangement or a 2.5D arrangement. In general, the bridge structure 1187 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The structure 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, the cache memory 1192 within the substrate can act as a global cache for the package assembly 1190, as part of a distributed global cache, or as a dedicated cache for the structure 1185.

[0184] Fig.11DA package assembly 1194 including interchangeable chiplets 1195 is illustrated according to an embodiment. Interchangeable chiplets 1195 can be assembled into standardized sockets on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. I / O and logic chiplets can communicate via an interconnect structure. The base chiplets can each support one or more sockets in a standardized format for logic or I / O or memory / cache.

[0185] In one embodiment, the SRAM and power delivery circuits may be fabricated into one or more of the base chiplets 1196, 1198, which may be fabricated using a different process technology relative to the interchangeable chiplets 1195, which are stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 may be fabricated using a larger process technology while the interchangeable chiplets may be fabricated using a smaller process technology. One or more of the interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package assembly 1194 based on power and / or performance for the product using the package assembly 1194. In addition, logic chiplets with different numbers of types of functional units may be selected at assembly time based on power and / or performance for the product. In addition, chiplets containing IP logic cores of different types may be inserted into the interchangeable chiplet socket, thereby enabling hybrid memory designs that can mix and match IP blocks of different technologies.

[0186] Exemplary System-on-Chip Integrated Circuit

[0187] Figure 12-Figure 1 3 illustrates an exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0188] Fig.121 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same design facility or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, including a USB controller 1225, a UART controller 1230, a SPI / SDIO controller 1235, and an I2S / I2C controller 1240. In addition, the integrated circuit may include a display device 1245, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 1265 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270 .

[0189] Figure 13A-13B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.13A An exemplary graphics processor 1310 of a system on chip integrated circuit that may be fabricated using one or more IP cores is illustrated in accordance with an embodiment. Fig. 13B An additional exemplary graphics processor 1340 is illustrated that may be fabricated using one or more IP cores of a system on a chip integrated circuit in accordance with an embodiment. Fig.13A Graphics processor 1310 is an example of a low-power graphics processor core. Fig. 13B The graphics processor 1340 of FIG. 1 is an example of a higher performance graphics processor core. Each of the graphics processors 1310 and 1340 may be Fig.12 A variant of graphics processor 1210.

[0190] like Fig.13AAs shown in , the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, all the way to 1315N-1 and 1315N). The graphics processor 1310 can execute different shader programs via separate logic, so that the vertex processor 1305 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitive data and vertex data. (Multiple) fragment processors 1315A-1315N use the primitive data and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on the display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0191] The graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual to physical address mappings for the graphics processor 1310 (including for the vertex processor 1305 and / or fragment processor(s) 1315A-1315N), which may reference vertex data or image / texture data stored in memory in addition to vertex data or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B may be synchronized with other MMUs within the system so that each processor 1205-1220 may participate in a shared or unified virtual memory system, including with other MMUs within the system. Fig.12 One or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220. According to an embodiment, one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0192] like Fig. 13B As shown in FIG. 1 , the graphics processor 1340 includes Fig.13AOne or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of a graphics processor 1310. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, all the way to 1355N-1 and 1355N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary by embodiment and implementation. In addition, the graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial consistency within a scene or to optimize the use of internal caches. Machine Learning Overview

[0193] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numeric value given an input; and a pattern recognition algorithm can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0194] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each consecutive layer in the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0195] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is propagated backward through the layers of the network, the weights associated with the connections are adjusted to minimize that error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

[0196] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to exploit the parallel processing hardware within general-purpose graphics processing devices.

[0197] Fig.14 is a generalized diagram of a machine learning software stack 1400. Machine learning applications 1402 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 1402 may include training and inference functions for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 1402 may implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0198] Hardware acceleration for machine learning applications 1404 can be enabled via a machine learning framework 1402. The machine learning framework 1404 can provide a library of machine learning primitives. Machine learning primitives are basic operations often performed by machine learning algorithms. Without the machine learning framework 1404, the developer of the machine learning algorithm would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when a new parallel processor is developed. Instead, the machine learning application can be configured to use the primitives provided by the machine learning framework 1404 to perform the necessary calculations. Exemplary primitives include tensor convolutions, excitation activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 1404 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0199] The machine learning framework 1404 can process input data received from the machine learning application 1402 and generate appropriate inputs to the computation framework 1406. The computation framework 1406 can abstract the underlying instructions provided to the GPGPU driver 1408 to enable the machine learning framework 1404 to take advantage of hardware acceleration via the GPGPU hardware 1410 without requiring the machine learning framework 1404 to be intimately familiar with the architecture of the GPGPU hardware 1410. In addition, the computation framework 1406 can enable hardware acceleration for the machine learning framework 1404 across various types and generations of GPGPU hardware 1410. Machine Learning Neural Network Implementation

[0200] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0201] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network for processing data (such as image data) with a known, grid-like topology. Therefore, CNNs are commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized as a set of "filters" (feature detectors stimulated by the receptive fields found in the retina), and the output of each filter set is propagated to the nodes in the successive layers of the network. The calculation for CNN includes applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to the convolution layer can be a multidimensional data array defining the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by the training process for the neural network.

[0202] Recurrent Neural Networks (RNNs) are a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future moments, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data that can be composed.

[0203] The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiments described herein, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques.

[0204] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition that produces reduced output errors relative to shallow machine learning techniques.

[0205] The deep neural network used in deep learning typically includes a front-end network for performing feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. Instead, a deep neural network can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0206] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each of the neurons in the output layer. The error values ​​are then propagated backward until each neuron has an associated error value that roughly represents the contribution of the neuron to the original output. The network can then learn through those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0207] Figure 15A-15B Illustration of an example convolutional neural network. Fig.15A The diagram shows the various layers within a CNN. Fig.15A As shown in , an exemplary CNN for modeling image processing may receive an input 1502 that describes the red, green, and blue (RGB) components of an input image. The input 1502 may be processed by a plurality of convolutional layers (e.g., a first convolutional layer 1504, a second convolutional layer 1506). The outputs from the plurality of convolutional layers may optionally be processed by a collection 1508 of fully connected layers. As previously described for feedforward networks, neurons in a fully connected layer have full connections to all activations in the previous layer. The outputs from the fully connected layer 1508 may be used to generate output results from the network. Activations within the fully connected layer 1508 may be calculated using matrix multiplication instead of convolution. Not all CNN implementations utilize a fully connected layer 1508. For example, in some implementations, the second convolutional layer 1506 may generate the output of the CNN.

[0208] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1508. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, as shown, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0209] Fig. 15B An exemplary computational stage within a convolutional layer of a CNN is shown. An input 1512 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 1514. The three stages may include a convolutional stage 1516, a detector stage 1518, and a pooling stage 1520. Subsequently, the convolutional layer 1514 may output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0210] In convolution stage 1516, several convolutions are performed in parallel to produce a set of linear activations. Convolution stage 1516 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific area in the input, which can be determined as a local area associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the area in the local input to which the neuron is connected. The output from convolution stage 1516 defines a set of linear activations processed by the successive stages of convolution layer 1514.

[0211] The linear activations may be processed by the detector stage 1518. In the detector stage 1518, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the threshold of the activation function is set to zero.

[0212] Pooling stage 1520 uses a pooling function that replaces the output of the second convolutional layer 1506 with summary statistics of nearby outputs. Pooling functions can be used to introduce translation invariance into neural networks so that small translations to the input do not change the pooled output. Local translation invariance can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during pooling stage 1520, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations substitute additional convolution stages with increased strides relative to the previous convolution stages.

[0213] Subsequently, the output from the convolutional layer 1514 may be processed by the next layer 1522. The next layer 1522 may be an additional convolutional layer or a layer in the fully connected layer 1508. For example, Fig.15A The first convolutional layer 1504 can output to the second convolutional layer 1506, and the second convolutional layer can output to the first layer in the fully connected layer 1508.

[0214] Fig.16 An exemplary recursive neural network 1600 is illustrated. In a recursive neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be built in various ways using various functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given previous word sequences. The illustrated RNN 1600 can be described as having the following: an input layer 1602, which receives an input vector; a hidden layer 1604, which is used to implement a recursive function; a feedback mechanism 1605, which is used to enable "memory" of previous states; and an output layer 1606, which is used to output a result. The RNN 1600 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1605. For a given time step, the state of the hidden layer 1604 is defined by the previous state and the input at the current time step. At the initial input (x 1 ) can be processed by the hidden layer 1604. The second input (x 2 ) can be used by the hidden layer 1604 to process the initial input (x 1 ) is processed by the state information determined during the period. A given state can be calculated as s t =f(Ux t +Ws (t-1)), where U and W are parameter matrices. The function f is generally nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in the hidden layer 1604 may vary depending on the specific implementation details of the RNN 1600.

[0215] In addition to the basic CNN network and RNN network described, changes in those networks can also be implemented. An example RNN variant is a long short-term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a structure similar to CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train DBN layer by layer. Subsequently, the learned weights of the DBN can be used to provide a pre-trained neural network by determining the best initial weight set for the neural network.

[0216] Fig.17 The training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training dataset 1702. Various training frameworks 1704 have been developed to enable hardware acceleration of the training process. For example, Fig.14 The machine learning framework 1404 of can be configured as a training framework 1704. The training framework 1704 can be hooked up to an untrained neural network 1706 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1708. To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Subsequently, a training cycle is performed in a supervised or unsupervised manner.

[0217] Supervised learning is a learning method in which training is performed as an intermediate operation, such as when the training data set 1702 includes an input paired with an expected output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the resulting output with the expected output or a set of expected outputs. Subsequently, the error is back-propagated through the system. The training framework 1704 can be adjusted to adjust the weights that control the untrained neural network 1706. The training framework 1704 can provide tools to monitor how well the untrained neural network 1706 converges to a model that is suitable for generating the correct answer based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1708. Subsequently, the trained neural network 1708 can be deployed to implement any number of machine learning operations to generate inference results 1714 based on the input of new data 1712.

[0218] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1702 will include input data without any associated output data. The untrained neural network 1706 can learn the groupings within the unlabeled inputs and can determine how the individual inputs are related to the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a class of trained neural networks 1708 that can perform operations that help reduce the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0219] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which a mixture of labeled and unlabeled data having the same distribution is included in the training data set 1702. Incremental learning is a variation of supervised learning in which input data is continually used to further train the model. Incremental learning enables a trained neural network 1708 to adapt to new data 1712 without forgetting the knowledge embedded within the network during initial training.

[0220] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than using a single computing node.

[0221] Fig.181802, data parallelism 1804, or a combination of model parallelism and data parallelism 1804.

[0222] In model parallelism 1802, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0223] In data parallelism 1804, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. Subsequently, the results from different nodes are combined. Although different methods for data parallelism are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, with the exception that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0224] Combined model and data parallelism 1806 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with multiple separate GPUs within each node used to train different parts of the model.

[0225] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization. Example Machine Learning Applications

[0226] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than previously feasible training data sets to train computer vision applications, and enables the use of low-power parallel processors to deploy inference systems.

[0227] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described in this article enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0228] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled an alternative to the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0229] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0230] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node, multi-GPU training, while deployed machine learning (e.g., inference) platforms typically include low-power parallel processors suitable for use in products such as: cameras, autonomous robots, and autonomous vehicles.

[0231] Denoising has become a key feature for both real-time and offline ray tracing, significantly reducing rendering times without sacrificing image clarity and smoothness. Currently, the highest quality denoising algorithms are almost exclusively based on deep learning, specifically convolutional neural networks (CNNs). While denoising the final frame, images tone mapped using CNNs are usually straightforward because color values ​​have a lower dynamic range and can be easily scaled to [0, 1], processing high dynamic range images is much more challenging. Color values ​​in HDR images can span several orders of magnitude, which makes training the network very difficult and leads to loss of detail and artifacts, such as residual fireflies and ringing around highlights.

[0232] Tone mapping is a technique used in image processing and computer graphics to map one set of colors to another set of colors to approximate the appearance of a high dynamic range image in a medium with a more limited dynamic range.

[0233] Few existing CNN-based denoising methods work well with HDR images. One existing approach separates the image into a low dynamic range (LDR) diffuse component and an HDR specular component and denoises these components separately. To minimize the amount of denoising artifacts, a logarithmic transformation (log(x+1)) is applied to the specular values ​​before feeding them into the network, and the inverse transformation is applied at the end. Another newer approach is to use gamma correction ((x / (x+1)) 1 / 2.2 ) applies the well-known Reinhard tone mapping operator to the entire image without diffuse / specular decomposition, which seems attractive because it is much simpler and compresses all possible values ​​to [0, 1]. This method suggests pre-scaling the pixels with a uniform exposure constant before applying the transformation, but no details are provided.

[0234] This newer method with a simple logarithmic transform significantly compresses the dynamic range, but is still prone to artifacts around highlights and fails to remove strong fireflies when used without a diffuse / specular decomposition. The problem with using the Reinhard operator is that the inverse transform is numerically very unstable for high luminances, which can lead to severe artifacts in bright areas. There is no known method that can robustly process HDR images without a decomposition.

[0235] The present design significantly downsamples the image (e.g., changes resolution, downsamples by an integer factor) and computes an auto-exposure value based on the average log luminance. This auto-exposure value is then used to prescale the image and then used to scale the image using a gamma-corrected logarithmic function (e.g., log2 (x+1) / 16) 1 / 2.2 ) tone maps the image. This converts the image to a roughly perceptually linear and normalized (between [0, 1]) color space without destroying the dynamic range of the original image. The neural network receives this tone mapped image as input and is used to determine the final result, applying an inverse tone mapping operator and inverse scaling to the output of the network.

[0236] Compared to existing methods, this design significantly improves the denoising quality of HDR images, especially if these existing methods do not decompose the image into diffuse and specular components, because the network denoises the image in a roughly perceptually linear and normalized color space. This design helps remove firefly artifacts, avoids artifacts around bright spots, and better preserves details, especially when the number of samples is small. This design performs image processing (e.g., anti-aliasing, super-resolution, demosaicing, denoising) on ​​HDR images through deep learning-based processing.

[0237] Fig.19 A method 1900 according to one embodiment is illustrated, having an exemplary sequence of operations for image processing an HDR image using a graphics processing unit, a graphics multiprocessor, a graphics processor, or a CPU. The graphics processing unit, the graphics multiprocessor, the graphics processor, or the CPU performs the operations 1900 according to one embodiment. For example, in one embodiment, a tensor core (e.g., tensor core 244) of a GPU implements a deep learning neural network to perform denoising on a frame generated by a ray tracing core (e.g., by ray tracing core 245). However, CPU(s) 246, graphics core 243, and / or ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0238] In operation 1902, the method includes downsampling the image in each dimension (eg, downsampling by a factor of at least 16 in each dimension using a simple box filter). In operation 1903, the method includes calculating an auto-exposure ratio for the image to enable effective tone mapping of the image.

[0239] In operation 1904 , the method includes scaling the image using the calculated auto-exposure ratio.

[0240] In operation 1906, the method includes applying a tone mapping operator (e.g., a logarithmic function) to the image and scaling the logarithmic function to generate a tone mapped image. The logarithmic function significantly compresses the range of values ​​of the image. In operation 1908, the method includes applying gamma correction to the tone mapped image to generate a gamma corrected tone mapped image and making the tone mapping curve more perceptually linear. In operation 1910, the method includes providing the tone mapped image as an input to a neural network (e.g., CNN). In operation 1912, the neural network processes (e.g., denoising algorithm, anti-aliasing algorithm, super resolution, demosaicing, etc.) the tone mapped image to generate an output of the neural network. In operation 1914, the method applies an inverse tone mapping operator to the output of the neural network and then applies an inverse exposure ratio to the output of the neural network to generate a final output image.

[0241] Fig. 20 A method 2000 is illustrated according to one embodiment, which has an exemplary sequence of operations for performing image processing (e.g., anti-aliasing, super-resolution, demosaicing, noise reduction, etc.) on an HDR image using a graphics processing unit, a graphics multiprocessor, a graphics processor, or a CPU. The graphics processing unit, the graphics multiprocessor, the graphics processor, or the CPU performs the operations 2000 according to one embodiment. For example, in one embodiment, a tensor core (e.g., tensor core 244) of a GPU implements a deep learning neural network to perform noise reduction on a frame generated by a ray tracing core (e.g., ray tracing core 245). However, (multiple) CPUs 246, graphics cores 243, and / or ray tracing cores 245 may also implement all or part of the image processing and / or deep learning algorithms.

[0242] In operation 2002, the method includes downsampling the image in each dimension (e.g., downsampling at least 16 times in each dimension using a simple filter box). In operation 2003, the method includes calculating an auto-exposure ratio for the image to be able to effectively tone map the image. In one example, the method calculates the log brightness of each pixel, determines the average of these values, and calculates the ratio as follows: ratio = hue / exp(average log brightness), where hue is typically 0.18 to 0.2 (18% to 20% middle gray). This works well for noise-free, fully focused images, but due to noise in the image, the calculated ratio can vary significantly (even by an order of magnitude), causing the tone mapped image to be severely overexposed or underexposed, which reduces the quality of the noise reduction.

[0243] In operation 2004 , the method includes scaling the image using the calculated auto-exposure ratio (eg, multiplying pixel values ​​by the calculated auto-exposure ratio).

[0244] In operation 2006, the method includes applying a tone mapping operator (eg, a logarithmic function, (log 2 (x+1) / 16) 1 / 2.2 ) is applied to the image and the logarithmic function is scaled to generate a tone-mapped image. The logarithmic function significantly compresses the range of values ​​of the image, but the resulting values ​​can still be greater than 1. However, in most HDR pipelines, images are stored in FP16 format at some point, which can represent values ​​up to 65504. Therefore, the present design optionally safely clips higher brightness values ​​and scales the logarithmic values ​​by 1 / 16, so that all FP16 values ​​are compressed to the [0, 1] range. This makes training neural networks faster and more stable because all features (such as color, reflectivity (the proportion of incident light or radiation reflected by the surface), normals, etc.) can be represented in the same range. However, the logarithmic function is insufficient because the result is far from perceptually linear, mapping dark tones and mid-tones to very small values, while mapping firefly artifacts to relatively high values. This makes it very difficult to filter out fireflies and also results in loss of detail.

[0245] The present design solves this problem by applying a standard 2.2 gamma correction to make the tone mapping curve more perceptually linear. In operation 2008, the method includes applying gamma correction to the tone mapped image to generate a gamma corrected tone mapped image and generate a more perceptually linear tone mapping curve. In operation 210, the method includes providing the tone mapped image as an input to a neural network (e.g., CNN). In operation 2012, the neural network processes (e.g., denoising algorithms, anti-aliasing algorithms, super-resolution, demosaicing, etc.) the tone mapped image to generate an output of the neural network. In the case of training, in operation 2013, the method applies tone mapping to both the input image and the target image and calculates the loss directly in the tone mapped color space.

[0246] In operation 214, the method applies an inverse tone mapping operator (eg, the inverse of the logarithmic function, (log 2 (x+1) / 16) 1 / 2.2 The inverse of (inverse of) is applied to this output of the neural network, and the inverse exposure ratio is then applied to this output of the neural network to generate the final output image.

[0247] The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0248] Some embodiments relate to Example 1, which includes a graphics multiprocessor, the graphics multiprocessor including: a media pipeline for generating a media request for processing an image; and an execution unit for receiving the media request from the media pipeline. The execution unit is configured to: calculate an auto-exposure ratio of the image to effectively tonemap the image; scale the image using the calculated auto-exposure ratio; and apply a tone mapping operator including a logarithmic function to the image and scale the logarithmic function to generate a tone-mapped image.

[0249] Example 2 includes the subject matter of Example 1, wherein the logarithmic function compresses the range of values ​​of the image.

[0250] Example 3 includes the subject matter of Examples 1-2, wherein the execution unit is configured to apply gamma correction to the tone mapped image to generate a gamma corrected tone mapped image and to make the tone mapping curve perceptually more linear for the image.

[0251] Example 4 includes the subject matter of Examples 1-3, wherein the neural network processes the tone mapped image to generate an output of the neural network.

[0252] Example 5 includes the subject matter of Examples 1-4, wherein the neural network processes the tone mapped image to generate an output of the neural network.

[0253] Example 6 includes the subject matter of Examples 1-5, wherein the execution unit is configured to apply an inverse tone mapping operator to the output of the neural network and then apply an inverse exposure scale to the output of the neural network to generate a final output image.

[0254] Some embodiments relate to Example 7, which includes a graphics processing unit, the graphics processing unit including: a memory for storing graphics data of an image; and a core having a plurality of execution units for performing graphics operations. At least one execution unit is configured to: downsample the image in multiple dimensions, calculate an auto-exposure ratio of the image to effectively tone map the image, scale the image using the calculated auto-exposure ratio, and apply a tone mapping operator including a logarithmic function to the image and scale the logarithmic function to generate a tone mapped image.

[0255] Example 8 includes the subject matter of Example 7, wherein the at least one execution unit is configured to apply gamma correction to the tone mapped image to generate a gamma corrected tone mapped image.

[0256] Example 9 includes the subject matter of Examples 7-8, wherein the at least one execution unit is configured to provide the tone mapped image as an input to a convolutional neural network (CNN).

[0257] Example 10 includes the subject matter of Examples 7-9, wherein the neural network processes the tone mapped image using a noise reduction algorithm, an anti-aliasing algorithm, super resolution, or demosaicing to generate an output of the neural network.

[0258] Example 11 includes the subject matter of Examples 7-10, wherein at least one execution unit is configured to apply an inverse tone mapping operator to the output of the neural network and subsequently apply an inverse exposure scale to the output of the neural network to generate an output image having a high dynamic range (HDR) of the image.

[0259] Example 12 includes the subject matter of Examples 7-11, wherein the tone mapping operator comprises (log 2 (x+1) / 16) 1 / 2.2 .

[0260] Example 13 includes the subject matter of Examples 7-12, wherein the value of the logarithmic function is scaled by 1 / 16 so that the floating point values ​​are compressed between 0 and 1.

[0261] Some embodiments relate to Example 14, which includes a computer-implemented method for tone mapping an image. The method includes: downsampling the image in multiple dimensions; calculating an auto-exposure ratio of the image using a graphics processing unit (GPU) to effectively tone map the image; scaling the image using the calculated auto-exposure ratio; and applying a tone mapping operator including a logarithmic function to the image and scaling the logarithmic function to generate a tone mapped image.

[0262] Example 15 includes the subject matter of Example 14, further comprising: applying gamma correction to the tone mapped image to generate a gamma corrected tone mapped image, and generating a perceptually linear tone mapping curve.

[0263] Example 16 includes the subject matter of Examples 14-15, further comprising: providing the tone mapped image as an input to a convolutional neural network (CNN); and processing the tone mapped image to generate an output of the CNN, the processing comprising one of a noise reduction algorithm and an anti-aliasing algorithm.

[0264] Example 17 includes the subject matter of Examples 14-16, wherein the processing includes applying tone mapping to the image and the target image and computing the loss directly in the tone mapped color space.

[0265] Example 18 includes the subject matter of Examples 14-17, further comprising: applying the inverse of the tone mapping operator to the output of the CNN.

[0266] Example 19 includes the subject matter of Examples 14-18, further comprising: applying the inverse of the exposure ratio to the output of the CNN to generate a final output image.

[0267] The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. At least one memory comprising machine-readable instructions for causing at least one processor circuit to perform at least the following operations: causing at least one tensor core to perform an operation associated with the neural network; providing an input image to the neural network; and A high dynamic range image is obtained based on the output of the neural network, wherein the high dynamic range image is configured to have a higher resolution than the input image.

2. At least one memory as claimed in claim 1, in, The machine-readable instructions are for causing one or more of the at least one processor circuits to cause an inverse tone mapping operation to be performed on the output of the neural network.

3. At least one memory as claimed in claim 2, in, The at least one processor circuit includes a graphics processing unit, and the inverse tone mapping operation is performed by the graphics processing unit.

4. At least one memory as claimed in claim 1, in, The neural network is a deep learning neural network.

5. At least one memory as claimed in claim 1, in, The neural network is a convolutional neural network.

6. At least one memory as claimed in claim 1, in, The input image has a different dynamic range than the high dynamic range image.

7. At least one memory as claimed in claim 6, in, The machine-readable instructions are for causing one or more of the at least one processor circuit to perform operations to cause the high dynamic range image to have a higher dynamic range than the input image.

8. At least one memory as claimed in claim 1, in, The input image is a video frame.

9. A method, include: causing one or more tensor cores of at least one tensor core of the graphics processing unit to perform operations associated with the neural network; providing an input image to the neural network; as well as A high dynamic range image is obtained based on the output of the neural network, wherein the high dynamic range image is configured to have a higher resolution than the input image.

10. The method of claim 9, further comprising performing an inverse tone mapping operation on the output of the neural network.

11. The method according to claim 9, in, The neural network is a deep learning neural network.

12. The method according to claim 9, in, The neural network is a convolutional neural network.

13. The method of claim 9, further comprising performing operations to cause the high dynamic range image to have a higher dynamic range than the input image.

14. The method according to claim 9, in, The input image is a video frame.

15. A computer readable medium comprising instructions which, when executed by at least one processor, cause the processor to perform the method of any one of claims 9 to 14.

16. A device, include: Interface circuit; machine-readable instructions; as well as At least one processor circuit adapted to be programmed by said machine readable instructions to perform the method of any one of claims 9 to 14.

17. An apparatus comprising means for performing the method as claimed in any one of claims 9 to 14.

18. A computer program product comprising instructions which, when executed by at least one processor, cause the processor to perform the method of any one of claims 9 to 14.

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