Driving module, driving method and display device

Abstract

The present invention provides a drive module, a drive method, and a display device. The drive module includes a multi-stage drive circuit; the drive circuit includes an input circuit, a first reset circuit, and a second reset circuit; the input circuit controls the potential of a pull-up node based on an input signal; the first reset circuit inputs a first voltage signal to the pull-up node under the control of the first reset signal; the first pull-down noise reduction circuit inputs a second voltage signal to the pull-up node under the control of the potential of the first pull-down node; the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal. The present invention can reduce the absolute value of the drain-source voltage of the transistor included in the first reset circuit, prevent characteristic drift of the transistor included in the first reset circuit, and improve the reliability of the display product.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving module, a driving method and a display device. Background Art

[0002] In the relevant driving circuit, the first transistor is used to reset the pull-up node through the third low-voltage signal provided by the third low-voltage terminal. The voltage value of the third low-voltage signal provided by the third low-voltage terminal is relatively low, so that the absolute value of the drain-source voltage of the first transistor is relatively large, and the impact current of the first transistor is relatively large, causing the characteristics of the first transistor to drift, resulting in a serious lack of on-current of the first transistor, the potential of the pull-up node cannot be pulled down, the cascade relationship fails, and the reliability of the display product is affected. Summary of the Invention

[0003] The main purpose of the present invention is to provide a driving module, a driving method and a display device to solve the problem of low reliability of display products caused by characteristic drift of a first transistor in a related driving circuit.

[0004] In one aspect, an embodiment of the present invention provides a driving module, comprising a multi-stage driving circuit; the driving circuit comprises an input circuit, a first reset circuit, and a first pull-down noise reduction circuit;

[0005] The input circuit is electrically connected to the input terminal and the pull-up node respectively, and is used to control the potential of the pull-up node according to the input signal provided by the input terminal;

[0006] The first reset circuit is electrically connected to the first reset terminal, the pull-up node and the first voltage terminal respectively, and is configured to input a first voltage signal provided by the first voltage terminal to the pull-up node under the control of a first reset signal provided by the first reset terminal;

[0007] The first pull-down noise reduction circuit is electrically connected to the first pull-down node, the pull-up node, and the second voltage terminal, and is configured to input a second voltage signal provided by the second voltage terminal to the pull-up node under the control of the potential of the first pull-down node;

[0008] A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal.

[0009] Optionally, the driving circuit further includes a second reset circuit;

[0010] The second reset circuit is electrically connected to the first pull-down node, the pull-up node of the adjacent first m-stage driver circuit, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driver circuit and the second voltage terminal under the control of the potential of the first pull-down node;

[0011] m is a positive integer.

[0012] Optionally, the driving circuit further includes a second reset circuit;

[0013] The second reset circuit is electrically connected to the first pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node.

[0014] Optionally, the driving circuit further includes a third reset circuit;

[0015] The third reset circuit is electrically connected to the second pull-down node, the pull-up node of the adjacent first m-stage driving circuit and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driving circuit and the second voltage terminal under the control of the potential of the second pull-down node.

[0016] Optionally, the driving circuit further includes a third reset circuit;

[0017] The third reset circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the second pull-down node.

[0018] Optionally, the driving circuit further includes a second pull-down noise reduction circuit;

[0019] The second pull-down noise reduction circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to input the second voltage signal provided by the second voltage terminal to the pull-up node under the control of the second pull-down node.

[0020] Optionally, the driving circuit further includes a first noise reduction circuit;

[0021] The first noise reduction circuit is electrically connected to the first noise reduction control terminal, the first pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first pull-down node and the second voltage terminal under the control of a first noise reduction control signal provided by the first noise reduction control terminal;

[0022] The first noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal.

[0023] Optionally, the driving circuit further includes a second noise reduction circuit;

[0024] The second noise reduction circuit is electrically connected to the second noise reduction control terminal, the second pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the second pull-down node and the second voltage terminal under the control of a second noise reduction control signal provided by the second noise reduction control terminal;

[0025] The second noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal; m is a positive integer.

[0026] Optionally, the first reset circuit includes a first transistor;

[0027] The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0028] Optionally, a channel length of the first transistor is greater than a channel length threshold, and a channel width-to-length ratio of the first transistor is less than a width-to-length ratio threshold.

[0029] Optionally, the second reset circuit includes a second transistor;

[0030] The gate of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0031] Optionally, the second reset circuit includes a second transistor;

[0032] A gate of the second transistor is electrically connected to the first pull-down node, a first electrode of the second transistor is electrically connected to the pull-up node, and a second electrode of the second transistor is electrically connected to the second voltage terminal.

[0033] Optionally, the third reset circuit includes a third transistor;

[0034] The gate of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the third transistor is electrically connected to the second voltage terminal.

[0035] Optionally, the third reset circuit includes a third transistor;

[0036] A gate of the third transistor is electrically connected to the second pull-down node, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the second voltage terminal.

[0037] Optionally, the first noise reduction circuit includes a fourth transistor;

[0038] A gate of the fourth transistor is electrically connected to the first noise reduction control terminal, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0039] Optionally, the second noise reduction circuit includes a fifth transistor;

[0040] A gate of the fifth transistor is electrically connected to the second noise reduction control terminal, a first electrode of the fifth transistor is electrically connected to the second pull-down node, and a second electrode of the fifth transistor is electrically connected to the second voltage terminal.

[0041] Optionally, the driving circuit further includes a driving signal output terminal and a driving reset circuit;

[0042] The driving reset circuit is electrically connected to the pull-down node, the driving signal output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the driving signal output terminal and the first voltage terminal under the control of the potential of the pull-down node; or

[0043] The drive reset circuit is electrically connected to the pull-down node, the drive signal output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the pull-down node; the third voltage terminal is a different voltage terminal from the first voltage terminal.

[0044] Optionally, the driving reset circuit includes a sixth transistor and a seventh transistor, and the pull-down node includes a first pull-down node and a second pull-down node;

[0045] The gate of the sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal or the third voltage terminal;

[0046] The gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the driving signal output terminal, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal or the third voltage terminal.

[0047] Optionally, the driving circuit further includes a carry output terminal, a pull-up node control circuit, a pull-down node control circuit, a carry output circuit, a driving output circuit and an energy storage circuit;

[0048] The pull-up node control circuit is electrically connected to the pull-up node, the frame reset terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0049] The pull-down node control circuit is electrically connected to the pull-down node and the control voltage terminal, respectively, and is used to control the potential of the pull-down node under the control of the control voltage provided by the control voltage terminal;

[0050] The driving output circuit is electrically connected to the pull-up node, the first clock signal terminal and the driving signal output terminal respectively, and is used to provide the first clock signal provided by the first clock signal terminal to the driving signal output terminal under the control of the potential of the pull-up node;

[0051] The carry output circuit is electrically connected to the pull-up node, the pull-down node, the carry output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is configured to control, under the control of the potential of the pull-up node, the second clock signal provided by the second clock signal terminal to be provided to the carry output terminal, and, under the control of the potential of the pull-down node, control the connection or disconnection between the carry output terminal and the second voltage terminal;

[0052] The energy storage circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used for storing electric energy.

[0053] Optionally, the input circuit includes an eighth transistor, the pull-up node control circuit includes a ninth transistor, the pull-down node includes a first pull-down node and a second pull-down node, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; and the drive circuit further includes a second pull-down noise reduction circuit;

[0054] The pull-down node control circuit includes a tenth transistor and a twelfth transistor, the first pull-down noise reduction circuit includes an eleventh transistor, the second pull-down noise reduction circuit includes a thirteenth transistor, the drive output circuit includes a fourteenth transistor, the carry output circuit includes a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, and the energy storage circuit includes a storage capacitor;

[0055] The gate electrode of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the pull-up node;

[0056] The gate of the ninth transistor is electrically connected to the frame reset terminal, the first electrode of the ninth transistor is electrically connected to the pull-up node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal;

[0057] The gate electrode of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first pull-down node;

[0058] The gate of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the first pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal;

[0059] The gate electrode of the twelfth transistor and the first electrode of the twelfth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0060] The gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0061] The gate of the fourteenth transistor is electrically connected to the pull-up node, the first electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive signal output terminal;

[0062] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the carry output terminal;

[0063] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the carry output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage terminal;

[0064] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the carry output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage terminal;

[0065] A first end of the storage capacitor is electrically connected to the pull-up node, and a second end of the storage capacitor is electrically connected to the driving signal output end.

[0066] Optionally, the input terminal of the current-stage driving circuit is electrically connected to the output terminal of the adjacent m-stage driving circuit, and the first reset terminal of the current-stage driving circuit is electrically connected to the output terminal of the adjacent m+1-stage driving circuit.

[0067] The output end is a carry signal output end or a drive signal output end.

[0068] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving module. The driving method includes:

[0069] The input circuit controls the potential of the pull-up node according to the input signal provided by the input terminal;

[0070] The first reset circuit inputs a first voltage signal to the pull-up node under the control of a first reset signal provided by the first reset terminal;

[0071] The first pull-down noise reduction circuit inputs a second voltage signal to the pull-up node under the control of the first pull-down node;

[0072] A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal.

[0073] Optionally, the driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit;

[0074] The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes:

[0075] In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal;

[0076] In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node;

[0077] In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node;

[0078] In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal;

[0079] In the fifth stage, the second reset circuit in the adjacent m-stage driving circuit controls the connection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node in the adjacent m-stage driving circuit;

[0080] m is a positive integer.

[0081] Optionally, the driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to a first noise reduction control terminal, and the second noise reduction circuit is electrically connected to a second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are both input terminals of the adjacent first m-stage driving circuit; and the driving cycle includes a noise reduction stage provided before the first stage;

[0082] The driving method further includes:

[0083] In the noise reduction stage, the first noise reduction circuit controls the connection between the first pull-down node and the second voltage terminal under the control of the signal provided by the input terminal of the adjacent first m-stage driving circuit; the second noise reduction circuit controls the connection between the second pull-down node and the second voltage terminal under the control of the signal provided by the input terminal of the adjacent first m-stage driving circuit.

[0084] Optionally, the driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit;

[0085] The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes:

[0086] In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal;

[0087] In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node;

[0088] In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node;

[0089] In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal;

[0090] In the fifth stage, the second reset circuit controls the connection between the pull-up node and the second voltage terminal under the control of the first pull-down node of the current stage.

[0091] Optionally, the driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to the first noise reduction control terminal, and the second noise reduction circuit is electrically connected to the second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are first reset terminals; the first noise reduction control terminal is a noise reduction stage provided before the first stage in the driving cycle;

[0092] The driving method further includes:

[0093] In the fourth stage, the first noise reduction circuit controls the connection between the first pull-down node and the second voltage end under the control of the first reset signal; the second noise reduction circuit controls the connection between the second pull-down node and the second voltage end under the control of the first reset signal.

[0094] In a third aspect, an embodiment of the present invention provides a display device including the above-mentioned driving module.

[0095] The present invention can reduce the absolute value of the drain-source voltage of the transistor included in the first reset circuit, prevent the characteristic drift of the transistor included in the first reset circuit, and improve the reliability of the display product. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] Figure 1 is a circuit diagram of the relevant drive circuit;

[0097] Figure 2A yes Figure 1 The working timing diagram of the related driving circuit shown;

[0098] Figure 2B yes Figure 1 Characteristic curve of the first transistor in the related driving circuit shown;

[0099] Figure 3 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0100] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0101] Figure 5 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0102] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0103] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0104] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0105] Figure 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0106] Figure 10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0107] Figure 11 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0108] Figure 12 yes Figure 11 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0109] Figure 13 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0110] Figure 14 yes Figure 13 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0111] Figure 15 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0112] Figure 16 yes Figure 15 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0113] Figure 17 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0114] Figure 18 yes Figure 17 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0115] Figure 19A yes Figure 15 A simulated waveform diagram of a driving signal output by G1 when at least one embodiment of the driving circuit shown is in operation;

[0116] Figure 19B It is a simulation waveform diagram of the driving signal output by G1 when the relevant driving circuit is working;

[0117] Figure 19C yes Figure 15 A simulation waveform diagram of the pull-up node PU when at least one embodiment of the driving circuit shown is in operation;

[0118] Figure 19D is a simulation waveform diagram of the pull-up node PU when at least one embodiment of the related driving circuit is in operation;

[0119] Figure 19E yes Figure 15 The simulated waveform diagram of the first pull-down node PD1 when at least one embodiment of the driving circuit is in operation is shown;

[0120] Figure 19F yes Figure 15 The simulated waveform diagram of the first pull-down node PD1 when at least one embodiment of the driving circuit is in operation is shown;

[0121] Figure 19G yes Figure 15 A comparison diagram of a simulated waveform diagram X3 of a driving signal output by G1 when at least one embodiment of the driving circuit is in operation, and a simulated waveform diagram X4 of a driving signal output by G1 when a related driving circuit is in operation;

[0122] Figure 19H yes Figure 15 A waveform diagram X5 of the potential of the pull-up node PU when at least one embodiment of the driving circuit is in operation, and a comparison diagram of a waveform diagram X6 of the potential of the pull-up node PU when a related driving circuit is in operation;

[0123] Figure 19I yes Figure 15 A waveform diagram X7 of the potential of the pull-down node PD when at least one embodiment of the driving circuit is in operation, and a comparison diagram of a waveform diagram X8 of the potential of the pull-down node PD when a related driving circuit is in operation;

[0124] Figure 20 is a structural diagram of a first transistor in a related driving circuit;

[0125] Figure 21 is a structural diagram of a first transistor in at least one embodiment of the present invention;

[0126] Figure 22A yes Figure 21 Layout diagram of the gate metal layer in FIG;

[0127] Figure 22B yes Figure 21 A layout diagram of the semiconductor layer in FIG.

[0128] Figure 22C yes Figure 21 Layout diagram of the source and drain metal layers in FIG;

[0129] Figure 23 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0130] Figure 24 yes Figure 23 The working timing diagram of at least one embodiment of the driving module is shown. DETAILED DESCRIPTION

[0131] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0132] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0133] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0134] like Figure 1 As shown, in the relevant driving circuit, the drain of the first transistor M1 is electrically connected to the third low voltage terminal LVGL. The voltage value of the third low voltage signal provided by the third low voltage terminal LVGL is relatively low, which makes the absolute value of the drain-source voltage of the first transistor M1 relatively large. The inrush current of the first transistor M1 is relatively large, causing the characteristic drift of M1, resulting in a serious shortage of the on-current Ion of M1. The potential of the pull-up node cannot be pulled down, and the cascade relationship fails, affecting the reliability of the display product. Figure 1 In the related driving circuit shown, each transistor is an n-type transistor.

[0135] Figure 2A yes Figure 1 The working timing diagram of the related driving circuit is shown.

[0136] like Figure 2AAs shown, when the potential of the pull-up node is a high voltage, the potential of the first pull-down node PD1 is a low voltage, and the pull-up node PU is reset after a delay of 1H (1H is a row scan time). Under the control of the potential of the pull-up node PU, G1 is connected to CLK. At this time, CLK outputs a low voltage signal, and the potential of the driving signal output by G1 is first pulled down to a third low voltage value (the third low voltage value is the voltage value of the third low voltage signal provided by the third low voltage terminal LVGL, and the low voltage value of the clock signal provided by the clock signal terminal CLK is also the third low voltage value). After that, the potential of PD1 or PD2 The potential of the pull-up node PU is a high voltage, and the potential of the drive signal output by G1 is then pulled down to the first low voltage value (the first low voltage value is the voltage value of the first low voltage signal provided by the first low voltage terminal VGL1). The inventors found that since the third low voltage value is less than the first low voltage value, the delay of the drive signal output terminal is smaller, which is conducive to charging and prevents the phenomenon of large-size mischarging; the potential of the pull-up node PU is continuously high for a long time, for example, 9H, and the bias time is too long. Therefore, affected by the potential bootstrap of PU, the source-drain voltage difference of M1 is large, and the characteristics of M1 are prone to drift. Based on this, the embodiment of the present invention reduces the absolute value of the drain-source voltage of the transistor included in the first reset circuit to prevent the characteristics of the transistor included in the first reset circuit from drifting, thereby improving the reliability of the display product.

[0137] exist Figure 2B Among them, the one labeled X0 is the initial characteristic curve of M1, and the one labeled X1 is the characteristic curve of M1 after characteristic drift.

[0138] like Figure 2B As shown in FIG, when the characteristic of M1 drifts, the characteristic curve of M1 shifts rightward and downward. When the gate-source voltage of M1 is greater than the threshold voltage of M1 and M1 is turned on, the on-current Ion of M1 becomes smaller, which makes it impossible to pull up the potential of PU.

[0139] exist Figure 2B In the figure, the horizontal axis is the gate-source voltage Vgs, the unit is V (volt), and the vertical axis is the on-state current Ion, the unit is A (ampere).

[0140] exist Figure 1In the embodiment, M2 is the second transistor, M3 is the third transistor, M4 is the fourth transistor, M5 is the fifth transistor, M6 is the sixth transistor, M7 is the seventh transistor, M8 is the eighth transistor, M9 is the ninth transistor, M10 is the tenth transistor, M11 is the eleventh transistor, M12 is the twelfth transistor, M13 is the thirteenth transistor, M14 is the fourteenth transistor, M15 is the fifteenth transistor, M16 is the sixth transistor, M17 is the eighth transistor, M18 is the ninth transistor, M19 is the ninth transistor, M20 is the tenth transistor, M21 is the tenth transistor, M22 is the twelfth transistor, M23 is the thirteenth transistor, M24 is the fourteenth transistor, M25 is the fifteenth transistor, M26 is the fifteenth transistor, M27 is the fifteenth transistor, M28 is the fifteenth transistor, M29 is the fifteenth transistor, M30 is the fifteenth transistor, M31 is the fifteenth transistor, M32 is the fifteenth transistor, M33 is the fifteenth transistor, M34 is the fifteenth transistor, M35 is the fifteenth transistor, M36 is the fifteenth transistor, M37 is the fifteenth transistor, M38 is the fifteenth transistor, M39 is the fifteenth transistor, M40 is the fifteenth transistor, M41 is the fifteenth transistor, M42 is the fifteenth transistor, M43 is the fifteenth transistor, M44 is the fifteenth transistor, M45 is the fifteenth transistor, M46 is the fifteenth transistor, M47 is the fifteenth transistor, M48 is the fifteenth transistor, M49 is the fifteenth transistor, M50 is the fifteenth transistor, M51 is the fifteenth transistor, M52 is the fifteenth transistor, There are sixteen transistors, labeled M17 is the seventeenth transistor, labeled C1 is the storage capacitor, labeled I1 is the input terminal, labeled R1 is the first reset terminal, labeled PU is the pull-up node, labeled PD1 is the first pull-down node, labeled PD2 is the second pull-down node, labeled VDDO is the first control voltage terminal, labeled VDDE is the second control voltage terminal, labeled CLK is the clock signal terminal, labeled G1 is the drive signal output terminal, labeled OC is the carry output terminal, labeled VGL1 is the first low voltage terminal, and labeled STV0 is the frame reset terminal.

[0141] The driving module described in the embodiment of the present invention includes a multi-stage driving circuit; Figure 3 As shown, the driving circuit includes an input circuit 11, a first reset circuit 12 and a first pull-down noise reduction circuit 13;

[0142] The input circuit 11 is electrically connected to the input terminal I1 and the pull-up node PU, and is used to control the potential of the pull-up node PU according to the input signal provided by the input terminal I1;

[0143] The first reset circuit 12 is electrically connected to the first reset terminal R1, the pull-up node PU and the first voltage terminal V1 respectively, and is configured to input the first voltage signal provided by the first voltage terminal V1 to the pull-up node PU under the control of the first reset signal provided by the first reset terminal R1;

[0144] The first pull-down noise reduction circuit 13 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively. The first pull-down noise reduction circuit 13 is configured to input a second voltage signal provided by the second voltage terminal V2 to the pull-up node PU under the control of the potential of the first pull-down node PD1;

[0145] A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal.

[0146] In an embodiment of the present invention, when the driving circuit resets the potential of the pull-up node PU, the first reset circuit 12 controls the connection between the pull-up node PU and the first voltage terminal V1 under the control of the first reset signal provided by the first reset terminal R1, and inputs the first voltage signal provided by the first voltage terminal V1 to the pull-up node PU; the first pull-down noise reduction circuit 13 inputs the second voltage signal provided by the second voltage terminal V2 to the pull-up node PU under the control of the potential of the first pull-down node PD1, and the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, so as to reduce the absolute value of the drain-source voltage of the transistor included in the first reset circuit 12, prevent the characteristic drift of the transistor included in the first reset circuit 12, and improve the reliability of the display product.

[0147] Optionally, the first voltage end may be a first low voltage end or a second low voltage end, and the second voltage end may be a third low voltage end, but is not limited thereto.

[0148] In at least one embodiment of the present invention, the voltage value of the first low voltage signal provided by the first low voltage terminal may be -10V or -8V, the voltage value of the second low voltage signal provided by the second low voltage terminal may be -10V or -8, and the voltage value of the third low voltage signal provided by the third low voltage terminal may be -15V, but is not limited thereto.

[0149] Optionally, the voltage value of the first low voltage signal and the voltage value of the second low voltage signal may be greater than or equal to -12V and less than or equal to -7V, and the voltage value of the third low voltage signal may be greater than or equal to -18V and less than or equal to -13V.

[0150] In at least one embodiment of the present invention, the driving circuit may further include a second reset circuit;

[0151] The second reset circuit is electrically connected to the first pull-down node, the pull-up node of the adjacent first m-stage driver circuit, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driver circuit and the second voltage terminal under the control of the potential of the first pull-down node;

[0152] m is a positive integer.

[0153] In a specific implementation, the driver circuit may include a second reset circuit, which, under the control of the potential of the first pull-down node, controls the reset of the pull-up node of the adjacent first m-stage driver circuit. Furthermore, the pull-up node of the current-stage driver circuit may be reset via the first pull-down node in the adjacent next m-stage driver circuit, so that the transistors included in the first reset circuit of the current-stage driver circuit and the transistors included in the second reset circuit of the adjacent next m-stage driver circuit are not turned on simultaneously, thereby avoiding short circuits.

[0154] In at least one embodiment of the present invention, the driving circuit further includes a second reset circuit;

[0155] The second reset circuit is electrically connected to the first pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node.

[0156] In a specific implementation, the driving circuit may include a second reset circuit, and the second reset circuit controls the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node.

[0157] In at least one embodiment of the present invention, the driving circuit further includes a third reset circuit;

[0158] The third reset circuit is electrically connected to the second pull-down node, the pull-up node of the adjacent first m-stage driver circuit, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driver circuit and the second voltage terminal under the control of the potential of the second pull-down node;

[0159] m is a positive integer.

[0160] In a specific implementation, the driver circuit may include a third reset circuit, which, under the control of the potential of the second pull-down node, controls the reset of the pull-up node of the adjacent first m-stage driver circuit. Furthermore, the pull-up node of the current-stage driver circuit may be reset via the second pull-down node in the adjacent next m-stage driver circuit, so that the transistor included in the first reset circuit of the current-stage driver circuit and the transistor included in the third reset circuit in the adjacent next m-stage driver circuit are not turned on simultaneously, thereby avoiding a short circuit.

[0161] In at least one embodiment of the present invention, the driving circuit further includes a third reset circuit;

[0162] The third reset circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the second pull-down node.

[0163] In a specific implementation, the driving circuit may further include a third reset circuit, and the third reset circuit controls the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the second pull-down node.

[0164] In at least one embodiment of the present invention, the driving circuit further includes a first noise reduction circuit;

[0165] The first noise reduction circuit is electrically connected to the first noise reduction control terminal, the first pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first pull-down node and the second voltage terminal under the control of a first noise reduction control signal provided by the first noise reduction control terminal;

[0166] The first noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal.

[0167] In a specific implementation, the driving circuit may further include a first noise reduction circuit, which resets the potential of the first pull-down node under the control of a first noise reduction control signal.

[0168] In at least one embodiment of the present invention, the driving circuit further includes a second noise reduction circuit;

[0169] The second noise reduction circuit is electrically connected to the second noise reduction control terminal, the second pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first pull-down node and the second voltage terminal under the control of a second noise reduction control signal provided by the second noise reduction control terminal;

[0170] The second noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal; m is a positive integer.

[0171] In a specific implementation, the driving circuit may further include a second noise reduction circuit, which resets the potential of the second pull-down node under the control of the first noise reduction control signal.

[0172] like Figure 4 As shown, in Figure 3 On the basis of at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit further includes a second reset circuit 14, a third reset circuit 40, a first noise reduction circuit 41 and a second noise reduction circuit 42;

[0173] The second reset circuit 14 is electrically connected to the first pull-down node PD1, the pull-up node PU-m of the adjacent first m-stage driver circuit, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU-m of the adjacent first m-stage driver circuit and the second voltage terminal V2 under the control of the potential of the first pull-down node PD1;

[0174] The third reset circuit 40 is electrically connected to the second pull-down node PD2, the pull-up node PU-m of the adjacent first m-stage driver circuit, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU-m of the adjacent first m-stage driver circuit and the second voltage terminal V2 under the control of the potential of the second pull-down node PD2;

[0175] The first noise reduction circuit 41 is electrically connected to the first noise reduction control terminal Ct1, the first pull-down node PD1, and the second voltage terminal V2, respectively, and is configured to control the connection or disconnection between the first pull-down node PD1 and the second voltage terminal V2 under the control of a first noise reduction control signal provided by the first noise reduction control terminal Ct1;

[0176] The second noise reduction circuit 42 is electrically connected to the second noise reduction control terminal Ct2, the second pull-down node PD2 and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second pull-down node PD2 and the second voltage terminal V2 under the control of a second noise reduction control signal provided by the second noise reduction control terminal Ct2.

[0177] like Figure 5 As shown, in Figure 3 On the basis of at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit further includes a second reset circuit 14, a third reset circuit 40, a first noise reduction circuit 41 and a second noise reduction circuit 42;

[0178] The second reset circuit 14 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU and the second voltage terminal V2 under the control of the potential of the first pull-down node PD1;

[0179] The third reset circuit 40 is electrically connected to the second pull-down node PD2, the pull-up node PU, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU and the second voltage terminal V2 under the control of the potential of the second pull-down node PD2;

[0180] The first noise reduction circuit 41 is electrically connected to the first noise reduction control terminal Ct1, the first pull-down node PD1, and the second voltage terminal V2, respectively, and is configured to control the connection or disconnection between the first pull-down node PD1 and the second voltage terminal V2 under the control of a first noise reduction control signal provided by the first noise reduction control terminal Ct1;

[0181] The second noise reduction circuit 42 is electrically connected to the second noise reduction control terminal Ct2, the second pull-down node PD2 and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second pull-down node PD2 and the second voltage terminal V2 under the control of a second noise reduction control signal provided by the second noise reduction control terminal Ct2.

[0182] In at least one embodiment of the present invention, the driving circuit may further include a second pull-down noise reduction circuit;

[0183] The second pull-down noise reduction circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to input the second voltage signal provided by the second voltage terminal to the pull-up node under the control of the second pull-down node.

[0184] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a second pull-down noise reduction circuit 43;

[0185] The second pull-down noise reduction circuit 43 is electrically connected to the second pull-down node PD2, the pull-up node PU and the second voltage terminal V2 respectively. The second pull-down noise reduction circuit 43 is used to input the second voltage signal provided by the second voltage terminal V2 to the pull-up node PU under the control of the second pull-down node PD2.

[0186] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the driving circuit may further include a second pull-down noise reduction circuit 43;

[0187] The second pull-down noise reduction circuit 43 is electrically connected to the second pull-down node PD2, the pull-up node PU and the second voltage terminal V2 respectively. The second pull-down noise reduction circuit 43 is used to input the second voltage signal provided by the second voltage terminal V2 to the pull-up node PU under the control of the second pull-down node PD2.

[0188] Optionally, the first reset circuit includes a first transistor;

[0189] The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0190] In at least one embodiment of the present invention, a channel length of the first transistor is greater than a channel length threshold, and a channel width-to-length ratio of the first transistor is less than a width-to-length ratio threshold.

[0191] At least one embodiment of the present invention can reduce the impact of the rush current of the first transistor by increasing the channel length of the first transistor and reducing the channel width-to-length ratio of the first transistor.

[0192] In a specific implementation, the overlapping area between the gate metal layer and the source-drain metal layer of the first transistor remains unchanged, so the parasitic capacitance between the gate and the source-drain of the first transistor remains unchanged, and does not affect the bootstrap pull-up of the potential of the pull-up node. At the same time, the leakage of the first transistor is small, and the channel width-to-length ratio of the first transistor becomes smaller, so the impact current of the first transistor becomes smaller, which can improve the performance of the first transistor and reduce the performance drift of the first transistor.

[0193] Optionally, the second reset circuit includes a second transistor;

[0194] The gate of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0195] Optionally, the second reset circuit includes a second transistor;

[0196] A gate of the second transistor is electrically connected to the first pull-down node, a first electrode of the second transistor is electrically connected to the pull-up node, and a second electrode of the second transistor is electrically connected to the second voltage terminal.

[0197] Optionally, the third reset circuit includes a third transistor;

[0198] The gate of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the third transistor is electrically connected to the second voltage terminal.

[0199] Optionally, the third reset circuit includes a third transistor;

[0200] A gate of the third transistor is electrically connected to the second pull-down node, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the second voltage terminal.

[0201] Optionally, the first noise reduction circuit includes a fourth transistor;

[0202] A gate of the fourth transistor is electrically connected to the first noise reduction control terminal, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the second voltage terminal.

[0203] Optionally, the second noise reduction circuit includes a fifth transistor;

[0204] A gate of the fifth transistor is electrically connected to the second noise reduction control terminal, a first electrode of the fifth transistor is electrically connected to the second pull-down node, and a second electrode of the fifth transistor is electrically connected to the second voltage terminal.

[0205] In at least one embodiment of the present invention, the driving circuit further includes a driving signal output terminal and a driving reset circuit;

[0206] The driving reset circuit is electrically connected to the pull-down node, the driving signal output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the driving signal output terminal and the first voltage terminal under the control of the potential of the pull-down node; or

[0207] The drive reset circuit is electrically connected to the pull-down node, the drive signal output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the pull-down node; the first voltage terminal and the third voltage terminal are different voltage terminals.

[0208] In a specific implementation, the driving circuit may include a driving reset circuit, which can control the connection between the driving signal output terminal and the first voltage terminal or the third voltage terminal under the control of the potential of the pull-down node to reset the driving signal provided by the driving signal output terminal.

[0209] In at least one embodiment of the present invention, the third voltage end may be the first low voltage end, but is not limited thereto.

[0210] Optionally, the driving reset circuit includes a sixth transistor and a seventh transistor, and the pull-down node includes a first pull-down node and a second pull-down node;

[0211] The gate of the sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal or the third voltage terminal;

[0212] The gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the driving signal output terminal, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal or the third voltage terminal.

[0213] In at least one embodiment of the present invention, the driving circuit further includes a carry output terminal, a pull-up node control circuit, a pull-down node control circuit, a carry output circuit, a driving output circuit, and an energy storage circuit;

[0214] The pull-up node control circuit is electrically connected to the pull-up node, the frame reset terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0215] The pull-down node control circuit is electrically connected to the pull-down node, the control voltage terminal, and the second voltage terminal, respectively, and is used to control the potential of the pull-down node under the control of the control voltage provided by the control voltage terminal;

[0216] The driving output circuit is electrically connected to the pull-up node, the first clock signal terminal and the driving signal output terminal respectively, and is used to provide the first clock signal provided by the first clock signal terminal to the driving signal output terminal under the control of the potential of the pull-up node;

[0217] The carry output circuit is electrically connected to the pull-up node, the pull-down node, the carry output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is configured to control, under the control of the potential of the pull-up node, the second clock signal provided by the second clock signal terminal to be provided to the carry output terminal, and, under the control of the potential of the pull-down node, control the connection or disconnection between the carry output terminal and the second voltage terminal;

[0218] The energy storage circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used for storing electric energy.

[0219] In a specific implementation, the drive circuit may further include a carry output terminal, a pull-up node control circuit, a pull-down node control circuit, a carry output circuit, a drive output circuit and a storage circuit; the pull-up node control circuit controls the connection or disconnection between the pull-up node and the second voltage terminal under the control of the frame reset signal; the pull-down node control circuit controls the potential of the pull-down node under the control of the control voltage; the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the carry output circuit controls the provision of a second clock signal to the carry output terminal under the control of the potential of the pull-up node, and controls the connection or disconnection between the carry output terminal and the second voltage terminal under the control of the potential of the pull-down node.

[0220] In at least one embodiment of the present invention, the first clock signal terminal and the second clock signal terminal may be the same clock signal terminal, connected to the same clock signal, or the first clock signal terminal and the second clock signal terminal may be different clock signal terminals, connected to different clock signals.

[0221] In a specific implementation, between adjacent frame display times, or before a frame display time, the frame reset terminal provides a valid frame reset signal to control the connection between the pull-up node and the second voltage terminal, thereby resetting the potential of the pull-up node.

[0222] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit may further include a driving signal output terminal G1, a driving reset circuit 51, a carry output terminal OC, a pull-up node control circuit 52, a pull-down node control circuit 53, a carry output circuit 54, a driving output circuit 55, and an energy storage circuit 56;

[0223] The driving reset circuit 51 is electrically connected to the first pull-down node PD1, the second pull-down node PD2, the driving signal output terminal G1, and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first pull-down node PD1, and to control the connection or disconnection between the driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the second pull-down node PD2;

[0224] The pull-up node control circuit 52 is electrically connected to the pull-up node PU, the frame reset terminal STV0, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU and the second voltage terminal V2 under the control of the frame reset signal provided by the frame reset terminal STV0;

[0225] The pull-down node control circuit 53 is electrically connected to the first pull-down node PD1, the second pull-down node PD2, the first control voltage terminal VDDO, and the second control voltage terminal VDDE, respectively, and is configured to control the potential of the first pull-down node PD1 under the control of a first control voltage provided by the first control voltage terminal VDDO, and to control the potential of the second pull-down node PD2 under the control of a second control voltage provided by the second control voltage terminal VDDE;

[0226] The driving output circuit 55 is electrically connected to the pull-up node PU, the clock signal terminal CLK and the driving signal output terminal G1 respectively, and is used to provide the clock signal provided by the clock signal terminal CLK to the driving signal output terminal G1 under the control of the potential of the pull-up node PU;

[0227] The carry output circuit 54 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the carry output terminal OC, the clock signal terminal CLK, and the second voltage terminal V2, respectively, and is configured to control, under the control of the potential of the pull-up node PU, the clock signal provided by the clock signal terminal CLK to be provided to the carry output terminal OC; under the control of the potential of the first pull-down node PD1, control the connection or disconnection between the carry output terminal OC and the second voltage terminal V2; and under the control of the potential of the second pull-down node PD2, control the connection or disconnection between the carry output terminal OC and the second voltage terminal V2;

[0228] The energy storage circuit 56 is electrically connected to the pull-up node PU and the driving signal output terminal G1 respectively, and is used to store electrical energy.

[0229] exist Figure 8 In at least one embodiment of the driving circuit shown, the first voltage terminal may be a first low voltage terminal VGL1 , and the second voltage terminal may be a third low voltage terminal LVGL.

[0230] exist Figure 8 In at least one embodiment of the driving circuit shown, the first clock signal terminal and the second clock signal terminal are both clock signal terminals CLK;

[0231] like Figure 9 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit may further include a driving signal output terminal G1, a driving reset circuit 51, a carry output terminal OC, a pull-up node control circuit 52, a pull-down node control circuit 53, a carry output circuit 54, a driving output circuit 55, and an energy storage circuit 56;

[0232] The driving reset circuit 51 is electrically connected to the first pull-down node PD1, the second pull-down node PD2, the driving signal output terminal G1, and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the driving signal output terminal G1 and the third voltage terminal V3 under the control of the potential of the first pull-down node PD1, and to control the connection or disconnection between the driving signal output terminal G1 and the third voltage terminal V3 under the control of the potential of the second pull-down node PD2;

[0233] The pull-up node control circuit 52 is electrically connected to the pull-up node PU, the frame reset terminal STV0, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the pull-up node PU and the second voltage terminal V2 under the control of the frame reset signal provided by the frame reset terminal STV0;

[0234] The pull-down node control circuit 53 is electrically connected to the first pull-down node PD1, the second pull-down node PD2, the first control voltage terminal VDDO, and the second control voltage terminal VDDE, respectively, and is configured to control the potential of the first pull-down node PD1 under the control of a first control voltage provided by the first control voltage terminal VDDO, and to control the potential of the second pull-down node PD2 under the control of a second control voltage provided by the second control voltage terminal VDDE;

[0235] The driving output circuit 55 is electrically connected to the pull-up node PU, the clock signal terminal CLK and the driving signal output terminal G1 respectively, and is used to provide the clock signal provided by the clock signal terminal CLK to the driving signal output terminal G1 under the control of the potential of the pull-up node PU;

[0236] The carry output circuit 54 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the carry output terminal OC, the clock signal terminal CLK, and the second voltage terminal V2, respectively, and is configured to control, under the control of the potential of the pull-up node PU, the clock signal provided by the clock signal terminal CLK to be provided to the carry output terminal OC, control, under the control of the potential of the first pull-down node PD1, the connection or disconnection between the carry output terminal OC and the second voltage terminal V2, and control, under the control of the potential of the second pull-down node PD2, the connection or disconnection between the carry output terminal OC and the second voltage terminal V2;

[0237] The energy storage circuit 56 is electrically connected to the pull-up node PU and the driving signal output terminal G1 respectively, and is used to store electrical energy.

[0238] exist Figure 9 In at least one embodiment of the driving circuit shown, the first voltage terminal may be the second low voltage terminal VGL2 , the second voltage terminal may be the third low voltage terminal LVGL, and the third voltage terminal may be the first low voltage terminal VGL1 .

[0239] exist Figure 9 In at least one embodiment of the driving circuit shown, the voltage value of the second low voltage signal provided by the second low voltage terminal VGL2 is greater than the voltage value of the third low voltage signal provided by the third low voltage terminal.

[0240] Optionally, the input circuit includes an eighth transistor, the pull-up node control circuit includes a ninth transistor, the pull-down node includes a first pull-down node and a second pull-down node, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; and the drive circuit further includes a second pull-down noise reduction circuit;

[0241] The pull-down node control circuit includes a tenth transistor and a twelfth transistor, the first pull-down noise reduction circuit includes an eleventh transistor, and the second pull-down noise reduction circuit includes a thirteenth transistor; the drive output circuit includes a fourteenth transistor, the carry output circuit includes a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, and the energy storage circuit includes a storage capacitor;

[0242] The gate electrode of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the pull-up node;

[0243] The gate of the ninth transistor is electrically connected to the frame reset terminal, the first electrode of the ninth transistor is electrically connected to the pull-up node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal;

[0244] The gate electrode of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first pull-down node;

[0245] The gate of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the first pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal;

[0246] The gate electrode of the twelfth transistor and the first electrode of the twelfth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0247] The gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0248] The gate of the fourteenth transistor is electrically connected to the pull-up node, the first electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive signal output terminal;

[0249] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the carry output terminal;

[0250] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the carry output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage terminal;

[0251] The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the carry output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage terminal;

[0252] A first end of the storage capacitor is electrically connected to the pull-up node, and a second end of the storage capacitor is electrically connected to the driving signal output end.

[0253] Optionally, the input terminal of the current-stage driving circuit is electrically connected to the output terminal of the adjacent m-stage driving circuit, and the first reset terminal of the current-stage driving circuit is electrically connected to the output terminal of the adjacent m+1-stage driving circuit.

[0254] The output end is a carry signal output end or a drive signal output end.

[0255] In at least one embodiment of the present invention, an input signal can be provided to a current-stage driving circuit via the adjacent front m-stage driving circuit, and a first reset signal can be provided to the current-stage driving circuit via the adjacent rear m+1-stage driving circuit. The input end of the front m-stage driving circuit included in the driving module can be electrically connected to the starting voltage end, and the starting voltage end provides an input signal to the front m-stage driving circuit included in the driving module.

[0256] For example, m may be equal to 4, but is not limited thereto.

[0257] like Figure 10 As shown, in Figure 8 Based on at least one embodiment of the driving circuit shown, the first reset circuit includes a first transistor M1;

[0258] The gate of the first transistor M1 is electrically connected to the first reset terminal R1, the source of the first transistor M1 is electrically connected to the pull-up node PU, and the drain of the first transistor M1 is electrically connected to the first low voltage terminal VGL1;

[0259] The second reset circuit includes a second transistor M2;

[0260] The gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU(n-4) of the n-4th stage driving circuit, and the drain of the second transistor M2 is electrically connected to the third low voltage terminal LVGL;

[0261] Optionally, at least one embodiment of the driving circuit further includes a third reset circuit, and the third reset circuit includes a third transistor M3;

[0262] The gate of the third transistor M3 is electrically connected to the second pull-down node PD2, the source of the third transistor M3 is electrically connected to the pull-up node PU(n-4) of the n-4th stage driving circuit, and the drain of the third transistor M3 is electrically connected to the third low voltage terminal LVGL;

[0263] The first noise reduction circuit includes a fourth transistor M4;

[0264] The gate of the fourth transistor M4 is electrically connected to the input terminal I1(n-4) of the n-4th stage driving circuit, the source of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and the drain of the fourth transistor M4 is electrically connected to the third low voltage terminal LVGL;

[0265] The second noise reduction circuit includes a fifth transistor M5;

[0266] The gate of the fifth transistor M5 is electrically connected to the input terminal I1(n-4) of the n-4th stage driving circuit, the source of the fifth transistor M5 is electrically connected to the second pull-down node PD2, and the drain of the fifth transistor M5 is electrically connected to the third low voltage terminal LVGL;

[0267] The driving reset circuit includes a sixth transistor M6 and a seventh transistor M7, and the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2;

[0268] The gate of the sixth transistor M6 is electrically connected to the first pull-down node PD1, the source of the sixth transistor M6 is electrically connected to the driving signal output terminal G1, and the drain of the sixth transistor M6 is electrically connected to the first low voltage terminal VGL1;

[0269] The gate of the seventh transistor M7 is electrically connected to the second pull-down node PD2, the source of the seventh transistor M7 is electrically connected to the driving signal output terminal G1, and the drain of the seventh transistor M7 is electrically connected to the first low voltage terminal VGL1;

[0270] The input circuit includes an eighth transistor M8, the pull-up node control circuit includes a ninth transistor M9, the control voltage terminal includes a first control voltage terminal VDDO and a second control voltage terminal VDDE; the pull-down node control circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; the drive output circuit includes a fourteenth transistor M14; the carry output circuit includes a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17; and the energy storage circuit includes a storage capacitor C1;

[0271] The gate and source of the eighth transistor M8 are both electrically connected to the input terminal I1, and the drain of the eighth transistor M8 is electrically connected to the pull-up node PU. Optionally, the gate and source of the eighth transistor M8 may be connected to signals separately. For example, the gate of the eighth transistor M8 may be electrically connected to the carry output terminal of the upper-level driving circuit, and the source of the eighth transistor M8 may be connected to an effective level signal (for example, when the transistor whose gate is electrically connected to the pull-up node PU included in the driving circuit is an n-type transistor, the effective level signal is a high-level signal; when the transistor whose gate is electrically connected to the pull-up node PU included in the driving circuit is a p-type transistor, the effective level signal may be a low-level signal). Alternatively, the gate of the eighth transistor M8 may be electrically connected to the carry output terminal of the upper-level driving circuit, and the source of the eighth transistor M8 may be electrically connected to the drive signal output terminal of the upper-level driving circuit. Specifically, the upper-level driving circuit may be an adjacent i-level driving circuit, where i is a positive integer and is not limited here.

[0272] The gate of the ninth transistor M9 is electrically connected to the frame reset terminal STV0, the source of the ninth transistor M9 is electrically connected to the pull-up node PU, and the drain of the ninth transistor M9 is electrically connected to the third low voltage terminal LVGL; the ninth transistor M9 is used to reset the pull-up node PU before a frame time starts or between adjacent frame times;

[0273] The gate of the tenth transistor M10 and the source of the tenth transistor M10 are both electrically connected to the first control voltage terminal VDDO, and the drain of the tenth transistor M10 is electrically connected to the first pull-down node PD1;

[0274] The gate of the eleventh transistor M11 is electrically connected to the pull-up node PU, the source of the eleventh transistor M11 is electrically connected to the first pull-down node PD1, and the drain of the eleventh transistor M11 is electrically connected to the third low voltage terminal LVGL;

[0275] The gate of the twelfth transistor M12 and the source of the twelfth transistor M12 are both electrically connected to the second control voltage terminal VDDE, and the drain of the twelfth transistor M12 is electrically connected to the second pull-down node PD2;

[0276] A gate of the thirteenth transistor M13 is electrically connected to the pull-up node PU, a source of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, and a second electrode of the thirteenth transistor M13 is electrically connected to the third low voltage terminal LVGL;

[0277] The gate of the fourteenth transistor M14 is electrically connected to the pull-up node PU, the source of the fourteenth transistor M14 is electrically connected to the clock signal terminal CLK, and the drain of the fourteenth transistor M14 is electrically connected to the driving signal output terminal G1;

[0278] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the clock signal terminal CLK, and the drain of the fifteenth transistor M15 is electrically connected to the carry output terminal OC;

[0279] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the source of the sixteenth transistor M16 is electrically connected to the carry output terminal OC, and the drain of the sixteenth transistor M16 is electrically connected to the third low voltage terminal LVGL;

[0280] A gate of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, a first electrode of the seventeenth transistor is electrically connected to the carry output terminal OC, and a drain of the seventeenth transistor M17 is electrically connected to the third low voltage terminal LVGL;

[0281] A first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and a second end of the storage capacitor C1 is electrically connected to the driving signal output terminal G1.

[0282] exist Figure 10 In at least one embodiment of the driver circuit shown, all transistors are n-type transistors.

[0283] In at least one embodiment of the present invention, the driving circuit may be an oxide driving circuit, but the invention is not limited thereto. In actual operation, the driving circuit may also be an amorphous silicon (a-Si) driving circuit. At least one embodiment of the present invention is applicable to a-Si display products that improve charging rates, such as gaming products.

[0284] exist Figure 10 In at least one embodiment of the driving circuit shown, the driving circuit is an n-th stage driving circuit, where n is a positive integer.

[0285] exist Figure 10 In at least one embodiment of the driving circuit shown, the first voltage terminal is a first low voltage terminal VGL1 , and the second voltage terminal is a third low voltage terminal LVGL.

[0286] The voltage value of the first low voltage signal provided by the first low voltage terminal VGL1 may be -10V, and the voltage value of the third low voltage signal provided by the third low voltage terminal LVGL may be -15V.

[0287] exist Figure 10 In at least one embodiment of the driving circuit shown, the input terminal I1 can be electrically connected to the carry output terminals of the adjacent first four stages of driving circuits, and the first reset terminal R1 can be electrically connected to the carry output terminals of the adjacent last five stages of driving circuits.

[0288] Figure 10 When at least one embodiment of the driving circuit shown is in operation, the high voltage value VGH of the clock signal provided by the clock signal end can be reduced from 32V to 30V, and the drain voltage of M2 can be changed from -15V to -10V. When the potential of the pull-up node PU is a high voltage, the absolute value of the voltage difference between the source of M1 and the drain of M1 is reduced to improve the pressure resistance of M1, prevent M1 from drifting under the stress of large Vds, improve the reliability of the display product, and avoid the reduction of the output capacity of the driving module.

[0289] In at least one embodiment of the present invention, the low voltage value of the clock signal provided by the clock signal terminal may be a third low voltage value, and the third low voltage value may be a voltage value of a third low voltage signal provided by the third low voltage terminal LVGL.

[0290] like Figure 11 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown, a second reset circuit in the n+4th stage driving circuit and a third reset circuit in the n+4th stage driving circuit are further shown. The second reset circuit in the n+4th stage driving circuit includes a second transistor M2-4, and the third reset circuit in the n+4th stage driving circuit includes a third transistor M3-4.

[0291] The gate of M2-4 is electrically connected to the first pull-down node PD1(n+4) in the n+4th stage driving circuit, the source of M2-4 is electrically connected to the pull-up node PU, and the drain of M2-4 is electrically connected to the third low voltage terminal LVGL;

[0292] The gate of M3-4 is electrically connected to the second pull-down node PD2(n+4) in the n+4th stage driving circuit, the source of M3-4 is electrically connected to the pull-up node PU, and the drain of M3-4 is electrically connected to the third low voltage terminal LVGL.

[0293] Figure 11 When working, at least one embodiment of the driving circuit shown resets the potential of the pull-up node PU under the control of the potential of the first pull-down node PD1(n+4) in the n+4th level driving circuit and the potential of the second pull-down node PD2(n+4) in the n+4th level driving circuit.

[0294] exist Figure 11In at least one embodiment of the driving circuit shown, the source of M2 is electrically connected to the pull-up node PU(n-4) of the n-4th level driving circuit, the source of M3 is electrically connected to the pull-up node PU(n-4) of the n-4th level driving circuit, and the gate of M4 and the gate of M5 are both electrically connected to the input terminal I1(n-4) of the n-4th level driving circuit, that is, M2, M3, M4 and M5 are connected to the same level driving circuit, which corresponds to the n-4th level driving circuit in this embodiment. This ensures that when the n-4th level driving circuit is -When the potential of the pull-up node in the n-4th level driving circuit is a high voltage, I1(n-4) controls M4 and M5 to turn on, and the signal provided by LVGL is transmitted to the first pull-down node PD1 and the second pull-down node PD2, so that the first pull-down node PD1 and the second pull-down node PD2 control M2 and M3 in the n-th level driving circuit to be in a closed state, preventing M2 and M3 in the n-th level driving circuit from being turned on, causing the potential of the pull-up node PU(n-4) in the n-4th level driving circuit to be mistakenly pulled low.

[0295] like Figure 12 As shown, Figure 11 When at least one embodiment of the driving circuit shown is in operation, a driving cycle may include a first stage S1, a second stage S2, a third stage S3, a fourth stage S4 and a fifth stage S5 which are arranged in sequence;

[0296] In the first phase S1, I1 provides a high voltage signal, CLK provides a low voltage signal, M8 is turned on, the potential of PU rises for the first time, M14 is turned on, M15 is turned on, and OC and G1 both output low voltage signals;

[0297] The first stage S1 may last for 4 hours, wherein 1 hour is the charging time for one row;

[0298] In the second stage S2, CLK provides a high voltage signal, I1 provides a low voltage signal, M14 and M15 are turned on, OC and G1 both output high voltage signals, and due to the bootstrap effect of C1, the potential of PU rises for the second time;

[0299] In the third stage S3, CLK provides a low voltage signal, I1 provides a low voltage signal, M14 and M15 are turned on, OC and G1 both output low voltage signals, and the potential of PU drops for the first time;

[0300] The duration of the third stage S3 may be 1 hour;

[0301] In the fourth stage S4, I1 provides a low voltage signal, CLK provides a low voltage signal, R1 provides a high voltage signal, M1 is turned on, PU is connected to VGL1, and the potential of PU drops for the second time;

[0302] The fourth stage S4 is a reset stage, and R1 can be electrically connected to the carry output terminal of the adjacent lower-level driving circuit;

[0303] In the fifth stage S5, I1 provides a low voltage signal, the potential of PD1(n+4) is high, M2-4 is turned on, PU is connected to LVGL, and the potential of PU drops for the third time.

[0304] like Figure 12 As shown, in the third stage S3, G1 outputs a low voltage signal, and the voltage value of the low voltage signal output by G1 is a third low voltage value, which is equal to the voltage value of the third voltage signal provided by LVGL.

[0305] Figure 11 In at least one embodiment of the driving circuit shown, when in operation, VDDO and VDDE alternately output high voltage signals, so that PD1 and PD2 operate alternately.

[0306] like Figure 12 As shown, in the fourth stage S4, the potential of PD1 is high, M2 is turned on, and PU(n-4) is connected to LVGL.

[0307] Figure 11 When working, at least one embodiment of the driving circuit shown adopts a method of pre-lowering the potential of the pull-down node in advance and delaying the noise reduction of the pull-up node, thereby lowering the potential of the pull-down node 4 hours in advance, so that the potential of the pull-down node is maintained at a low level for more than 4 hours, and the pull-up node of the current level driving circuit opens M2-4 or M3-4 through the pull-down node in the n+4th level driving circuit to reduce noise.

[0308] In at least one embodiment of the present invention, M1 uses VGL1 to pull down the potential of the PU, and M2-4 or M3-4 uses LVGL to pull down the potential of the PU. After the period of time in which the potential of the PU remains high, M1 first pulls down the potential of the PU to a first low voltage value (the first low voltage value is the voltage value of the first low voltage signal) or a second low voltage value (the second low voltage value is the voltage value of the second low voltage signal), and then M2-4 or M3-4 pulls down the potential of the PU to a third low voltage value. This reduces the absolute value of the drain-source voltage Vds of M1 when M1 is turned off, thereby reducing the characteristic offset of M1. When M1 is turned on, the source-drain voltage difference of M1 is reduced, thereby reducing the instantaneous current. At least one embodiment of the present invention achieves source-drain voltage reduction of M1 by changing the existing signal connection method without the need for additional GOA (Gate On Array, a gate drive circuit provided on the array substrate).

[0309] In at least one embodiment of the present invention, M1 and M2-4 are not turned on at the same time, and M1 and M3-4 are not turned on at the same time to avoid short circuit when M1 and M2-4 are turned on at the same time, or M1 and M3-4 are turned on at the same time.

[0310] In actual operation, when M1 and M2-4 are turned on simultaneously, or when M1 and M3-4 are turned on simultaneously, the PU is connected to both VGL1 and LVGL, which can easily cause a short circuit. At least one embodiment of the present invention prevents short circuits by controlling M1 and M2-4 to not turn on simultaneously, and M1 and M3-4 to not turn on simultaneously.

[0311] Figure 13 At least one embodiment of the driving circuit shown is similar to Figure 11 The difference of at least one embodiment of the driving circuit shown is that the drain of M1 is electrically connected to the second low voltage terminal VGL2 .

[0312] exist Figure 13 In at least one embodiment of the driving circuit shown, the voltage value of the first low voltage signal provided by the first low voltage terminal VGL1 can be -10V, the voltage value of the second low voltage signal provided by the second low voltage terminal VGL2 can be -8V, and the voltage value of the point three low voltage signal provided by the third low voltage terminal LVGL can be -15V.

[0313] exist Figure 13 In at least one embodiment of the driving circuit shown, the drain of M1 is electrically connected to VGL2 to reduce the load of the first low voltage terminal VGL1 and enhance the effect of resetting the driving signal output terminal G1.

[0314] like Figure 14 As shown, Figure 13 When at least one embodiment of the driving circuit shown is in operation, a driving cycle may include a first stage S1, a second stage S2, a third stage S3, a fourth stage S4 and a fifth stage S5 which are arranged in sequence;

[0315] In the first phase S1, I1 provides a high voltage signal, CLK provides a low voltage signal, M8 is turned on, the potential of PU rises for the first time, M14 is turned on, M15 is turned on, and OC and G1 both output low voltage signals;

[0316] The first stage S1 may last for 4 hours, wherein 1 hour is a line scan time;

[0317] In the second stage S2, CLK provides a high voltage signal, I1 provides a low voltage signal, M14 and M15 are turned on, OC and G1 both output high voltage signals, and due to the bootstrap effect of C1, the potential of PU rises for the second time;

[0318] In the third stage S3, CLK provides a low voltage signal, I1 provides a low voltage signal, M14 and M15 are turned on, OC and G1 both output low voltage signals, and the potential of PU drops for the first time;

[0319] The duration of the third stage S3 may be 1 hour;

[0320] In the fourth stage S4, I1 provides a low voltage signal, CLK provides a low voltage signal, R1 provides a high voltage signal, M1 is turned on, PU is connected to VGL2, and the potential of PU drops for the second time;

[0321] In the fifth stage S5, I1 provides a low voltage signal, CLK provides a high voltage signal, the potential of PD1(n+4) is high, M2-4 is turned on, PU is connected to LVGL, and the potential of PU drops for the third time.

[0322] like Figure 14 As shown, in the third stage S3, G1 outputs a low voltage signal, and the voltage value of the low voltage signal output by G1 is a third low voltage value, which is equal to the voltage value of the third voltage signal provided by LVGL.

[0323] Figure 14 In at least one embodiment of the driving circuit shown, when in operation, VDDO and VDDE alternately output high voltage signals, so that PD1 and PD2 operate alternately;

[0324] In the fourth stage S4, the potential of PD1 is high, M2 is turned on, and PU(n-4) is connected to LVGL.

[0325] Figure 13 In at least one embodiment of the driving circuit shown, when in operation, VGL2 is a separate low-voltage terminal, and the voltage value of the second low-voltage signal provided by VGL2 can be appropriately adjusted to match the pressure resistance of M1 while being compatible with the competitive relationship among M11, M2, and M3. In addition, VGL1 provides a low-voltage signal to G1, and M1 is not electrically connected to VGL1 to avoid affecting the effective display area.

[0326] like Figure 15 As shown, in Figure 8 Based on at least one embodiment of the driving circuit shown, the first reset circuit includes a first transistor M1;

[0327] The gate of the first transistor M1 is electrically connected to the first reset terminal R1, the source of the first transistor M1 is electrically connected to the pull-up node PU, and the drain of the first transistor M1 is electrically connected to the first low voltage terminal VGL1;

[0328] The second reset circuit includes a second transistor M2;

[0329] The gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the third low voltage terminal LVGL;

[0330] The third reset circuit includes a third transistor M3;

[0331] The gate of the third transistor M3 is electrically connected to the second pull-down node PD2, the source of the third transistor M3 is electrically connected to the pull-up node PU, and the drain of the third transistor M3 is electrically connected to the third low voltage terminal LVGL;

[0332] The first noise reduction circuit includes a fourth transistor M4;

[0333] The gate of the fourth transistor M4 is electrically connected to the first reset terminal R1, the source of the fourth transistor M4 is electrically connected to the first pull-down node PD1, and the drain of the fourth transistor M4 is electrically connected to the third low voltage terminal LVGL;

[0334] The second noise reduction circuit includes a fifth transistor M5;

[0335] The gate of the fifth transistor M5 is electrically connected to the first reset terminal R1, the source of the fifth transistor M5 is electrically connected to the second pull-down node PD2, and the drain of the fifth transistor M5 is electrically connected to the third low voltage terminal LVGL;

[0336] The driving reset circuit includes a sixth transistor M6 and a seventh transistor M7, and the pull-down node includes a first pull-down node PD1 and a second pull-down node PD2;

[0337] The gate of the sixth transistor M6 is electrically connected to the first pull-down node PD1, the source of the sixth transistor M6 is electrically connected to the driving signal output terminal G1, and the drain of the sixth transistor M6 is electrically connected to the first low voltage terminal VGL1;

[0338] The gate of the seventh transistor M7 is electrically connected to the second pull-down node PD2, the source of the seventh transistor M7 is electrically connected to the driving signal output terminal G1, and the drain of the seventh transistor M7 is electrically connected to the first low voltage terminal VGL1;

[0339] The input circuit includes an eighth transistor M8, the pull-up node control circuit includes a ninth transistor M9, the control voltage terminal includes a first control voltage terminal VDDO and a second control voltage terminal VDDE; the pull-down node control circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; the drive output circuit includes a fourteenth transistor M14; the carry output circuit includes a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17; and the energy storage circuit includes a storage capacitor C1;

[0340] The gate of the eighth transistor M8 and the source of the eighth transistor M8 are both electrically connected to the input terminal I1, and the drain of the eighth transistor M8 is electrically connected to the pull-up node PU;

[0341] The gate of the ninth transistor M9 is electrically connected to the frame reset terminal STV0, the source of the ninth transistor M9 is electrically connected to the pull-up node PU, and the drain of the ninth transistor M9 is electrically connected to the third low voltage terminal LVGL;

[0342] The gate of the tenth transistor M10 and the source of the tenth transistor M10 are both electrically connected to the first control voltage terminal VDDO, and the drain of the tenth transistor M10 is electrically connected to the first pull-down node PD1;

[0343] The gate of the eleventh transistor M11 is electrically connected to the pull-up node PU, the source of the eleventh transistor M11 is electrically connected to the first pull-down node PD1, and the drain of the eleventh transistor M11 is electrically connected to the third low voltage terminal LVGL;

[0344] The gate of the twelfth transistor M12 and the source of the twelfth transistor M12 are both electrically connected to the second control voltage terminal VDDE, and the drain of the twelfth transistor M12 is electrically connected to the second pull-down node PD2;

[0345] A gate of the thirteenth transistor M13 is electrically connected to the pull-up node PU, a source of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, and a second electrode of the thirteenth transistor M13 is electrically connected to the third low voltage terminal LVGL;

[0346] The gate of the fourteenth transistor M14 is electrically connected to the pull-up node PU, the source of the fourteenth transistor M14 is electrically connected to the clock signal terminal CLK, and the drain of the fourteenth transistor M14 is electrically connected to the driving signal output terminal G1;

[0347] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the clock signal terminal CLK, and the drain of the fifteenth transistor M15 is electrically connected to the carry output terminal OC;

[0348] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the source of the sixteenth transistor M16 is electrically connected to the carry output terminal OC, and the drain of the sixteenth transistor M16 is electrically connected to the third low voltage terminal LVGL;

[0349] A gate of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, a first electrode of the seventeenth transistor is electrically connected to the carry output terminal OC, and a drain of the seventeenth transistor M17 is electrically connected to the third low voltage terminal LVGL;

[0350] A first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and a second end of the storage capacitor C1 is electrically connected to the driving signal output terminal G1.

[0351] exist Figure 15 In at least one embodiment of the driver circuit shown, all transistors are n-type transistors.

[0352] exist Figure 15 In at least one embodiment of the driving circuit shown, the driving circuit is an n-th stage driving circuit, where n is a positive integer.

[0353] exist Figure 15 In at least one embodiment of the driving circuit shown, the first voltage terminal is a first low voltage terminal VGL1 , and the second voltage terminal is a third low voltage terminal LVGL.

[0354] exist Figure 15 In at least one embodiment of the driving circuit shown, the input terminal I1 can be electrically connected to the carry output terminals of the adjacent first four stages of driving circuits, and the first reset terminal R1 can be electrically connected to the carry output terminals of the adjacent last five stages of driving circuits.

[0355] Figure 15 When at least one embodiment of the driving circuit shown is in operation, the voltage value of the first low voltage signal provided by VGL1 can be -8V, and the voltage value of the third low voltage signal provided by LVGL can be -15V; the high voltage value provided by CLK can be 32V; the drain voltage of M2 can be changed from -15V to -8V. When the potential of the pull-up node PU is a high voltage, the absolute value of the voltage difference between the source of M1 and the drain of M1 is reduced to improve the pressure resistance of M1, prevent the characteristics of M1 from drifting under large Vds stress, and improve the reliability of the display product.

[0356] Figure 15 In at least one embodiment of the driving circuit shown, when in operation, VDDO and VDDE alternately output high voltage signals, so that PD1 and PD2 operate alternately.

[0357] like Figure 16 As shown, Figure 15 When at least one embodiment of the driving circuit shown is in operation, a driving cycle may include a first stage S1, a second stage S2, a third stage S3, a fourth stage S4 and a fifth stage S5 which are arranged in sequence;

[0358] In the first phase S1, I1 provides a high voltage signal, CLK provides a low voltage signal, M8 is turned on, the potential of PU rises for the first time, M14 and M15 are both turned on, and G1 and OC both output low voltage signals;

[0359] In the second stage S2, I1 provides a low voltage signal, CLK provides a high voltage signal, M14 and M15 are both turned on, G1 and OC both output high voltage signals, and due to the bootstrap pull-up effect of C1, the potential of PU rises for the second time;

[0360] In the third stage S3, I1 provides a low voltage signal, CLK provides a low voltage signal, M14 and M15 are both turned on, G1 and OC both output low voltage signals, and the potential of PU is pulled low for the first time due to the action of C1;

[0361] The duration of the third stage S3 may be 1 hour;

[0362] In the fourth stage S4, I1 provides a low voltage signal, CLK provides a low voltage signal, R1 provides a high voltage signal, M1 is turned on, PU is connected to VGL1, and the potential of PU is pulled low for the second time;

[0363] In the fifth stage S5, I1 provides a low voltage signal, CLK provides a high voltage signal, R1 provides a low voltage signal, the potential of PD1 is high voltage, M2 is turned on, PU is connected to LVGL, and the potential of PU is pulled low for the third time.

[0364] like Figure 16 As shown, in the third stage S3, G1 outputs a low voltage signal, and the voltage value of the low voltage signal output by G1 is a third low voltage value, which is equal to the voltage value of the third voltage signal provided by LVGL.

[0365] exist Figure 15In at least one embodiment of the driving circuit shown, the first reset terminal R1 is used to act on the gate of M4 and the gate of M5 to ensure that when the potential of the pull-down node is at a low level, M2 and M3 cannot reduce the potential of the pull-up node PU. After M1 finishes reducing the potential of the pull-up node PU, M2 or M3 is turned on again to reduce the potential of the pull-up node PU and control the connection between PU and LVGL.

[0366] Figure 17 At least one embodiment of the driving circuit shown is similar to Figure 15 The difference of at least one embodiment of the driving circuit shown is that the drain of M1 is electrically connected to the second low voltage terminal VGL2 .

[0367] exist Figure 17 In at least one embodiment of the driving circuit shown, the voltage value of the first low voltage signal provided by the first low voltage terminal VGL1 can be -10V, the voltage value of the second low voltage signal provided by the second low voltage terminal VGL2 can be -8V, and the voltage value of the point three low voltage signal provided by the third low voltage terminal LVGL can be -15V.

[0368] exist Figure 17 In at least one embodiment of the driving circuit shown, the drain of M1 is electrically connected to VGL2 to reduce the load of the first low voltage terminal VGL1 and enhance the effect of resetting the driving signal output terminal G1.

[0369] like Figure 18 As shown, Figure 17 When at least one embodiment of the driving circuit shown is in operation, a driving cycle may include a first stage S1, a second stage S2, a third stage S3, a fourth stage S4 and a fifth stage S5 which are arranged in sequence;

[0370] In the first phase S1, I1 provides a high voltage signal, CLK provides a low voltage signal, M8 is turned on, the potential of PU rises for the first time, M14 and M15 are both turned on, and G1 and OC both output low voltage signals;

[0371] In the second stage S2, I1 provides a low voltage signal, CLK provides a high voltage signal, M14 and M15 are both turned on, G1 and OC both output high voltage signals, and due to the bootstrap pull-up effect of C1, the potential of PU rises for the second time;

[0372] In the third stage S3, I1 provides a low voltage signal, CLK provides a low voltage signal, M14 and M15 are both turned on, G1 and OC both output low voltage signals, and the potential of PU is pulled low for the first time due to the action of C1;

[0373] The duration of the third stage S3 may be 1 hour;

[0374] In the fourth stage S4, I1 provides a low voltage signal, CLK provides a low voltage signal, R1 provides a high voltage signal, M1 is turned on, PU is connected to VGL2, and the potential of PU is pulled low for the second time;

[0375] In the fifth stage S5, I1 provides a low voltage signal, CLK provides a high voltage signal, R1 provides a low voltage signal, the potential of PD1 is high voltage, M2 is turned on, PU is connected to LVGL, and the potential of PU is pulled low for the third time.

[0376] like Figure 18 As shown, in the third stage S3, G1 outputs a low voltage signal, and the voltage value of the low voltage signal output by G1 is a third low voltage value, which is equal to the voltage value of the third voltage signal provided by LVGL.

[0377] Figure 19A yes Figure 15 A simulated waveform diagram of a driving signal output by G1 when at least one embodiment of the driving circuit shown is in operation; Figure 19B It is a simulation waveform diagram of the driving signal output by G1 when the relevant driving circuit is working;

[0378] Figure 19C yes Figure 15 A simulation waveform diagram of the pull-up node PU when at least one embodiment of the driving circuit shown is in operation; Figure 19D is a simulation waveform diagram of the pull-up node PU when at least one embodiment of the related driving circuit is in operation;

[0379] Figure 19E yes Figure 15 The simulated waveform diagram of the first pull-down node PD1 when at least one embodiment of the driving circuit is in operation is shown; Figure 19F yes Figure 15 The diagram shows a simulated waveform of the first pull-down node PD1 when at least one embodiment of the driving circuit is in operation.

[0380] Figure 19G yes Figure 15 A comparison diagram of a simulated waveform diagram X3 of a driving signal output by G1 when at least one embodiment of the driving circuit is in operation, and a simulated waveform diagram X4 of a driving signal output by G1 when a related driving circuit is in operation;

[0381] Figure 19H yes Figure 15 A waveform diagram X5 of the potential of the pull-up node PU when at least one embodiment of the driving circuit is in operation, and a comparison diagram of a waveform diagram X6 of the potential of the pull-up node PU when a related driving circuit is in operation;

[0382] Figure 19I yes Figure 15The waveform diagram X7 of the potential of the pull-down node PD when at least one embodiment of the driving circuit is working, and the waveform diagram X8 of the potential of the pull-down node PD when the related driving circuit is working are compared.

[0383] exist Figure 19G In the figure, the horizontal axis is time t, the unit is μs (microseconds), and the vertical axis is the voltage value of the drive signal output by G1, the unit is V (volt);

[0384] exist Figure 19H In the figure, the horizontal axis is time t, the unit is μs (microseconds), and the vertical axis is the potential of the pull-up node PU, the unit is V;

[0385] exist Figure 19I , the horizontal axis is time t, the unit is μs (microseconds), and the vertical axis is the potential of the pull-down node PD, the unit is V.

[0386] Depend on Figure 19A 、 Figure 19B and Figure 19G It can be seen that Figure 15 In at least one embodiment of the illustrated driving circuit, the driving signal provided by G1 maintains a low voltage for a longer period of time during operation. This is primarily because the potential of PD remains at a low level for an extended period, M6 or M7 is not turned on, and G1 is connected to LVGL. However, this waveform does not affect the charging and discharging of the effective display area.

[0387] Depend on Figure 19C 、 Figure 19D and Figure 19H It can be seen that Figure 15 In at least one embodiment of the driving circuit shown, when the potential of the PU is bootstrapped, it first reaches a low voltage and then reaches another lower low voltage, and the potential of the PU is pulled down three times;

[0388] like Figure 19H As shown, Figure 15 In at least one embodiment of the driving circuit shown, when in operation, the potential of PU first reaches about 70V after bootstrapping, then drops to about 28V, then reaches about -15V, and then drops to about -7V.

[0389] When the relevant driving circuit is working, the potential of PU is automatically pulled up to about 70V, then dropped to about 28V, and then directly dropped to about -7V.

[0390] Depend on Figure 19E 、 Figure 19F and Figure 19I It can be seen that Figure 15 In at least one embodiment of the driving circuit shown, when in operation, the time during which the potential of PD1 remains at a low level is prolonged.

[0391] like Figure 19IIt can be seen that Figure 15 When at least one embodiment of the driving circuit shown is in operation, the time during which the potential of the PD remains less than 0V is approximately 40 μs; and when the related driving circuit is in operation, the time during which the potential of the PD remains less than 0V is approximately 30 μs.

[0392] like Figure 20 As shown, in the related art, the channel length L0 of M1 can be 8.5 μm;

[0393] like Figure 21 As shown, in at least one embodiment of the present invention, the channel length L1 of M1 can be greater than 8.5 μm, for example, 10 μm, 11 μm, 12 μm, etc., to reduce the channel width-to-length ratio of the first transistor M1 and reduce the impact of the inrush current of the first transistor M1.

[0394] In the related art and at least one embodiment of the present invention, the channel width of the first transistor M1 may be 160 μm. In the related art, the channel width-to-length ratio of the first transistor may be 160 / 8. In at least one embodiment of the present invention, the channel width-to-length ratio of the first transistor may be 160 / 11, but is not limited thereto.

[0395] like Figure 21 As shown, the overlapping area between the gate metal layer and the source-drain metal layer of the first transistor M1 remains unchanged, so the parasitic capacitance between the gate and the source-drain of the first transistor M1 remains unchanged, and does not affect the bootstrap pull-up of the potential of the pull-up node PU. At the same time, the leakage of the first transistor M1 is small, and the channel width-to-length ratio of the first transistor M1 becomes smaller, so the impact current of the first transistor M1 becomes smaller, which can improve the performance of the first transistor M1 and reduce the performance drift of the first transistor M1.

[0396] In a specific implementation, the channel length of the first transistor can be changed from 8.5 μm to 11 μm, and the peak current per unit length of the first transistor can be reduced from 7.87 μA / μm to 7.06 μA / μm.

[0397] Figure 22A yes Figure 21 The layout diagram of the gate metal layer in Figure 22B yes Figure 21 The layout of the semiconductor layer in Figure 22C yes Figure 21 Layout diagram of the source and drain metal layers.

[0398] like Figure 23 As shown, the driving module according to at least one embodiment of the present invention includes a multi-stage driving circuit;

[0399] exist Figure 23, the first-stage driving circuit is labeled GA1, the second-stage driving circuit is labeled GA2; the third-stage driving circuit is labeled GA3, the fourth-stage driving circuit is labeled GA4; the fifth-stage driving circuit is labeled GA5, the sixth-stage driving circuit is labeled GA6; the seventh-stage driving circuit is labeled GA7, the eighth-stage driving circuit is labeled GA8; the ninth-stage driving circuit is labeled GA9, and the tenth-stage driving circuit is labeled GA10;

[0400] GA1 is electrically connected to the first clock signal line CK1, GA2 is electrically connected to the second clock signal line CK2, GA3 is electrically connected to the third clock signal line CK3, and GA4 is electrically connected to the fourth clock signal line CK4; GA5 is electrically connected to the fifth clock signal line CK5, GA6 is electrically connected to the sixth clock signal line CK6, GA7 is electrically connected to the seventh clock signal line CK7, and GA8 is electrically connected to the eighth clock signal line CK8; GA9 is electrically connected to the ninth clock signal line CK9, and GA10 is electrically connected to the tenth clock signal line CK10 (it should be noted that this application uses ten clock signal lines for schematic illustration. In actual operation, the driving module can also be electrically connected to other numbers of clock signal lines. For example, the number of clock signal lines can be 6, 8, 12, 14, 16, etc., which is not limited here);

[0401] The first-level drive signal output terminal is labeled G11, the second-level drive signal output terminal is labeled G12, the third-level drive signal output terminal is labeled G13, and the fourth-level drive signal output terminal is labeled G14; the fifth-level drive signal output terminal is labeled G15, the sixth-level drive signal output terminal is labeled G16, the seventh-level drive signal output terminal is labeled G17, and the eighth-level drive signal output terminal is labeled G18; the ninth-level drive signal output terminal is labeled G19, and the tenth-level drive signal output terminal is labeled G110;

[0402] The one labeled OC1 is the first-level carry output terminal, the one labeled OC2 is the second-level carry output terminal, the one labeled OC3 is the third-level carry output terminal, and the one labeled OC4 is the fourth-level carry output terminal; the one labeled OC5 is the fifth-level carry output terminal, the one labeled OC6 is the sixth-level carry output terminal, the one labeled OC7 is the seventh-level carry output terminal, and the one labeled OC8 is the eighth-level carry output terminal; the one labeled OC9 is the ninth-level carry output terminal, and the one labeled OC10 is the tenth-level carry output terminal;

[0403] The input terminals of GA1, GA2, GA3 and GA4 are all electrically connected to a starting voltage line STV, which provides input signals to GA1, GA2, GA3 and GA4.

[0404] OC1 provides an input signal to the input terminal of GA5, OC2 provides an input signal to the input terminal of GA6, OC3 provides an input signal to the input terminal of GA7, OC4 provides an input signal to the input terminal of GA8, OC5 provides an input signal to the input terminal of GA9, and OC6 provides an input signal to the input terminal of GA10. That is, the carry output terminal of the n-4th stage driving circuit provides an input signal to the nth stage driving circuit;

[0405] OC6 provides a reset signal for GA1, OC7 provides a reset signal for GA2, OC8 provides a reset signal for GA3, OC9 provides a reset signal for GA4, and OC10 provides a reset signal for GA5. That is, the carry output of the n-th level driver circuit provides a reset signal to the n-5th level driver circuit. For example, Figure 10 , the carry output terminal of the nth stage driving circuit provides a reset signal to the n-5th stage driving circuit.

[0406] Figure 24 yes Figure 23 When at least one embodiment of the driving module shown is in operation, the waveform of the starting voltage provided by the starting voltage line STV, the waveform of the clock signal provided by each clock signal line, the waveform of the first control voltage provided by VDDO, and the waveform of the second control voltage provided by VDDE.

[0407] like Figure 24 As shown, the voltage value of the starting voltage continues to be a high voltage for 6 hours. Optionally, the starting voltage line provides an initial driving voltage to the transistors used for input of the adjacent first 4-level driving circuits. The potential of each clock signal continues to be a high voltage for 4 hours. The duty cycle of the clock signal is 40%, that is, the high level time is 4 hours and the low level time is 6 hours.

[0408] The driving method according to an embodiment of the present invention is applied to the above-mentioned driving module, and the driving method includes:

[0409] The input circuit controls the potential of the pull-up node according to an input signal provided by the input terminal;

[0410] The first reset circuit inputs a first voltage signal to the pull-up node under the control of a first reset signal provided by the first reset terminal;

[0411] The second reset circuit inputs a second voltage signal to the pull-up node under the control of a second reset signal provided by the second reset terminal;

[0412] A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal.

[0413] In an embodiment of the present invention, when the driving circuit resets the potential of the pull-up node, the first reset circuit, under the control of the first reset signal provided by the first reset terminal, controls the connection between the pull-up node and the first voltage terminal, and inputs the first voltage signal to the pull-up node. Thereafter, the second reset circuit, under the control of the second reset signal provided by the second reset terminal, controls the connection between the pull-up node and the second voltage terminal, and inputs the second voltage signal to the pull-up node. The voltage value of the first voltage signal is greater than the voltage value of the second voltage signal, so as to reduce the absolute value of the drain-source voltage of the transistor included in the first reset circuit, prevent the characteristic drift of the transistor included in the first reset circuit, and improve the reliability of the display product.

[0414] In at least one embodiment of the present invention, the driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit;

[0415] The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes:

[0416] In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal;

[0417] In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node;

[0418] In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node;

[0419] In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal;

[0420] In the fifth stage, the second reset circuit in the adjacent m-stage driving circuit controls the connection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node in the adjacent m-stage driving circuit;

[0421] m is a positive integer.

[0422] Optionally, the driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to a first noise reduction control terminal, and the second noise reduction circuit is electrically connected to a second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are both adjacent first m stage input terminals; and the driving cycle includes a noise reduction stage provided before the first stage;

[0423] The driving method further includes:

[0424] In the noise reduction stage, the first noise reduction circuit controls the connection between the first pull-down node and the second voltage terminal under the control of the signal provided by the adjacent first m stage input terminals; the second noise reduction circuit controls the connection between the second pull-down node and the second voltage terminal under the control of the signal provided by the adjacent first m stage input terminals.

[0425] In at least one embodiment of the present invention, the driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit;

[0426] The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes:

[0427] In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal;

[0428] In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node;

[0429] In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node;

[0430] In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal;

[0431] In the fifth stage, the second reset circuit controls the connection between the pull-up node and the second voltage terminal under the control of the first pull-down node of the current stage.

[0432] Optionally, the driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to the first noise reduction control terminal, and the second noise reduction circuit is electrically connected to the second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are first reset terminals; the first noise reduction control terminal is a noise reduction stage provided before the first stage in the driving cycle;

[0433] The driving method further includes:

[0434] In the fourth stage, the first noise reduction circuit controls the connection between the first pull-down node and the second voltage end under the control of the first reset signal; the second noise reduction circuit controls the connection between the second pull-down node and the second voltage end under the control of the first reset signal.

[0435] The display device according to the embodiment of the present invention includes the above-mentioned driving module.

[0436] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A driving module, characterized in that: It includes a multi-stage driving circuit; the driving circuit includes an input circuit, a first reset circuit and a first pull-down noise reduction circuit; The input circuit is electrically connected to the input terminal and the pull-up node respectively, and is used to control the potential of the pull-up node according to the input signal provided by the input terminal; The first reset circuit is electrically connected to the first reset terminal, the pull-up node and the first voltage terminal respectively, and is configured to input a first voltage signal provided by the first voltage terminal to the pull-up node under the control of a first reset signal provided by the first reset terminal; The first pull-down noise reduction circuit is electrically connected to the first pull-down node, the pull-up node, and the second voltage terminal, and is configured to input a second voltage signal provided by the second voltage terminal to the first pull-down node under the control of the potential of the pull-up node; A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal; The driving circuit further includes a second reset circuit; The second reset circuit is electrically connected to the first pull-down node, the pull-up node of the adjacent first m-stage driver circuit, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driver circuit and the second voltage terminal under the control of the potential of the first pull-down node; m is a positive integer; The first voltage terminal is a second low voltage terminal, and the second voltage terminal is a third low voltage terminal; the voltage value of the second low voltage signal provided by the second low voltage terminal is greater than the voltage value of the third low voltage signal provided by the third low voltage terminal.

2. The driving module according to claim 1, wherein: The driving circuit further includes a second reset circuit; The second reset circuit is electrically connected to the first pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node.

3. The driving module according to claim 1, wherein: The driving circuit further includes a third reset circuit; The third reset circuit is electrically connected to the second pull-down node, the pull-up node of the adjacent first m-stage driving circuit and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node of the adjacent first m-stage driving circuit and the second voltage terminal under the control of the potential of the second pull-down node.

4. The driving module according to claim 2, wherein: The driving circuit further includes a third reset circuit; The third reset circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the potential of the second pull-down node.

5. The driving module according to claim 1, wherein: The driving circuit further includes a second pull-down noise reduction circuit; The second pull-down noise reduction circuit is electrically connected to the second pull-down node, the pull-up node and the second voltage terminal respectively, and is used to input the second voltage signal provided by the second voltage terminal to the second pull-down node under the control of the pull-up node.

6. The driving module according to claim 1, wherein: The driving circuit further includes a first noise reduction circuit; The first noise reduction circuit is electrically connected to the first noise reduction control terminal, the first pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first pull-down node and the second voltage terminal under the control of a first noise reduction control signal provided by the first noise reduction control terminal; The first noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal.

7. The driving module according to claim 6, wherein: The driving circuit further includes a second noise reduction circuit; The second noise reduction circuit is electrically connected to the second noise reduction control terminal, the second pull-down node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the second pull-down node and the second voltage terminal under the control of a second noise reduction control signal provided by the second noise reduction control terminal; The second noise reduction control terminal is an input terminal of the adjacent first m-stage driving circuit or the first reset terminal; m is a positive integer.

8. The driving module according to claim 1, wherein: The first reset circuit includes a first transistor; The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

9. The driving module according to claim 8, wherein: A channel length of the first transistor is greater than a channel length threshold, and a channel width-to-length ratio of the first transistor is less than a width-to-length ratio threshold.

10. The driving module according to claim 1, wherein: The second reset circuit includes a second transistor; The gate of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

11. The driving module according to claim 2, wherein: The second reset circuit includes a second transistor; A gate of the second transistor is electrically connected to the first pull-down node, a first electrode of the second transistor is electrically connected to the pull-up node, and a second electrode of the second transistor is electrically connected to the second voltage terminal.

12. The driving module according to claim 3, wherein: The third reset circuit includes a third transistor; The gate of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node of the adjacent first m-stage driving circuit, and the second electrode of the third transistor is electrically connected to the second voltage terminal.

13. The driving module according to claim 4, wherein: The third reset circuit includes a third transistor; A gate of the third transistor is electrically connected to the second pull-down node, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the second voltage terminal.

14. The driving module according to claim 6, wherein: The first noise reduction circuit includes a fourth transistor; A gate of the fourth transistor is electrically connected to the first noise reduction control terminal, a first electrode of the fourth transistor is electrically connected to the first pull-down node, and a second electrode of the fourth transistor is electrically connected to the second voltage terminal.

15. The driving module according to claim 7, wherein: The second noise reduction circuit includes a fifth transistor; A gate of the fifth transistor is electrically connected to the second noise reduction control terminal, a first electrode of the fifth transistor is electrically connected to the second pull-down node, and a second electrode of the fifth transistor is electrically connected to the second voltage terminal.

16. The driving module according to any one of claims 1 to 15, wherein: The driving circuit also includes a driving signal output terminal and a driving reset circuit; The driving reset circuit is electrically connected to the pull-down node, the driving signal output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the driving signal output terminal and the first voltage terminal under the control of the potential of the pull-down node; or The drive reset circuit is electrically connected to the pull-down node, the drive signal output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the pull-down node; the third voltage terminal is a different voltage terminal from the first voltage terminal.

17. The driving module according to claim 16, wherein: The driving reset circuit includes a sixth transistor and a seventh transistor, and the pull-down node includes a first pull-down node and a second pull-down node; The gate of the sixth transistor is electrically connected to the first pull-down node, the first electrode of the sixth transistor is electrically connected to the drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal or the third voltage terminal; The gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the driving signal output terminal, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal or the third voltage terminal.

18. The driving module according to any one of claims 1 to 15, wherein: The driving circuit further includes a carry output terminal, a pull-up node control circuit, a pull-down node control circuit, a carry output circuit, a driving output circuit and an energy storage circuit; The pull-up node control circuit is electrically connected to the pull-up node, the frame reset terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the second voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The pull-down node control circuit is electrically connected to the pull-down node and the control voltage terminal, respectively, and is used to control the potential of the pull-down node under the control of the control voltage provided by the control voltage terminal; The driving output circuit is electrically connected to the pull-up node, the first clock signal terminal and the driving signal output terminal respectively, and is used to provide the first clock signal provided by the first clock signal terminal to the driving signal output terminal under the control of the potential of the pull-up node; The carry output circuit is electrically connected to the pull-up node, the pull-down node, the carry output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is configured to control, under the control of the potential of the pull-up node, the second clock signal provided by the second clock signal terminal to be provided to the carry output terminal, and, under the control of the potential of the pull-down node, control the connection or disconnection between the carry output terminal and the second voltage terminal; The energy storage circuit is electrically connected to the pull-up node and the drive signal output terminal respectively, and is used for storing electric energy.

19. The driving module according to claim 18, wherein: The input circuit includes an eighth transistor, the pull-up node control circuit includes a ninth transistor, the pull-down node includes a first pull-down node and a second pull-down node, and the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the drive circuit further includes a second pull-down noise reduction circuit; The pull-down node control circuit includes a tenth transistor and a twelfth transistor, the first pull-down noise reduction circuit includes an eleventh transistor, the second pull-down noise reduction circuit includes a thirteenth transistor, the drive output circuit includes a fourteenth transistor, the carry output circuit includes a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor, and the energy storage circuit includes a storage capacitor; The gate electrode of the eighth transistor and the first electrode of the eighth transistor are both electrically connected to the input terminal, and the second electrode of the eighth transistor is electrically connected to the pull-up node; The gate of the ninth transistor is electrically connected to the frame reset terminal, the first electrode of the ninth transistor is electrically connected to the pull-up node, and the second electrode of the ninth transistor is electrically connected to the second voltage terminal; The gate electrode of the tenth transistor and the first electrode of the tenth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the tenth transistor is electrically connected to the first pull-down node; The gate of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the first pull-down node, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal; The gate electrode of the twelfth transistor and the first electrode of the twelfth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal; The gate of the fourteenth transistor is electrically connected to the pull-up node, the first electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the drive signal output terminal; The gate of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the carry output terminal; The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first electrode of the sixteenth transistor is electrically connected to the carry output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage terminal; The gate of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the carry output terminal, and the second electrode of the seventeenth transistor is electrically connected to the second voltage terminal; A first end of the storage capacitor is electrically connected to the pull-up node, and a second end of the storage capacitor is electrically connected to the driving signal output end.

20. The driving module according to any one of claims 1 to 15, wherein: When the input end of the current stage driving circuit is electrically connected to the output end of the adjacent m-stage driving circuit, and the first reset end of the current stage driving circuit is electrically connected to the output end of the adjacent m+1-stage driving circuit; The output end is a carry signal output end or a drive signal output end.

21. A driving method, applied to the driving module according to any one of claims 1 to 20, characterized in that: The driving method includes: The input circuit controls the potential of the pull-up node according to the input signal provided by the input terminal; The first reset circuit inputs a first voltage signal to the pull-up node under the control of a first reset signal provided by the first reset terminal; The first pull-down noise reduction circuit inputs a second voltage signal to the pull-up node under the control of the first pull-down node; A voltage value of the first voltage signal is greater than a voltage value of the second voltage signal.

22. The driving method according to claim 21, wherein: The driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit; The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes: In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal; In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node; In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node; In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal; In the fifth stage, the second reset circuit in the adjacent m-stage driving circuit controls the connection between the pull-up node and the second voltage terminal under the control of the potential of the first pull-down node in the adjacent m-stage driving circuit; m is a positive integer.

23. The driving method according to claim 22, wherein: The driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to a first noise reduction control terminal, and the second noise reduction circuit is electrically connected to a second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are both input terminals of the adjacent first m-stage driving circuit; the driving cycle includes a noise reduction phase provided before the first phase; The driving method further includes: In the noise reduction stage, the first noise reduction circuit controls the connection between the first pull-down node and the second voltage terminal under the control of the signal provided by the input terminal of the adjacent first m-stage driving circuit; the second noise reduction circuit controls the connection between the second pull-down node and the second voltage terminal under the control of the signal provided by the input terminal of the adjacent first m-stage driving circuit.

24. The driving method according to claim 21, wherein: The driving circuit in the driving module further includes a second reset circuit, a driving output circuit and an energy storage circuit; The driving cycle includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage; and the driving method includes: In the first stage, the input terminal provides a valid input signal, and the input circuit controls the potential of the current stage pull-up node to be a first potential according to the input signal; In the second stage, the drive output circuit provides a first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; the potential of the first clock signal is a second potential, and the energy storage circuit bootstraps the potential of the current stage pull-up node; In the third stage, the potential of the first clock signal drops from the second potential to the third potential, and the drive output circuit provides the first clock signal to the drive signal output terminal under the control of the potential of the pull-up node; as the potential of the first clock signal drops, the energy storage circuit pulls down the potential of the current stage pull-up node; In the fourth stage, the first reset circuit controls the connection between the pull-up node and the first voltage terminal under the control of the first reset signal; In the fifth stage, the second reset circuit controls the connection between the pull-up node and the second voltage terminal under the control of the first pull-down node of the current stage.

25. The driving method according to claim 24, wherein: The driving circuit further includes a first noise reduction circuit and a second noise reduction circuit; the first noise reduction circuit is electrically connected to the first noise reduction control terminal, and the second noise reduction circuit is electrically connected to the second noise reduction control terminal; the first noise reduction control terminal and the second noise reduction control terminal are first reset terminals; the first noise reduction control terminal is a noise reduction stage provided before the first stage in the driving cycle; The driving method further includes: In the fourth stage, the first noise reduction circuit controls the first pull-down node to be connected to the second voltage terminal under the control of the first reset signal; The second noise reduction circuit controls the second pull-down node to be connected to the second voltage terminal under the control of the first reset signal.

26. A display device, characterized in that: The drive module comprises the drive module according to any one of claims 1 to 20.

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