Display device

Abstract

The invention provides a display device, which comprises a plurality of cascaded gate driving units, a gate driving transistor in each gate driving unit comprises an active layer, a gate layer arranged in different layers with the active layer, and a source and drain electrode layer arranged in different layers with the active layer and the gate layer, the source and drain electrode layer is connected with the active layer, and the active layer is connected with the gate layer. An active layer of at least one gate driving transistor comprises at least two active parts which are arranged on the same layer at intervals, a gate layer is overlapped with the at least two corresponding active parts, a source-drain layer is connected with the at least two corresponding active parts, and heat is dispersed by arranging the active layer into the at least two separated active parts. The influence on the electrical property of the gate driving transistor is reduced, so that the reliability of the gate signal output by the gate driving unit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] The size of the active layer of the transistor of the gate drive circuit of the display product needs to be set larger to meet the functional requirements of the display product. However, the larger active layer will cause the transistor to have a transient large current when it is turned on, thereby generating heat, affecting the electrical properties of the transistor, causing the gate signal output by the gate drive circuit to be abnormal, and affecting the opening of the sub-pixel. Summary of the invention

[0003] The embodiments of the present application provide a display device to solve the technical problem that the gate signal outputted by the existing gate driving circuit is abnormal due to the large size of the active layer.

[0004] An embodiment of the present application provides a display device, including a gate driving circuit, wherein the gate driving circuit includes a plurality of cascaded gate driving units, and the gate driving unit includes:

[0005] A plurality of gate drive transistors, at least one of the gate drive transistors comprises an active layer, a gate layer disposed at a different layer from the active layer, and a source-drain electrode layer disposed at a different layer from both the active layer and the gate layer, the source-drain electrode layer being connected to the active layer;

[0006] The active layer includes at least two active parts which are in the same layer and are spaced apart from each other, the gate layer overlaps with the corresponding at least two active parts, and the source-drain layer is connected with the corresponding at least two active parts.

[0007] In some embodiments, at least two of the active portions have equal widths;

[0008] And / or, the active layer includes at least three active parts that are in the same layer and spaced apart from each other, and the distance between every two adjacent active parts is equal.

[0009] In some embodiments, at least two of the active portions in the active layer are arranged along a first direction, and the gate layer at least extends along the first direction to overlap with the corresponding at least two active portions.

[0010] In some embodiments, at least two of the active portions in the active layer are arranged along a first direction, the source-drain layer extends at least along the first direction to overlap with the corresponding at least two active portions, a portion of the film layer between the source-drain layer and the active layer corresponding to the overlap of the source-drain layer and the active layer includes a via, and the source-drain layer is connected to the active layer through a conductive portion located in the via.

[0011] In some embodiments, the source-drain electrode layer includes a source electrode and a drain electrode that are in the same layer and are spaced apart from each other, the source electrode is connected to the corresponding first portion of the active layer, the drain electrode is connected to the corresponding second portion of the active layer, and the source electrode and the drain electrode both extend at least along the first direction;

[0012] The first gate driving transistor and the second gate driving transistor in the plurality of gate driving transistors each include the active layer, the corresponding gate layer and the corresponding source and drain layer;

[0013] Among them, one of the source and the drain of the first gate-driving transistor and one of the source and the drain of the second gate-driving transistor constitute a common part, and the common part is embedded in the other of the source and the drain of the first gate-driving transistor and the other of the source and the drain of the second gate-driving transistor.

[0014] In some embodiments, it further includes a plurality of pixel circuits and a plurality of gate lines, each of the gate lines being electrically connected to a corresponding plurality of the pixel circuits;

[0015] Among them, one of the source and the drain of the first gate driving transistor and one of the source and the drain of the second gate driving transistor in the gate driving unit are both electrically connected to the corresponding gate line to output a gate signal.

[0016] In some embodiments, the pixel circuit comprises:

[0017] Light emitting element;

[0018] A driving transistor, wherein one of a source and a drain of the driving transistor is electrically connected to the light emitting element;

[0019] a first reset transistor electrically connected to the gate of the driving transistor, and configured to transmit a first reset signal to the gate of the driving transistor in response to a first gate signal;

[0020] a second reset transistor, electrically connected to one end of the light emitting element, for transmitting a second reset signal to one end of the light emitting element in response to a second gate signal;

[0021] The display device comprises at least two gate driving circuits, wherein the at least two gate driving circuits comprise a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit comprises a plurality of first gate driving units for generating a plurality of the first gate signals and being cascaded, and the second gate driving circuit comprises a plurality of second gate driving units for generating a plurality of the second gate signals and being cascaded;

[0022] The first gate signal is used to control the first reset transistor to be turned on in a writing phase to transmit the first reset signal to the gate of the driving transistor, and is used to control the first reset transistor to be turned off in a holding phase corresponding to the writing phase;

[0023] The second gate signal is used to control the second reset transistor to be turned on during the writing phase and the holding phase corresponding to the writing phase, so as to transmit the second reset signal to one end of the light emitting element.

[0024] In some embodiments, the first gate signal comprises at least two first gate pulses in the writing phase, and each of the first gate pulses is used to control the first reset transistor to be turned on;

[0025] The second gate signal includes at least two second gate pulses in each of the writing phase and a corresponding holding phase after the writing phase, and each second gate pulse is used to control the second reset transistor to be turned on.

[0026] In some embodiments, the pixel circuit further comprises:

[0027] a compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor, and configured to form a current path between one of the source and the drain of the driving transistor and the gate of the driving transistor in response to a third gate signal;

[0028] a light emitting control transistor, electrically connected to the other of the source and the drain of the driving transistor, and configured to transmit the first voltage signal to the other of the source and the drain of the driving transistor in response to a fourth gate signal;

[0029] Wherein, at least two of the gate driving circuits further include a third gate driving circuit and a fourth gate driving circuit, the third gate driving circuit includes a plurality of third gate driving units for generating a plurality of the third gate signals and being cascaded, and the fourth gate driving circuit includes a plurality of fourth gate driving units for generating a plurality of the fourth gate signals and being cascaded;

[0030] The third gate signal is used to control the compensation transistor to be turned on in the writing phase so as to form a current path between one of the source and the drain of the driving transistor and the gate of the driving transistor, and is used to control the compensation transistor to be turned off in the holding phase corresponding to the writing phase;

[0031] The fourth gate signal is used to control the light emission control transistor to be turned on during the writing phase and the holding phase corresponding to the writing phase.

[0032] In some embodiments, the display device includes a display area and a non-display area located at least on one side of the display area, a plurality of the pixel circuits are located in the display area, and a plurality of the gate driving circuits are located in the non-display area;

[0033] The second gate driving circuit, the first gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit are arranged in sequence in a direction away from the display area.

[0034] In some embodiments, the first gate driving circuit further includes at least one first virtual gate driving unit located before the first gate driving unit of the first stage and / or after the first gate driving unit of the last stage;

[0035] And / or, the second gate driving circuit further includes at least one second virtual gate driving unit located before the second gate driving unit of the first stage and / or after the second gate driving unit of the last stage;

[0036] And / or, the third gate driving circuit further includes at least one third virtual gate driving unit located before the third gate driving unit of the first stage and / or after the third gate driving unit of the last stage;

[0037] And / or, the fourth gate driving circuit further includes at least one fourth virtual gate driving unit located before the fourth gate driving unit of the first stage and / or after the fourth gate driving unit of the last stage.

[0038] In some embodiments, the display device further includes a first clock signal line and a second clock signal line for transmitting a clock signal, wherein the number of metal layers included in the first clock signal line is less than the number of metal layers included in the second clock signal line;

[0039] The first gate driving unit, the second gate driving unit and the third gate driving unit are electrically connected to the first clock signal line, and the fourth gate driving unit is electrically connected to the second clock signal line.

[0040] The present application provides a display device, including a plurality of cascaded gate driving units, wherein the active layer in at least one gate driving transistor in the gate driving unit is arranged to include at least two active parts that are in the same layer and arranged at intervals, the gate layer overlaps with the corresponding at least two active parts, and the source-drain layer is connected to the corresponding at least two active parts. While maintaining its overall signal transmission function, the arrangement density of the active layer is dispersed to avoid the active layer being concentrated in a continuous area. When the gate driving transistor is turned on, the path through which the current flows in the active part can also be dispersed, so that the heat generated can also be dispersed, reducing the impact on the electrical properties of the gate driving transistor, thereby improving the reliability of the gate signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A top view of a display device provided in an embodiment of the present application.

[0042] Figure 2 and Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of the present application.

[0043] Figure 4 , Figure 5 and Figure 8 A layout diagram of a gate drive circuit provided in an embodiment of the present application.

[0044] Figure 6 A circuit diagram of a pixel circuit provided in an embodiment of the present application.

[0045] Figure 7 A timing diagram of a pixel circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0047] The terms "first", "second", "third", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other steps or modules inherent to these processes, methods, products or devices.

[0048] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0049] Embodiments of the present application provide a display device, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0050] In some embodiments, Figure 1 As shown, the display device 100 includes a gate driving circuit 10, wherein the gate driving circuit 10 includes a plurality of cascaded gate driving units 101, Figures 2 to 5 As shown, the gate driving unit 101 includes: a plurality of gate driving transistors (including but not limited to Figure 2 The first gate transistor T1, the second gate transistor T2 to the eighth gate transistor T8, the first capacitor C1 and the second capacitor C2, and Figure 3 The first gate transistor T1, the second gate transistor T2 to the thirteenth gate transistor T13, the first capacitor C1 and the second capacitor C2), at least one of the gate drive transistors (including but not limited to Figure 1 and / or Figure 2 The first gate transistor T1 and the second gate transistor T2 in the transistor include an active layer 01, a gate layer 02 which is arranged at a different layer from the active layer 01, and a source-drain layer 03 which is arranged at a different layer from both the active layer 01 and the gate layer 02, and the source-drain layer 03 is connected to the active layer 01; wherein the active layer 01 includes at least two active portions 011 which are arranged at the same layer and at intervals, the gate layer 02 overlaps with the corresponding at least two active portions 011, and the source-drain layer 03 is connected to the corresponding at least two active portions 011.

[0051] like Figure 1 As shown, the display device 100 may include a display area A and a non-display area B located at least on one side of the display area A. The display area A is provided with a plurality of pixel circuits 20 and a plurality of gate lines (not shown), and the non-display area B is provided with the above-mentioned gate driving circuit 10. Figure 6As shown, the pixel circuit 20 includes: a light-emitting element 201; a driving transistor T1', one of the source and the drain of the driving transistor T1' (electrically connected to the first node B) is electrically connected to the light-emitting element 201; a first reset transistor T4', electrically connected to the gate of the driving transistor T1' (electrically connected to the second node Q), and used to respond to the first gate signal Reset_Q to transmit the first reset signal Vi to the gate of the driving transistor T1'; a second reset transistor T7', electrically connected to one end of the light-emitting element 201 (electrically connected to the third node C), and used to respond to the second gate signal Reset_C to transmit a second reset signal (which may be the same as or different from the first reset signal Vi, and the two are the same as an example here) to one end of the light-emitting element 201.

[0052] Among them, this embodiment may include one or more gate driving circuits 10, each gate driving circuit 10 may include multiple cascaded gate driving units 101, the first gate signal Reset_Q and the second gate signal Reset_C may be generated by two gate driving units 101 of different levels in the same gate driving circuit 10, or may be generated by gate driving units 101 of the same or different levels in two gate driving circuits 10.

[0053] Further, such as Figure 6 As shown, the pixel circuit 20 may further include a compensation transistor T3' electrically connected between the first node B and the second node Q, a data writing transistor T2' electrically connected between the source and the other of the drain of the driving transistor T1' (electrically connected to the fourth node A) and a data line for transmitting the data signal Data, a first light emission control transistor T5' electrically connected between the fourth node A and a first voltage line for transmitting the first voltage signal VDD, a second light emission control transistor T6' electrically connected between the first node B and the third node C, and a storage capacitor Cst electrically connected between the second node Q and the first voltage line. The data writing transistor T2' is used to respond to the third gate signal Pscan to transmit the data signal Data to the fourth node A, and the first light emission control transistor T5' and the second light emission control transistor T6' are used to respond to the fourth gate signal EM to form a current path between the first voltage line and the second voltage line electrically connected to the other end of the light emitting element 201 and used to transmit the second voltage signal VSS.

[0054] Correspondingly, the present embodiment may further include a gate driving circuit 10 for generating a third gate signal Pscan and a gate driving circuit 10 for generating a fourth gate signal EM. That is, the present embodiment may include at most four gate driving circuits 10 for generating the above four gate signals respectively.

[0055] Specifically, Figure 4 The circuit layout diagrams of the first gate driving circuit 1011, the second gate driving circuit 1012, the third gate driving circuit 1013, and the fourth gate driving circuit 1014 for generating the first gate signal Reset_Q, the second gate signal Reset_C, the third gate signal Pscan, and the fourth gate signal EM are shown in FIG. The circuit diagrams of the first three can be referred to Figure 2 The circuit diagram of the latter can be referred to Figure 3 It should be noted that since the circuit diagrams of the first three can be the same, the circuit layout diagrams of the three (including the first gate transistor T1, the second gate transistor T2 to the eighth gate transistor T8, the first capacitor C1 and the second capacitor C2) can also be the same. Figure 3 Although the device names in Figure 2 The two are the same, but their specific functions and connection relationships are different. Figure 5 Can be Figure 4 FIG. 1 is a circuit layout diagram of at least one gate driving transistor in at least one gate driving circuit 10 .

[0056] Combination Figures 2 to 4 As shown, the above four gate driving circuits all need to be connected to the high-voltage signal line VGH, the low-voltage signal line VGL and the clock signal line (including the forward clock signal line CK and the reverse clock signal line XCK, the clock signals transmitted by the two are reverse signals to each other), wherein the forward clock signal line CK and the reverse clock signal line XCK electrically connected to each level of the gate driving unit 101 can be two of the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3 and the fourth clock signal line CK4, respectively, and the periods of the four clock signals respectively transmitted by these four clock signal lines are the same.

[0057] Understandable, such as Figure 5 As shown, in this embodiment, based on the fact that the gate driving transistor includes an active layer 01, a gate layer 02 arranged at a different layer from the active layer 01, a source-drain electrode layer 03 arranged at a different layer from both the active layer 01 and the gate layer 02, and the film layer relationship and connection relationship between the source-drain electrode layer 03 and the active layer 01, the active layer 01 is arranged to include at least two active parts 011 that are in the same layer and arranged at intervals, and the gate layer 02 overlaps with the corresponding at least two active parts 011, and the source-drain electrode layer 03 is connected to the corresponding at least two active parts 011, that is, the active layer 01 is no longer arranged continuously, but the arrangement density of the active layer 01 is dispersed while maintaining its overall signal transmission function, so as to avoid the active layer 01 being concentrated in a continuous area. When the gate driving transistor is turned on, the path through which the current flows in the active part 011 can also be dispersedly arranged, so that the heat generated can also be dispersed, thereby reducing the influence on the electrical properties of the gate driving transistor.

[0058] Further, combined with Figures 2 to 5 As shown, the first gate driving transistor T1 and the second gate driving transistor T2 in the plurality of gate driving transistors both include the active layer 01, the corresponding gate layer 02 and the corresponding source-drain layer 03, that is, the active layer 01, the gate layer 02 and the source-drain layer 03 of the first gate driving transistor T1 and the second gate driving transistor T2 conform to the above settings, wherein one of the source and the drain of the first gate driving transistor T1 and one of the source and the drain of the second gate driving transistor T2 are both electrically connected to the corresponding gate line (the first gate line L1 corresponding to the first gate driving circuit 1011, the second gate line L2 corresponding to the second gate driving circuit 1012, the third gate line L3 corresponding to the third gate driving circuit 1013 or the fourth gate line L4 corresponding to the fourth gate driving circuit 1014) to output a gate signal (a corresponding one of the above four gate signals).

[0059] It can be understood that the active layer 01 in the first gate driving transistor T1 and the second gate driving transistor T2 in the gate driving circuit 10 electrically connected to the gate line for outputting the gate signal is further defined as being arranged as at least two active parts 011 arranged in the same layer and spaced apart in the above manner, and the connection and position relationship between the gate layer 02 and the source-drain layer 03 and the active layer 01 also corresponds to the above arrangement, so as to disperse the arrangement density of the active layer 01 while maintaining its overall signal transmission function. Figure 2 or Figure 3 The first gate-driving transistor T1 and the second gate-driving transistor T2 shown in the figure both function to transmit the high potential or low potential of the corresponding gate signal to the gate line, thereby forming a complete gate signal. Since each gate line needs to be electrically connected to the corresponding multiple pixel circuits 20, the required driving current is relatively large, that is, the current flowing through the first gate-driving transistor T1 and the second gate-driving transistor T2 is relatively large. At least the active layers 01 of the two are dispersed, which can reduce the impact on the electrical properties of the gate driving transistor with the greatest risk of large current, and can greatly improve the reliability of the gate driving circuit 10.

[0060] In some embodiments, Figure 5As shown, at least two of the active parts 011 have the same width; and / or, the active layer 01 includes at least three active parts 011 in the same layer and spaced apart, and the spacing between each two adjacent active parts 011 is equal. It can be understood that in this embodiment, the widths of the multiple active parts 011 are set to be equal, so that the heat borne by each active part 011 is equal, avoiding the risk of local failure caused by uneven heat borne by different active parts 011, and / or, the spacing between each two of the multiple active parts 011 is set to be equal, so that the heat dissipation space between each two adjacent active parts 011 is equal, avoiding the risk of heat accumulation caused by uneven heat dissipation.

[0061] Specifically, Figure 5 As shown, at least two active portions 011 in the active layer 01 are arranged along the first direction D1, and the gate layer 02 at least extends along the first direction D1 to overlap with the corresponding at least two active portions 011. That is, based on the arrangement of multiple active portions 011 along the first direction D1, in order to facilitate the overlap of the gate layer 02 with the multiple active portions 011, the gate layer 02 is configured to include at least a portion extending along the first direction D1.

[0062] Similarly, if Figure 5 As shown, based on the arrangement of multiple active parts 011 along the first direction, the source-drain layer 03 also extends at least along the first direction D1 to overlap with the corresponding at least two active parts 011. Considering that the two need to be electrically connected, the film layer (which may include an insulating layer) between the source-drain layer 03 and the active layer 01 includes a via 04 in the portion corresponding to the overlap of the source-drain layer 03 and the active layer 01, and the source-drain layer 03 is connected to the active layer 01 through the conductive portion located in the via 04. Among them, a plurality of vias 04 arranged in the first direction D1 may be provided in the portion where the source-drain layer 03 overlaps with each active part 011, and a conductive portion may be provided in each via 04 to improve the reliability of the electrical connection.

[0063] Furthermore, in order to increase the facing area of ​​the gate layer 02 and the source-drain layer 03, the two can be arranged to be bent along a second direction D2 perpendicular to the first direction D1 to form an "S-type" or "C-type", and the two can be embedded, that is, at least part of the gate layer 02 is embedded in the source-drain layer 03, and / or, at least part of the source-drain layer 03 is embedded in the gate layer 02.

[0064] In some embodiments, Figure 5As shown, the source-drain layer 03 includes a source 031 and a drain 032 in the same layer and arranged at intervals, the source 031 is connected to the first part of the corresponding active layer 01, the drain 032 is connected to the second part of the corresponding active layer 01, and the source 031 and the drain 032 both extend at least along the first direction D1; one of the source 031 and the drain 032 of the first gate-driven transistor T1 and one of the source 031 and the drain 032 of the second gate-driven transistor T2 constitute a common portion, and the common portion is embedded in the other of the source 031 and the drain 032 of the first gate-driven transistor T1 and the other of the source 031 and the drain 032 of the second gate-driven transistor T2.

[0065] For ease of description, Figure 5 In the example, the drain 032 of the first gate transistor T1 and the drain 032 of the second gate transistor T2 constitute a common part, that is, the drains 032 of the two can be integrally formed into a "common part" structure. Figure 5 As shown, the source 031 of the first gate-driven transistor T1 and the source 031 of the second gate-driven transistor T2 can both be "C-shaped", the above-mentioned "common part" can be "3-shaped" (that is, including three protrusions arranged along the second direction D2), the upper protrusion and the lower protrusion of the "common part" can be respectively embedded in the recessed part of the upper source 031 and the recessed part of the lower source 031, and the middle protrusion of the "common part" is embedded in the gap between the above-mentioned two recessed parts. The gate layer 02 of the first gate-driven transistor T1 and the gate layer 02 of the second gate-driven transistor T2 can both be "S-shaped", the upper gate layer 02 can be arranged around the upper protrusion of the "common part" and the lower half of the corresponding source 031 (in the "C-shaped"), and the lower gate layer 02 can be arranged around the lower protrusion of the "common part" and the upper half of the corresponding source 031 (in the "C-shaped").

[0066] It should be noted that, combined with Figure 2 , Figure 3 and Figure 5 As shown, since the drain 032 of the first gate-driven transistor T1 and the drain 032 of the second gate-driven transistor T2 are both electrically connected to the gate line, the drains 032 of the two can be integrally formed to form a common portion to save process steps.

[0067] Combined with the above discussion, we can see that Figures 2 to 4 , Figure 6 and Figure 7As shown, the display device 100 includes at least two gate drive circuits 10, and the at least two gate drive circuits 10 include the above-mentioned first gate drive circuit 1011 and the second gate drive circuit 1012, the first gate drive circuit 1011 includes a plurality of first gate drive units for generating a plurality of the first gate signals Reset_Q and cascaded, and the second gate drive circuit 1012 includes a plurality of second gate drive units for generating a plurality of the second gate signals Reset_C and cascaded. Wherein, the first gate signal Reset_Q is used to control the first reset transistor T4' to be turned on in the writing stage t1 so as to transmit the first reset signal Vi to the gate of the driving transistor T1', and is used to control the first reset transistor T4' to be turned off in the corresponding holding stage t2 after the writing stage t1; the second gate signal Reset_C is used to control the second reset transistor T7' to be turned on in the writing stage t1 and the corresponding holding stage t2 after the writing stage t1 so as to transmit the second reset signal (for example, the same as the first reset signal Vi) to one end of the light-emitting element 201.

[0068] It should be noted that for low refresh rate display, since each frame includes a writing phase t1 and a corresponding holding phase t2 after the writing phase t1, combined with Figure 6 and Figure 7 As shown, in the writing stage t1, the first reset transistor T4' and the second reset transistor T7' need to be turned on first to reset the second node Q and the third node C respectively, and then the data writing transistor T2' needs to be turned on to write the data signal Data into the storage capacitor Cst, and finally the first light-emitting control transistor T5' and the second light-emitting control transistor T6' need to be turned on to make the light-emitting element 201 emit light. When the refresh rate is lower, the number of holding stages t2 (the duration of each holding stage t2 can be equal to the duration of the writing stage t1) in each frame is greater, and the holding stage t2 no longer writes the data signal Data (the effective potential, for example, the effective potential is less than the invalid potential), that is, the light-emitting element 201 needs to maintain the light emission for a longer time on the basis of emitting light in the writing stage t1, resulting in a larger difference in its brightness from the brightness in the writing stage t1, and the brightness will change after the data signal Data is written in each frame. Such a cycle will cause flickering problems.

[0069] It can be understood that in this embodiment, different first gate driving circuits 1011 and second gate driving circuits 1012 are set to respectively generate first gate signals Reset_Q and second gate signals Reset_C with different periods (rather than generating first gate signals Reset_Q and second gate signals Reset_C with the same period by gate driving units of different levels of the same gate driving circuit), the first gate signal Reset_Q only includes the first gate pulse p1 in the writing stage t1 of a frame to reset the second node Q, and does not include the first gate pulse p1 in the holding stage t2 to avoid affecting the potential stored in the storage capacitor Cst and thus avoiding affecting the magnitude of the driving current, and the second gate signal Reset_C includes the second gate pulse p2 in the writing stage t1 of a frame and the holding stage t2 thereafter to reset the third node C, so that the light-emitting element 201 can also emit light after being reset by the anode or cathode in the holding stage t2, thereby reducing the difference in light-emitting brightness from the writing stage t1, thereby improving the flicker problem.

[0070] Further, combined with Figure 6 and Figure 7 As shown, the first gate signal Reset_Q includes at least two of the above-mentioned first gate pulses p1 in the writing stage t1, and each of the first gate pulses p1 is used to control the first reset transistor T4' to be turned on; the second gate signal Reset_C includes at least two second gate pulses p2 in each of the writing stage t1 and the corresponding holding stage t2 after the writing stage t1, and each of the second gate pulses p2 is used to control the second reset transistor T7' to be turned on.

[0071] It can be understood that in this embodiment, by setting the first gate signal Reset_Q to include multiple first gate pulses p1 in the corresponding time period, and setting the second gate signal Reset_C to include multiple second gate pulses p2 in the corresponding time period, the first reset transistor T4' is controlled to be turned on multiple times in the corresponding time period, and the second reset transistor T7' is also turned on multiple times in the corresponding time period, wherein the number of first gate pulses p1 and the number of second gate pulses p2 in the write phase t1 are the same, for example, after the first reset transistor T4' is turned on each time to reset the second node Q once, the second reset transistor T7' is also turned on to reset the third node C once, so as to achieve a complete reset of both.

[0072] In some embodiments, Figure 6As shown, the pixel circuit 20 further includes: the compensation transistor T3', which is electrically connected between one of the source and the drain of the driving transistor T1' and the gate of the driving transistor T1', and is used to respond to the third gate signal Pscan to form a current path between one of the source and the drain of the driving transistor T1' and the gate of the driving transistor T1'; a light emitting control transistor (for example, the first light emitting control transistor T5'), which is electrically connected to the other of the source and the drain of the driving transistor T1' (electrically connected to the fourth node); A), for transmitting the first voltage signal VDD to the other of the source and the drain of the driving transistor T1' in response to the fourth gate signal EM; wherein at least two of the gate driving circuits 10 further include the third gate driving circuit 1013 and the fourth gate driving circuit 1014, the third gate driving circuit 1013 includes a plurality of third gate driving units for generating a plurality of the third gate signals Pscan and cascaded, and the fourth gate driving circuit includes a plurality of fourth gate driving units for generating a plurality of the fourth gate signals EM and cascaded; Figure 7 As shown, the third gate signal Pscan is used to control the compensation transistor T3' to be turned on in the writing stage t1 so as to form a current path between one of the source and the drain of the driving transistor T1' and the gate of the driving transistor T1', and is used to control the compensation transistor T3' to be turned off in the holding stage t2 corresponding to the writing stage t1; the fourth gate signal EM is used to control the light-emitting control transistor (for example, the above-mentioned first light-emitting control transistor T5') to be turned on in the writing stage t1 and the holding stage t2 corresponding to the writing stage t1 so as to form a current path between the first voltage line and the second voltage line.

[0073] Specific, combined Figure 6 and Figure 7 As shown, the writing phase t1 may include the following phases:

[0074] In the first stage t11, the first gate pulse p1 of the first gate signal Reset_Q first controls T4' to be turned on to transmit the first reset signal Vi to the gate of the driving transistor T1' to reset it, and then the second gate pulse p2 of the second gate signal Reset_C controls the second reset transistor T7' to be turned on to transmit the second reset signal (for example, the same as the first reset signal Vi) to one end of the light emitting element 201 to reset it, and at the same time, the third gate pulse p3 of the third gate signal Pscan controls the compensation transistor T3' to be turned on so that a current path is formed between one of the source and the drain of the driving transistor T1' and the gate of the driving transistor T1' to reset one of the source and the drain of the driving transistor T1', and the third gate pulse p3 of the third gate signal Pscan also controls the data writing transistor T2' to be turned on to transmit the invalid potential of the data signal Data to the other of the source and the drain of the driving transistor T1' to reset it;

[0075] The second stage t12 repeats the first stage t11;

[0076] In the third stage t13, the first reset signal Vi is also transmitted to the gate of the driving transistor T1' to reset it, and then the second reset signal (for example, the same as the first reset signal Vi) is transmitted to one end of the light emitting element 201 to reset it. However, while resetting the third node C, the effective potential of the data signal Data is transmitted to the other of the source and the drain of the driving transistor T1', and is transmitted to the gate of the driving transistor T1' through the turned-on compensation transistor T3';

[0077] In the fourth stage t14, the fourth pulse p4 of the fourth gate signal EM controls the first light-emitting control transistor T5' and the second light-emitting control transistor T6' to be turned on to generate a current path, so that the driving current flows through the light-emitting element 201, and the magnitude of the driving current is related to the gate-source voltage of the driving transistor T1', that is, related to the effective potential of the corresponding data signal Data.

[0078] In each holding stage t2 set after the writing stage t1, only the second gate pulse p2 in the second gate signal Reset_C is used to reset one end of the light-emitting element 201 to reduce the brightness difference between the writing stage t1 and the writing stage t2, thereby improving the flicker problem under low refresh rate.

[0079] In some embodiments, in combination Figures 1 to 4 , Figure 8As shown, the second gate driving circuit 1012, the first gate driving circuit 1011, the third gate driving circuit 1013, and the fourth gate driving circuit 1014 are arranged in sequence in a direction away from the display area A. Specifically, when the gate driving circuit 10 includes the above four gate driving circuits, on the one hand, in this embodiment, considering that the pulse width of the fourth pulse p4 of the fourth gate signal EM is larger than the pulse width of the pulses of other gate signals, even if the signal attenuation affects the shape of its pulse less, the fourth gate driving circuit 1014 can be arranged farthest from the display area A to reduce the risk of distortion of other gate signals to a great extent; on the other hand, in this embodiment, considering that the third gate pulse p3 of the third gate signal Pscan needs to control the writing of the effective potential of the data signal Data and control the conduction between the first node B and the second node Q, the distance between it and the display area A cannot be too close or too far.

[0080] It should be noted that Figure 4 In order to facilitate viewing of the circuit layout of the four gate drive circuits, the original Figure 8 The four shown on the same horizontal line are moved to the same vertical line. It can be observed that since the second gate driving circuit 1012, the first gate driving circuit 1011, the third gate driving circuit 1013, and the fourth gate driving circuit 1014 are arranged in sequence in the direction away from the display area A, the fourth gate line L4 needs to extend from the fourth gate driving circuit 1014 to the display area A to pass through the third gate driving circuit 1013, the first gate driving circuit 1011, and the second gate driving circuit 1012 in sequence, and the third gate line L3 needs to extend from the third gate driving circuit 1013 to the display area A to pass through the first gate driving circuit 1011 and the second gate driving circuit 1012 in sequence, and so on. The second gate line L2 only needs to extend from the second gate driving circuit 1012 to the display area A.

[0081] Furthermore, in order to reduce the width of the non-display area B, the number of the above-mentioned clock signal lines can be reduced, for example, from the above-mentioned first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3 and the fourth clock signal line CK4 to two of them, to serve as the driving signal of each level of the gate driving unit 101.

[0082] In particular, considering that the amplitude of the fourth gate signal EM generated by the fourth gate driving circuit 1014 is related to the amplitudes of the signals transmitted by the high-voltage signal line VGH and the low-voltage signal line VGL, but has nothing to do with the amplitude of the clock signal, it is different from the amplitudes of the gate signals generated by the first gate driving circuit 1011, the second gate driving circuit 1012, and the third gate driving circuit 1013, which are related to the amplitude of the clock signal. Therefore, the attenuation degree of the clock signal has little effect on the amplitude of the fourth gate signal EM generated by the fourth gate driving circuit 1014. Therefore, the number of film layers of the metal layer contained in the part of the clock signal line electrically connected to the fourth gate driving circuit 1014 can be less than the number of film layers of the metal layer contained in the part of the clock signal line electrically connected to the other three gate driving circuits.

[0083] Specifically, the above-mentioned clock signal line (including the forward clock signal line CK and the reverse clock signal line XCK) can be divided into a first clock signal line and a second clock signal line according to the difference in the number of metal layers included therein, and the number of metal layers included in the first clock signal line is less than the number of metal layers included in the second clock signal line; wherein the first gate driving unit, the second gate driving unit and the third gate driving unit are electrically connected to the first clock signal line, and the fourth gate driving unit is electrically connected to the second clock signal line.

[0084] In some embodiments, in combination Figures 6 to 8 As shown, the first gate driving circuit 1011 also includes at least one first virtual gate driving unit (not shown) located before the first gate driving unit of the first stage and / or after the first gate driving unit of the last stage; and / or, the second gate driving circuit 1012 also includes at least one second virtual gate driving unit (not shown) located before the second gate driving unit of the first stage and / or after the second gate driving unit of the last stage; and / or, the third gate driving circuit 1013 also includes at least one third virtual gate driving unit (not shown) located before the third gate driving unit of the first stage and / or after the third gate driving unit of the last stage; and / or, the fourth gate driving circuit 1014 also includes at least one fourth virtual gate driving unit located before the fourth gate driving unit of the first stage and / or after the fourth gate driving unit of the last stage.

[0085] The circuit architecture of the first / second / third / fourth virtual gate drive unit is the same as that of the first / second / third / fourth gate drive unit, except that all the terminals in the former can be electrically connected to the high-voltage signal line VGH, so that the gate drive transistor therein is turned off to prevent the first / second / third / fourth virtual gate drive unit from working and generating a corresponding gate signal. Based on this, the first / second / third / fourth virtual gate drive unit and the corresponding first-stage or last-stage first / second / third / fourth gate drive unit can be electrically connected or disconnected.

[0086] It can be understood that in this embodiment, by setting at least one first / second / third / fourth virtual gate driving unit before the first / second / third / fourth gate driving unit of the first stage and / or after the first / second / third / fourth gate driving unit of the last stage, it is possible to avoid a sudden change in the distribution density of the multiple gate driving units 101 in the gate driving circuit 10 at the first-stage or last-stage gate driving unit, so that the distribution density of the multiple first / second / third / fourth gate driving units for outputting the first / second / third / fourth gate signals is equal everywhere, thereby reducing the impact on the first / second / third / fourth gate signals.

[0087] The above is a detailed introduction to a display device provided by an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that: The invention comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving unit comprises: A plurality of gate drive transistors, at least one of the gate drive transistors comprises an active layer, a gate layer disposed at a different layer from the active layer, and a source-drain electrode layer disposed at a different layer from both the active layer and the gate layer, the source-drain electrode layer being connected to the active layer; The active layer includes at least two active parts which are in the same layer and are spaced apart from each other, the gate layer overlaps with the corresponding at least two active parts, and the source-drain layer is connected with the corresponding at least two active parts.

2. The display device according to claim 1, characterized in that At least two of the active portions have equal widths; And / or, the active layer includes at least three active parts that are in the same layer and spaced apart from each other, and the distance between every two adjacent active parts is equal.

3. The display device according to claim 1, characterized in that At least two of the active portions in the active layer are arranged along a first direction, and the gate layer at least extends along the first direction to overlap with the corresponding at least two active portions.

4. The display device according to claim 1, characterized in that: At least two of the active parts in the active layer are arranged along a first direction, the source-drain layer extends at least along the first direction to overlap with the corresponding at least two active parts, a portion of the film layer between the source-drain layer and the active layer corresponding to the overlap of the source-drain layer and the active layer includes a via hole, and the source-drain layer is connected to the active layer through a conductive portion located in the via hole.

5. The display device according to claim 4, characterized in that: The source-drain electrode layer comprises a source electrode and a drain electrode which are arranged in the same layer and spaced apart from each other, the source electrode is connected to the first part of the corresponding active layer, the drain electrode is connected to the second part of the corresponding active layer, and the source electrode and the drain electrode both extend at least along the first direction; The first gate driving transistor and the second gate driving transistor in the plurality of gate driving transistors each include the active layer, the corresponding gate layer and the corresponding source and drain layer; Among them, one of the source and the drain of the first gate-driving transistor and one of the source and the drain of the second gate-driving transistor constitute a common part, and the common part is embedded in the other of the source and the drain of the first gate-driving transistor and the other of the source and the drain of the second gate-driving transistor.

6. The display device according to claim 5, characterized in that: It also includes a plurality of pixel circuits and a plurality of gate lines, each of the gate lines being electrically connected to a corresponding plurality of the pixel circuits; Among them, one of the source and the drain of the first gate driving transistor and one of the source and the drain of the second gate driving transistor in the gate driving unit are both electrically connected to the corresponding gate line to output a gate signal.

7. The display device according to claim 6, characterized in that: The pixel circuit comprises: Light emitting element; A driving transistor, wherein one of a source and a drain of the driving transistor is electrically connected to the light emitting element; a first reset transistor electrically connected to the gate of the driving transistor, and configured to transmit a first reset signal to the gate of the driving transistor in response to a first gate signal; a second reset transistor, electrically connected to one end of the light emitting element, for transmitting a second reset signal to one end of the light emitting element in response to a second gate signal; The display device comprises at least two gate driving circuits, wherein the at least two gate driving circuits comprise a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit comprises a plurality of first gate driving units for generating a plurality of the first gate signals and being cascaded, and the second gate driving circuit comprises a plurality of second gate driving units for generating a plurality of the second gate signals and being cascaded; The first gate signal is used to control the first reset transistor to be turned on in a writing phase to transmit the first reset signal to the gate of the driving transistor, and is used to control the first reset transistor to be turned off in a holding phase corresponding to the writing phase; The second gate signal is used to control the second reset transistor to be turned on during the writing phase and the holding phase corresponding to the writing phase, so as to transmit the second reset signal to one end of the light emitting element.

8. The display device according to claim 7, characterized in that: The first gate signal comprises at least two first gate pulses in the writing phase, and each of the first gate pulses is used to control the first reset transistor to be turned on; The second gate signal includes at least two second gate pulses in each of the writing phase and a corresponding holding phase after the writing phase, and each second gate pulse is used to control the second reset transistor to be turned on.

9. The display device according to claim 7, characterized in that: The pixel circuit further comprises: a compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor, and configured to form a current path between one of the source and the drain of the driving transistor and the gate of the driving transistor in response to a third gate signal; a light emitting control transistor, electrically connected to the other of the source and the drain of the driving transistor, and configured to transmit the first voltage signal to the other of the source and the drain of the driving transistor in response to a fourth gate signal; Wherein, at least two of the gate driving circuits further include a third gate driving circuit and a fourth gate driving circuit, the third gate driving circuit includes a plurality of third gate driving units for generating a plurality of the third gate signals and being cascaded, and the fourth gate driving circuit includes a plurality of fourth gate driving units for generating a plurality of the fourth gate signals and being cascaded; The third gate signal is used to control the compensation transistor to be turned on in the writing phase so as to form a current path between one of the source and the drain of the driving transistor and the gate of the driving transistor, and is used to control the compensation transistor to be turned off in the holding phase corresponding to the writing phase; The fourth gate signal is used to control the light emission control transistor to be turned on during the writing phase and the holding phase corresponding to the writing phase.

10. The display device according to claim 9, characterized in that: The display device comprises a display area and a non-display area located at least on one side of the display area, a plurality of the pixel circuits are located in the display area, and a plurality of the gate driving circuits are located in the non-display area; The second gate driving circuit, the first gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit are arranged in sequence in a direction away from the display area.

11. The display device according to claim 9, characterized in that: The first gate driving circuit further includes at least one first virtual gate driving unit located before the first gate driving unit of the first stage and / or after the first gate driving unit of the last stage; And / or, the second gate driving circuit further includes at least one second virtual gate driving unit located before the second gate driving unit of the first stage and / or after the second gate driving unit of the last stage; And / or, the third gate driving circuit further includes at least one third virtual gate driving unit located before the third gate driving unit of the first stage and / or after the third gate driving unit of the last stage; And / or, the fourth gate driving circuit further includes at least one fourth virtual gate driving unit located before the fourth gate driving unit of the first stage and / or after the fourth gate driving unit of the last stage.

12. The display device according to claim 9, characterized in that: Also comprising a first clock signal line and a second clock signal line for transmitting a clock signal, wherein the number of metal layers included in the first clock signal line is less than the number of metal layers included in the second clock signal line; The first gate driving unit, the second gate driving unit and the third gate driving unit are electrically connected to the first clock signal line, and the fourth gate driving unit is electrically connected to the second clock signal line.

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