Pixel circuit and driving method thereof, display panel, controller and display device

Abstract

The invention discloses a pixel circuit and a driving method thereof, a display panel, a controller and a display device, and relates to the technical field of driving display, the pixel circuit comprises a signal write-in sub-circuit, a first driving sub-circuit, a second driving sub-circuit and a third driving sub-circuit, the signal write-in sub-circuit is electrically connected with the second driving sub-circuit through a first node; the first end of the third driving sub-circuit is electrically connected with the fourth node, and the second end of the third driving sub-circuit is used for receiving a first reference voltage signal; the first driving sub-circuit comprises a double-gate transistor, a first gate of the double-gate transistor is electrically connected with the fourth node, and a second gate of the double-gate transistor is used for receiving a second reference voltage signal. The light-emitting time of the light-emitting sub-circuit can be controlled by utilizing the double-gate characteristic of the double-gate transistor and controlling the on-off time of the double-gate transistor. The problem of serious color cast of a display product caused by too low current density is effectively solved, and the display effect optimization is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of driving display technology, and more specifically, to a pixel circuit, a display panel, a driving method of a pixel circuit, a controller, and a display device. Background Art

[0002] When driven by currents of different magnitudes, the peak wavelength of OLED (Organic Light Emitting Diode) shows a U-shaped change, and this phenomenon also exists in most LEDs (Light Emitting Diode). At the same time, under the same environmental conditions, the smaller the current density flowing through the OLED, the greater the wavelength shift, which may lead to aggravated color shift in electronic display products made of OLED, affecting the display effect.

[0003] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this disclosure does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present disclosure provides a pixel circuit, comprising:

[0006] A signal writing subcircuit, a first driving subcircuit, a second driving subcircuit and a third driving subcircuit, wherein:

[0007] The signal writing subcircuit is electrically connected to the second driving subcircuit via the first node, and the signal writing subcircuit is used to receive a display signal, wherein the display signal includes a data signal;

[0008] A first end of the third driving sub-circuit is electrically connected to the fourth node, and a second end of the third driving sub-circuit is used to receive a first reference voltage signal;

[0009] The first driving subcircuit is electrically connected to the second driving subcircuit via the second node, wherein the first driving subcircuit includes a dual-gate transistor, a first gate of the dual-gate transistor is electrically connected to the fourth node, the second gate of the dual-gate transistor is used to receive a second reference voltage signal, a first electrode of the dual-gate transistor is used to receive a first power supply signal, and the second electrode of the dual-gate transistor is used to be electrically connected to the second node, wherein the first electrode is one of the source and the drain of the dual-gate transistor, and the second electrode is the other of the source and the drain of the dual-gate transistor.

[0010] In some embodiments, after the data signal is written to the first node and when the second driving subcircuit is turned on, under the action of the first reference voltage signal and the second reference voltage signal, the threshold voltage of the dual-gate transistor increases over time, and the dual-gate transistor is turned on when the threshold voltage of the dual-gate transistor is greater than a first voltage difference, wherein the first voltage difference is the voltage difference between the first electrode and the first gate of the dual-gate transistor.

[0011] In some embodiments, the voltage difference between the first electrode and the second gate of the dual-gate transistor is a second voltage difference. After the data signal is written to the first node and the second driving sub-circuit is turned on, the rate at which the second reference voltage signal decreases over time is a first rate. The second reference voltage signal is used to control the second voltage difference to decrease at the first rate. The rate at which the threshold voltage of the dual-gate transistor increases over time is a second rate, and the first rate is positively correlated with the second rate.

[0012] In some implementations, the first reference voltage signal is used to control the first voltage difference to be constant.

[0013] In some embodiments, within the same frame, the duration that the first voltage difference is greater than the threshold voltage of the dual-gate transistor is a first duration, the duration that the first voltage difference is less than the threshold voltage of the dual-gate transistor is a second duration, and the second duration is greater than the first duration.

[0014] In some embodiments, it further comprises:

[0015] a reset subcircuit, comprising a first transistor, a gate of the first transistor being used to receive a third scanning signal, a first electrode of the first transistor being electrically connected to the second driving subcircuit via a third node, and a second electrode of the first transistor being used to receive a second power supply signal;

[0016] The signal writing subcircuit is used to be turned on or off under the action of the first scanning signal;

[0017] After the data signal is written into the first node, an effective level end point of the first scanning signal is before an effective level end point of the third scanning signal.

[0018] In some embodiments, the third driving subcircuit includes: a second transistor and a first capacitor, the gate of the second transistor is used to receive a second scanning signal, the first electrode of the second transistor is electrically connected to the second end of the third driving subcircuit, the second electrode of the second transistor is electrically connected to the first end of the third driving subcircuit, one end of the first capacitor is electrically connected to the fourth node, the other end of the first capacitor is grounded, and the second transistor is used to be turned on or off under the action of the second scanning signal.

[0019] In some embodiments, the second driving subcircuit includes a third transistor and a second capacitor, wherein one end of the second capacitor is electrically connected to the gate of the third transistor, the other end of the second capacitor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0020] In some embodiments, the display signal further includes an initial signal, and when the signal writing subcircuit is turned on and the initial signal is written into the first node, the second reference voltage signal is a low level signal;

[0021] At the effective level end point of the first scanning signal and the second scanning signal, the second reference voltage signal is transformed from a low level signal to a high level signal;

[0022] After the data signal is written into the first node and the second driving sub-circuit is turned on, the second reference voltage signal decreases from a high level signal to a low level signal at a first rate over time.

[0023] In a second aspect, a display panel is also proposed, comprising: the pixel circuit as described above.

[0024] In a third aspect, a driving method of a pixel circuit is also proposed, which is used to drive the pixel circuit as described above, and the driving method includes:

[0025] The control signal writing subcircuit is turned on to write a data signal to the first node;

[0026] Controlling the second driving sub-circuit and the third driving sub-circuit to be turned on;

[0027] Based on the first reference voltage signal and the second reference voltage signal, the on-time of the dual-gate transistor is controlled.

[0028] In some implementations, controlling the on-time of the dual-gate transistor based on the first reference voltage signal and the second reference voltage signal includes:

[0029] Based on the first reference voltage signal and the second reference voltage signal, the threshold voltage of the dual-gate transistor is controlled to increase over time, and the dual-gate transistor is turned on when the threshold voltage of the dual-gate transistor is greater than a first voltage difference, wherein the first voltage difference is the voltage difference between the first electrode and the first gate of the dual-gate transistor.

[0030] In some embodiments, a rate at which the second reference voltage signal decreases over time is a first rate, a rate at which the threshold voltage of the dual-gate transistor increases over time is a second rate, and the first rate is positively correlated with the second rate.

[0031] In some embodiments, the method further comprises:

[0032] The value of the first rate is adjusted to control the ratio of the on time to the off time of the first driving sub-circuit.

[0033] In some embodiments, after the data signal is written to the first node and the second driving sub-circuit is turned on, the third transistor in the second driving sub-circuit is in a saturation region of the output characteristic curve.

[0034] In some embodiments, the display signal further includes an initial signal, and when the signal writing subcircuit is turned on and the initial signal is written into the first node, the second reference voltage signal is a low level signal;

[0035] At the effective level end point of the first scanning signal and the second scanning signal, the second reference voltage signal is transformed from a low level signal to a high level signal;

[0036] After the data signal is written into the first node and the second driving sub-circuit is turned on, the second reference voltage signal decreases from a high level signal to a low level signal at a first rate over time.

[0037] In some embodiments, before the control signal writing subcircuit is turned on to write the data signal to the first node, the method further includes:

[0038] Convert the original signal into a data signal.

[0039] In some embodiments, after the data signal is written into the first node, an effective level end point of the first scanning signal is before an effective level end point of the third scanning signal.

[0040] In a fourth aspect, a controller is also proposed, comprising:

[0041] a memory storing a computer program;

[0042] The processor is used to call the computer program in the memory, and the computer program is used to execute the driving method as described above.

[0043] In a fifth aspect, a display device is also proposed, comprising the display panel as described above and / or the controller as described above.

[0044] The disclosed embodiment can utilize the dual-gate characteristics of the dual-gate transistor, and in the light-emitting stage of the light-emitting sub-circuit, by controlling the on and off time of the third driving sub-circuit, the dual-gate transistor can adjust the on and off time under the action of the second reference voltage signal when the first reference voltage signal is written, thereby realizing the control of the light-emitting time of the light-emitting sub-circuit. In addition, the serious color shift problem of related electronic display products caused by too low current density can be effectively solved, the display effect optimization is improved, and the visual experience of consumers is improved.

[0045] The pixel circuit of the present disclosure and other advantages, objectives and features of the present disclosure will be reflected in part through the following description, and will also be understood by those skilled in the art through research and practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0048] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0049] Figure 1 A schematic block diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0050] Figure 2 A timing diagram of a driving circuit provided in an embodiment of the present disclosure;

[0051] Figure 3 A dynamic linear diagram showing the change of the threshold voltage of the dual-gate transistor according to the embodiment of the present disclosure as a function of the second voltage difference;

[0052] Figure 4 A schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0053] Figure 5 Another driving circuit timing diagram provided by an embodiment of the present disclosure;

[0054] Figure 6 A schematic flow chart of a driving method provided in an embodiment of the present disclosure;

[0055] Figure 7 A schematic structural block diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0057] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments.

[0058] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0059] In order to solve the above technical problem, according to a first aspect of the present disclosure, a pixel circuit is proposed. Figure 1 Schematic block diagram of a pixel circuit provided by an embodiment of the present disclosure. Figure 1As shown, the pixel circuit may include: a signal writing subcircuit 110, a first driving subcircuit 120, a second driving subcircuit 130 and a third driving subcircuit 150, wherein the signal writing subcircuit 110 is electrically connected to the second driving subcircuit 130 via a first node N1, and the signal writing subcircuit 110 is used to receive a display signal Pixel data. A first end of the third driving subcircuit 150 is electrically connected to a fourth node N4, and a second end of the third driving subcircuit 150 is used to receive a first reference voltage signal PWM data. The first driving subcircuit 120 is electrically connected to the second driving subcircuit 130 via a second node N2. The first driving subcircuit 120 includes a dual-gate transistor M1, a first gate G of the dual-gate transistor M1 is electrically connected to the fourth node N4, a second gate B of the dual-gate transistor M1 is used to receive a second reference voltage signal SWEEP, a first electrode S of the dual-gate transistor M1 is used to receive a first power supply signal ELVDD, and a second electrode D of the dual-gate transistor M1 is used to be electrically connected to a second node N2.

[0060] For example, see Figure 1 , the first gate of the dual-gate transistor M1 is a positive gate G, the second gate is a back gate B, the first electrode is a source S, and the second electrode is a drain D. It should be noted that, Figure 1 The arrangement of the electrodes of the dual-gate transistor M1 in the illustrated embodiment is merely exemplary and is not intended to be a specific limitation of the present disclosure. The first electrode may be one of the source and drain of the dual-gate transistor M1, and the second electrode may be the other of the source and drain of the dual-gate transistor M1; the first gate may be one of the positive gate and the back gate of the dual-gate transistor M1, and the second gate may be the other of the positive gate and the back gate of the dual-gate transistor M1. When the third driving subcircuit 150 is turned on, the first reference voltage signal PWM data may be written to the fourth node N4, that is, the first reference voltage signal PWM data may be written to the first gate G of the dual-gate transistor M1. Under the action of the first reference voltage signal PWM data and the second reference voltage signal SWEEP, the dual-gate transistor M1 may be turned on, and the first power supply signal ELVDD may be written to the second node N2. Exemplarily, the display signal Pixel data may include a data signal, and the data signal may drive the pixel to emit light of corresponding intensity. When the signal writing subcircuit 110 is turned on, the data signal may be written to the first node N1. Exemplarily, the pixel circuit may further include a light emitting subcircuit, which may be electrically connected to the second driving subcircuit 130. The second driving subcircuit 130 may be turned on under the action of the data signal and the first power signal ELVDD, and supply power to the light emitting subcircuit.

[0061] See also Figure 1It should be noted that the magnitude relationship between the voltage difference between the first gate G and the first electrode S of the dual-gate transistor M1 and the threshold voltage determines whether the dual-gate transistor M1 can be turned on. Whether the first reference voltage signal PWM data can be written to the first gate G depends on whether the third driving sub-circuit 150 is turned on. According to the characteristics of the dual-gate transistor, the threshold voltage of the dual-gate transistor M1 is related to the voltage difference between the second gate B and the first electrode S. Therefore, by changing the second reference voltage signal SWEEP, the threshold voltage of the dual-gate transistor M1 can be adjusted. Therefore, when the data signal is written to the first node and the second driving sub-circuit is turned on, it can be determined whether the light-emitting sub-circuit emits light and how long it emits light by controlling the turn-on time of the third driving sub-circuit and adjusting the second reference voltage signal.

[0062] The disclosed embodiment can utilize the dual-gate characteristics of the dual-gate transistor, and in the light-emitting stage of the light-emitting sub-circuit, by controlling the on and off time of the third driving sub-circuit, the dual-gate transistor can adjust the on and off time under the action of the second reference voltage signal when the first reference voltage signal is written, thereby realizing the control of the light-emitting time of the light-emitting sub-circuit. In addition, the serious color shift problem of related electronic display products caused by too low current density can be effectively solved, the display effect optimization is improved, and the visual experience of consumers is improved.

[0063] For example, see Figure 1 After the data signal is written into the first node N1, and when the second driving subcircuit 130 is turned on, if the first driving subcircuit 120 is also in the on state, the light-emitting subcircuit electrically connected to the second driving subcircuit 130 can emit light under the action of the data signal and by the power supply of the first power signal ELVDD. Exemplarily, by controlling the on and off time of the first driving subcircuit 120, the light-emitting time of the light-emitting subcircuit can be controlled.

[0064] Figure 2 A timing diagram of a driving circuit provided in an embodiment of the present disclosure. For example, see Figure 1 and Figure 2, the dual-gate transistor M1 in the first driving sub-circuit 120 can be turned on under the joint action of the first reference voltage signal PWM data and the second reference voltage signal SWEEP. Among them, the first electrode of the dual-gate transistor M1 is used to receive the first power supply signal ELVDD, and the third driving sub-circuit 150 is in a conducting state. When ELVDD is constant, the first reference voltage signal PWM data can be input to the first gate of the dual-gate transistor M1. The difference between the first reference voltage signal PWM data and the first power supply signal ELVDD is the first voltage difference Vgs1. According to the working principle of the dual-gate transistor, when the threshold voltage Vth1 of the dual-gate transistor M1 is greater than the first voltage difference Vgs1, the dual-gate transistor M1 can be turned on. Exemplarily, the threshold voltage Vth1 of the dual-gate transistor M1 can change with the change of the voltage difference between the first electrode and the second gate, wherein the voltage difference between the first electrode and the second gate is referred to as the second voltage difference. See. Figure 1 The second voltage difference may be a difference between the second reference voltage signal SWEEP and the first power signal ELVDD, expressed as Vbs.

[0065] Figure 3 A dynamic linear diagram of the threshold voltage of the dual-gate transistor according to the embodiment of the present disclosure as the second voltage difference changes. For example, when the first power signal ELVDD is fixed, see Figure 2 When the second reference voltage signal SWEEP decreases from the second reference value Vref2 to the first reference value Vref1 over time, the second voltage difference Vbs also decreases accordingly. Figure 3 , when the second voltage difference Vbs decreases, the threshold voltage Vth1 of the dual-gate transistor M1 increases accordingly. Figure 2 When the threshold voltage Vth1 of the dual-gate transistor M1 increases to be greater than the first voltage difference Vgs1, that is, after reaching point a, the dual-gate transistor M1 can be turned on. That is, after point a, the light-emitting subcircuit can continue to emit light, while before point a, the light-emitting subcircuit remains off.

[0066] Therefore, under the action of the first reference voltage signal and the second reference voltage signal, the light-emitting time of the light-emitting sub-circuit is controlled by controlling the on and off time of the dual-gate transistor.

[0067] In some embodiments, see Figure 2 , after the data signal Vdata is written into the first node N1 and the second driving sub-circuit 130 is turned on, the rate at which the second reference voltage signal SWEEP decreases over time is the first rate, that is, the ratio of the time required for the second reference voltage signal SWEEP to decrease from the second reference value Vref2 to the first reference value Vref1. Figure 2The slope of the second reference voltage signal SWEEP reflects the numerical value of the first rate. An increase in the absolute value of the slope indicates an increase in the first rate, and conversely, a decrease in the absolute value of the slope indicates a decrease in the first rate. Under the action of the second reference voltage signal SWEEP, the second voltage difference Vbs also decreases at the first rate. The rate at which the threshold voltage Vth1 of the dual-gate transistor increases over time is the second rate, that is, the ratio of the threshold voltage Vth1 from A to B to the time required. Figure 3 Since the threshold voltage Vth1 of the dual-gate transistor is inversely correlated with the second voltage difference Vbs, the first rate is positively correlated with the second rate. For example, the second rate can be regulated by adjusting the value of the first rate. Figure 2 , by adjusting the slope of the second reference voltage signal SWEEP, the slope of the threshold voltage Vth1 can be adjusted. After the slope of the threshold voltage Vth1 changes, the position of point a can be translated on the first voltage difference Vgs1. When point a moves to the left, the threshold voltage Vth1 is greater than the first voltage difference Vgs1 at an earlier time, so the light-emitting time of the light-emitting sub-circuit becomes longer. Conversely, when point a moves to the right, the threshold voltage Vth1 is greater than the first voltage difference Vgs1 at a later time, so the light-emitting time of the light-emitting sub-circuit becomes shorter.

[0068] Therefore, the light-emitting time of the light-emitting sub-circuit can be indirectly controlled by adjusting the first rate, thereby achieving a PWM (Pulse width modulation) effect.

[0069] In some embodiments, within the same frame, the duration that the first voltage difference is greater than the threshold voltage of the dual-gate transistor is a first duration, and the duration that the first voltage difference is less than the threshold voltage of the dual-gate transistor is a second duration, and the second duration is greater than the first duration. Figure 2 The first duration can be represented by the length of Vgs1 before point a, and the second duration can be represented by the length of Vgs1 after point a. When the second duration is greater than the first duration, it can indicate that the light-emitting time of the light-emitting sub-circuit is greater than the off time, thereby ensuring the effective light-emitting time and achieving improved display effect.

[0070] In some embodiments, the first reference voltage signal is used to control the first voltage difference to be constant. Exemplarily, the difference between the first reference voltage signal and the first power supply signal is the first voltage difference. Exemplarily, the first reference voltage signal can be regarded as a power supply signal. When the first reference voltage signal and the first power supply signal are both constant, the obtained first voltage difference is constant, that is, the first voltage difference is in a stable state. After the threshold voltage of the dual-gate transistor is regulated by the above scheme, based on the comparison result of the first voltage difference and the threshold voltage, accurate control of whether the dual-gate transistor is turned on or not can be achieved, providing reliable guarantee for the subsequent regulation of the light-emitting time.

[0071] Figure 4 A schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. For example, see Figure 4 , the second driving subcircuit 130 may include a third transistor M4 and a second capacitor C2. Among them, one end of the second capacitor C2 is electrically connected to the gate of the third transistor M4, the other end of the second capacitor C2 is electrically connected to the second node N2, the first electrode of the third transistor M4 is electrically connected to the second node N2, and the second electrode of the third transistor M4 is electrically connected to the third node N3. The fifth node N5 and the second node N2 are equivalent circuit points. The signal writing subcircuit 110 may include a fourth transistor M5. The fourth transistor M5 is used to turn on or off under the action of the first scan signal SCAN1. The pixel circuit may also include: a reset subcircuit 140, including a first transistor M2, the gate of the first transistor M2 is used to receive the third scan signal SCAN3, that is, the first transistor M2 is turned on or off under the action of the third scan signal SCAN3. The first electrode of the first transistor M2 is electrically connected to the second driving subcircuit 130 via the third node N3, and the second electrode of the first transistor M2 is used to receive the second power supply signal VSS. The third driving sub-circuit 150 may include a second transistor M3 and a first capacitor C1. The gate of the second transistor M3 is used to receive the second scan signal SCAN2, that is, the second transistor M3 is turned on or off under the action of the second scan signal SCAN2. The first electrode of the second transistor may be electrically connected to the second end of the third driving sub-circuit. Figure 4 In the illustrated embodiment, the first electrode of the second transistor M3 serves as the second terminal of the third driving sub-circuit 150, for receiving the first reference voltage signal PWM data. The second electrode of the second transistor can be electrically connected to the first terminal of the third driving sub-circuit. Figure 4 In the illustrated embodiment, the second electrode of the second transistor M3 serves as the first terminal of the third driving sub-circuit 150 and is electrically connected to the fourth node N4. Figure 4 , the second electrode of the second transistor M3 is electrically connected to the first gate of the dual-gate transistor M1 via the fourth node N4, one end of the first capacitor C1 is electrically connected to the fourth node N4, and the other end of the first capacitor C1 is grounded. Exemplarily, the first transistor M2 can be an N-type transistor, and the second transistor M3, the third transistor M4 and the fourth transistor M5 can be P-type. For an N-type transistor, it can be turned on when the driving signal of its gate is a high-level signal, that is, the effective level is a high level. For a P-type transistor, it can be turned on when the driving signal of its gate is a low-level signal, that is, the effective level is a low level. Exemplarily, the light-emitting sub-circuit electrically connected to the third node N3 can be Figure 4The OLED shown, the corresponding display panel is an active light emitting display panel. Exemplarily, the third node N3 can also be connected to a pixel electrode, and the display panel can be a liquid crystal display panel.

[0072] Figure 5 Another driving circuit timing diagram provided by the embodiment of the present disclosure. Figure 5 The timing shown is Figure 4 The pixel circuit shown is driven, and the driving method is as follows:

[0073] For example, the driving sequence can be divided into Figure 5 The four stages shown are ① initialization stage, ② self-discharge stage, ③ data writing and threshold voltage compensation stage, and ④ light emitting stage. Figure 5 , in the initialization stage ①, the first scan signal SCAN1 and the second scan signal SCAN2 are at a low level, and the third scan signal SCAN3 is at a high level. At this time, the first transistor, the second transistor and the fourth transistor are turned on. When the fourth transistor is turned on, the display signal can be written to the first node N1. In the initialization stage, the display signal is the initial signal Vinit. After the signal writing subcircuit is turned on and the initial signal Vinit is written to the first node N1, the second reference voltage signal SWEEP is a low level signal, SWEEP = Vref1. When the second transistor is turned on, the first reference voltage signal PWM data is written to the fourth node, PWM data = Vref3, and the first capacitor C1 can store Vref3, so that when the second transistor is turned off, the voltage of the fourth node, i.e., the first gate of the dual-gate transistor, can be stabilized at a certain value. In this case, it can be determined that the signal waveform of the second voltage difference Vbs is substantially the same as the second reference voltage signal SWEEP, and then according to the inverse relationship between the second voltage difference Vbs and the threshold voltage Vth1 of the dual-gate transistor, it can be determined Figure 5 The waveform of Vth1 in the initialization stage. At this time, Vth1 is greater than the first voltage difference Vgs1, and the dual-gate transistor is turned on. Figure 4 , after the dual-gate transistor is turned on, the voltages of the second node N2 and the fifth node N5 are both equal to the first power signal ELVDD. When the fourth transistor is turned on, the gate voltage of the third transistor is equal to the written initial signal Vinit, and the gate-source voltage difference Vgs2 of the third transistor is less than the threshold voltage Vth2, so the third transistor is turned on. Figure 4 When the first transistor is turned on, the voltage of the third node N3 = the anode voltage of the OLED = the second power signal VSS, the cathode voltage of the OLED = ELVSS, ELVSS is greater than or equal to VSS, so the OLED is in an off state.

[0074] See also Figure 5In the self-discharge stage ②, the states of the first scan signal SCAN1 and the second scan signal SCAN2 change from low level to high level, and the second transistor and the fourth transistor are turned off. At this time, at the effective level end point of the first scan signal SCAN1 and the second scan signal SCAN2, that is, at the moment of changing from low level to high level, the second reference voltage signal SWEEP changes from the low level signal Vref1 to the high level signal Vref2, the second voltage difference Vbs increases, and the threshold voltage Vth1 of the dual-gate transistor decreases. Vth1<the first voltage difference Vgs1, and the dual-gate transistor is turned off. The third scan signal SCAN3 maintains a high level signal unchanged, so the first transistor is still in the on state, and the OLED is still in the off state. See Figure 4 , since the second capacitor has the function of storing energy for the initial signal, the gate of the third transistor still maintains the initial signal Vinit. Similarly, the capacitor C3 can also store energy for the first power supply signal, so that the fifth node and the second node are both maintained at ELVDD. The gate-source voltage difference Vgs2 of the third transistor is less than the threshold voltage Vth2, and the third transistor remains on. However, with the effect of the substrate bias effect, the gate-source voltage difference Vgs2 of the third transistor will gradually reach the threshold voltage Vth2, causing the third transistor to switch from the on state to the off state.

[0075] See also Figure 5 , in the data writing and threshold voltage compensation stage ③, the state of the first scan signal SCAN1 changes again, from a high level to a low level, the fourth transistor is turned on, and the display signal can be written to the first node N1, and the display signal is the data signal Vdata at this time. Exemplarily, before the fourth transistor is turned on to write the data signal Vdata to the first node, the initial signal Vinit can be converted into the data signal Vdata. The data signal prepared in advance is written at the first time when the state of the first scan signal SCAN1 changes again, ensuring the timely writing of the data signal and improving the display efficiency. For multiple pixel circuits, there are differences in the threshold voltage of the third transistor, which may cause the luminous brightness of the luminous sub-circuit in each pixel circuit to be different. Since the second capacitor has an energy storage function, the threshold voltage of the corresponding third transistor can be compensated by the second capacitor in each pixel circuit to make up for the difference in luminous brightness and ensure the display effect. After the data signal Vdata is written to the first node N1, the effective level end point of the first scan signal SCAN1 is before the effective level end point of the third scan signal SCAN3. That is, the first scan signal SCAN1 changes state again in the third stage, from low level to high level, while the state of the third scan signal SCAN3 remains unchanged. At this time, the first transistor is still in the on state, so that the OLED is still in the off state.

[0076] See also Figure 5, in the ④ light-emitting stage, the first scan signal SCAN1 remains at a high level, and the fourth transistor remains off. However, according to the aforementioned stage ③, the data signal Vdata has been written to the first node N1 and is maintained by the second capacitor C2. The state of the third scan signal SCAN3 changes from a high level to a low level, and the first transistor is turned off. At this time, the gate-source voltage difference of the third transistor is less than its own threshold voltage, the third transistor is turned on, and is in the saturation region of the output characteristic curve, and the driving current is constant. The first gate voltage of the dual-gate transistor is equal to the fourth node voltage, that is, the first voltage difference Vgs1 of the dual-gate transistor remains unchanged. At this time, the second reference voltage signal SWEEP decreases from the high-level signal Vref2 to the low-level signal Vref1 at a first rate over time, which is equivalent to the second gate voltage of the dual-gate transistor decreasing from Vref2 to Vref1, and the second voltage difference Vbs gradually decreases. According to the threshold dynamic characteristics of the dual-gate transistor described above, the threshold voltage Vth1 of the dual-gate transistor gradually increases. Therefore, in the fourth light-emitting stage, when the first voltage difference Vgs1 of the dual-gate transistor is greater than the threshold voltage Vth1, the dual-gate transistor is cut off and the OLED is in an extinguished state (emission off). When the first voltage difference Vgs1 of the dual-gate transistor is less than the threshold voltage Vth1, the dual-gate transistor is turned on and the OLED is in an emitting state (emission on). In the light-emitting stage, by changing the value of the first rate, that is, changing the slope of the second reference voltage SWEEP, the slope of the threshold voltage Vth1 can be changed, and the effective light-emitting time of the OLED can be indirectly controlled to achieve the effect of PWM modulation.

[0077] According to the second aspect of the present disclosure, a display panel is also provided. The display panel may include a plurality of pixel circuits as described above. Exemplarily, the light emitting subcircuit electrically connected to the third node N3 may be Figure 4 The OLED shown, the corresponding display panel is an active light emitting display panel. Exemplarily, the third node N3 can also be connected to a pixel electrode, and the display panel can be a liquid crystal display panel.

[0078] According to a third aspect of the present disclosure, a method for driving a pixel circuit is also proposed, which is used to drive the pixel circuit as described above. Figure 6 A schematic flow chart of a driving method provided by an embodiment of the present disclosure. Figure 6 , the method may include the following steps:

[0079] Step S610 , the control signal writing sub-circuit is turned on to write a data signal to the first node.

[0080] For example, see Figure 4 and Figure 5When the first scan signal SCAN1 is at a low level, the signal writing sub-circuit 110 is turned on. When the signal writing sub-circuit 110 is turned on, the data signal Vdata can be written to the first node N1.

[0081] Step S620, controlling the second driving sub-circuit and the third driving sub-circuit to be turned on.

[0082] For example, see Figure 4 and Figure 5 , when the signal writing subcircuit 110 is turned on, the gate voltage of the third transistor M4 of the second driving subcircuit 130 is equal to the written data signal Vdata, the gate-source voltage difference of the third transistor M4 is less than its own threshold voltage, the third transistor M4 is turned on, and is in the saturation region of the output characteristic curve, the driving current is constant, that is, the second driving subcircuit 130 is turned on. Figure 4 and Figure 5 The gate of the second transistor M3 of the third driving sub-circuit 150 is used to receive the second scanning signal SCAN2. In the light-emitting stage, the second scanning signal SCAN2 is at a high level, the second transistor M3 is turned on, that is, the third driving sub-circuit 150 is turned on.

[0083] Step S630 , controlling the on-time of the dual-gate transistor based on the first reference voltage signal and the second reference voltage signal.

[0084] Exemplarily, when the third driving subcircuit is turned on, a first reference voltage signal can be written to the first gate of the dual-gate transistor. The magnitude relationship between the voltage difference between the first gate and the first electrode of the dual-gate transistor and the threshold voltage determines whether the dual-gate transistor can be turned on. According to the characteristics of the dual-gate transistor, the threshold voltage of the dual-gate transistor is related to the voltage difference between the second gate and the first electrode. Therefore, by changing the second reference voltage signal, the threshold voltage of the dual-gate transistor can be adjusted, and then the turn-on time of the dual-gate transistor can be controlled.

[0085] In some implementations, controlling the on-time of the dual-gate transistor based on the first reference voltage signal and the second reference voltage signal includes:

[0086] Based on the first reference voltage signal and the second reference voltage signal, the threshold voltage of the dual-gate transistor is controlled to increase over time, and the dual-gate transistor is turned on when the threshold voltage of the dual-gate transistor is greater than a first voltage difference, wherein the first voltage difference is the voltage difference between the first electrode and the first gate of the dual-gate transistor.

[0087] For example, see Figure 4 and Figure 5, the dual-gate transistor M1 can be turned on under the combined action of the first reference voltage signal PWM data and the second reference voltage signal SWEEP. Among them, the first electrode of the dual-gate transistor M1 is used to receive the first power supply signal ELVDD, and the first reference voltage signal PWM data can be input to the first gate of the dual-gate transistor M1. According to the working principle of the dual-gate transistor M1, when the threshold voltage Vth1 of the dual-gate transistor M1 is greater than the first voltage difference Vgs1 between the first reference voltage signal PWM data and the first power supply signal ELVDD, the dual-gate transistor M1 can be turned on. Exemplarily, the threshold voltage Vth1 of the dual-gate transistor M1 can change with the change of the second voltage difference Vbs between the first electrode and the second gate. When the second reference voltage signal SWEEP changes with time from the high-level signal Vref2 to the low-level signal Vref1, the second voltage difference Vbs also decreases accordingly. When the second voltage difference Vbs decreases, the threshold voltage Vth1 of the dual-gate transistor M1 increases accordingly. When the threshold voltage Vth1 of the dual-gate transistor M1 increases to be greater than the first voltage difference Vgs1, the dual-gate transistor M1 can be turned on.

[0088] In some embodiments, a rate at which the second reference voltage signal decreases over time is a first rate, a rate at which the threshold voltage of the dual-gate transistor increases over time is a second rate, and the first rate is positively correlated with the second rate.

[0089] For example, see Figure 4 and Figure 5 , after the data signal Vdata is written into the first node N1 and the second driving sub-circuit 130 is turned on, the rate at which the second reference voltage signal SWEEP decreases over time is the first rate, that is, the ratio of the time required for the second reference voltage signal SWEEP to decrease from the high level signal Vref2 to the low level signal Vref1. Under the action of the second reference voltage signal SWEEP, the second voltage difference Vbs also decreases at the first rate. The rate at which the threshold voltage Vth1 of the dual-gate transistor increases over time is the second rate. Since the threshold voltage Vth1 of the dual-gate transistor M1 is inversely correlated with the second voltage difference Vbs, the first rate is positively correlated with the second rate.

[0090] In some implementations, the method further includes: adjusting a numerical value of the first rate to control a ratio of an on-time to an off-time of the first driving subcircuit.

[0091] For example, see Figure 5, the second rate can be regulated by adjusting the value of the first rate. By adjusting the slope of the second reference voltage signal SWEEP, the slope of the threshold voltage Vth1 can be adjusted, so that the threshold voltage Vth1 is greater than the first voltage difference Vgs1 at an earlier or later time, so that the conduction time of the first driving sub-circuit 120 becomes longer or shorter, and the light-emitting time of the light-emitting sub-circuit is regulated.

[0092] In some embodiments, the display signal further includes an initial signal, and after the signal writing subcircuit is turned on and the initial signal is written to the first node, the second reference voltage signal is a low level signal. At the effective level end point of the first scanning signal and the second scanning signal, the second reference voltage signal is transformed from a low level signal to a high level signal; after the data signal is written to the first node and the second driving subcircuit is turned on, the second reference voltage signal decreases from a high level signal to a low level signal at a first rate over time.

[0093] For example, see Figure 5 , the first scan signal SCAN1 and the second scan signal SCAN2 are at a low level, and the third scan signal SCAN3 is at a high level. At this time, the first transistor M2, the second transistor M3 and the fourth transistor M5 are turned on. When the fourth transistor M5 is turned on, a display signal can be written to the first node N1. In the initialization stage, the display signal is the initial signal Vinit. After the signal writing subcircuit 110 is turned on and the initial signal Vinit is written into the first node N1, the second reference voltage signal SWEEP is a low level signal Vref1.

[0094] See also Figure 5 , the states of the first scanning signal SCAN1 and the second scanning signal SCAN2 change from low level to high level, and the second transistor M3 and the fourth transistor M5 are turned off. At this time, at the effective level end point of the first scanning signal SCAN1 and the second scanning signal SCAN2, that is, at the moment of changing from low level to high level, the second reference voltage signal SWEEP is changed from the low level signal Vref1 to the high level signal Vref2, the second voltage difference Vbs increases, the threshold voltage Vth1 of the dual-gate transistor M1 decreases, the threshold voltage Vth1<the first voltage difference Vgs1, and the dual-gate transistor M1 is turned off.

[0095] See also Figure 5, the state of the first scan signal SCAN1 changes again, from a high level to a low level, the fourth transistor M5 is turned on, and a display signal can be written to the first node N1, and the display signal is the data signal Vdata at this time. Exemplarily, before the fourth transistor M5 is turned on to write the data signal Vdata to the first node N1, the initial signal Vinit can be converted into the data signal Vdata. The data signal Vdata prepared in advance is written at the first time when the state of the first scan signal SCAN1 changes again. After the data signal Vdata is written to the first node N1, the effective level end point of the first scan signal SCAN1 is before the effective level end point of the third scan signal SCAN3. That is, the first scan signal SCAN1 changes its state again at this stage, from a low level to a high level, while the state of the third scan signal SCAN3 remains unchanged, and the first transistor M2 is still in the on state at this time.

[0096] See also Figure 5 , the state of the third scan signal SCAN3 changes from a high level to a low level, and the first transistor M2 is turned off. At this time, the gate-source voltage difference Vgs2 of the third transistor M4 is less than its own threshold voltage Vth2, the third transistor M4 is turned on, and is in the saturation region of the output characteristic curve, and the driving current is constant. The first gate voltage of the dual-gate transistor M1 is equal to the fourth node voltage, that is, the first voltage difference Vgs1 of the dual-gate transistor M1 remains unchanged. At this time, the second reference voltage signal SWEEP decreases from the high-level signal Vref2 to the low-level signal Vref1 at the first rate over time, and the second voltage difference Vbs gradually decreases. According to the threshold dynamic characteristics of the dual-gate transistor M1 described above, the threshold voltage Vth1 of the dual-gate transistor M1 gradually increases. When the first voltage difference Vgs1 of the dual-gate transistor M1 is greater than the threshold voltage Vth1, the dual-gate transistor M1 is turned off. When the first voltage difference Vgs1 of the dual-gate transistor M1 is less than the threshold voltage Vth1, the dual-gate transistor M1 is turned on.

[0097] According to a fourth aspect of the present disclosure, a controller is also proposed, comprising: a memory storing a computer program; a processor for calling the computer program in the memory, wherein the computer program is used to execute the driving method as described above.

[0098] Exemplarily, the controller may be integrated in a driving circuit, the driving circuit may use a driving chip to implement the above driving function, and the driving chip may be bound to a non-display area of ​​the display panel. In some embodiments, the controller may also be integrated in a driving chip.

[0099] In a fifth aspect, a display device is also proposed. Figure 7 A schematic structural block diagram of a display device provided in an embodiment of the present disclosure. Figure 7, the display device 700 may include both the display panel 710 and the controller 720 as described above. In some embodiments, the display device 700 may further include one of the display panel 710 or the controller 720.

[0100] Illustratively, the display device 700 of the embodiment of the present disclosure can be applied to scenarios such as vehicle-mounted display, smart phones, computers, medical monitors, televisions, smart wearable displays, etc. Smart wearable devices may include smart watches, AR (augmented reality) devices, and VR (virtual reality) devices, etc., which are not specifically limited by the embodiment of the present disclosure.

[0101] A person skilled in the art may understand the specific details and beneficial effects of the display panel, the controller and the display device by reading the above description of the pixel circuit and the driving method thereof, which will not be described herein for the sake of brevity.

[0102] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and / or equipment can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0103] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0105] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0106] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: A signal writing subcircuit, a first driving subcircuit, a second driving subcircuit and a third driving subcircuit, wherein: The signal writing subcircuit is electrically connected to the second driving subcircuit via the first node, and the signal writing subcircuit is used to receive a display signal, wherein the display signal includes a data signal; The first end of the third driving sub-circuit is electrically connected to the fourth node, and the second end of the third driving sub-circuit is used to receive a first reference voltage signal; The first driving subcircuit is electrically connected to the second driving subcircuit via a second node, wherein the first driving subcircuit includes a dual-gate transistor, a first gate of the dual-gate transistor is electrically connected to the fourth node, a second gate of the dual-gate transistor is used to receive a second reference voltage signal, a first electrode of the dual-gate transistor is used to receive a first power supply signal, and a second electrode of the dual-gate transistor is used to be electrically connected to the second node, wherein the first electrode is one of the source and the drain of the dual-gate transistor, and the second electrode is the other of the source and the drain of the dual-gate transistor.

2. The pixel circuit according to claim 1, characterized in that: After the data signal is written to the first node and when the second driving subcircuit is turned on, under the action of the first reference voltage signal and the second reference voltage signal, the threshold voltage of the dual-gate transistor increases over time, and the dual-gate transistor is turned on when the threshold voltage of the dual-gate transistor is greater than a first voltage difference, wherein the first voltage difference is the voltage difference between the first electrode and the first gate of the dual-gate transistor.

3. The pixel circuit according to claim 2, characterized in that: The voltage difference between the first electrode and the second gate of the dual-gate transistor is a second voltage difference. After the data signal is written into the first node and the second driving sub-circuit is turned on, the rate at which the second reference voltage signal decreases over time is a first rate. The second reference voltage signal is used to control the second voltage difference to decrease at the first rate. The rate at which the threshold voltage of the dual-gate transistor increases over time is a second rate. The first rate is positively correlated with the second rate.

4. The pixel circuit according to claim 3, characterized in that: The first reference voltage signal is used to control the first voltage difference to be constant.

5. The pixel circuit according to claim 3, characterized in that: In the same frame, the duration that the first voltage difference is greater than the threshold voltage of the dual-gate transistor is a first duration, the duration that the first voltage difference is less than the threshold voltage of the dual-gate transistor is a second duration, and the second duration is greater than the first duration.

6. The pixel circuit according to claim 3, characterized in that: Also includes: a reset subcircuit, comprising a first transistor, a gate of the first transistor being used to receive a third scanning signal, a first electrode of the first transistor being electrically connected to the second driving subcircuit via a third node, and a second electrode of the first transistor being used to receive a second power supply signal; The signal writing subcircuit is used to be turned on or off under the action of the first scanning signal; After the data signal is written into the first node, an effective level end point of the first scanning signal is before an effective level end point of the third scanning signal.

7. The pixel circuit according to claim 6, characterized in that: The third driving subcircuit includes: a second transistor and a first capacitor, the gate of the second transistor is used to receive a second scanning signal, the first electrode of the second transistor is electrically connected to the second end of the third driving subcircuit, the second electrode of the second transistor is electrically connected to the first end of the third driving subcircuit, one end of the first capacitor is electrically connected to the fourth node, the other end of the first capacitor is grounded, and the second transistor is used to be turned on or off under the action of the second scanning signal.

8. The pixel circuit according to claim 6, characterized in that: The second driving subcircuit includes a third transistor and a second capacitor, wherein one end of the second capacitor is electrically connected to the gate of the third transistor, the other end of the second capacitor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

9. The pixel circuit according to claim 7, characterized in that: The display signal further includes an initial signal, and when the signal writing subcircuit is turned on and the initial signal is written into the first node, the second reference voltage signal is a low level signal; At the effective level end point of the first scanning signal and the second scanning signal, the second reference voltage signal is transformed from the low level signal to a high level signal; After the data signal is written into the first node and the second driving sub-circuit is turned on, the second reference voltage signal decreases from the high level signal to the low level signal at the first rate over time.

10. A display panel, characterized in that: include: The pixel circuit according to any one of claims 1 to 9.

11. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 9, the driving method comprising: Controlling the signal writing subcircuit to be turned on to write the data signal to the first node; Controlling the second driving sub-circuit and the third driving sub-circuit to be turned on; Based on the first reference voltage signal and the second reference voltage signal, a turn-on time of the dual-gate transistor is controlled.

12. The driving method according to claim 11, characterized in that: The controlling the on-time of the dual-gate transistor based on the first reference voltage signal and the second reference voltage signal comprises: Based on the first reference voltage signal and the second reference voltage signal, the threshold voltage of the dual-gate transistor is controlled to increase over time, and the dual-gate transistor is turned on when the threshold voltage of the dual-gate transistor is greater than a first voltage difference, wherein the first voltage difference is the voltage difference between the first electrode and the first gate of the dual-gate transistor.

13. The driving method according to claim 12, characterized in that: The rate at which the second reference voltage signal decreases over time is a first rate, and the rate at which the threshold voltage of the dual-gate transistor increases over time is a second rate. The first rate is positively correlated with the second rate.

14. The driving method according to claim 13, characterized in that: The method further comprises: The value of the first rate is adjusted to control the ratio of the on time to the off time of the first driving sub-circuit.

15. The driving method according to claim 12, characterized in that: After the data signal is written into the first node and the second driving sub-circuit is turned on, the third transistor in the second driving sub-circuit is in the saturation region of the output characteristic curve.

16. The driving method according to claim 13, characterized in that: The display signal further includes an initial signal, and when the signal writing subcircuit is turned on and the initial signal is written into the first node, the second reference voltage signal is a low level signal; At the effective level end point of the first scanning signal and the second scanning signal, the second reference voltage signal is transformed from the low level signal to a high level signal; After the data signal is written into the first node and the second driving sub-circuit is turned on, the second reference voltage signal decreases from the high level signal to the low level signal at the first rate over time.

17. The driving method according to claim 16, characterized in that: Before controlling the signal writing subcircuit to be turned on to write the data signal to the first node, the method further includes: The initial signal is converted into the data signal.

18. The driving method according to claim 12, characterized in that: After the data signal is written into the first node, an effective level end point of the first scanning signal is before an effective level end point of the third scanning signal.

19. A controller, characterized in that: include: a memory storing a computer program; A processor, configured to call the computer program in the memory, wherein the computer program is configured to execute the driving method according to any one of claims 10 to 18.

20. A display device, characterized in that: Includes the display panel as claimed in claim 10 and / or the controller as claimed in claim 19.

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