A test circuit and memory

Abstract

The present disclosure provides a test circuit and a memory, wherein the test circuit includes a first control module, a state decoding module, and a second control module. The first control module generates and outputs a parity indication signal, a flip indication signal, and a topology indication signal based on an address jump pulse; the state decoding module counts and decodes the topology indication signal to obtain an intermediate decoding signal; and the second control module generates and outputs a first state signal and a second state signal based on the parity indication signal, the flip indication signal, and the intermediate decoding signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor memories, and in particular to a test circuit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM), a type of semiconductor memory, particularly 5th generation DDR (5th Double Data Rate, DDR5), is widely used in various electronic products due to its high performance and low cost. Currently, the most commonly used memory testing method is the Memory Build in Self Test (MBIST). The MBIST circuit automatically generates memory test circuits for the memory and executes specific test algorithms to detect certain defects in the memory. Summary of the Invention

[0003] The present disclosure provides a test circuit and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a test circuit for performing a read and write test on a storage array using multiple preset data topologies; the test circuit includes:

[0006] A first control module is configured to generate and output a parity indication signal, a flip indication signal, and a topology indication signal based on a received address jump pulse; wherein the address jump pulse indicates that the count value of the row address for which a target operation has been performed has reached an even highest bit or an odd highest bit, and the target operation is a read operation or a write operation;

[0007] a state decoding module, connected to the first control module, and configured to count and decode the topology indication signal to obtain an intermediate decoding signal;

[0008] a second control module connected to the first control module and the state decoding module, and configured to generate and output a first state signal and a second state signal based on the parity indication signal, the flip indication signal and the intermediate decoding signal;

[0009] Among them, the first state signal is used to select one of the first data sequence and the second data sequence as the target data sequence, the second state signal indicates whether each data of the target data sequence is flipped, and the target data sequence or the flipped target data sequence is used to constitute the preset data topology.

[0010] In some embodiments, the preset data topology has A groups, each group of the preset data topology includes a first data topology and a second data topology, and each of the first data topology and the second data topology includes an odd data topology and an even data topology;

[0011] The odd-even indication signal indicates that the row address of the storage unit corresponding to the target operation is an odd row address or an even row address, and generates the corresponding odd data topology or the even data topology;

[0012] The topology indication signal indicates the group number of the preset data topology corresponding to the target operation; the flip indication signal indicates the first data topology or the second data topology corresponding to the target operation.

[0013] In some embodiments, the first control module is further configured to generate and output a read / write indication signal based on receiving the address jump pulse; wherein the read / write indication signal indicates a read operation or a write operation.

[0014] In some embodiments, the test circuit further comprises a test module;

[0015] The test module is connected to both the first control module and the second control module, and is configured to receive the read / write indication signal, the first status signal, and the second status signal; when the read / write indication signal indicates a write operation, write the corresponding preset data topology to the storage array based on the first status signal and the second status signal; or, when the read / write indication signal indicates a read operation, read data from the storage array and compare the read data based on the first status signal and the second status signal.

[0016] In some embodiments, the first control module is specifically configured to control the level state of the parity indication signal to flip once every time one address jump pulse is received; control the level state of the read / write indication signal to flip once every time two address jump pulses are received; control the level state of the flip indication signal to flip once every time four address jump pulses are received; and generate one topology indication signal every time eight address jump pulses are received.

[0017] In some embodiments, the first control module includes:

[0018] a first signal unit configured to sample and process the inverted signal of the parity indication signal using the address jump pulse to generate a new parity indication signal;

[0019] a second signal unit connected to the first signal unit and configured to perform logic processing on the parity indication signal and the read / write indication signal to generate a first intermediate signal; and to sample the first intermediate signal based on the address jump pulse to generate a new read / write indication signal;

[0020] a third signal unit connected to the second signal unit, configured to perform logic processing on the parity indication signal, the read / write indication signal, and the flip indication signal to generate a second intermediate signal; and to sample the second intermediate signal based on the address jump pulse to generate a new flip indication signal;

[0021] A fourth signal unit is connected to the third signal unit and is configured to perform logical processing on the parity indication signal, the read / write indication signal and the flip indication signal to obtain a third intermediate signal; and generate the topology indication signal based on the third intermediate signal, the address jump pulse and the preset system clock signal.

[0022] In some embodiments, the state decoding module includes a counting unit and C decoding units, and the number of the intermediate decoded signals is C;

[0023] The counting unit is connected to the first control module and is configured to count the pulses of the topology indication signal to generate a first count value;

[0024] The jth decoding unit is connected to the counting unit and is configured to control the jth intermediate decoding signal to be in a first state when the first counting value meets the jth decoding condition; and to control the jth intermediate decoding signal to be in a second state when the first counting value does not meet the jth decoding condition; wherein j is an integer greater than or equal to 1 and less than or equal to C; C≤A; the first counting value includes a B-bit sub-parameter, 2B≥A.

[0025] In some embodiments, the second control module includes:

[0026] a first logic unit configured to perform logic processing on the C intermediate decoded signals and output a first-state even signal, a first-state odd signal, a second-state even signal, and a second-state odd signal;

[0027] a second logic unit configured to output one of the first-state even signal and the first-state odd signal as a first preselected signal based on the parity indication signal; and output one of the second-state even signal and the second-state odd signal as a second preselected signal based on the parity indication signal;

[0028] The output unit is configured to output the first preselected signal as the first state signal; and, based on the flip indication signal, output one of the second preselected signal and the inverted signal of the second preselected signal as the second state signal.

[0029] In some embodiments, the first logic unit includes:

[0030] a preprocessing unit configured to perform logic processing on the C intermediate decoded signals and output a first selected even signal, a first selected odd signal, a second selected even signal, and a second selected odd signal;

[0031] a selection unit configured to output one of a standard 0 signal and a standard 1 signal as the first state even signal based on the first selection even signal;

[0032] Based on the first selection odd signal, outputting one of the standard 0 signal and the standard 1 signal as the first state odd signal;

[0033] Based on the second selection even signal, outputting one of the standard 0 signal and the standard 1 signal as the second state even signal;

[0034] Based on the second selection odd signal, one of a standard 0 signal and a standard 1 signal is output as the second state odd signal.

[0035] In some embodiments, the first signal unit includes a first flip-flop: a clock terminal of the first flip-flop receives the address jump pulse, an input terminal of the first flip-flop is connected to an inverting output terminal thereof, and a non-inverting output terminal of the first flip-flop outputs the parity indication signal;

[0036] The second signal unit includes a first XOR gate and a second flip-flop; the first input end of the first XOR gate receives the parity indication signal, the second input end of the first XOR gate is connected to the positive phase output end of the second flip-flop, the output end of the first XOR gate outputs the first intermediate signal, the input end of the second flip-flop receives the first intermediate signal, the clock end of the second flip-flop receives the address jump pulse, and the positive phase output end of the second flip-flop outputs the read / write indication signal;

[0037] The third signal unit includes a first AND gate, a second XOR gate and a third flip-flop; the first input end of the first AND gate receives the read / write indication signal, the second input end of the first AND gate receives the parity indication signal, the output end of the first AND gate is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the positive phase output end of the third flip-flop, the output end of the second XOR gate outputs the second intermediate signal, the input end of the third flip-flop receives the second intermediate signal, the clock end of the third flip-flop receives the address jump pulse, and the positive phase output end of the third flip-flop outputs the flip indication signal;

[0038] The fourth signal unit includes a second AND gate, a third XOR gate, a fourth flip-flop, a fifth flip-flop and a fourth XOR gate; the first input end of the second AND gate is connected to the output end of the first AND gate, the second input end of the second AND gate receives the flip indication signal, the output end of the second AND gate is connected to the first input end of the third XOR gate, the second input end of the third XOR gate is connected to the positive phase output end of the fourth flip-flop, the output end of the third XOR gate outputs the third intermediate signal, the input end of the fourth flip-flop receives the third intermediate signal, the clock end of the fourth flip-flop receives the address jump pulse, the positive phase output end of the fourth flip-flop is connected to the input end of the fifth flip-flop, the clock end of the fifth flip-flop receives the preset system clock signal, the positive phase output end of the fifth flip-flop is connected to the first input end of the fourth XOR gate, the second input end of the fourth XOR gate is connected to the positive phase output end of the fourth flip-flop, and the output end of the fourth XOR gate outputs the topology indication signal.

[0039] In some embodiments, when 2A=12, B=3, C=5;

[0040] Accordingly, the counting unit includes a sixth trigger, a fifth XOR gate, a seventh trigger, a third AND gate, a sixth XOR gate and an eighth trigger;

[0041] The clock terminals of the sixth flip-flop, the seventh flip-flop, and the eighth flip-flop receive the topology indication signal, the input terminal of the sixth flip-flop is connected to its inverting output terminal, the positive-phase output terminal of the sixth flip-flop is connected to the first input terminal of the fifth XOR gate, the second input terminal of the fifth XOR gate is connected to the positive-phase output terminal of the seventh flip-flop, the output terminal of the fifth XOR gate is connected to the input terminal of the seventh flip-flop, the positive-phase output terminal of the seventh flip-flop is connected to the first input terminal of the third AND gate, the second input terminal of the third AND gate is connected to the positive-phase output terminal of the sixth flip-flop, the output terminal of the third AND gate is connected to the first input terminal of the sixth XOR gate, the second input terminal of the sixth XOR gate is connected to the positive-phase output terminal of the eighth flip-flop, and the output terminal of the sixth XOR gate is connected to the input terminal of the eighth flip-flop; the positive-phase output terminal of the sixth flip-flop outputs the first-bit sub-parameter of the first count value, the positive-phase output terminal of the seventh flip-flop outputs the second-bit sub-parameter of the first count value, and the positive-phase output terminal of the eighth flip-flop outputs the third-bit sub-parameter of the first count value.

[0042] In some embodiments, the pre-processing unit includes a first logic unit, a second logic unit, a third logic unit, and a fourth logic unit;

[0043] An input end of the first logic unit receives C partial signals of the intermediate decoded signals, and an output end of the first logic unit outputs the first selected even signal;

[0044] An input end of the second logic unit receives C partial signals of the intermediate decoded signals, and an output end of the second logic unit outputs the first selected odd signal;

[0045] An input end of the third logic unit receives C partial signals of the intermediate decoded signals, and an output end of the third logic unit outputs the second selected even signal;

[0046] An input end of the fourth logic unit receives C partial signals of the intermediate decoded signals, and an output end of the fourth logic unit outputs the second selected odd signal;

[0047] When the intermediate decoded signals are different, the first selected even signal, the first selected odd signal, the second selected even signal and the second selected even signal are not completely the same.

[0048] In some embodiments, the selection unit includes a first selector, a second selector, a third selector, and a fourth selector;

[0049] The first input terminal of the first selector receives the standard 1 signal, the second input terminal of the first selector receives the standard 0 signal, the control terminal of the first selector receives the first selection even signal, and the output terminal of the first selector outputs the first state even signal;

[0050] The first input terminal of the second selector receives the standard 1 signal, the second input terminal of the second selector receives the standard 0 signal, the control terminal of the second selector receives the first selection odd signal, and the output terminal of the second selector outputs the first state odd signal;

[0051] The first input terminal of the third selector receives the standard 0 signal, the second input terminal of the first selector receives the standard 1 signal, the control terminal of the third selector receives the second selection even signal, and the output terminal of the third selector outputs the second state even signal;

[0052] The first input end of the fourth selector receives the standard 0 signal, the second input end of the fourth selector receives the standard 1 signal, the control end of the fourth selector receives the second selection odd signal, and the output end of the fourth selector outputs the second state odd signal.

[0053] In some embodiments,

[0054] The second logic unit includes a fifth selector and a sixth selector; a first input terminal of the fifth selector receives the first state even signal, a second input terminal of the fifth selector receives the first state odd signal, a control terminal of the fifth selector receives the parity indication signal, and an output terminal of the fifth selector outputs the first pre-selected signal; a first input terminal of the sixth selector receives the second state even signal, a second input terminal of the sixth selector receives the second state odd signal, a control terminal of the sixth selector receives the parity indication signal, and an output terminal of the sixth selector outputs the second pre-selected signal;

[0055] The output unit includes a buffer, a third NOT gate and a seventh selector; the input end of the buffer receives the first pre-selection signal, and the output end of the buffer outputs the first state signal; the input end of the third NOT gate receives the second pre-selection signal, the output end of the third NOT gate is connected to the first input end of the seventh selector, the second input end of the seventh selector receives the second pre-selection signal, the control end of the seventh selector receives the flip indication signal, and the output end of the seventh selector outputs the second state signal.

[0056] In some embodiments, all reset terminals of the first to eighth triggers receive a start signal; wherein, if the start signal instructs the test circuit to start working, the first to eighth triggers all perform a reset operation.

[0057] In a second aspect, an embodiment of the present disclosure provides a memory, which includes the test circuit as described in any one of the first aspects.

[0058] An embodiment of the present disclosure provides a test circuit and a memory, which can automatically complete the read and write operations of a preset data topology after receiving an address jump pulse, an odd-even indication signal, a flip indication signal, and a topology indication signal; moreover, the test circuit can change the input data when the odd or even count reaches the highest bit, change the read and write state after the address traversal is completed, and after completing the test of one preset data topology, implement the test of another preset data topology by flipping the test data, and loop control until all preset data topologies are tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic diagram of a data topology provided in an embodiment of the present disclosure;

[0060] Figure 2 A schematic diagram of the structure of a test circuit provided in an embodiment of the present disclosure;

[0061] Figure 3 A schematic diagram of the structure of another test circuit provided in an embodiment of the present disclosure;

[0062] Figure 4 A control schematic diagram of a test circuit provided in an embodiment of the present disclosure;

[0063] Figure 5 A signal timing provided by an embodiment of the present disclosure Figure 1 ;

[0064] Figure 6 A signal timing provided by an embodiment of the present disclosure Figure 2 ;

[0065] Figure 7 A schematic structural diagram of a first control module provided in an embodiment of the present disclosure;

[0066] Figure 8 A schematic diagram of the structure of a state decoding module provided in an embodiment of the present disclosure;

[0067] Figure 9 A schematic structural diagram of a counting unit provided in an embodiment of the present disclosure;

[0068] Figure 10A schematic structural diagram of a decoding unit provided in an embodiment of the present disclosure;

[0069] Figure 11 A schematic structural diagram of a second control module provided in an embodiment of the present disclosure;

[0070] Figure 12 A schematic structural diagram of a first logic unit provided in an embodiment of the present disclosure;

[0071] Figure 13 A schematic diagram of the structure of a pre-processing unit provided in an embodiment of the present disclosure;

[0072] Figure 14 A schematic diagram of the structure of a selection unit provided in an embodiment of the present disclosure;

[0073] Figure 15 A schematic diagram of the structure of a second logic unit provided in an embodiment of the present disclosure

[0074] Figure 16 A schematic structural diagram of an output unit provided in an embodiment of the present disclosure;

[0075] Figure 17 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0076] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0078] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0079] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0080] Memory testability technologies include direct testing, testing using an embedded CPU, and built-in self-test (MBIST). MBIST offers numerous advantages over the other two technologies. First, it automates design for testability and automatically implements common memory test algorithms, achieving high test quality and low test costs. Second, the MBIST circuit can utilize the system clock for full-speed testing, thereby covering more generated defects and reducing test time. Finally, it provides self-diagnosis and self-repair capabilities for each memory cell. Furthermore, MBIST's initialization test vectors can be run on very low-cost test equipment. Therefore, from the perspective of high test quality and low test costs, MBIST is currently the mainstream technology for embedded memory test design.

[0081] For DDR5, according to the Joint Electron Device Engineering Council (JEDEC), MBIST is activated by the mode register MR23:OP[4] and the four MR24 guard keys, and then the MBIST operation is performed. The self-test time (tSELFTEST) of DDR5 with a storage capacity of 8 / 16 Gigabytes (Gb) does not exceed 9 seconds, and the data topology tested during this period is designed by the designer according to actual needs.

[0082] The currently designed MBIST includes the following when running on the host side Figure 1 When MBIST receives the enable signal from the host, it will automatically execute Figure 1 The data in two adjacent Data topo in the 12 data topologies are inversely proportional. For example, for Datatopo2, the data corresponding to each storage unit is the inverse of the data corresponding to the corresponding storage unit in Datatopo1. Figure 1 The WL on the chip represents the word line, and the BL represents the bit line. The intersection of the bit line and the corresponding word line is the memory cell, and each memory cell stores "0" or "1".

[0083] That is, see Figure 1 When MBIST receives the enable signal sent by the host, it first uses Datatopo1 and Data topo2 to perform the test. The specific process is as follows:

[0084] (1) Start counting at the even row address and write the even data topology in Data topo1 (i.e., 00000000 corresponding to WL0 / WL2WL4 / WL6 in Data topo1) into the even row address such as WL0 / WL2WL4 / WL6...

[0085] (2) After counting to the highest bit of the even number, start counting the odd row address and write the odd data topology in Data topo1 (i.e., 10101010 corresponding to WL1 / WL3WL5 / WL76 in Data topo1) into the odd row address such as WL1 / WL3WL5 / WL7...

[0086] (3) After the odd row address count reaches the highest bit, the read operation begins and the read data is compared with the written data;

[0087] (4) Start counting at the even row addresses and write the even data topology in Data topo2 (i.e., 11111111 corresponding to WL0 / WL2WL4 / WL6 in Data topo2) into the even row addresses such as WL0 / WL2WL4 / WL6...

[0088] (5) After counting to the highest bit of the even number, start counting the odd row address and write the odd data topology in Data topo2 (i.e., 01010101 corresponding to WL1 / WL3WL5 / WL76 in Data topo2) into the odd row address such as WL1 / WL3WL5 / WL7...

[0089] (6) After the odd row address count reaches the highest bit, the read operation is started and the read data is compared with the written data, thereby completing the test of Data topo1 and Data topo2.

[0090] Continue to follow the above steps to complete the test of Data topo3 and Data topo4, the test of Data topo6 and Datatopo6, the test of Data topo7 and Data topo8, the test of Data topo9 and Data topo10, and the test of Datatopo11 and Data topo12.

[0091] Based on this, the disclosed embodiments provide a test circuit that automatically completes the read and write operations for the 12 data topo types described above upon receiving an enable signal from the host. It switches to the even row address when the odd row address reaches the highest bit, or switches to the odd row address when the even row address reaches the highest bit, and changes the corresponding input data. The circuit then changes the read and write state after traversing the row address of a data topo until all data topo types are tested. This saves test time and improves test efficiency.

[0092] In one embodiment of the present disclosure, Figure 2 FIG. 1 shows a structure of a test circuit 10. The test circuit 10 performs a read and write test on a storage array using a plurality of preset data topologies. The test circuit 10 includes:

[0093] A first control module 11 is configured to generate and output a parity indication signal, a flip indication signal, and a topology indication signal based on a received address jump pulse; wherein the address jump pulse indicates that the count value of the row address for which a target operation has been performed has reached the highest even bit or the highest odd bit, and the target operation is a read operation or a write operation;

[0094] The state decoding module 12 is connected to the first control module 11 and is configured to count and decode the topology indication signal to obtain an intermediate decoding signal;

[0095] The second control module 13 is connected to the first control module 11 and the state decoding module 12, and is configured to generate and output a first state signal and a second state signal based on the parity indication signal, the flip indication signal and the intermediate decoding signal;

[0096] Among them, the first state signal is used to select one of the first data sequence and the second data sequence as the target data sequence, and the second state signal indicates whether each data of the target data sequence is flipped. The target data sequence or the flipped target data sequence is used to form a preset data topology Data topo.

[0097] The embodiments of the present disclosure relate to the design of a memory built-in self-test circuit in integrated circuit design, and more particularly to the state machine design of a 16Gb DDR5 built-in self-test circuit when running on the host side. The design is applied to the automatic generation and change of control signals when performing various data topology tests in a 16Gb DDR5 chip, but is not limited to this scope. This design can also be used in other command planning and generation circuits and counting timing control circuits.

[0098] It should be noted that the first state signal and the second state signal jointly determine the type of data sequence. Specifically, the first state signal has a first state and a second state. The first state corresponds to the first data sequence, and the second state corresponds to the second data sequence. Depending on the state of the first state signal, either the first data sequence or the second data sequence is selected as the target data sequence for testing. The second state signal has a third state and a fourth state. When the second state signal is in the third state, the target data sequence remains unchanged. When the second state signal is in the fourth state, the target data sequence is flipped. This enables automatic data flipping, allowing for more efficient completion of data topology read and write tests.

[0099] In some embodiments, the preset data topology has A groups, each group of preset data topologies Data topo includes a first data topology and a second data topology, and each of the first data topology and the second data topology includes an odd data topology and an even data topology; the odd-even indication signal indicates that the row address of the storage unit corresponding to the target operation is an odd row address or an even row address, and generates a corresponding odd data topology or even data topology; the topology indication signal indicates the group number of the preset data topology corresponding to the target operation; the flip indication signal indicates the first data topology or the second data topology corresponding to the target operation.

[0100] It should also be noted that the parity indicator signal, depending on its level, selects whether to perform a read operation on odd-numbered row addresses or even-numbered row addresses. For example, when the parity indicator signal is at a first level, the target operation is performed on the data array with even-numbered row addresses in the Data topo. After the target operation is completed on the last even-numbered row address in the Data topo, the parity indicator signal changes from the first level to the second level, and the target operation continues on the data array with odd-numbered row addresses in the Data topo.

[0101] Simply put, the parity indication signal corresponds to the switching between odd data topology and even data topology in the same preset data topology, the flip indication signal corresponds to the switching between the first data topology and the second data topology in the same group of preset data topologies, and the topology indication signal corresponds to the switching between different groups of preset data topology groups.

[0102] See also Figure 1 Since the data of every two Data topo are reversed, two Data topo are taken as a group, for a total of 6 groups of Data topo, that is, A=6.

[0103] In some embodiments, see Figure 4The first control module 11 is further configured to generate and output a read / write indication signal (WR_RD) based on receiving an address jump pulse; wherein the read / write indication signal (WR_RD) indicates a read operation or a write operation.

[0104] It should be noted that the disclosed embodiment uses a jump addressing method. When the first control module 11 receives an address jump pulse, it indicates that the count value of the odd-numbered row address or the even-numbered row address in a data topo has reached the highest bit. At this time, the input target data sequence is changed. When all row addresses of a data topo are traversed, the read / write status is changed through the read / write indication signal. In other words, the data sequences of odd-numbered row addresses and even-numbered row addresses are different.

[0105] In some embodiments, as Figure 3 As shown, the test circuit 10 further includes a test module 14;

[0106] The test module 14 is connected to both the first control module 11 and the second control module 13, and is configured to receive a read / write indication signal, a first status signal, and a second status signal; when the read / write indication signal indicates a write operation, write the corresponding data topo to the storage array based on the first status signal and the second status signal; or, when the read / write indication signal indicates a read operation, read the data from the storage array and compare the read data based on the first status signal and the second status signal.

[0107] It should be noted that during testing, the read / write indication signal determines whether to write the data topo to the storage array or read the data from the storage array. Specifically, when the read / write indication signal is at a first level, the corresponding data topo is written to the storage array; when the read / write indication signal is at a second level, the data from the storage array is read. Furthermore, by comparing the written data with the read data, it is possible to determine which data error has occurred, allowing for timely resolution and improving testing efficiency.

[0108] In some embodiments, see Figures 4 to 6 The first control module 11 is specifically configured to control the level state of the parity indication signal Data_change to flip once every time it receives one address jump pulse EVEN_ODD; control the level state of the read / write indication signal WR_RD to flip once every time it receives two address jump pulses EVEN_ODD; control the level state of the inversion indication signal INVERT to flip once every time it receives four address jump pulses EVEN_ODD; and generate one topology indication signal S_CLK every time it receives eight address jump pulses EVEN_ODD.

[0109] It should be noted that Figure 4 When testing the state machine, different signals need to be controlled. <0> For the first preselected signal, DATA <1> is the second preselection signal, the first preselection signal DATA <0> and the second preselect signal DATA <1> Together they decide what data to input into Data topo. Moreover, the first preselected signal DATA <0> The first state signal and the second preselection signal DATA <0> After the flip, it becomes the second state signal. ADDR represents the addressing control signal, and default is the default value of the state machine. As can be seen from the above description, the addressing methods used in the embodiments of the present disclosure are all jump addressing (JUMP) that distinguishes between odd and even.

[0110] according to Figure 4 Different values ​​of the control signal, Figure 1 The Data topo1 and Data topo2 in the example are used to illustrate the corresponding timing diagram. Figure 5 As shown:

[0111] (1) Flip indication signal = 0 (no flip), read / write indication signal WR_RD = 0 (write phase), parity indication signal Data_change = 0. At this time, the input preselection signal DATA<1:0> is 00, thereby writing the corresponding even data topology to the even row address;

[0112] (2) When the flip indication signal = 0 (no flip), the read / write indication signal WR_RD = 0 (write phase), and the parity indication signal Data_change = 1, the input preselection signal DATA<1:0> is 01, thereby writing the corresponding odd data topology into the odd row address; thus writing a complete Data topology;

[0113] (3) Flip indication signal = 0 (no flip), read / write indication signal WR_RD = 1 (read phase), parity indication signal Data_change = 0. At this time, the data of the even row address is read and compared with the even data topology corresponding to the preselection signal DATA<1:0> being 00;

[0114] (4) The flip indication signal = 0 (no flip), the read / write indication signal WR_RD = 1 (read phase), and the parity indication signal Data_change = 1. At this time, the data of the odd row address is read out, and the read data is compared with the odd data topology corresponding to the pre-selected signal DATA<1:0> being 01 to complete the test of the Data topo.

[0115] (5) Flip indication signal = 1 (flip), read / write indication signal WR_RD = 0 (write phase), parity indication signal Data_change = 0. At this time, the input preselection signal DATA<1:0> is 11, thereby writing the corresponding even data topology to the even row address;

[0116] (6) When the flip indication signal = 1 (flip), the read / write indication signal WR_RD = 0 (write phase), and the parity indication signal Data_change = 1, the input preselection signal DATA<1:0> is 10, thereby writing the corresponding odd data topology into the odd row address; thus writing a complete Data topology;

[0117] (7) Flip signal = 1 (flip), read / write indication signal WR_RD = 1 (read phase), thereby reading the corresponding data result. At the same time, the two sets of pre-selection signals DATA<1:0> input are 11, and the parity indication signal Data_change = 0. At this time, the data of the even row address is read and compared with the even data topology corresponding to the pre-selection signal DATA<1:0> being 11;

[0118] (4) Flip indication signal = 1 (flip), read / write indication signal WR_RD = 1 (read phase), parity indication signal Data_change = 1. At this time, the data of the odd row address is read out, and the read data is compared with the odd data topology corresponding to the preselection signal DATA<1:0> being 10, completing the test of the Data topo, and also completing the test of this group of Data topo.

[0119] It should be noted that, since the address jump pulse EVEN_ODD indicates that the count value of the row address on which the target operation has been executed has reached the highest even bit or the highest odd bit, once the first control module 11 receives an address jump pulse EVEN_ODD, it indicates that the test circuit 10 has completed counting the even row addresses of Data topo; if the previous parity indication signal Data_change is in the first level state, the parity indication signal Data_change will switch to the second level state at this time, and start to execute the test of the storage unit corresponding to the odd row address.

[0120] It should be noted that when the first control module 11 receives two address jump pulses EVEN_ODD, it means that a certain Data topo has been written. At this time, the level state of the read-write indication signal switches from the original write operation to the read operation. In other words, when the first control module 11 receives two address jump pulses EVEN_ODD, it means that the write operation on a Datatopo is completed; when the first control module 11 receives four address jump pulses EVEN_ODD, the read operation on the above-mentioned Datatopo is completed. In other words, when the first control module 11 receives four address jump pulses EVEN_ODD, the test of the Data topo is completed, and the next Data topo needs to be tested. Since the data between two adjacent Data topo (a group of Data topo) are inverted, the flip indication signal INVERT flips the data of the previous Data topo to obtain the next Data topo.

[0121] As mentioned above, when the first control module 11 receives 4 address jump pulses EVEN_ODD, the test of the Data topo is completed. Then, when the first control module 11 receives 8 address jump pulses EVEN_ODD, it means that the test of two adjacent Data topo is completed, and a topology indication signal S_CLK is generated. Therefore, Figure 6 As shown, every two Datatopos need to control the change of the preselection signal DATA<1:0> once, so a counter is added after the data inversion signal INVERT, so that it is flipped once every 8 address jump pulses EVEN_ODD (i.e., a group of Data topo), and then XORed to generate a topology indication signal S_CLK after shifting, and the number of groups of Data topo is counted (every two Data topo is a group). Therefore, one topology indication signal S_CLK indicates that the test of two adjacent Data topo is completed. The embodiment of the present disclosure groups the 12 Data topo into two groups. When the test circuit 10 generates 6 topology indication signals S_CLK, it means that the test of all 12 Data topo is completed.

[0122] In this way, splitting the signal to be controlled layer by layer can more conveniently realize the control of the host side and make it easier to adjust.

[0123] In some embodiments, as Figure 7 As shown, the first control module 11 includes:

[0124] The first signal unit 111 is configured to sample and process the inverted signal of the parity indication signal Data_change using the address jump pulse EVEN_ODD to generate a new parity indication signal;

[0125] The second signal unit 112 is connected to the first signal unit 111 and is configured to perform logic processing on the parity indication signal Data_change and the read / write indication signal WR_RD to generate a first intermediate signal; and to sample the first intermediate signal based on the address jump pulse EVEN_ODD to generate a new read / write indication signal;

[0126] The third signal unit 113 is connected to the second signal unit 112 and is configured to perform logic processing on the parity indication signal Data_change, the read / write indication signal WR_RD, and the inversion indication signal INVERT to generate a second intermediate signal; and to sample the second intermediate signal based on the address jump pulse EVEN_ODD to generate a new inversion indication signal;

[0127] The fourth signal unit 114 is connected to the third signal unit 113 and is configured to perform logical processing on the parity indication signal Data_change, the read / write indication signal WR_RD and the inversion indication signal INVERT to obtain a third intermediate signal; and generate a topology indication signal S_CLK based on the third intermediate signal, the address jump pulse EVEN_ODD and the preset system clock signal BIST_CLK.

[0128] Specifically, see Figure 7 The first signal unit 111 includes a first trigger 21: a clock terminal CLK of the first trigger 21 receives an address jump pulse EVEN_ODD, an input terminal of the first trigger 21 is connected to an inverting output terminal thereof, and a non-inverting output terminal of the first trigger 21 outputs a parity indication signal Data_change;

[0129] The second signal unit 112 includes a first XOR gate 22 and a second flip-flop 23; a first input terminal of the first XOR gate 22 receives the parity indication signal Data_change, a second input terminal of the first XOR gate 22 is connected to a positive phase output terminal of the second flip-flop 23, an output terminal of the first XOR gate 22 outputs a first intermediate signal, an input terminal of the second flip-flop 23 receives the first intermediate signal, a clock terminal CLK of the second flip-flop 23 receives an address jump pulse EVEN_ODD, and a positive phase output terminal of the second flip-flop 23 outputs a read / write indication signal WR_RD;

[0130] The third signal unit 113 includes a first AND gate 24, a second XOR gate 25, and a third flip-flop 26; a first input terminal of the first AND gate 24 receives a read / write indication signal WR_RD, a second input terminal of the first AND gate 24 receives a parity indication signal Data_change, an output terminal of the first AND gate 24 is connected to a first input terminal of the second XOR gate 25, a second input terminal of the second XOR gate 25 is connected to a positive phase output terminal of the third flip-flop 26, an output terminal of the second XOR gate 25 outputs a second intermediate signal, an input terminal of the third flip-flop 26 receives the second intermediate signal, a clock terminal CLK of the third flip-flop 26 receives an address jump pulse EVEN_ODD, and a positive phase output terminal of the third flip-flop 26 outputs an inversion indication signal INVERT;

[0131] The fourth signal unit 114 includes a second AND gate 27, a third XOR gate 28, a fourth flip-flop 29, a fifth flip-flop 30, and a fourth XOR gate 31; the first input terminal of the second AND gate 27 is connected to the output terminal of the first AND gate 24, the second input terminal of the second AND gate 27 receives the flip indication signal INVERT, the output terminal of the second AND gate 27 is connected to the first input terminal of the third XOR gate 28, the second input terminal of the third XOR gate 28 is connected to the positive phase output terminal of the fourth flip-flop 29, the output terminal of the third XOR gate 28 outputs the third intermediate signal, and the positive phase output terminal of the fourth flip-flop 29 is connected to the positive phase output terminal of the fourth flip-flop 29. The input end receives the third intermediate signal, the clock end CLK of the fourth trigger 29 receives the address jump pulse EVEN_ODD, the positive phase output end of the fourth trigger 29 is connected to the input end of the fifth trigger 30, the clock end CLK of the fifth trigger 30 receives the preset system clock signal BIST_CLK, the positive phase output end of the fifth trigger 30 is connected to the first input end of the fourth XOR gate 31, the second input end of the fourth XOR gate 31 is connected to the positive phase output end of the fourth trigger 29, and the output end of the fourth XOR gate 31 outputs the topology indication signal S_CLK.

[0132] It should be noted that the first signal unit 111, the second signal unit 112, the third signal unit 113, and the fourth signal unit 114 together constitute a synchronous counter, and each signal unit 111 outputs a corresponding indication signal. The first signal unit 111 outputs the parity indication signal Data_change, the second signal unit 112 outputs the read / write indication signal WR_RD, the third signal unit 113 outputs the inversion indication signal INVERT, and the fourth signal unit 114 outputs the topology indication signal S_CLK.

[0133] It should also be noted that the address jump pulse EVEN_ODD and the preset system clock signal BIST_CLK do not both sample the third intermediate signal. The preset system clock signal BIST_CLK samples the output of the previous stage trigger (the fourth trigger 29).

[0134] In some embodiments, as Figure 8 As shown, the state decoding module 12 includes a counting unit 121 and C decoding units 122, and the number of intermediate decoding signals is C;

[0135] The counting unit 121 is connected to the first control module 11 and configured to count the pulses of the topology indication signal S_CLK to generate a first count value;

[0136] The j-th decoding unit 122 is connected to the counting unit 121 and is configured to control the j-th intermediate decoding signal to be in a first state when the first count value meets the j-th decoding condition; and to control the j-th intermediate decoding signal to be in a second state when the first count value does not meet the j-th decoding condition; wherein j is an integer greater than or equal to 1 and less than or equal to C; C≤A; the first count value includes a B-bit sub-parameter, 2B≥A.

[0137] It should be noted that the first count value is the number of topology indication signals S_CLK. Therefore, if the first count value includes B as a sub-parameter, B topology indication signals S_CLK are generated. Since every two data topo points generate one topology indication signal S_CLK, 2B must be greater than or equal to the number of data topo points A to ensure that all data topo points are tested.

[0138] Specifically, if Figure 9 As shown, in the case of 2A=12, B=3, C=5;

[0139] Accordingly, the counting unit 121 includes a sixth flip-flop 32, a fifth XOR gate 33, a seventh flip-flop 34, a third AND gate 35, a sixth XOR gate 36 and an eighth flip-flop 37;

[0140] The clock terminals CLK of the sixth flip-flop 32, the seventh flip-flop 34, and the eighth flip-flop 37 receive the topology indication signal S_CLK. The input terminal of the sixth flip-flop 32 is connected to its inverting output terminal. The positive-phase output terminal of the sixth flip-flop 32 is connected to the first input terminal of the fifth XOR gate 33. The second input terminal of the fifth XOR gate 33 is connected to the positive-phase output terminal of the seventh flip-flop 34. The output terminal of the fifth XOR gate 33 is connected to the input terminal of the seventh flip-flop 34. The positive-phase output terminal of the seventh flip-flop 34 is connected to the first input terminal of the third AND gate 35. The second input terminal of the third AND gate 35 is connected to the positive-phase output terminal of the sixth flip-flop 32. The output terminal of the third AND gate 35 is connected to the first input terminal of the sixth XOR gate 36. The second input terminal of the sixth XOR gate 36 is connected to the positive-phase output terminal of the eighth flip-flop 37. The output terminal of the sixth XOR gate 36 is connected to the input terminal of the eighth flip-flop 37. The positive-phase output terminal of the sixth flip-flop 32 outputs the first-bit sub-parameter S of the first count value. <0> The positive phase output terminal of the seventh flip-flop 34 outputs the second bit parameter S of the first count value. <1> The positive phase output terminal of the eighth flip-flop 37 outputs the third bit sub-parameter S of the first count value. <3> .

[0141] It should be noted that the value of the first count value S<2:0> also represents the state of the state machine. In the disclosed embodiment, both the first control module 11 and the counting unit 121 utilize synchronous counters, which provide faster counting speeds and better clock synchronization. Of course, in other embodiments, asynchronous counters may also be employed to implement related functions, depending on circuit design and actual needs.

[0142] In some embodiments, as Figure 10 As shown, the j-th decoding unit 122 includes a first NOR gate 38, a first NOT gate 39, a first NAND gate 40 and a second NOT gate 41. The second input terminal of the first NOR gate 38 receives the first bit sub-parameter S of the first count value. <0> The first input terminal of the first NOR gate 38 receives the second bit sub-parameter S of the first count value. <1> The input end of the first NOT gate 39 receives the third bit sub-parameter S of the first count value. <2> The first input end of the first NAND gate 40 is connected to the output end of the first NOT gate 39, the second input end of the first NAND gate 40 is connected to the output end of the first NOR gate 38, the output end of the first NAND gate 40 is connected to the input end of the second NOT gate 41, and the output end of the second NOT gate 41 outputs the j-th intermediate decoding signal.

[0143] It should be noted that when 2A=12, that is, A=6, the maximum value of the corresponding topology indication signal S_CLK is 6. When B=3, the maximum first count value is 8, and the counting range of the counting unit 121 is 000-111. As described above, the topology indication signal S_CLK indicates the group number of the Data topo corresponding to the target operation. Figure 1The 12 Data topologies can generate 6 preset data topology groups, so the first count value can be used to indicate the state of the state machine. The relationship between the state of the state machine and DATA_IN<1:0> is shown in Table 1:

[0144] Table 1

[0145]

[0146] It should be understood that TOPO CNT is the state machine S<2:0>, and S<2:0> is the first count value. Since there are 6 groups of Data topo in the embodiment of the present disclosure, Table 1 lists the 6 states of the state machine S<2:0>. Here DATA_IN <0> Is the first state signal, DATA_IN <1> Is the second state signal. Among them, the first state signal DATA_IN <0> The first preselection signal and the second state signal DATA_IN are <1> It is the second preselected signal DATA after flipping <1> .

[0147] The first row in Table 1 is now used as an example for explanation, and the other rows can be understood with reference to the first row.

[0148] The first row is the first group of Data topo, which is also the first state of the state machine. When DATA_IN<1:0> is 00 / 01 / 00 / 01, the corresponding Figure 1 The first two 00 / 01 correspond to the write operation of Data topo1, and the second two 00 / 01 correspond to the read operation of Data topo1, thus completing the test of Data topo1. Then, using the inversion indicator signal INVERT, the high bits of DATA_IN<1:0> are flipped to 10 / 11 / 10 / 11, which is the DATA_IN<1:0> corresponding to Data topo2. Similarly, the first two 10 / 11 correspond to the write operation of Data topo2, and the second two 10 / 11 correspond to the read operation of Data topo2. Therefore, the first row in Table 1 completes the test of Data topo1 and Data topo2. During this period, the automatic flipping of the Data topo is completed.

[0149] Now, taking the first row in Table 1 as an example, the first state signal DATA_IN <0> and the second state signal DATA_IN <1> A brief explanation of how to obtain the corresponding Data topo. Figure 4As shown in Table 1, when DATA_IN<1:0> is 00, the first state signal DATA_IN <0> and the second state signal DATA_IN <1> When DATA_IN<1:0> is 01, the first state signal DATA_IN is <0> is 1, the second state signal DATA_IN <1> If is 0, the corresponding data sequence is 10101010. Figure 1 , the data topo of the even number data sequence is 00000000 and the odd number data sequence is 10101010 is Data topo1. Similarly, when the first state signal DATA_IN <0> is 0, the second state signal DATA_IN <1> Both are 1, because DATA_IN <1> When 1, DATA_IN <0> The corresponding data sequence needs to be flipped when DATA_IN <0> When DATA_IN<1:0> is 11, the corresponding data sequence is 11111111. When DATA_IN<1:0> is 11, the first state signal DATA_IN<1:0> is 0. <0> and the second state signal DATA_IN <1> The data topo with the even data sequence of 11111111 and the odd data sequence of 01010101 is Data topo2.

[0150] That is, the embodiment of the present disclosure controls the first state signal DATA_IN <0> and the second state signal DATA_IN <0> To control the automatic input and testing of 12 types of Data topo.

[0151] In other words, referring to Table 1, it can be considered that the state machine has six states: TOPO CNT0, TOPO CNT1, TOPOCNT2, TOPO CNT3, TOPO CNT4, and TOPO CNT5.

[0152] In one design, we can find (1) DATA_IN <1> =0, DATA_IN <0> =0, the state of the state machine, at this time it is necessary to determine the TOPO CNT0 ~ TOPO CNT5 states;

[0153] In another design, we can find (1) DATA_IN <1> =0, DATA_IN <0> =1, the state of the state machine, at this time it is also necessary to determine the TOPO CNT0 ~ TOPO CNT5 states;

[0154] In another design, (1) DATA_IN can be found <1> =1, DATA_IN <0> =1, the state of the state machine. At this time, it is also necessary to determine the states of TOPO CNT0~TOPO CNT5.

[0155] In another design, (1) DATA_IN can be found <1> =1, DATA_IN <0> =0, the state of the state machine. At this time, it is also necessary to determine the states of TOPO CNT0, TOPO CNT1, TOPO CNT2, TOPO CNT3, and TOPO CNT5; there is no need to find the state of TOPO CNT4, which can be defined by the inverse of other states.

[0156] Therefore, with the last design, only five states of the state machine need to be found, thus reducing the number of decoding devices.

[0157] Specifically, such as Figure 10 As shown, find DATA_IN in Table 1 <0> 0 and DATA_IN <1> When it is 1, the state of the state machine is decoded to generate the intermediate decoding signals DATA0 (indicating whether the state machine is in the TOPO CNT0 state), DATA1 (indicating whether the state machine is in the TOPO CNT1 state), DATA2 (indicating whether the state machine is in the TOPO CNT2 state), DATA3 (indicating whether the state machine is in the TOPO CNT3 state) and DATA5 (indicating whether the state machine is in the TOPO CNT5 state), which are used to subsequently generate the preselection signal DATA<1:0>.

[0158] In some embodiments, as Figures 11 to 14 As shown, the second control module 13 includes:

[0159] The first logic unit 131 is configured to perform logic processing on the C intermediate decoded signals (DATA0, DATA1, DATA2, DATA3, and DATA5) and output a first-state even signal DATA0_EVEN, a first-state odd signal DATA0_ODD, a second-state even signal DATA1_EVEN, and a second-state odd signal DATA1_ODD;

[0160] The second logic unit 132 is configured to output one of the first state even signal DATA0_EVEN and the first state odd signal DATA0_ODD as the first pre-selected signal DATA based on the parity indication signal Data_change. <0> and outputting one of the second state even signal DATA1_EVEN and the second state odd signal DATA1_ODD as the second preselected signal DATA based on the parity indication signal Data_change. <1> ;

[0161] The output unit 133 is configured to output the first preselected signal DATA <0> Output is the first state signal DATA_IN <0> And, based on the flip indication signal INVERT, the second preselect signal DATA <1> One of the two signals, the inverted signal of the second preselected signal, is output as the second state signal DATA_IN <1> .

[0162] For details, see Figure 12 , the first logic unit 131 includes:

[0163] The pre-processing unit 1311 is configured to perform logic processing on the C intermediate decoded signals (DATA0, DATA1, DATA2, DATA3 and DATA5), and output a first selected even signal EVEN_DATA0_EN, a first selected odd signal ODD_DATA0_EN, a second selected even signal EVEN_DATA1_EN and a second selected odd signal ODD_DATA1_EN;

[0164] The selection unit 1312 is configured to output one of the standard 0 signal and the standard 1 signal as the first state even signal DATA0_EVEN based on the first selection even signal EVEN_DATA0_EN;

[0165] Based on the first selection odd signal ODD_DATA0_EN, one of the standard 0 signal and the standard 1 signal is output as the first state odd signal DATA0_ODD;

[0166] Based on the second selection even signal EVEN_DATA1_EN, outputting one of the standard 0 signal and the standard 1 signal as the second state even signal DATA1_EVEN;

[0167] Based on the second selection odd signal ODD_DATA1_EN, one of the normal 0 signal and the normal 1 signal is output as the second state odd signal DATA1_ODD.

[0168] like Figure 13 As shown, the pre-processing unit 1311 includes a first logic unit 42, a second logic unit 43, a third logic unit 44 and a fourth logic unit 45;

[0169] An input terminal of the first logic unit 42 receives partial signals of the C intermediate decoded signals, and an output terminal of the first logic unit 42 outputs a first selection even signal EVEN_DATA0_EN;

[0170] An input terminal of the second logic unit 43 receives partial signals of the C intermediate decoded signals, and an output terminal of the second logic unit 43 outputs a first selection odd signal ODD_DATA0_EN;

[0171] An input terminal of the third logic unit 44 receives partial signals of the C intermediate decoded signals, and an output terminal of the third logic unit 44 outputs a second selection even signal EVEN_DATA1_EN;

[0172] An input terminal of the fourth logic unit 45 receives partial signals of the C intermediate decoded signals, and an output terminal of the fourth logic unit 45 outputs a second selection odd signal ODD_DATA1_EN;

[0173] When the intermediate decoded signals are different, the first selected even signal EVEN_DATA0_EN, the first selected odd signal ODD_DATA0_EN, the second selected even signal EVEN_DATA1_EN, and the second selected even signal ODD_DATA1_EN are not completely the same.

[0174] It should be noted that Figure 13 Taking the example that the first logic device 42, the second logic device 43 and the third logic device 44 are all OR gates and the fourth logic device 45 is two NOT gates, of course, in specific design, other logic gates or logic circuit combinations can also be used to replace the OR gate.

[0175] It should also be noted that, taking the first selection even signal EVEN_DATA0_EN as an example, it represents the first state signal DATA_IN during even addressing. <0> =0, find the first state signal DATA_IN from the intermediate decoded signals DATA0, DATA1, DATA2, DATA3 and DATA5 <0> If the value is 0, the first selection even signal EVEN_DATA0_EN can be generated through the OR logic. Similarly, the first selection odd signal ODD_DATA0_EN, the second selection even signal EVEN_DATA1_EN, and the second selection odd signal ODD_DATA1_EN are generated. Since the first column of DATA_IN<1:0> in Table 1 corresponds to the even data sequence in the Data topo, and the second column corresponds to the odd data sequence in the Data topo, the subsequent columns are recursively calculated. Taking the first and second columns in Table 1 as an example:

[0176] When performing even addressing (column 1 of Table 1), the first state signal DATA_IN is found from the intermediate decoded signals DATA0, DATA1, DATA2, DATA3 and DATA5. <0> The value of 0 is DATA0, DATA1 and DATA3. Through the OR logic, the first selection even signal EVEN_DATA0_EN can be generated; then find the second state signal DATA_IN <1> The value of 1 is DATA2 and DATA5, and the second selection even signal EVEN_DATA1_EN can be generated through OR logic.

[0177] Similarly, when performing odd addressing (column 2 of Table 1), the first state signal DATA_IN is found from the intermediate decoded signals DATA0, DATA1, DATA2, DATA3 and DATA5. <0> The value of 0 is DATA1, DATA3 and DATA5, and the first selection odd signal ODD_DATA0_EN can be generated through the OR logic; then find the second state signal DATA_IN <1> The value of 1 is DATA3, and the second selection odd signal ODD_DATA1_EN can be generated by two inversion processes.

[0178] It should be understood that the data written when traversing odd-numbered row addresses and even-numbered row addresses are different. Since addressing is divided into odd and even, parity is also required here. In this way, the addressing method is unified and the control logic is clear.

[0179] Correspondingly, such as Figure 14 As shown, the selection unit 1312 includes a first selector 46, a second selector 47, a third selector 48 and a fourth selector 49;

[0180] The first input terminal of the first selector 46 receives the standard 1 signal, the second input terminal of the first selector 46 receives the standard 0 signal, the control terminal of the first selector 46 receives the first selection even signal EVEN_DATA0_EN, and the output terminal of the first selector 46 outputs the first state even signal DATA0_EVEN;

[0181] The first input terminal of the second selector 47 receives the standard 1 signal, the second input terminal of the second selector 47 receives the standard 0 signal, the control terminal of the second selector 47 receives the first selection odd signal ODD_DATA0_EN, and the output terminal of the second selector 47 outputs the first state odd signal DATA0_ODD;

[0182] The first input terminal of the third selector 48 receives the standard 0 signal, the second input terminal of the first selector 48 receives the standard 1 signal, the control terminal of the third selector 48 receives the second selected even signal DATA1_EVEN, and the output terminal of the third selector 48 outputs the second state even signal DATA1_EVEN;

[0183] The first input terminal of the fourth selector 49 receives the standard 0 signal, the second input terminal of the fourth selector 49 receives the standard 1 signal, the control terminal of the fourth selector 49 receives the second selection odd signal DATA1_ODD, and the output terminal of the fourth selector 49 outputs the second state odd signal DATA1_ODD.

[0184] It should be noted that the values ​​of the first-state even signal DATA0_EVEN, the first-state odd signal DATA0_ODD, the second-state even signal DATA1_EVEN, and the second-state odd signal DATA1_ODD are selected using the first-selected even signal EVEN_DATA0_EN, the first-selected odd signal ODD_DATA0_EN, the second-selected even signal DATA1_EVEN, and the second-state odd signal DATA1_ODD generated by the processing unit 1311. For example, when the first-selected even signal EVEN_DATA0_EN is 1, the first-state even signal DATA0_EVEN is 0, otherwise it is 1. The other three signals can be understood by reference and are not further described here.

[0185] In some embodiments, as Figure 15 As shown, the second logic unit 132 includes a fifth selector 50 and a sixth selector 51; the first input terminal of the fifth selector 50 receives the first state even signal DATA0_EVEN, the second input terminal of the fifth selector 50 receives the first state odd signal DATA0_ODD, the control terminal of the fifth selector 50 receives the parity indication signal Data_change, and the output terminal of the fifth selector 50 outputs the first pre-selection signal DATA <0> The first input terminal of the sixth selector 51 receives the second state even signal DATA1_EVEN, the second input terminal of the sixth selector 51 receives the second state odd signal DATA1_ODD, the control terminal of the sixth selector 51 receives the parity indication signal Data_change, and the output terminal of the sixth selector 51 outputs the second pre-selected signal DATA <1> .

[0186] like Figure 16 As shown, the output unit 133 includes a buffer 52, a third NOT gate 53 and a seventh selector 54; the input end of the buffer 52 receives the first preselection signal DATA <0> , the output terminal of the buffer 52 outputs the first state signal DATA_IN <0> The input terminal of the third NOT gate 53 receives the second preselected signal DATA <1> The output end of the third NOT gate 53 is connected to the first input end of the seventh selector 54, and the second input end of the seventh selector 54 receives the second preselection signal DATA <1> The control end of the seventh selector 54 receives the inversion indication signal INVERT, and the output end of the seventh selector 54 outputs the second state signal DATA_IN <1> .

[0187] It should be noted that the buffer 52 is composed of two NOT gates, namely the first preselected signal DATA <0> The first state signal DATA_IN can be obtained by inverting twice <0> That is, in the embodiment of the present disclosure, the first preselection signal DATA <0> It is the first state signal DATA_IN <0> , the second state signal DATA_IN <1> The second preselect signal DATA <1> The inverted signal.

[0188] At the same time, the odd-even indication signal Data_change can be used to select whether the specific output DATA<1:0> is an odd row address or an even row address, and the inversion indication signal INVERT is used to determine whether DATA<1:0> is an odd row address or an even row address. <1> Whether the value needs to be flipped.

[0189] For the state machine, at the beginning of the test, the state machine S<2:0> is 0, and the decoding unit 122 decodes DATA0 as 1, and DATA1, DATA2, DATA3, and DATA5 as 0. Since DATA0 is 1, the first selection even signal EVEN_DATA0_EN obtained by the pre-processing unit 1311 is 1, and the first selection odd signal ODD_DATA0_EN, the second selection even signal EVEN_DATA1_EN, and the second selection odd signal ODD_DATA1_EN are all 0. Then, the selection unit 1312 selects the first state even signal DATA0_EVEN as 0, the first state odd signal DATA0_ODD as 1, the second state even signal DATA1_EVEN as 0, and the second state odd signal DATA1_ODD as 0. At this time, the parity indication signal Data_change and the inversion indication signal INVERT maintain the initialized values, and the first pre-selection signal DATA <0> The first state even signal DATA0_EVEN, the second preselected signal DATA <1> The second state signal DATA1_EVEN is even, the second state signal DATA_IN is <1> The second preselect signal DATA <1> , no flip occurs, that is, DATA_IN<1:0> is 00; when the even address reaches the maximum value, the parity indication signal Data_change flips, the flip indication signal INVERT remains unchanged, and the first pre-selected signal DATA is selected <0> The first state odd signal DATA0_ODD, the second preselected signal DATA <1> The second state signal DATA1_ODD is the odd signal, the second state signal DATA_IN is <1> The second preselect signal DATA <1> , that is, DATA_IN<1:0> is 01. At this point, the odd-row address and even-row address of a Data topo have been traversed, that is, the full address has been written, and then the full address is read, and the data changes are the same as above. When the read and write operations of a Data topo are completed, the next Data topo will be written and read. At this time, the inversion indication signal INVERT will be flipped, and the other changes remain unchanged, so DATA_IN<1:0> changes to 10 / 11 / 10 / 11; the second Data topo read and write traversal will pass through the first control module 11 and the counting unit 121, so that the topology indication signal S_CLK generates a pulse, so that the state of the state machine changes from 0 to 1, and the corresponding write data will also produce the same change as state 0, and this cycle will be repeated until 6 states, that is, 12 types of Data topo, are traversed.

[0190] In some embodiments, all reset terminals of the first to eighth triggers 21 to 37 receive the start signal Rst; wherein, if the start signal Rst instructs the test circuit 10 to start working, the first to eighth triggers 21 to 37 all perform a reset operation.

[0191] In addition, when the first count value reaches 110 (the next state after DATA5), the reset signal is also generated to start the next cycle.

[0192] That is, in order to achieve the aforementioned test requirements, the present disclosure provides a test circuit 10, which needs to include the following: Figure 4 The following functions are shown:

[0193] 1. Control addressing mode. When MBIST receives the enable signal from the host, it will use the jump addressing mode and select the data sequence corresponding to the even row address or the odd row address in the Data topo for read and write operations through the parity indication signal Data_change.

[0194] 2. Control the selection of test input data (preselection signal DATA<1:0>). The first preselection signal DATA <0> and the second preselect signal DATA <1> Together they determine the data sequence that is input to the MBIST circuit each time. For example, when the first preselection signal DATA <0> =0, second preselection signal DATA <1> =0, the data sequence is 00000000; when the first preselect signal DATA <0> =0, second preselection signal DATA <1> =1, the data sequence is 11111111; when the first preselect signal DATA <0> =1, second preselection signal DATA <1> =0, the data sequence is 10101010; when the first preselect signal DATA <0> =1, second preselection signal DATA <1> =1, the data sequence is 01010101.

[0195] 3. Control read and write (WR_RD) commands. When the MBIST circuit is testing, the data sequence changes whenever the odd row address or the even row address reaches the highest bit. Moreover, the read and write status will change each time the row address is traversed (that is, the read and write operations of one Data topo are completed). In other words, for a Data topo, the write operation (WR) is performed first, and then the read operation (RD) is performed. When the read and write operations in the Data topo are completed, the flip indication signal INVERT will be activated. It should be understood that the flip indication signal INVERT and the second pre-selected signal DATA are the same. <1> The invert in the invert signal INVERT is different from the invert in the invert signal INVERT, which is used to control the input of the next Data topo, and the second preselected signal DATA <1> The invert in is used to control the input in the same Data topo.

[0196] In another embodiment of the present disclosure, Figure 17As shown, a memory 60 provided by an embodiment of the present disclosure is shown. The memory 60 includes the test circuit 10 described in any one of the aforementioned embodiments.

[0197] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0198] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0199] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0200] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0201] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0202] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0203] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A test circuit, characterized in that: The test circuit performs a read and write test on the storage array using a plurality of preset data topologies; the test circuit includes: A first control module is configured to generate and output a parity indication signal, a flip indication signal, and a topology indication signal based on a received address jump pulse; wherein the address jump pulse indicates that the count value of the row address for which a target operation has been performed has reached an even highest bit or an odd highest bit, and the target operation is a read operation or a write operation; a state decoding module, connected to the first control module, and configured to count and decode the topology indication signal to obtain an intermediate decoding signal; a second control module connected to the first control module and the state decoding module, and configured to generate and output a first state signal and a second state signal based on the parity indication signal, the flip indication signal and the intermediate decoding signal; The first state signal is used to select one of the first data sequence and the second data sequence as a target data sequence, the second state signal indicates whether each data in the target data sequence is flipped, and the target data sequence or the flipped target data sequence is used to form the preset data topology; The first control module is further configured to generate and output a read / write indication signal based on receiving the address jump pulse; wherein the read / write indication signal indicates a read operation or a write operation; The test circuit further includes a test module; The test module is connected to both the first control module and the second control module, and is configured to receive the read / write indication signal, the first status signal, and the second status signal; when the read / write indication signal indicates a write operation, write the corresponding preset data topology to the storage array based on the first status signal and the second status signal; or, when the read / write indication signal indicates a read operation, read data from the storage array and compare the read data based on the first status signal and the second status signal.

2. The test circuit according to claim 1, wherein: The preset data topology has A groups, each group of the preset data topology includes a first data topology and a second data topology, and each of the first data topology and the second data topology includes an odd data topology and an even data topology; The odd-even indication signal indicates that the row address of the storage unit corresponding to the target operation is an odd row address or an even row address, and generates the corresponding odd data topology or the even data topology; The topology indication signal indicates the group number of the preset data topology corresponding to executing the target operation; The flip indication signal indicates executing the first data topology or the second data topology corresponding to the target operation.

3. The test circuit according to claim 1, wherein: The first control module is specifically configured to control the level state of the parity indication signal to flip once every time it receives one address jump pulse; control the level state of the read / write indication signal to flip once every time it receives two address jump pulses; control the level state of the flip indication signal to flip once every time it receives four address jump pulses; and generate one topology indication signal every time it receives eight address jump pulses.

4. The test circuit according to claim 1, wherein: The first control module includes: a first signal unit configured to sample and process the inverted signal of the parity indication signal using the address jump pulse to generate a new parity indication signal; a second signal unit connected to the first signal unit and configured to perform logic processing on the parity indication signal and the read / write indication signal to generate a first intermediate signal; and to sample the first intermediate signal based on the address jump pulse to generate a new read / write indication signal; a third signal unit connected to the second signal unit, configured to perform logic processing on the parity indication signal, the read / write indication signal, and the flip indication signal to generate a second intermediate signal; and to sample the second intermediate signal based on the address jump pulse to generate a new flip indication signal; A fourth signal unit is connected to the third signal unit and is configured to perform logical processing on the parity indication signal, the read / write indication signal and the flip indication signal to obtain a third intermediate signal; and generate the topology indication signal based on the third intermediate signal, the address jump pulse and the preset system clock signal.

5. The test circuit according to claim 4, characterized in that: The state decoding module includes a counting unit and C decoding units, and the number of the intermediate decoding signals is C; The counting unit is connected to the first control module and is configured to count the pulses of the topology indication signal to generate a first count value; The jth decoding unit is connected to the counting unit and is configured to control the jth intermediate decoding signal to be in a first state when the first counting value meets the jth decoding condition; and to control the jth intermediate decoding signal to be in a second state when the first counting value does not meet the jth decoding condition; wherein j is an integer greater than or equal to 1 and less than or equal to C; C≤A; the first counting value includes a B-bit sub-parameter, 2B≥A.

6. The test circuit according to claim 5, characterized in that: The second control module includes: a first logic unit configured to perform logic processing on the C intermediate decoded signals and output a first-state even signal, a first-state odd signal, a second-state even signal, and a second-state odd signal; a second logic unit configured to output one of the first-state even signal and the first-state odd signal as a first preselected signal based on the parity indication signal; and output one of the second-state even signal and the second-state odd signal as a second preselected signal based on the parity indication signal; The output unit is configured to output the first preselected signal as the first state signal; and, based on the flip indication signal, output one of the second preselected signal and the inverted signal of the second preselected signal as the second state signal.

7. The test circuit according to claim 6, characterized in that: The first logic unit includes: a preprocessing unit configured to perform logic processing on the C intermediate decoded signals and output a first selected even signal, a first selected odd signal, a second selected even signal, and a second selected odd signal; a selection unit configured to output one of a standard 0 signal and a standard 1 signal as the first state even signal based on the first selection even signal; Based on the first selection odd signal, outputting one of the standard 0 signal and the standard 1 signal as the first state odd signal; Based on the second selection even signal, outputting one of the standard 0 signal and the standard 1 signal as the second state even signal; Based on the second selection odd signal, one of a standard 0 signal and a standard 1 signal is output as the second state odd signal.

8. The test circuit according to claim 5, characterized in that: The first signal unit includes a first trigger: a clock terminal of the first trigger receives the address jump pulse, an input terminal of the first trigger is connected to an inverting output terminal thereof, and a non-inverting output terminal of the first trigger outputs the parity indication signal; The second signal unit includes a first XOR gate and a second flip-flop; the first input end of the first XOR gate receives the parity indication signal, the second input end of the first XOR gate is connected to the positive phase output end of the second flip-flop, the output end of the first XOR gate outputs the first intermediate signal, the input end of the second flip-flop receives the first intermediate signal, the clock end of the second flip-flop receives the address jump pulse, and the positive phase output end of the second flip-flop outputs the read / write indication signal; The third signal unit includes a first AND gate, a second XOR gate and a third flip-flop; the first input end of the first AND gate receives the read / write indication signal, the second input end of the first AND gate receives the parity indication signal, the output end of the first AND gate is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the positive phase output end of the third flip-flop, the output end of the second XOR gate outputs the second intermediate signal, the input end of the third flip-flop receives the second intermediate signal, the clock end of the third flip-flop receives the address jump pulse, and the positive phase output end of the third flip-flop outputs the flip indication signal; The fourth signal unit includes a second AND gate, a third XOR gate, a fourth flip-flop, a fifth flip-flop and a fourth XOR gate; the first input end of the second AND gate is connected to the output end of the first AND gate, the second input end of the second AND gate receives the flip indication signal, the output end of the second AND gate is connected to the first input end of the third XOR gate, the second input end of the third XOR gate is connected to the positive phase output end of the fourth flip-flop, the output end of the third XOR gate outputs the third intermediate signal, the input end of the fourth flip-flop receives the third intermediate signal, the clock end of the fourth flip-flop receives the address jump pulse, the positive phase output end of the fourth flip-flop is connected to the input end of the fifth flip-flop, the clock end of the fifth flip-flop receives the preset system clock signal, the positive phase output end of the fifth flip-flop is connected to the first input end of the fourth XOR gate, the second input end of the fourth XOR gate is connected to the positive phase output end of the fourth flip-flop, and the output end of the fourth XOR gate outputs the topology indication signal.

9. The test circuit according to claim 8, characterized in that: In the case of 2A=12, B=3, C=5; Accordingly, the counting unit includes a sixth trigger, a fifth XOR gate, a seventh trigger, a third AND gate, a sixth XOR gate and an eighth trigger; The clock terminals of the sixth flip-flop, the seventh flip-flop and the eighth flip-flop receive the topology indication signal, the input terminal of the sixth flip-flop is connected to the inverting output terminal thereof, the positive-phase output terminal of the sixth flip-flop is connected to the first input terminal of the fifth XOR gate, the second input terminal of the fifth XOR gate is connected to the positive-phase output terminal of the seventh flip-flop, the output terminal of the fifth XOR gate is connected to the input terminal of the seventh flip-flop, the positive-phase output terminal of the seventh flip-flop is connected to the first input terminal of the third AND gate, the second input terminal of the third AND gate is connected to the positive-phase output terminal of the sixth flip-flop, the output terminal of the third AND gate is connected to the first input terminal of the sixth XOR gate, the second input terminal of the sixth XOR gate is connected to the positive-phase output terminal of the eighth flip-flop, and the output terminal of the sixth XOR gate is connected to the input terminal of the eighth flip-flop; The positive phase output terminal of the sixth flip-flop outputs the first sub-parameter of the first count value, the positive phase output terminal of the seventh flip-flop outputs the second sub-parameter of the first count value, and the positive phase output terminal of the eighth flip-flop outputs the third sub-parameter of the first count value.

10. The test circuit according to claim 7, characterized in that: The pre-processing unit includes a first logic unit, a second logic unit, a third logic unit and a fourth logic unit; An input end of the first logic unit receives C partial signals of the intermediate decoded signals, and an output end of the first logic unit outputs the first selected even signal; An input end of the second logic unit receives C partial signals of the intermediate decoded signals, and an output end of the second logic unit outputs the first selected odd signal; An input end of the third logic unit receives C partial signals of the intermediate decoded signals, and an output end of the third logic unit outputs the second selected even signal; An input end of the fourth logic unit receives C partial signals of the intermediate decoded signals, and an output end of the fourth logic unit outputs the second selected odd signal; When the intermediate decoded signals are different, the first selected even signal, the first selected odd signal, the second selected even signal and the second selected even signal are not completely the same.

11. The test circuit according to claim 7, wherein: The selection unit includes a first selector, a second selector, a third selector and a fourth selector; The first input terminal of the first selector receives the standard 1 signal, the second input terminal of the first selector receives the standard 0 signal, the control terminal of the first selector receives the first selection even signal, and the output terminal of the first selector outputs the first state even signal; The first input terminal of the second selector receives the standard 1 signal, the second input terminal of the second selector receives the standard 0 signal, the control terminal of the second selector receives the first selection odd signal, and the output terminal of the second selector outputs the first state odd signal; The first input terminal of the third selector receives the standard 0 signal, the second input terminal of the first selector receives the standard 1 signal, the control terminal of the third selector receives the second selection even signal, and the output terminal of the third selector outputs the second state even signal; The first input end of the fourth selector receives the standard 0 signal, the second input end of the fourth selector receives the standard 1 signal, the control end of the fourth selector receives the second selection odd signal, and the output end of the fourth selector outputs the second state odd signal.

12. The test circuit according to claim 6, wherein: The second logic unit includes a fifth selector and a sixth selector; a first input terminal of the fifth selector receives the first state even signal, a second input terminal of the fifth selector receives the first state odd signal, a control terminal of the fifth selector receives the parity indication signal, and an output terminal of the fifth selector outputs the first pre-selected signal; a first input terminal of the sixth selector receives the second state even signal, a second input terminal of the sixth selector receives the second state odd signal, a control terminal of the sixth selector receives the parity indication signal, and an output terminal of the sixth selector outputs the second pre-selected signal; The output unit includes a buffer, a third NOT gate and a seventh selector; the input end of the buffer receives the first pre-selection signal, and the output end of the buffer outputs the first state signal; the input end of the third NOT gate receives the second pre-selection signal, the output end of the third NOT gate is connected to the first input end of the seventh selector, the second input end of the seventh selector receives the second pre-selection signal, the control end of the seventh selector receives the flip indication signal, and the output end of the seventh selector outputs the second state signal.

13. The test circuit according to claim 9, wherein: All reset terminals of the first to eighth triggers receive a start signal; If the start signal instructs the test circuit to start working, the first trigger to the eighth trigger all perform a reset operation.

14. A memory, characterized in that: The test circuit comprises the test circuit according to any one of claims 1 to 13.

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