Semiconductor structure manufacturing method, semiconductor structure and CMOS circuit

Abstract

The embodiment of the present application provides a method for manufacturing a semiconductor structure, a semiconductor structure and a CMOS circuit, wherein the method for manufacturing the semiconductor structure comprises: providing a semiconductor substrate; wherein the semiconductor substrate comprises a semiconductor substrate and a buffer layer and a stress layer covering the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure is formed on the surface of the PMOS region; the buffer layer covering the side of the PMOS gate structure and the buffer layer covering the surface of the semiconductor substrate form an adjacent region; removing part of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residue on the surface of the adjacent region of the buffer layer away from the semiconductor substrate; performing an ion implantation process in the PMOS region; wherein the region where the ion implantation process is performed comprises a stress layer residue, so that the etching rate of the stress layer residue being etched is increased; etching to remove the stress layer residue. Through the embodiment of the present application, the electrical performance of the CMOS circuit as a whole is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a method for manufacturing a semiconductor structure, a semiconductor structure, and a CMOS circuit. Background Art

[0002] In the manufacturing process of chips with a process node of 90nm and below, stress memorization technique (SMT) is usually used to improve the electrical performance of transistors. Specifically, the SMT process can be performed after the source / drain ion implantation process is completed, and the carrier mobility is increased by inducing stress in the channel area of ​​the MOSFET, thereby accelerating the response speed of the MOSFET.

[0003] In the existing SMT process, inducing stress in the channel region of MOSFET is mainly achieved by the following methods: depositing a stress layer on the N-channel metal oxide semiconductor (NMOS) transistor and the P-channel metal oxide semiconductor (PMOS) transistor formed after the source / drain ion implantation, and then performing high temperature annealing, so as to transfer the stress to the channel region of MOSFET through the stress layer. However, for PMOS transistors, inducing stress in the channel region will lead to a decrease in carrier mobility, which in turn leads to a decrease in the response speed of PMOS. Therefore, in order to reduce the negative impact on the electrical performance of PMOS transistors, it is necessary to remove the stress layer covering the PMOS transistor before performing the high temperature annealing process.

[0004] At present, the stress layer covering the PMOS transistor is mainly removed by photolithography and dry etching processes. However, in the process of removing the stress layer by dry etching, there is over-etching or under-etching, and it is difficult to control the degree of removal of the stress layer, thereby affecting the electrical performance of the NMOS transistor or PMOS transistor, resulting in a decrease in the overall electrical performance of the complementary metal oxide semiconductor (CMOS) circuit. Summary of the invention

[0005] In view of this, multiple embodiments of the present application provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a CMOS circuit to improve the overall electrical performance of the CMOS circuit.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: providing a semiconductor substrate; wherein the semiconductor substrate comprises a semiconductor substrate and a buffer layer and a stress layer covering the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure protruding from the surface of the semiconductor substrate is formed on the surface of the PMOS region; the buffer layer covering the side of the PMOS gate structure forms an adjacent region with the buffer layer covering the surface of the semiconductor substrate; the stress layer is used to introduce stress into the semiconductor substrate; removing part of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residue in the adjacent region of the buffer layer away from the surface of the semiconductor substrate; performing an ion implantation process in the PMOS region; wherein the region where the ion implantation process is performed includes the stress layer residue, so that the etching rate of the stress layer residue is increased; and etching to remove the stress layer residue.

[0007] Optionally, in the semiconductor substrate, a PMOS lightly doped region is formed in the PMOS region; the step of performing an ion implantation process in the PMOS region includes: injecting ions into the PMOS region along the normal direction of the semiconductor substrate to form a PMOS source doping region, a PMOS drain doping region, and a PMOS transition doping region located between the PMOS lightly doped region and the PMOS source doping region and between the PMOS lightly doped region and the PMOS drain doping region in the PMOS region; wherein, under the blocking effect of the residual portion of the stress layer, the ion doping concentration of the PMOS transition doping region is higher than the ion doping concentration of the PMOS lightly doped region, and is lower than the ion doping concentration of the PMOS source doping region and the ion doping concentration of the PMOS drain doping region.

[0008] Optionally, the step of providing a semiconductor base includes: providing a semiconductor substrate; wherein the semiconductor substrate includes an NMOS region and a PMOS region; an NMOS gate structure protruding from the surface of the semiconductor substrate is formed on the surface of the NMOS region; an ion implantation process is performed in the NMOS region to form an NMOS transistor in the NMOS region; and a buffer layer and a stress layer covering the NMOS region and the PMOS region are sequentially formed on the semiconductor substrate.

[0009] Optionally, the buffer layer has a thickness of 100-200Å.

[0010] Optionally, before the step of removing part of the stress layer covering the PMOS region in the semiconductor substrate, it also includes: forming a hard mask layer covering the NMOS region and the PMOS region on the stress layer; and removing the hard mask layer covering the PMOS region to expose the stress layer covering the PMOS region.

[0011] Optionally, the hard mask layer includes a first sub-hard mask layer and a second sub-hard mask layer; the step of forming a hard mask layer covering the NMOS region and the PMOS region on the stress layer includes: sequentially forming a first sub-hard mask layer and a second sub-hard mask layer covering the NMOS region and the PMOS region on the stress layer; wherein the material of the first sub-hard mask layer is amorphous carbon; and the material of the second sub-hard mask layer is polycrystalline silicon.

[0012] Optionally, after the step of etching away the residual portion of the stress layer, it also includes: using a wet etching process to remove the second sub-hard mask layer covering the NMOS region; using an ashing process to remove the first sub-hard mask layer covering the NMOS region to expose the stress layer covering the NMOS region.

[0013] Optionally, a dry etching process is used to remove a portion of the stress layer covering the PMOS region in the semiconductor substrate; and a wet etching process is used to etch away the remaining portion of the stress layer.

[0014] In another aspect, an embodiment of the present application provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method described in the above embodiment.

[0015] In another aspect, an embodiment of the present application provides a CMOS circuit, wherein the CMOS circuit includes a semiconductor structure manufactured by the method for manufacturing a semiconductor structure described in the above embodiment.

[0016] In multiple embodiments provided in the present application, an area where an ion implantation process is performed in a PMOS region of a semiconductor substrate includes an unremoved stress layer residue on the PMOS region, so that the chemical properties of the stress layer residue are changed due to the influence of ion doping, thereby increasing the etching rate of the stress layer residue in the process of etching away the stress layer residue, and then etching away the stress layer residue, thereby achieving unexpected effects including: completely removing the stress layer in the PMOS region without damaging the device, reducing the influence of the stress layer removal on the electrical performance of the NMOS transistor or the PMOS transistor, and improving the overall electrical performance of the CMOS circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0019] Figure 2 A schematic diagram of a semiconductor substrate provided for one embodiment of the present application.

[0020] Figure 3 A schematic diagram of a semiconductor substrate provided for one embodiment of the present application.

[0021] Figure 4 A schematic diagram of forming a hard mask layer on a semiconductor substrate is provided according to an embodiment of the present application.

[0022] Figure 5 A schematic diagram of removing a hard mask layer and a portion of a stress layer covering a PMOS region and forming a stress layer residue in an adjacent region of a buffer layer away from a surface of a semiconductor substrate provided in an embodiment of the present application.

[0023] Figure 6 A schematic diagram of performing an ion implantation process in a PMOS region is provided for one embodiment of the present application.

[0024] Figure 7 A schematic diagram of removing the residual portion of the stress layer provided in one embodiment of the present application.

[0025] Figure 8 A schematic diagram of removing a hard mask layer covering an NMOS region is provided for one embodiment of the present application.

[0026] Structure number description

[0027] 100. semiconductor substrate; 101. substrate; 102. isolation layer; 110. NMOS region; 111. first sub-NMOS lightly doped region; 112. second sub-NMOS lightly doped region; 113. NMOS source doping region; 114. NMOS drain doping region; 115. NMOS gate structure; 120. PMOS region; 121. first sub-PMOS lightly doped region; 122. second sub-PMOS lightly doped region; 123. PMOS gate structure; 124. PMOS source doping region; 125. PMOS drain doping region; 126. PMOS transition doping region; 130. separation region; 140. buffer layer; 150. stress layer; 151. stress layer residue; 160. hard mask layer; 161. first sub-hard mask layer; 162. second sub-hard mask layer. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0029] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0030] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0031] At present, the process of removing the stress layer covering the PMOS transistor by using photolithography and dry etching processes generally includes the following process steps: first, a stress layer is deposited on a semiconductor substrate on which an NMOS transistor and a PMOS transistor are formed, then a photoresist is coated on the stress layer, and the photoresist in the PMOS transistor area is removed by developing exposure to expose the stress layer in the PMOS transistor area, and finally, the stress layer in the PMOS transistor area is removed by dry etching.

[0032] In the related art, in order to completely remove the stress layer in the PMOS transistor area, an over-etching method is usually used when performing the dry etching step. However, over-etching will inevitably cause damage or destruction to the area that has been etched. In order to reduce the damage caused by over-etching to the device, under-etching can also be used when performing the dry etching step, but under-etching may cause stress layer residue in the corner area formed by the side of the PMOS gate structure and the surface of the semiconductor substrate, resulting in the response speed of the PMOS transistor still being affected by the stress layer and reduced.

[0033] In order to reduce the damage of over-etching to the device and reduce the adverse effects of under-etching on the performance of the PMOS transistor, a buffer layer can be deposited before depositing the stress layer, and then the stress layer in the PMOS transistor area can be removed by over-etching. In order to give full play to the protective effect of the buffer layer on the device, the buffer layer needs to have a large thickness. However, a thicker buffer layer will reduce the stress transferred to the channel area of ​​the NMOS transistor, reduce the degree of improvement of the carrier mobility of the NMOS transistor, and the degree of acceleration of the response speed of the NMOS transistor is difficult to achieve as expected.

[0034] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure, in which an ion implantation process is performed in a PMOS region of a semiconductor substrate, including an unremoved stress layer residue on the PMOS region, so that the chemical properties of the stress layer residue are changed by the influence of ion doping, so that in the process of etching and removing the stress layer residue, the etching rate of the stress layer residue is increased, and then the stress layer residue is etched and removed, so that when the buffer layer thickness is small, the stress layer residue can be completely removed without damaging the device, thereby reducing the influence of the stress layer removal on the electrical performance of the NMOS transistor or the PMOS transistor, and improving the overall electrical performance of the CMOS circuit.

[0035] See also Figure 1 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The manufacturing method may include the following steps.

[0036] S110: providing a semiconductor substrate.

[0037] See also Figure 2 and Figure 3 In the present embodiment, the semiconductor base may include a semiconductor substrate 100 and a buffer layer 140 and a stress layer 150 covering the semiconductor substrate 100. Specifically, the step of providing the semiconductor base may include: providing the semiconductor substrate 100; performing an ion implantation process in the NMOS region 110 included in the semiconductor substrate 100 to form an NMOS transistor in the NMOS region 110; and sequentially forming the buffer layer 140 and the stress layer 150 covering the semiconductor substrate 100 on the semiconductor substrate 100.

[0038] In the related art, since the buffer layer 140 and the stress layer 150 are formed on the surface of the NMOS transistor and the PMOS transistor after ion implantation, even under the protection of the buffer layer 140, there is still a risk of damaging the PMOS transistor by removing the stress layer 150 on the surface of the PMOS transistor by over-etching. To solve the above problem, the buffer layer 140 and the stress layer 150 can be formed on the semiconductor substrate 100 on which the NMOS transistor has been formed but the PMOS transistor has not been formed, so as to reduce the impact of the process step of removing the stress layer 150 covering the PMOS region 120 on the performance of the PMOS transistor and the NMOS transistor.

[0039] In some embodiments, the semiconductor substrate 100 may include an NMOS region 110 for forming an NMOS transistor and a PMOS region 120 for forming a PMOS transistor. Specifically, the semiconductor substrate 100 may include a substrate 101 and an isolation layer 102 disposed on the surface of the substrate 101. The substrate 101 may serve as a support for transistors and other semiconductor components. Considering factors such as dielectric loss requirements, manufacturing processes, and manufacturing costs, the material of the substrate 101 may be selected from silicon or sapphire. The isolation layer 102 may be used to isolate the electric field between the MOS transistor gate structure and the substrate 101 to reduce interference and leakage of carriers. The material of the isolation layer 102 may be selected from insulating materials such as silicon nitride or silicon oxide. The embodiments of the present application do not specifically limit the material of the substrate 101 and the material of the isolation layer 102.

[0040] In the present embodiment, an NMOS gate structure 115 protruding from the surface of the semiconductor substrate 100 is formed on the surface of the NMOS region 110, and a PMOS gate structure 123 protruding from the surface of the semiconductor substrate 100 is formed on the surface of the PMOS region 120. Specifically, the NMOS gate structure 115 can be formed on the surface of the isolation layer 102 of the NMOS region 110 and protrude from the surface of the isolation layer 102, and the NMOS gate structure 115 can include an NMOS gate, a first NMOS gate sidewall and a second NMOS gate sidewall. Similarly, the PMOS gate structure 123 can be formed on the surface of the isolation layer 102 of the PMOS region 120 and protrude from the surface of the isolation layer 102, and the PMOS gate structure 123 can include a PMOS gate, a first PMOS gate sidewall and a second PMOS gate sidewall.

[0041] In this embodiment, a first sub-NMOS lightly doped region 111 and a second sub-NMOS lightly doped region 112 may be formed in the substrate 101 of the NMOS region 110. Specifically, the first sub-NMOS lightly doped region 111 and the second sub-NMOS lightly doped region 112 may be formed by ion implantation of the NMOS region 110 based on the first NMOS gate sidewall. The first sub-NMOS lightly doped region 111 and the second sub-NMOS lightly doped region 112 may be used to reduce the electric field gradient, so as to reduce the electric field concentration near the NMOS source doping region 113 and the NMOS drain doping region 114, reduce the hot carrier effect, and improve the electrical performance of the NMOS transistor. Correspondingly, a first sub-PMOS lightly doped region 121 and a second sub-PMOS lightly doped region 122 may be formed in the substrate 101 of the PMOS region 120. The formation method and function of the first sub-PMOS lightly doped region 121 and the second sub-PMOS lightly doped region 122 are similar to those of the first sub-NMOS lightly doped region 111 and the second sub-NMOS lightly doped region 112, and will not be repeated here.

[0042] In some embodiments, the semiconductor substrate 100 may further be provided with a separation region 130 for separating the NMOS region 110 and the PMOS region 120. For example, the separation region 130 may be a shallow trench isolation (STI) structure for reducing leakage.

[0043] In some embodiments, the buffer layer 140 can be used to protect the semiconductor substrate 100 during the process of removing the stress layer 150. Specifically, the material of the buffer layer 140 can be an oxide, for example, silicon dioxide, and the embodiment of the present application does not impose any specific restrictions on the material of the buffer layer 140. Since the PMOS gate structure 123 protrudes from the surface of the isolation layer 102, a corner is formed in the area where the PMOS gate structure 123 contacts the isolation layer 102. Therefore, the buffer layer 140 covering the side of the PMOS gate structure 123 and the buffer layer 140 covering the surface of the semiconductor substrate 100, that is, the buffer layer 140 covering the surface of the isolation layer 102, form an adjacent area.

[0044] In some embodiments, the stress layer 150 can be used to introduce stress into the semiconductor substrate 100. Specifically, considering the stress characteristic requirements, manufacturing process, manufacturing cost and other factors, the material of the stress layer 150 can be silicon nitride (SiN), and the embodiment of the present application does not specifically limit the material of the stress layer 150.

[0045] In some embodiments, an ion implantation process is performed in the NMOS region 110 to form an NMOS transistor in the NMOS region 110 . N-type ions, for example, phosphorus ions or arsenic ions, may be implanted into the NMOS region 110 along a normal direction of the semiconductor substrate 100 to form an NMOS source doping region 113 and an NMOS drain doping region 114 in the NMOS region 110 .

[0046] In some embodiments, a buffer layer 140 and a stress layer 150 covering the NMOS region 110 and the PMOS region 120 are sequentially formed on the semiconductor substrate 100 , and the buffer layer 140 and the stress layer 150 covering the NMOS region 110 and the PMOS region 120 are sequentially deposited on the isolation layer 102 .

[0047] By forming a buffer layer 140 and a stress layer 150 on a semiconductor substrate 100 on which an NMOS transistor has been formed but on which a PMOS transistor has not been formed, the risk of damaging the PMOS transistor due to removal of the stress layer 150 covering the PMOS region 120 can be reduced, and the impact of removing the stress layer 150 covering the PMOS region 120 on the performance of the NMOS transistor and the PMOS transistor can be reduced.

[0048] In the related art, in order to reduce the damage of over-etching to the PMOS transistor in the process of completely removing the stress layer 150 on the PMOS transistor, it is necessary to provide a thicker buffer layer 140, for example, a buffer layer 140 with a thickness of 200-400Å. However, an overly thick buffer layer 140 reduces the stress transfer effect, resulting in a decrease in the performance of the NMOS transistor. To solve the above problem, in some embodiments, the thickness of the buffer layer 140 can be 100-200Å to reduce the adverse effect of the thickness of the buffer layer 140 on the stress transfer effect.

[0049] S120: removing a portion of the stress layer covering the PMOS region in the semiconductor substrate, and forming a residual portion of the stress layer in an adjacent region of the buffer layer away from the surface of the semiconductor substrate.

[0050] See also Figure 4 and Figure 5 In this embodiment, a dry etching process may be used to remove a portion of the stress layer 150 in the semiconductor substrate that covers the PMOS region 120. The embodiment of the present application does not specifically limit the gas used for dry etching.

[0051] In the related art, in order to protect the stress layer 150 covering the NMOS transistor during the process of removing the stress layer 150 covering the PMOS transistor, it is usually necessary to coat a photoresist layer covering the NMOS transistor and the PMOS transistor on the stress layer 150, and then remove the photoresist layer covering the PMOS transistor by developing and exposing, so that the stress layer 150 covering the PMOS transistor is exposed. Due to the high cost of photoresist materials, the process cost of the above method is high. In order to reduce the process cost and save the amount of photoresist used, a hard mask layer 160 can be used instead of a photoresist layer as a protective layer for the stress layer 150 covering the NMOS transistor.

[0052] In some embodiments, before the step of removing a portion of the stress layer 150 covering the PMOS region 120 in the semiconductor substrate, the step may also include: forming a hard mask layer 160 covering the NMOS region 110 and the PMOS region 120 on the stress layer 150; and removing the hard mask layer 160 covering the PMOS region 120 to expose the stress layer 150 covering the PMOS region 120.

[0053] In this embodiment, in the process of removing part of the stress layer 150 covering the PMOS region 120 using a dry etching process, the hard mask layer 160 can serve as a protective layer for the stress layer 150 covering the NMOS region 110 to reduce the impact of the dry etching on the stress layer 150 covering the NMOS region 110.

[0054] In some embodiments, during the ion implantation process in the PMOS region 120 , the hard mask layer 160 may serve as an ion implantation barrier layer for the NMOS region 110 , and is used to prevent ions implanted in the PMOS region 120 from entering the NMOS region 110 , thereby reducing interference of the ion implantation in the PMOS region 120 on the NMOS region 110 .

[0055] In some embodiments, the hard mask layer 160 may be a single layer, and the material of the hard mask layer 160 may be amorphous carbon.

[0056] In order to enhance the protective effect of the hard mask layer 160 on the stress layer 150 covering the NMOS region 110, in the present embodiment, the hard mask layer 160 may include a first sub-hard mask layer 161 and a second sub-hard mask layer 162. Specifically, the material of the first sub-hard mask layer 161 may be amorphous carbon, and the material of the second sub-hard mask layer 162 may be polysilicon. Accordingly, the step of forming the hard mask layer 160 covering the NMOS region 110 and the PMOS region 120 on the stress layer 150 may include: sequentially forming the first sub-hard mask layer 161 and the second sub-hard mask layer 162 covering the NMOS region 110 and the PMOS region 120 on the stress layer 150. Specifically, the first sub-hard mask layer 161 and the second sub-hard mask layer 162 may be sequentially deposited on the stress layer 150.

[0057] In this embodiment, the hard mask layer 160 covering the PMOS region 120 may be removed by a dry etching process, so that the stress layer 150 covering the PMOS region 120 is exposed.

[0058] S130: performing an ion implantation process in the PMOS region; wherein the region where the ion implantation process is performed includes a stress layer residual portion, so that an etching rate of the stress layer residual portion is increased.

[0059] See also Figure 6 . In order to reduce the damage to the PMOS transistor caused by the dry over-etching used in the related art to remove the stress layer 150 covering the PMOS region 120, it is possible to consider using wet etching to remove the stress layer residue 151. However, since it is difficult to control the etching direction and precision in wet etching, directly using the wet etching process to remove the stress layer residue 151 may damage the stress layer 150 covering the NMOS region 110. In order to reduce the impact of using wet etching to remove the stress layer residue 151 on the stress layer 150 in the NMOS region 110, the chemical properties of the stress layer residue 151 can be changed by ion doping to make it easier to remove by wet etching. In order to reduce the impact of impurity ion doping on the performance of the PMOS transistor, the stress layer residue 151 can be included in the area where the ion implantation process is performed, so that the stress layer residue 151 is doped with P-type ions, so that in the process of removing the stress layer residue 151 by wet etching, the etching rate of the stress layer residue 151 is increased.

[0060] In this embodiment, the step of performing an ion implantation process in the PMOS region 120 may include: injecting ions into the PMOS region 120 along the normal direction of the semiconductor substrate to form a PMOS source doping region 124, a PMOS drain doping region 125, and a PMOS transition doping region 126 located between the PMOS lightly doped region and the PMOS source doping region 124 and between the PMOS lightly doped region and the PMOS drain doping region 125 in the PMOS region 120.

[0061] In the present embodiment, during the process of injecting P-type ions into the PMOS region 120, for example, during the process of injecting boron ions into the PMOS region 120, due to the blocking effect of the stress layer residue 151, some ions remain in the stress layer residue 151 and do not enter the PMOS region 120 of the semiconductor substrate 100, thereby forming a PMOS transition doping region 126 between the PMOS source doping region 124 and the first sub-PMOS lightly doped region 121, wherein the ion doping concentration is higher than that of the first sub-PMOS lightly doped region 121 and lower than that of the PMOS source doping region 124, and forming a PMOS transition doping region 126 between the PMOS drain doping region 125 and the second sub-PMOS lightly doped region 122, wherein the ion doping concentration is higher than that of the second sub-PMOS lightly doped region 122 and lower than that of the PMOS drain doping region 125, so as to reduce the electric field gradient, alleviate the hot carrier effect, and improve the electrical performance of the PMOS transistor.

[0062] S140: etching to remove the remaining portion of the stress layer.

[0063] See also Figure 7 In this embodiment, a wet etching process may be used to remove the stress layer residual portion 151. Specifically, the wet etching solution may be hydrofluoric acid, phosphoric acid, or the like.

[0064] In the present embodiment, the hard mask layer 160 can be used as a protective layer for the stress layer 150 covering the NMOS region 110 to reduce the influence of wet etching on the stress layer 150 covering the NMOS region 110. Taking hot phosphoric acid as an example of a wet etching solution, since the stress layer residue 151 is doped with P-type ions, its etching rate in hot phosphoric acid is relatively fast, while the stress layer 150 covering the NMOS region 110 is not doped with P-type ions due to the protective effect of the hard mask layer 160, and the contact surface with the hot phosphoric acid is only the side surface, and the etching rate is relatively low. Therefore, when the stress layer residue 151 is completely removed by hot phosphoric acid, the stress layer 150 covering the NMOS region 110 only has a small amount of consumption on the side surface, which has little effect on the performance of the NMOS transistor. Specifically, the etching rate of the stress layer residue 151 doped with P-type ions in hot phosphoric acid can be 2 to 3 times the etching rate of the stress layer 150 covering the NMOS region 110 in hot phosphoric acid.

[0065] In some embodiments, in order to facilitate the subsequent high temperature annealing process to induce stress in the channel region of the MOS transistor, the hard mask layer 160 covering the NMOS region 110 needs to be removed.

[0066] When the hard mask layer 160 is a single layer and made of amorphous carbon, after etching away the stress layer residue 151 , the hard mask layer 160 covering the NMOS region 110 may be removed by an ashing process to expose the stress layer 150 covering the NMOS region 110 .

[0067] Please also read Figure 7 and Figure 8 . In the case where the hard mask layer 160 includes a first sub-hard mask layer 161 and a second sub-hard mask layer 162, and the material of the first sub-hard mask layer 161 is amorphous carbon, and the material of the second sub-hard mask layer 162 is polysilicon, after the step of etching to remove the stress layer residue 151, it may also include: using a wet etching process to remove the second sub-hard mask layer 162 covering the NMOS region 110; using an ashing process to remove the first sub-hard mask layer 161 covering the NMOS region 110 to expose the stress layer 150 covering the NMOS region 110. Specifically, the wet etching solution for removing the second sub-hard mask layer 162 covering the NMOS region 110 using the wet etching process may be tetramethylammonium hydroxide (TMAH).

[0068] In an embodiment of the present application, for a semiconductor base including a semiconductor substrate, a buffer layer and a stress layer, a portion of the stress layer covering the PMOS region is removed, and a stress layer residue is formed on the surface of the adjacent region of the buffer layer away from the semiconductor substrate, and then an ion implantation process is performed in the PMOS region of the semiconductor substrate. The region where the ion implantation process is performed includes the stress layer residue that has not been removed on the PMOS region, so that the chemical properties of the stress layer residue are changed due to the influence of ion doping, thereby increasing the etching rate of the stress layer residue in the process of removing the stress layer residue by wet etching, and then removing the stress layer residue by wet etching, and the unexpected effects achieved include: when the buffer layer thickness is small, the stress layer residue is completely removed without damaging the device, reducing the influence of the stress layer removal on the electrical performance of the NMOS transistor or the PMOS transistor, and improving the overall electrical performance of the CMOS circuit.

[0069] An embodiment of the present application provides a semiconductor structure, which can be manufactured by the semiconductor structure manufacturing method described in the above embodiment.

[0070] An embodiment of the present application provides a CMOS circuit, which may include a semiconductor structure manufactured by the semiconductor structure manufacturing method described in the above embodiment.

[0071] The technical effects of the semiconductor structure and CMOS circuit described in the above embodiments can be explained by referring to other embodiments of the present application, and will not be repeated here.

[0072] It should be understood that the specific examples in this application are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the present invention.

[0073] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0074] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0075] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0076] In several embodiments provided in this application, it should be understood that the disclosed semiconductor structure or CMOS circuit can be implemented in other ways. For example, the embodiments of the semiconductor structure or CMOS circuit described above are merely illustrative.

[0077] The above is only a specific embodiment of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: A semiconductor substrate is provided; wherein the semiconductor substrate comprises a semiconductor substrate and a buffer layer and a stress layer covering the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure protruding from the surface of the semiconductor substrate is formed on the surface of the PMOS region; a buffer layer covering the side of the PMOS gate structure and a buffer layer covering the surface of the semiconductor substrate form an adjacent region; the stress layer is used to introduce stress into the semiconductor substrate; Removing a portion of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residual portion in an adjacent region of the buffer layer away from the surface of the semiconductor substrate; Performing an ion implantation process in the PMOS region; wherein the region where the ion implantation process is performed includes the stress layer residual portion, so that the etching rate of the stress layer residual portion is increased; The residual portion of the stress layer is removed by etching.

2. The method according to claim 1, characterized in that In the semiconductor substrate, a PMOS lightly doped region is formed in the PMOS region; and the step of performing an ion implantation process in the PMOS region includes: Ions are injected into the PMOS region along the normal direction of the semiconductor substrate to form a PMOS source doping region, a PMOS drain doping region, and a PMOS transition doping region located between the PMOS lightly doped region and the PMOS source doping region and between the PMOS lightly doped region and the PMOS drain doping region in the PMOS region; wherein, under the blocking effect of the residual portion of the stress layer, the ion doping concentration of the PMOS transition doping region is higher than the ion doping concentration of the PMOS lightly doped region, and is lower than the ion doping concentration of the PMOS source doping region and the ion doping concentration of the PMOS drain doping region.

3. The method according to claim 1, characterized in that The step of providing a semiconductor substrate comprises: Providing a semiconductor substrate; wherein the semiconductor substrate comprises an NMOS region and a PMOS region; an NMOS gate structure protruding from the surface of the semiconductor substrate is formed on the surface of the NMOS region; performing an ion implantation process in the NMOS region to form an NMOS transistor in the NMOS region; A buffer layer and a stress layer covering the NMOS region and the PMOS region are sequentially formed on the semiconductor substrate.

4. The method according to claim 1, characterized in that: The thickness of the buffer layer is 100-200Å.

5. The method according to claim 1, characterized in that Before the step of removing a portion of the stress layer covering the PMOS region in the semiconductor substrate, the method further comprises: forming a hard mask layer covering the NMOS region and the PMOS region on the stress layer; The hard mask layer covering the PMOS region is removed to expose the stress layer covering the PMOS region.

6. The method according to claim 5, characterized in that The hard mask layer includes a first sub-hard mask layer and a second sub-hard mask layer; the step of forming a hard mask layer covering the NMOS region and the PMOS region on the stress layer includes: A first sub-hard mask layer and a second sub-hard mask layer covering the NMOS region and the PMOS region are sequentially formed on the stress layer; wherein the material of the first sub-hard mask layer is amorphous carbon; and the material of the second sub-hard mask layer is polysilicon.

7. The method according to claim 6, characterized in that After the step of removing the residual portion of the stress layer by etching, the method further comprises: Removing the second sub-hard mask layer covering the NMOS region by a wet etching process; The first sub-hard mask layer covering the NMOS region is removed by an ashing process to expose the stress layer covering the NMOS region.

8. The method according to claim 1, characterized in that: A dry etching process is used to remove a portion of the stress layer covering the PMOS region in the semiconductor substrate; and a wet etching process is used to etch away the remaining portion of the stress layer.

9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8.

10. A CMOS circuit, characterized in that: The CMOS circuit comprises a semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8.

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