Transistor, semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a transistor, a semiconductor device and a manufacturing method thereof. In the transistor provided by the embodiment of the invention, the metal structure of which the work function is smaller than that of the first electrode part is arranged on the side wall of the first electrode part, so that the Fermi level of the surface of one end, close to the metal structure, of the first electrode part or the contact interface of the first electrode part and the metal structure moves upwards; the Fermi level of the metal structure and the Fermi level of the first electrode part are equal or close at the close position or the contact interface of the metal structure and the first electrode part, so that a conduction band and a valence band on the surface of the first electrode part are driven to be bent, the concentration of carriers on the surface of the first electrode part is increased, the resistance on the surface of the first electrode part can be reduced, and the service life of the first electrode part is prolonged. Furthermore, under the condition that the first electrode part of the transistor is connected with the bit line, the contact resistance between the surface of the first electrode part and the bit line can be reduced, so that ohmic contact is formed. And meanwhile, the first electrode part does not need to be heavily doped, so that the production efficiency and the yield of the transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a transistor, a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, semiconductor devices with vertical channel transistors are increasingly used.

[0003] However, in the manufacturing process of a semiconductor device with a vertical channel transistor, an array of semiconductor columns is first formed. Since the spacing between adjacent semiconductor columns is small, it is difficult to form a heavily doped region at the bottom of the semiconductor column during the process of doping the bottom of the semiconductor column to form a source or a drain through an ion implantation process, resulting in a larger resistance of the formed source or drain, resulting in poor performance of the transistor. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a transistor, a semiconductor device and a manufacturing method thereof, so as to solve the technical problem of large source or drain resistance of vertical channel transistors in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a transistor, including:

[0006] The semiconductor column comprises a first electrode portion and a channel portion stacked in sequence in a direction perpendicular to and away from the substrate, wherein the doping concentration of the first electrode portion is not greater than the doping concentration of the channel portion;

[0007] The metal structure is disposed on at least a portion of the sidewall of the first electrode portion, and the work function of the metal structure is smaller than the work function of the first electrode portion.

[0008] In a second aspect, an embodiment of the present application provides a semiconductor device, comprising: a plurality of word lines, a plurality of bit lines, and a plurality of transistors arranged in an array as provided in the first aspect;

[0009] The transistor is arranged on a side of the bit line away from the substrate; the bit line extends along a first direction, and each bit line is connected to a first electrode portion of a column of transistors arranged along the first direction;

[0010] The word lines extend along the second direction, and each word line is connected to the gates of transistors in the same row arranged along the second direction; the first direction is perpendicular to the second direction.

[0011] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0012] forming a plurality of semiconductor pillars arranged in an array on one side of the substrate;

[0013] forming a groove extending along a first direction below the first electrode portion in each semiconductor column;

[0014] forming a bit line in the groove;

[0015] A metal structure is formed at the side wall of the first electrode portion; a work function of the metal structure is not greater than a work function of the first electrode portion.

[0016] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0017] In the transistor provided in the embodiment of the present application, a metal structure having a work function smaller than that of the first electrode portion is provided at the side wall of the first electrode portion, so that the Fermi level of the first electrode portion at the surface of one end close to the metal structure or at the contact interface with the metal structure is shifted upward, so that the Fermi level of the metal structure and the Fermi level of the first electrode portion are equal or close to each other at the interface where the two are close to each other or in contact, thereby driving the bending of the conduction band and the valence band on the surface of the first electrode portion, increasing the concentration of carriers at the surface of the first electrode portion, thereby reducing the resistance of the surface of the first electrode portion, and further, when the first electrode portion of the transistor is connected to the bit line, the contact resistance between the surface of the first electrode portion and the bit line can be reduced, so that ohmic contact is formed between the first electrode portion and the bit line.

[0018] Moreover, there is no need to heavily dope the first electrode portion. By setting a metal structure with a work function smaller than that of the first electrode portion at the side wall of the first electrode portion, the resistance at the contact interface between the first electrode portion and the bit line can be significantly reduced, so that an ohmic contact is formed at the contact interface. This can avoid heavily doping the first electrode portion, reduce the difficulty of manufacturing the transistor, and improve the production efficiency and yield of the transistor.

[0019] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A schematic top view of a transistor provided in an embodiment of the present application;

[0022] Figure 2 Provided in the embodiments of this application Figure 1 A schematic cross-sectional view of the transistor at AA shown;

[0023] Figure 3a Provided in the embodiments of this application Figure 1An energy band diagram of the transistor before the metal structure and the first electrode portion are in contact or close to each other;

[0024] Figure 3b Provided in the embodiments of this application Figure 1 An energy band diagram of the transistor after the metal structure and the first electrode portion are in contact or close to each other;

[0025] Figure 4 A schematic diagram of the structure of another transistor provided in an embodiment of the present application;

[0026] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0027] Figure 6 A schematic top view of a film structure after a plurality of semiconductor pillars arranged in an array are formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a cross-sectional film layer at point aa after forming a first trench in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of a cross-sectional film layer at point aa after a groove is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of a cross-sectional film layer at point aa after forming a bit line in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0031] Fig.10 A schematic diagram of a cross-sectional film layer at point aa after a metal structure is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0032] Fig.11 A schematic diagram of a cross-sectional film layer at point aa after forming a first isolation structure in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0033] Fig.12 A schematic diagram of a cross-sectional film layer at point aa after forming a second dielectric structure in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0034] Fig.13 A schematic diagram of a cross-sectional film layer at point aa after forming a second isolation structure in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0035] Fig.14 A schematic diagram of a cross-sectional film layer at point aa after a gap is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0036] Fig.15 A schematic diagram of a cross-sectional film layer at point aa after a gate dielectric layer is formed in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0037] Fig.16 A schematic diagram of a cross-sectional film layer at point aa after forming a word line including a gate in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0038] Description of reference numerals:

[0039] 100-substrate;

[0040] 101 - first groove; 1021 - first dielectric structure; 1022 - second dielectric structure; 103 - groove;

[0041] 104-first isolation structure; 105-second isolation structure; 106-gap;

[0042] 10-semiconductor column; 11-first electrode portion; 12-channel portion; 14-second electrode portion;

[0043] 13-electrode; 20-metal structure; 31-gate dielectric layer; 32-gate; 40-dielectric structure;

[0044] 50 - bit line; 51 - metal silicide structure; 52 - connection structure. DETAILED DESCRIPTION

[0045] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0046] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or may refer to the connection relationship between the element and the other element established through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0048] Work function: refers to the minimum energy required to move an electron from the inside of a solid to the surface of the object.

[0049] However, in the manufacturing process of a semiconductor device with a vertical channel transistor, an array of semiconductor columns is first formed on one side of a substrate. The bottom of the semiconductor column is at a large distance from the top of the semiconductor column, and the spacing between adjacent semiconductor columns is small. In the process of heavily doping the bottom of the semiconductor column to form an electrode (one of the source or drain), ions are difficult to inject into the bottom of the semiconductor column, resulting in a low doping concentration at the bottom of the semiconductor column, resulting in a large resistance of the electrode, which seriously affects the performance of the transistor.

[0050] The transistor, semiconductor device and manufacturing method thereof provided in the present application are intended to solve the above technical problems of the prior art.

[0051] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0052] The present application embodiment provides a transistor, the schematic diagram of which is as follows Figure 1 and Figure 2 As shown, the transistor includes a semiconductor column 10 and a metal structure 20 .

[0053] In an embodiment of the present application, the semiconductor column 10 includes a first electrode portion 11 and a channel portion 12 stacked in sequence in a direction vertically and away from the substrate 100, and the doping concentration of the first electrode portion 11 is not greater than the doping concentration of the channel portion 12; the metal structure 20 is arranged on the side wall of at least a portion of the first electrode portion 11, and the work function of the metal structure 20 is less than the work function of the first electrode portion 11.

[0054] In the transistor provided in the embodiment of the present application, a metal structure 20 having a work function smaller than that of the first electrode portion 11 is provided at the side wall of the first electrode portion 11, so that the Fermi level of the first electrode portion 11 at the surface of one end close to the metal structure 20 or at the contact interface with the metal structure 20 is shifted upward, so that the Fermi level of the metal structure 20 and the Fermi level of the first electrode portion 11 are equal or close to each other at the interface where the two are close to each other or in contact, thereby driving the conduction band and the valence band on the surface of the first electrode portion 11 to bend, so that the concentration of carriers at the surface of the first electrode portion 11 is increased, thereby reducing the resistance of the surface of the first electrode portion 11, and further, when the first electrode portion 11 of the transistor is connected to the bit line, the contact resistance between the surface of the first electrode portion 11 and the bit line can be reduced, so that an ohmic contact is formed between the first electrode portion 11 and the bit line.

[0055] Moreover, there is no need to heavily dope the first electrode portion 11. By providing a metal structure 20 having a work function smaller than that of the first electrode portion 11 at the side wall of the first electrode portion 11, the resistance at the contact interface between the first electrode portion 11 and the bit line can be significantly reduced, so that ohmic contact is achieved at the contact interface. This avoids heavily doping the first electrode portion 11, reduces the difficulty of manufacturing the transistor, and improves the production efficiency and yield of the transistor.

[0056] In the embodiment of the present application, in order to facilitate the description of the positional relationship between various structures in the transistor, Figure 1 and Figure 2 The substrate 100 is introduced as a reference system.

[0057] In the embodiment of the present application, the semiconductor column 10 includes a first electrode portion 11 and a channel portion 12. Figure 2 As shown, along a direction perpendicular to and away from the substrate 100 , the first electrode portion 11 and the channel portion 12 are sequentially stacked on one side of the substrate 100 , that is, the channel portion 12 is located on a side of the first electrode portion 11 away from the substrate 100 .

[0058] Optionally, the doping concentration of the first electrode portion 11 is not greater than the doping concentration of the channel portion 12. Optionally, the doping concentration of the first electrode portion 11 is the same as the doping concentration of the channel portion 12, so that the first electrode portion 11 and the second electrode portion 12 can be formed simultaneously based on the same process, which can simplify the manufacturing process of the transistor.

[0059] Optionally, the first electrode portion 11 is a portion of the semiconductor column 10 corresponding to a source / drain of a transistor.

[0060] In the present application embodiment, Figure 2 As shown, a metal structure 20 is provided at the side wall of the first electrode portion 11, and the work function of the metal structure 20 is smaller than the work function of the first electrode portion 11. Electrons will flow from the metal to the semiconductor, so that the Fermi level at the contact interface between the first electrode portion 11 and the metal structure 20 moves up, and the energy band at the surface of the first electrode portion 11 is bent, which can increase the concentration of carriers at the surface of the first electrode portion 11, thereby significantly reducing the resistance at the surface of the first electrode portion 11, so that when the transistor is in the on state, the resistance between the channel portion 12 and the surface of the first electrode portion 11 is reduced, so that current can flow between the channel portion 12 and the first electrode portion 11.

[0061] In the embodiment of the present application, Figure 3a and Figure 3b In the figure, Metal is used to represent the metal structure 20, Si is used to represent the first electrode portion 11, and E F represents the Fermi level, E C represents the conduction band, E V represents the valence band, represents the barrier height between the metal structure 20 and the vacuum level, represents the barrier height between the first electrode 11 and the vacuum level, qX S represents the electron affinity of the first electrode portion 11 .

[0062] It should be noted that the metal structure 20 and the first electrode portion 11 are close to each other, which means that the metal structure 20 and the first electrode portion 11 are not in contact, and the distance between the metal structure 20 and the first electrode portion 11 is less than or equal to the maximum distance at which the metal structure 20 can affect the change of the Fermi level on the outer surface of the first electrode portion 11.

[0063] like Figure 3a and Figure 3b As shown, before the metal structure 20 and the first electrode portion 11 are not in contact or close to each other, the Fermi levels of the metal structure 20 and the first electrode portion 11 are different. When the metal structure 20 and the first electrode portion 11 are in contact or close to each other, the energy band at one end of the first electrode portion 11 close to the metal structure 20 or at the interface will bend under the influence of the free electrons of the metal structure 20, so that the Fermi level of the first electrode portion 11 moves up, so that the Fermi level of the metal structure 20 and the Fermi level of the first electrode portion 11 are equal or close to each other at the interface where the two are close to each other or in contact, thereby driving the conduction band E at the surface of one end of the first electrode portion 11 close to the metal structure 20 or at the interface (also belonging to the surface) in contact with the metal structure 20. C and valence band EV The bending of the valence increases the concentration of carriers at the surface of the first electrode portion 11, thereby reducing the resistance on the surface of the first electrode portion 11. Further, when the first electrode portion 11 of the transistor is connected to the bit line 50, the contact resistance between the first electrode portion 11 and the bit line 50 can be reduced, so that an ohmic contact is formed between the first electrode portion 11 and the bit line 50.

[0064] according to Figure 3a , Figure 3b The concentration of electrons on the surface of the first electrode portion 11 can be calculated using the following calculation formula (1).

[0065]

[0066] Here, n0 represents the doping concentration of the first electrode portion 11, k0 represents a coefficient, and T represents temperature.

[0067] In the present application embodiment, Figure 1 and Figure 2 As shown, the transistor further includes a gate dielectric layer 31 and a gate 32 . The gate dielectric layer 31 is disposed at the sidewall of the channel portion 12 , and the gate 32 is disposed at the sidewall of the gate dielectric layer 31 away from the channel portion 12 .

[0068] Alternatively, if Figure 2 As shown, along the direction perpendicular to the substrate 100 , the metal structure 20 and the gate 31 have a certain distance, so as to prevent the carriers on the surface of the first electrode portion 11 from affecting the channel portion 12 .

[0069] It should be noted that if Figure 2 As shown, in order to facilitate readers to intuitively understand each structure, the boundary between the substrate 100 and the semiconductor pillar 10, and the boundary between the first electrode portion 11 and the channel portion 12 are represented by dotted lines, which do not exist in actual products. Figure 2 Dotted line shown.

[0070] Alternatively, if Figure 4 As shown, in one embodiment of the present application, the transistor further includes a dielectric structure 40 , and along a direction parallel to the substrate 100 , the dielectric structure 40 is located between the side wall of the first electrode portion 11 and the metal structure 20 .

[0071] Alternatively, if Figure 4 As shown, by providing a dielectric structure 40 between the first electrode portion 11 and the metal structure 20 , the dielectric structure 40 can improve the uniformity of carrier distribution on the surface of the first electrode portion 11 , thereby helping to ensure the stability of the on-state current of the transistor.

[0072] Moreover, the probability of the pinning effect of the Fermi level at the contact interface between the first electrode portion 11 and the metal structure 20 can be reduced, so as to ensure that the conduction band E at the surface of one end of the first electrode portion 11 close to the metal structure 20 or at the interface (also belonging to the surface) in contact with the metal structure 20 is C and valence band E V Price bending.

[0073] Optionally, in the embodiment of the present application, the material of the dielectric structure 40 is the same as the material of the gate dielectric layer 31. Optionally, the material of the dielectric structure 40 includes silicon oxide.

[0074] Optionally, in the embodiment of the present application, along a direction parallel to the substrate 100 , a thickness d of the dielectric structure 40 is not less than 1 nanometer and not more than 5 nanometers.

[0075] Optionally, in an embodiment of the present application, along a direction parallel to the substrate 100, the thickness d of the dielectric structure 40 is not less than 1 nanometer and not more than 3 nanometers, thereby preventing the dielectric structure 40 with too large thickness d from affecting the change of the Fermi level at the contact interface between the first electrode portion 11 and the metal structure 20, thereby ensuring that the Fermi level at the surface of the first electrode portion 11 moves upward.

[0076] Alternatively, if Figure 2 and Figure 4 As shown, in one embodiment of the present application, the metal structure 20 surrounds the sidewall of the first electrode portion 11 .

[0077] Alternatively, if Figure 1 and Figure 2 As shown in FIG. 1 , the semiconductor column 10 is a cylindrical structure. Figure 2 and Figure 4 As shown, the metal structure 20 surrounds the sidewall of the first electrode portion 11 in the semiconductor pillar 10 , so that the carrier concentration on the surface of the peripheral wall of the first electrode portion 11 is increased.

[0078] Alternatively, if Figure 4 As shown, the dielectric structure 40 surrounds the side wall of the first electrode portion 11 , and the metal structure 20 surrounds the dielectric structure 40 away from the outer peripheral wall of the first electrode portion 11 , which can improve the uniformity of carriers on the peripheral wall surface of the first electrode portion 11 .

[0079] Those skilled in the art will Figure 4 The transistor shown was tested and found to be Figure 4 In the transistor shown in FIG. 1 , the carrier concentration on the surface of the first electrode portion 11 can reach e 20 , so that the resistance at the surface of the first electrode portion 11 is significantly reduced.

[0080] Alternatively, if Figure 2As shown, along the direction perpendicular to the substrate 100 , the size h of the metal structure 20 is not less than 5 nanometers and not more than 20 nanometers to ensure that the carriers on the surface of the first electrode portion 11 meet the requirements and at the same time, avoid the carriers on the surface of the carrier portion 11 from affecting the channel portion 12 .

[0081] Alternatively, if Figure 2 and Figure 4 As shown, in one embodiment of the present application, the transistor further includes: an electrode 13 disposed on a side of the channel portion 12 away from the substrate 100 .

[0082] Optionally, in the embodiment of the present application, Figure 2 and Figure 4 As shown, along a direction perpendicular to the substrate 100 , the first electrode portion 11 , the channel portion 12 and the electrode 13 are sequentially stacked on one side of the substrate 100 , so that the transistor is a transistor with a vertical channel.

[0083] Optionally, in the embodiment of the present application, the electrode 13 is obtained by doping the second electrode portion of the semiconductor column 10, which is arranged on the side of the channel portion 12 away from the substrate 100. Therefore, in the manufacturing process of the transistor, the semiconductor column 10 including the first electrode portion 11, the channel portion 12 and the second electrode portion can be manufactured at the same time, and then the second electrode portion is heavily doped to obtain the electrode 13.

[0084] Optionally, in an embodiment of the present application, the electrode 13 is obtained based on an epitaxial process, that is, after forming a semiconductor column 10 including a first electrode portion 11 and a channel portion 12, a semiconductor material is grown on a surface of the channel portion 12 away from the first electrode portion 11 based on an epitaxial growth process, and then heavily doped to obtain the electrode 13.

[0085] Based on the same inventive concept, an embodiment of the present application provides a semiconductor device, the semiconductor device comprising any transistor provided in the above embodiments. Optionally, the semiconductor device comprises a memory.

[0086] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a semiconductor device, and the flowchart of the manufacturing method is as follows: Figure 5 As shown, the method includes steps S501 to S504.

[0087] S501 , forming a plurality of semiconductor pillars arranged in an array on one side of a substrate.

[0088] S502 , forming a groove extending along a first direction below the first electrode portion in each semiconductor column.

[0089] S503, forming a bit line in the groove.

[0090] S504, forming a metal structure at the side wall of the first electrode portion; a work function of the metal structure is not greater than a work function of the first electrode portion.

[0091] In order to facilitate readers to intuitively understand the manufacturing method of the semiconductor device provided in the embodiment of the present application, the advantages of the manufacturing method and the advantages of the semiconductor device obtained based on the manufacturing method, the following will be combined with Figure 6-Figure 16 A method for manufacturing a semiconductor device will be described in detail.

[0092] Optionally, in one embodiment of the present application, the step S501 includes: forming a plurality of semiconductor pillars 10 arranged in an array on one side of the substrate 100 based on a SADP (Self-aligned Double Patterning) process.

[0093] Optionally, forming the semiconductor pillar 10 based on the SADP process specifically includes the following steps:

[0094] First, a first mask layer, a second mask layer and a third mask layer are sequentially formed on one side of the substrate 100 .

[0095] Optionally, the first mask layer, the second mask layer and the third mask layer each include at least one sub-mask layer.

[0096] Then, based on processes such as coating, exposure, and development, a patterned photoresist structure is formed on a side of the third mask layer away from the substrate 100 .

[0097] Optionally, the photoresist structure extends along a first direction parallel to the substrate 100 .

[0098] Next, the third mask layer is patterned based on the photoresist structure to form a third mask structure.

[0099] Then, a fourth mask layer covering the third mask structure is formed.

[0100] Optionally, the fourth mask layer includes a recessed portion located between any two adjacent third mask structures and a top portion located on a side of the second mask structure away from the substrate 100. Optionally, the recessed portion includes: a bottom wall and a side wall, a portion of the recessed portion that is in contact with the side wall of the third mask structure is a side wall, and a portion of the recessed portion located between two adjacent side walls is a bottom wall. Optionally, the fourth mask layer includes silicon oxide.

[0101] Next, the fourth mask layer is etched until the top of the fourth mask layer, the bottom wall of the concave portion and the third mask structure below the top are etched away, and the remaining sidewall of the concave portion forms the fourth mask structure.

[0102] Optionally, the fourth mask layer and the third mask structure are processed based on anisotropic etching, so that the sidewalls of the recess are retained, while the top of the fourth mask layer, the bottom wall of the recess and the third mask structure below the top are removed by etching.

[0103] Then, the second mask layer is etched using the fourth mask structure as a mask to form a second mask structure.

[0104] Optionally, the second mask layer includes a polysilicon layer.

[0105] Next, the first mask layer is etched using the second mask structure as a mask to form a first mask structure.

[0106] Optionally, the first mask layer includes SiNx (silicon nitride).

[0107] Then, using the first mask structure as a mask, a portion of the substrate 100 is etched to form a plurality of semiconductor walls arranged at intervals.

[0108] Optionally, the semiconductor walls extend along a first direction; and along a second direction parallel to the substrate 100 , the semiconductor walls are arranged at intervals.

[0109] Next, an isolation layer covering the semiconductor walls is formed, and the space between any two adjacent semiconductor walls is filled with the isolation layer.

[0110] Then, the isolation layer is processed based on a CMP (Chemical Mechanical Polishing) process to remove the first mask structure located on the top surface of the semiconductor wall.

[0111] Next, a fifth mask layer is formed on a side of the semiconductor wall and the isolation layer away from the substrate 100; the fifth mask layer is processed based on a patterning process to form a plurality of fifth mask structures extending along the second direction; the semiconductor wall is etched using the fifth mask structure as a mask to form a plurality of semiconductor pillars arranged at intervals; the fifth mask structure is removed to expose the top surface of the semiconductor pillar.

[0112] Alternatively, if Figure 6 and Figure 7 As shown, a plurality of semiconductor pillars 10 are formed on one side of the substrate 100, and the plurality of semiconductor pillars 10 are arranged in an array. It should be noted that in order to facilitate readers to intuitively understand the arrangement of the semiconductor pillars 10, Figure 6 The isolation layer is omitted.

[0113] Optionally, in an embodiment of the present application, after step S501 and before step S502 , the method further includes: patterning the isolation layer to form a plurality of first trenches 101 extending along the second direction.

[0114] Alternatively, if Figure 7As shown, along the first direction, any two adjacent semiconductor pillars 10 are separated by a first trench 101 .

[0115] Optionally, in one embodiment of the present application, the above step S502 includes: forming a dielectric layer covering the semiconductor pillar 10; etching the bottom wall of the recess in the dielectric layer to expose part of the substrate 100; based on the exposed part of the substrate 100, etching part of the substrate 100 to form a groove 103.

[0116] Optionally, forming a dielectric layer covering the semiconductor pillars 10 includes: forming the dielectric layer based on a deposition process, wherein the dielectric layer covers the top surface and the side surface of the semiconductor pillars 10 and a portion of the substrate 100 between any two adjacent semiconductor pillars 10 .

[0117] Optionally, the dielectric layer includes a recess between any two adjacent semiconductor pillars 10 and a top of the semiconductor pillar 10 away from the substrate 100. Optionally, the recess of the dielectric layer includes a sidewall that fits the sidewall of the semiconductor pillar 10 and a bottom wall between two adjacent sidewalls.

[0118] Optionally, etching the bottom wall of the recess in the dielectric layer to expose a portion of the substrate 100 includes: processing the dielectric layer based on an anisotropic dry etching process so that the etching rate in the dielectric layer along a direction perpendicular to the substrate 100 is much greater than the etching rate in a direction parallel to the substrate 100, thereby etching the bottom wall of the recess in the dielectric layer, so that the portion of the substrate 100 located between two adjacent semiconductor pillars 10 is exposed.

[0119] Alternatively, if Figure 8 As shown, the dielectric layer is etched to form a first dielectric structure 1021, and the first dielectric structure 1021 includes a dielectric structure 40 disposed on a side wall of the first electrode portion 11. Optionally, the dielectric structure 40 surrounds the first electrode portion 11.

[0120] Optionally, based on the exposed portion of the substrate 100, a portion of the substrate 100 is etched to form a groove 103, including: processing the exposed portion of the substrate 100 based on an isotropic etching process, so that a portion of the substrate 100 located below the first electrode portion 11 in the semiconductor column 10 is etched to form a groove 103 extending along the first direction.

[0121] Alternatively, if Figure 8 As shown, part of the groove 103 is located below the first electrode portion 11 , thereby providing space for the subsequent formation of the bit line 50 .

[0122] Optionally, in one embodiment of the present application, the above step S503 includes: forming a metal silicide structure 51 located in the groove 103; forming a connecting structure 52 for connecting any two adjacent metal silicide structures 51, and the bit line 50 includes a metal silicide structure 51 and a connecting structure 52 connected in sequence along a first direction.

[0123] Optionally, a metal silicide structure 51 located in the groove 103 is formed, including: based on a deposition process, depositing a metal material in the groove 103 so that the metal material can cover the curved wall of the groove 103; based on a metal silicide process, allowing the metal material to react with a portion of the substrate 100 located below the first electrode portion 11 to form a metal silicide structure 51 located below the first electrode portion 11.

[0124] Alternatively, if Fig. 9 As shown, the metal silicide structure 51 includes a curved surface that follows the shape of the groove 103. Optionally, the metal material used to form the metal silicide structure 51 includes Co (cobalt), Ti (titanium) or Ni (nickel).

[0125] Optionally, forming a connection structure 52 for connecting any two adjacent metal silicide structures 51 includes: based on a deposition process, depositing a metal material in the groove 103 until the metal material fills the groove 103, thereby forming a connection structure 52 for connecting the metal silicide structures 51. Optionally, the metal material used to form the connection structure 52 includes W (tungsten).

[0126] Optionally, after forming the bit line 50 , the step further includes etching back a portion of the connection structure 52 to prevent the top surface of the connection structure 52 from being higher than the bottom surface of the first electrode portion 11 , thereby ensuring that the subsequently formed metal structure 20 has a sufficient height.

[0127] Optionally, in an embodiment of the present application, the above step S504 includes: forming a metal structure 20 in the recessed portion of the dielectric layer.

[0128] Optionally, based on a deposition process, a material having a work function no greater than that of the first electrode portion 11 is deposited in the first trench 101 to form the metal structure 20 .

[0129] Alternatively, if Fig.10 As shown, the metal structure 20 is located on a side of the connection structure 52 of the bit line 50 away from the substrate 100. Optionally, the metal structure 20 surrounds the dielectric structure 40.

[0130] Optionally, the material used to form the metal structure 20 includes Al (aluminum) and Hf (hafnium).

[0131] Optionally, in an embodiment of the present application, after the above step S504 , the method further includes: forming a gate 32 surrounding the channel portion 12 of the semiconductor pillar 10 ; and forming an electrode 13 on a side of the channel portion 11 away from the substrate 100 .

[0132] Optionally, in one embodiment of the present application, a gate 32 surrounding the channel portion 12 of the semiconductor column 10 is formed, including: forming a first isolation structure 104 in a recessed portion of a dielectric layer; etching back the sidewalls of the recessed portion so that the sidewalls of the second electrode portion 14 in the semiconductor column 10 are exposed; forming a second isolation structure 105 filling the gap between the first isolation structure 104 and the second electrode portion 14; removing a portion of the sidewall of the recessed portion corresponding to the channel portion 12 so that at least a portion of the peripheral wall of the channel portion 12 is exposed; forming a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12; and forming a gate 32 surrounding the gate dielectric layer 31 and a word line connected to the gate 32.

[0133] Optionally, forming the first isolation structure 104 in the recessed portion of the dielectric layer includes: forming the first isolation structure 104 filling the first trench 101 based on a deposition process.

[0134] Alternatively, if Fig.11 As shown, the first isolation structure 104 is located on a side of the metal structure 20 away from the substrate 100 , and the first isolation structure 104 is used to separate any two adjacent semiconductor pillars 10 along the first direction.

[0135] Alternatively, if Figure 7 As shown, the formed semiconductor pillar 10 includes a first electrode portion 11 , a channel portion 12 , and a second electrode portion 14 which are sequentially stacked along a direction perpendicular to the substrate 100 .

[0136] Optionally, etching back the sidewall of the recessed portion to expose the sidewall of the second electrode portion 14 in the semiconductor pillar 10 includes: etching a portion of the first dielectric structure 1021 to expose the peripheral wall of the second electrode portion 14 .

[0137] Alternatively, if Fig.12 As shown, the first dielectric structure 1021 after etching forms a second dielectric structure 1022 , and the second dielectric structure 1022 includes the dielectric structure 40 .

[0138] Optionally, forming a second isolation structure 105 filling the gap between the first isolation structure 104 and the second electrode portion 14 includes: filling the gap between the first isolation structure 104 and the second electrode portion 14 with a dielectric material based on a deposition process to form the second isolation structure 105, such as Fig.13 shown.

[0139] Optionally, the first isolation structure 104 and the second isolation structure 105 are made of the same material. Optionally, the first isolation structure 104 and the second isolation structure 105 are made of SiNx.

[0140] Optionally, removing a portion of the side wall of the recess corresponding to the channel portion 12 so that at least a portion of the peripheral wall of the channel portion 12 is exposed includes: removing a portion of the side wall of the recess corresponding to the channel portion 12 so that a portion of the peripheral wall of the channel portion 12 is exposed.

[0141] Alternatively, if Fig.14 As shown, after the portion of the second dielectric structure 1022 other than the dielectric structure 40 is removed based on a wet etching process, a gap 106 is formed between the channel portion 12 and the first isolation structure 104 .

[0142] Optionally, forming a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12 includes: processing the exposed peripheral wall of the channel portion 12 based on an ISSG (In-situ steam generation) process, so that a portion of silicon in the peripheral wall of the channel portion 12 undergoes an oxidation reaction, thereby forming a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12.

[0143] Optionally, in the embodiment of the present application, in the process of processing the exposed peripheral wall of the channel portion 12 based on the ISSG process, in the oxidizing atmosphere, the silicon in the peripheral wall of the channel portion 12 undergoes an oxidation reaction to form silicon oxide, so that the exposed peripheral wall of the channel portion 12 is formed into silicon oxide, thereby forming a gate dielectric layer 31 surrounding the channel portion 12, such as Fig.15 shown.

[0144] Compared to forming the gate dielectric layer 31 based on a deposition process, in the embodiment of the present application, through the ISSG process, by controlling the distribution concentration of the oxidizing atmosphere, the silicon exposed in the channel portion 12 can undergo an oxidation reaction with a consistent oxidation rate, so that the formed silicon oxide is evenly distributed on the exposed peripheral wall of the channel portion 12, and the film thickness of the formed silicon oxide can be kept consistent, thereby improving the formation quality of the gate dielectric layer 31, which is beneficial to ensuring the performance of the subsequently formed semiconductor device.

[0145] Optionally, forming a word line including a gate 32 surrounding a gate dielectric layer 31 includes: forming a gate 32 surrounding a gate dielectric layer 31 and a connecting portion connecting any two adjacent gates 32 based on a deposition process, thereby obtaining a word line including the gate 32 and the connecting portion, such as Fig.16 shown.

[0146] Optionally, the work function of the gate 32 is greater than the work function of the metal structure 20. Optionally, the gate 32 includes TiN (titanium nitride) and Pt (platinum).

[0147] Optionally, in one embodiment of the present application, a gate 32 surrounding the channel portion 12 of the semiconductor column 10 is formed, including: forming a first isolation structure 104 in a recessed portion of a dielectric layer; etching back the sidewalls of the recessed portion to remove a portion of the sidewalls of the recessed portion corresponding to the channel portion 12, so that at least a portion of the peripheral wall of the channel portion 12 is exposed; forming a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12; and forming a gate 32 surrounding the gate dielectric layer 31 and a word line connected to the gate 32.

[0148] Optionally, in the embodiment of the present application, the semiconductor pillar 10 formed in step S501 includes a first electrode portion 11 and a channel portion 12 sequentially stacked in a direction perpendicular to the substrate 100 .

[0149] Optionally, forming the first isolation structure 104 in the recessed portion of the dielectric layer includes: forming the first isolation structure 104 filling the first trench 101 based on a deposition process.

[0150] Optionally, the first isolation structure 104 is used to separate any two adjacent semiconductor pillars 10 along the first direction.

[0151] Optionally, etching back the sidewall of the concave portion, removing the portion of the sidewall of the concave portion corresponding to the channel portion 12, so that at least a portion of the peripheral wall of the channel portion 12 is exposed, includes: etching back the portion of the first dielectric structure 1021 except the dielectric structure 40 based on the etching process, so that a portion of the peripheral wall of the channel portion 12 is exposed. After the etching, only the dielectric structure 40 remains in the first dielectric structure 1021, and a gap 106 is formed between the channel portion 12 and the first isolation structure 104.

[0152] Optionally, forming a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12 includes: processing the exposed peripheral wall of the channel portion 12 based on the ISSG process so that part of the silicon in the peripheral wall of the channel portion 12 undergoes an oxidation reaction to form a gate dielectric layer 31 surrounding the peripheral wall of the channel portion 12.

[0153] Optionally, forming a word line including a gate 32 surrounding a gate dielectric layer 31 includes: based on a deposition process, forming a gate 32 surrounding the gate dielectric layer 31 and a connecting portion connecting any two adjacent gates 32, thereby obtaining a word line including the gate 32 and the connecting portion.

[0154] Optionally, in one embodiment of the present application, the electrode 13 is formed on a side of the channel portion 12 away from the substrate 100 , including: forming the electrode 13 by processing the second electrode portion 14 based on a doping process, or forming the electrode 13 based on an epitaxial process.

[0155] Optionally, based on ion implantation technology, As (arsenic) is implanted into the second electrode portion 14 to form a highly doped electrode 13 .

[0156] Optionally, based on an epitaxial process, a semiconductor material is grown on the surface of the channel portion 12 away from the substrate 100 , and the grown semiconductor material is processed based on ion implantation technology to form an electrode 13 with a high doping concentration.

[0157] Optionally, based on the epitaxial process, polysilicon material is grown on the surface of the side of the channel portion 12 away from the substrate 100, and then metal material is deposited on one side of the polysilicon, and metal silicide is formed by rapid heat treatment to form an electrode 13, which can reduce the contact resistance between the electrode 13 and the subsequently formed capacitor device and help reduce the leakage of the capacitor device.

[0158] Optionally, in the embodiment of the present application, the first electrode portion 11 is a drain of the transistor, and the electrode 13 is a source of the transistor.

[0159] Optionally, before forming the electrode 13 on the side of the channel portion 12 away from the substrate 100 , the method further includes: forming a protection layer covering the gate dielectric layer 31 and the gate 32 , wherein an opening is formed in the protection layer to expose the top surface of the channel portion 12 .

[0160] Optionally, in an embodiment of the present application, the deposition process includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition) and ALD (Atomic Layer Deposition), etc.

[0161] Based on the same inventive concept, an embodiment of the present application provides a semiconductor device, which includes: multiple word lines, multiple bit lines 50 and multiple array-arranged transistors; the transistors are arranged on the side of the bit lines 50 away from the substrate 100; the bit lines 50 extend along a first direction, and each bit line 50 is connected to the first electrode portion 11 of a column of transistors arranged along the first direction; the word lines extend along a second direction, and each word line is connected to the gate 32 of a row of transistors arranged along the second direction; the first direction is perpendicular to the second direction.

[0162] Optionally, in the embodiment of the present application, since a metal structure 20 having a work function smaller than that of the first electrode portion 11 is provided at the side wall of the first electrode portion 11 in each transistor, the resistance at the surface of the first electrode portion 11 is significantly reduced, thereby reducing the contact resistance between the first electrode portion 11 and the bit line 50, thereby forming an ohmic contact between the first electrode portion 11 and the bit line 50, thereby improving the performance of the semiconductor device.

[0163] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes: any semiconductor device provided by the above embodiments.

[0164] In the embodiments of the present application, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0165] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0166] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided by the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided by the embodiments of the present application.

[0167] Those skilled in the art will appreciate that the electronic devices provided in the embodiments of the present application may be specially designed and manufactured for the desired purpose, or may also include known devices in general-purpose computers. These devices have any semiconductor device provided in the above embodiments.

[0168] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0169] In the transistor provided in the embodiment of the present application, a metal structure 20 having a work function smaller than that of the first electrode portion 11 is provided at the side wall of the first electrode portion 11, so that the Fermi level at the contact interface between the first electrode portion 11 and the metal structure 20 is shifted upward, the energy band at the interface is bent, and the concentration of carriers at the interface is increased, thereby significantly reducing the resistance on the surface of the first electrode portion 11.

[0170] At the same time, it is possible to avoid heavy doping of the first electrode portion 11 , reduce the difficulty of manufacturing the transistor, and improve the production efficiency and yield rate of the transistor.

[0171] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0172] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0173] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0174] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0175] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0176] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A transistor, It is characterized in that include: A semiconductor column, comprising a first electrode portion and a channel portion stacked in sequence in a direction perpendicular to and away from a substrate, wherein a doping concentration of the first electrode portion is not greater than a doping concentration of the channel portion; A metal structure is disposed on at least a portion of a sidewall of the first electrode portion, and a work function of the metal structure is smaller than a work function of the first electrode portion.

2. The transistor according to claim 1, It is characterized in that A dielectric structure is provided between the metal structure and a side wall of the first electrode portion along a direction parallel to the substrate; The material of the dielectric structure is the same as that of the gate dielectric layer; Along a direction parallel to the substrate, the thickness of the dielectric structure is not less than 0.5 nanometers and not more than 3 nanometers.

3. The transistor according to claim 2, It is characterized in that The metal structure surrounds the sidewall of the first electrode portion; Alternatively, the dielectric structure surrounds a side wall of the first electrode portion, and the metal structure surrounds a side wall of the dielectric structure.

4. The transistor according to claim 1, It is characterized in that Also includes: An electrode, disposed on a side of the channel portion away from the substrate; The electrode is obtained by doping a second electrode portion of the semiconductor column that is disposed on a side of the channel portion away from the substrate; or, the electrode is obtained by an epitaxial process.

5. A semiconductor device, It is characterized in that include: A plurality of word lines, a plurality of bit lines and a plurality of transistors as claimed in any one of claims 1 to 4 arranged in an array; The transistor is arranged on a side of the bit line away from the substrate; the bit line extends along a first direction, and each of the bit lines is connected to a first electrode portion of a column of the transistors arranged along the first direction; The word lines extend along a second direction, and each of the word lines is connected to gates of a row of transistors arranged along the second direction; the first direction is perpendicular to the second direction.

6. A method for manufacturing a semiconductor device, It is characterized in that include: forming a plurality of semiconductor pillars arranged in an array on one side of the substrate; forming a groove extending along a first direction below the first electrode portion in each of the semiconductor pillars; forming a bit line in the groove; A metal structure is formed at a side wall of the first electrode portion; a work function of the metal structure is not greater than a work function of the first electrode portion.

7. The method for manufacturing a semiconductor device according to claim 6, It is characterized in that A groove extending along a first direction is formed below the first electrode portion in each of the semiconductor pillars, comprising: forming a dielectric layer covering the semiconductor pillar; Etching the bottom wall of the recess in the dielectric layer so that a portion of the substrate is exposed; Based on the exposed portion of the substrate, a portion of the substrate is etched to form the groove.

8. The method for manufacturing a semiconductor device according to claim 7, It is characterized in that A metal structure is formed at a side wall of the first electrode portion, comprising: forming the metal structure in the recessed portion of the dielectric layer; And, after forming a metal structure at the side wall of the first electrode portion, the method further includes: forming a gate surrounding a channel portion of the semiconductor column; An electrode is formed on a side of the channel portion away from the substrate.

9. The method for manufacturing a semiconductor device according to claim 8, It is characterized in that Forming a gate surrounding a channel portion of the semiconductor column, comprising: forming a first isolation structure in the recessed portion of the dielectric layer; Carving back the sidewall of the recess so that the sidewall of the second electrode portion in the semiconductor column is exposed; forming a second isolation structure filling a gap between the first isolation structure and the second electrode portion; removing a portion of the side wall of the recess corresponding to the channel portion, so that at least a portion of the peripheral wall of the channel portion is exposed; forming a gate dielectric layer surrounding the peripheral wall of the channel portion; The gate surrounding the gate dielectric layer and a word line connected to the gate are formed.

10. The method for manufacturing a semiconductor device according to claim 8, It is characterized in that An electrode is formed on a side of the channel portion away from the substrate, comprising: The electrode is formed by processing the second electrode portion of the semiconductor column based on a doping process, or the electrode is formed based on an epitaxial process.

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