Digital-to-analog converter circuit supporting frequency mixing mode

Abstract

The invention belongs to the field of integrated circuits, and provides a digital-to-analog converter circuit supporting a frequency mixing mode, which comprises a frequency mixing module, a first sampling circuit and a second sampling circuit, the frequency mixing module comprises a first selection circuit, a second selection circuit and a phase inverter. According to the invention, through the first selection circuit, the second selection circuit, the phase inverter and the second sampling circuit, the defect that aliasing is generated when signals of a traditional digital-to-analog converter exceed the frequency spectrum of the first Nyquist region is solved, and a frequency mixing function and data conversion under a 2Gbps sampling rate and a second Nyquist region are realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a digital-to-analog converter circuit supporting a mixing mode. Background Art

[0002] With the rapid development of mobile communication technology, the demand for integrated circuits is also increasing. For example, in the field of daily communications, the 1G to 2GHz frequency band is a large-scale application band for various terminals. In order to increase the data transmission speed in this frequency band while taking into account low power consumption, more challenges are posed to the digital-to-analog units of common RF transceiver systems. For example, a conventional high-speed digital-to-analog chip with a sampling rate of 2Gbps, based on the modulation and demodulation principle of the signal, usually requires the signal to be in the first Nyquist interval of the sampling rate, so that the digital signal can be completely restored to an analog signal. In the field of communications, the frequency around 1.8GHz is a conventional application band. For the transmission of narrowband signals in this frequency band, a digital-to-analog conversion chip with a higher sampling rate is required to meet the first Nyquist sampling principle. This places higher requirements on the sampling rate and significantly increases the difficulty of clock design and power consumption.

[0003] The circuit scheme of the prior art is as follows Figure 1 As shown, data D enters the circuit and is sampled by a conventional sampling circuit CK. The sampled data Dout is converted by the post-stage circuit of the digital-to-analog converter to achieve the effect of the first Nyquist sampling. The advantage of this method is that the structure is simple and stable, and a more efficient sampling effect can be achieved through various deformation structures of the sampling module. The disadvantage is that once the signal exceeds the first Nyquist zone, the spectrum will cause aliasing. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a digital-to-analog converter circuit that supports a mixing mode. Through a first selection circuit, a second selection circuit, an inverter and a second sampling circuit, the defect that aliasing will occur when the signal of a traditional digital-to-analog converter exceeds the spectrum of the first Nyquist zone is solved, and the mixing function and data conversion at a 2Gbps sampling rate and a second Nyquist zone are realized.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A digital-to-analog converter circuit supporting a mixing mode comprises: a mixing module, a first sampling circuit and a second sampling circuit; the mixing module comprises: a first selection circuit, a second selection circuit and an inverter;

[0007] The input end of the first selection circuit is connected to the external first data end; the input end of the second selection circuit is connected to the external second data end; the output end of the first selection circuit and the output end of the second selection circuit are both connected to the input end of the inverter; the output end of the inverter is connected to the input end of the second sampling circuit; the input end of the first sampling circuit is connected to the external first data end; the output end of the first sampling circuit and the output end of the second sampling circuit are both connected to the external output data end; the forward control end and the reverse control end of the first selection circuit are respectively connected to the external reverse mixed data end and the external forward mixed data end; the forward control end and the reverse control end of the second selection circuit are respectively connected to the external forward mixed data end and the external reverse mixed data end; the forward clock signal control end and the reverse clock signal control end of the first sampling circuit are respectively connected to the external forward clock control data end and the reverse clock control data end; the forward clock signal control end and the reverse clock signal control end of the second sampling circuit are respectively connected to the external reverse clock control data end and the external forward clock control data end;

[0008] The first selection circuit is used to transfer the electrical signal input from the external first data terminal to the first sampling circuit through the inverter when the external forward mixed data terminal is at a low level and the external reverse mixed data terminal is at a high level; the second selection circuit is used to transfer the electrical signal input from the external second data terminal to the second sampling circuit through the inverter when the external forward mixed data terminal is at a high level and the external reverse mixed data terminal is at a low level; the second sampling circuit is used to sample the electrical signal input from the external first data terminal or the external second data terminal to obtain a second sampling signal, and when the external forward clock control data terminal is at a low level and the external reverse clock control data terminal is at a high level, the second sampling signal is transmitted to the external output data terminal; the first sampling circuit is used to sample the electrical signal from the external first data terminal to obtain a first sampling signal, and when the external forward clock control data terminal is at a high level and the external reverse clock control data terminal is at a low level, the first sampling signal is output to the external output data terminal.

[0009] Preferably, when the external forward mixed data terminal is at a low level, the calculation formula for the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DP*CKN; wherein Dout is the output level of the external output data terminal; CK is the level type of the external forward clock control data terminal; CKN is the level type of the external reverse clock control data terminal; Da is the output level of the first sampling circuit; Db is the output level of the second sampling circuit; DP is the input voltage of the external first data terminal;

[0010] When the external forward mixed data terminal is at a high level, the calculation formula for the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DN*CKN; wherein DN is the input voltage of the external second data terminal.

[0011] The present invention discloses the following technical effects:

[0012] The present invention provides a digital-to-analog converter circuit supporting a mixing mode. Through a first selection circuit, a second selection circuit, an inverter and a second sampling circuit, the defect that aliasing will occur when the signal of a traditional digital-to-analog converter exceeds the spectrum of the first Nyquist zone is solved, and a mixing function and data conversion at a 2Gbps sampling rate and a second Nyquist zone are realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0014] Figure 1 A circuit diagram of a conventional digital-to-analog converter provided by an embodiment of the present invention;

[0015] Figure 2 A circuit diagram of a digital-to-analog converter supporting a mixing mode provided by an embodiment of the present invention;

[0016] Figure 3 A sampling output simulation diagram provided by an embodiment of the present invention;

[0017] Description of reference numerals:

[0018] N1-first selection circuit, N2-second selection circuit, N3-inverter, N4-first sampling circuit, N5-second sampling circuit. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The purpose of the present invention is to provide a digital-to-analog converter circuit that supports a mixing mode. Through a first selection circuit, a second selection circuit, an inverter and a second sampling circuit, the defect that aliasing will occur when the signal of a traditional digital-to-analog converter exceeds the spectrum of the first Nyquist zone is solved, and the mixing function and data conversion at a 2Gbps sampling rate and a second Nyquist zone are realized.

[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Figure 1 A circuit diagram of a digital-to-analog converter supporting a mixing mode provided by an embodiment of the present invention, such as Figure 1 As shown, the present invention provides a digital-to-analog converter circuit supporting a mixing mode, comprising: a mixing module, a first sampling circuit N4 and a second sampling circuit N5; the mixing module comprises: a first selection circuit N1, a second selection circuit N2 and an inverter circuit N3;

[0023] The input end of the first selection circuit N1 is connected to the external first data end; the input end of the second selection circuit N2 is connected to the external second data end; the output end of the first selection circuit N1 and the output end of the second selection circuit N2 are both connected to the input end of the inverter circuit N3; the output end of the inverter circuit N3 is connected to the input end of the second sampling circuit N5; the input end of the first sampling circuit N4 is connected to the external first data end; the output end of the first sampling circuit N4 and the output end of the second sampling circuit N5 are both connected to the external output data end; the forward control end and the reverse control end of the first selection circuit N1 are respectively connected to the external reverse mixed data end and the external forward mixed data end; the forward control end and the reverse control end of the second selection circuit N2 are respectively connected to the external external forward mixed data end and the external reverse mixed data end; the forward clock signal control end and the reverse clock signal control end of the first sampling circuit N4 are respectively connected to the external forward clock control data end and the reverse clock control data end; the forward clock signal control end and the reverse clock signal control end of the second sampling circuit N5 are respectively connected to the external reverse clock control data end and the external forward clock control data end;

[0024] The first selection circuit N1 is used to transfer the electrical signal input from the external first data terminal to the first sampling circuit N4 through the inverter circuit N3 when the external forward mixed data terminal is at a low level and the external reverse mixed data terminal is at a high level; the second selection circuit N2 is used to transfer the electrical signal input from the external second data terminal to the second sampling circuit N5 through the inverter circuit N3 when the external forward mixed data terminal is at a high level and the external reverse mixed data terminal is at a low level; the second sampling circuit N5 is used to sample the electrical signal input from the external first data terminal or the external second data terminal to obtain a second sampling signal, and when the external forward clock control data terminal is at a low level and the external reverse clock control data terminal is at a high level, the second sampling signal is transmitted to the external output data terminal; the first sampling circuit N4 is used to sample the electrical signal from the external first data terminal to obtain a first sampling signal, and when the external forward clock control data terminal is at a high level and the external reverse clock control data terminal is at a low level, the first sampling signal is output to the external output data terminal.

[0025] Further, when the external forward mixed data terminal is at a low level, the calculation formula of the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DP*CKN; wherein Dout is the output level of the external output data terminal; CK is the level type of the external forward clock control data terminal; CKN is the level type of the external reverse clock control data terminal; Da is the output level of the first sampling circuit N4; Db is the output level of the second sampling circuit N5; DP is the input voltage of the external first data terminal;

[0026] When the external forward mixed data terminal is at a high level, the calculation formula for the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DN*CKN; wherein DN is the input voltage of the external second data terminal.

[0027] Specifically, the voltage types of the external positive clock control data terminal and the external reverse clock control data terminal are opposite; the voltage types of the external positive mixed data terminal and the external reverse mixed data terminal are opposite.

[0028] refer to Figure 3, when MIX=0, Dout=DP*CK+DP*CKN, "normal output" shows a sampling process of a normal sinusoidal signal, the output effect of MIX=0 shows a black and gray data effect, there is a sampling effect on both the rising and falling edges of the sampling clock, and finally when MIX=0, the sampling effect is consistent with the existing technology. When MIX=1, Dout=DP*CK+DN*CKN, and DP and DN are opposite data, the rising edge of the clock samples the DP signal, and the falling edge of the clock samples the DN signal, and finally the output form of Dout is shown in the figure, the reversal of the DP and DN signals causes the final output effect signal to be scattered on both sides.

[0029] Specifically, based on the mixing mode-based DAC circuit solution proposed in this embodiment, the DAC chip with a sampling rate of 2Gbps can be sampled in the second Nyquist zone, and the signal bandwidth supports 0 to 2GHz. After mass production, the linearity of the chip at 1 to 2GHz is comparable to that of conventional chips, with a linearity of more than 65dBc, and has the advantage of low power consumption.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention solves the defect that the conventional digital-to-analog converter signal will produce aliasing when it exceeds the first Nyquist zone spectrum through the first selection circuit, the second selection circuit, the inverter and the second sampling circuit, and realizes the mixing function and the data conversion under the 2Gbps sampling rate and the second Nyquist zone.

[0032] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0033] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A digital-to-analog converter circuit supporting a mixing mode, It is characterized in that include: A frequency mixing module, a first sampling circuit and a second sampling circuit; The frequency mixing module comprises: a first selection circuit, a second selection circuit and an inverter; The input end of the first selection circuit is connected to the external first data end; the input end of the second selection circuit is connected to the external second data end; the output end of the first selection circuit and the output end of the second selection circuit are both connected to the input end of the inverter; the output end of the inverter is connected to the input end of the second sampling circuit; the input end of the first sampling circuit is connected to the external first data end; the output end of the first sampling circuit and the output end of the second sampling circuit are both connected to the external output data end; the forward control end and the reverse control end of the first selection circuit are respectively connected to the external reverse mixed data end and the external forward mixed data end; the forward control end and the reverse control end of the second selection circuit are respectively connected to the external forward mixed data end and the external reverse mixed data end; the forward clock signal control end and the reverse clock signal control end of the first sampling circuit are respectively connected to the external forward clock control data end and the reverse clock control data end; the forward clock signal control end and the reverse clock signal control end of the second sampling circuit are respectively connected to the external reverse clock control data end and the external forward clock control data end; The first selection circuit is used to transfer the electrical signal input from the external first data terminal to the first sampling circuit through the inverter when the external forward mixed data terminal is at a low level and the external reverse mixed data terminal is at a high level; the second selection circuit is used to transfer the electrical signal input from the external second data terminal to the second sampling circuit through the inverter when the external forward mixed data terminal is at a high level and the external reverse mixed data terminal is at a low level; the second sampling circuit is used to sample the electrical signal input from the external first data terminal or the external second data terminal to obtain a second sampling signal, and when the external forward clock control data terminal is at a low level and the external reverse clock control data terminal is at a high level, the second sampling signal is transmitted to the external output data terminal; the first sampling circuit is used to sample the electrical signal from the external first data terminal to obtain a first sampling signal, and when the external forward clock control data terminal is at a high level and the external reverse clock control data terminal is at a low level, the first sampling signal is output to the external output data terminal.

2. A digital-to-analog converter circuit supporting a mixing mode according to claim 1, It is characterized in that When the external forward mixed data terminal is at a low level, the calculation formula of the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DP*CKN; wherein Dout is the output level of the external output data terminal; CK is the level type of the external forward clock control data terminal; CKN is the level type of the external reverse clock control data terminal; Da is the output level of the first sampling circuit; Db is the output level of the second sampling circuit; DP is the input voltage of the external first data terminal; When the external forward mixed data terminal is at a high level, the calculation formula for the output level of the external output data terminal is: Dout=Da*CK+Db*CKN=DP*CK+DN*CKN; wherein DN is the input voltage of the external second data terminal.

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