Conditional branch logic processing method for network traffic

Abstract

The present invention provides a conditional branch logic processing method for network traffic, the method comprising: obtaining a network message processed by a parser to obtain a message body and a first header vector; performing conditional judgment on the first header vector during the processing of the logic stage to obtain a conditional code for executing conditional processing in the logic stage; extracting the first header vector according to a local area network identifier and the conditional code to obtain a search key; determining a table lookup range identified by the conditional code in a table lookup engine according to the search key carrying the conditional code; matching an action table according to the table lookup range, sequentially executing all logic stage processing and performing inverse parsing. The present invention has the beneficial effects of: by adding a simple arithmetic logic operation mechanism based on a tree-shaped computing unit, the judgment of the branch statement condition is realized, and the conditional result is matched by the table lookup engine, and the matched action is executed by the action engine, thereby improving the complex logic processing of network traffic.

Description

Technical Field

[0001] The present invention relates to the technical field of computer networks, and in particular to a conditional branch logic processing method for network traffic. Background Art

[0002] The traditional network architecture based on distributed routing protocols has strong survivability and has made great contributions in the past 30 years, solving various customer needs. With the requirements of simplifying IP network management, improving service deployment efficiency and realizing network programmability, Software Defined Network (SDN) came into being. By separating the data plane and control plane in the traditional network, the control plane centrally controls the network element equipment and issues "flow tables", realizing network programmability, optimizing network management costs and enabling network services to be quickly deployed using the open interface provided by the controller. The OpenFlow protocol is the representative protocol of software-defined networks. Based on software-defined networks, the Reconfigurable Match Tables (RMT) model allows switching chips to process packets more flexibly and supports more complex processing of headers. It has a milestone significance for network programmability and gradually becomes the next generation architecture of the software-defined network route.

[0003] The RMT (Reconfigurable Matching Table) pipeline in a programmable switch represents a complete set of data processing flows, which is similar to the pipeline in a traditional switch. The RMT pipeline allows users to program to control the forwarding behavior of messages on the data plane through P4 on programmable network cards, switches, routers and other network devices, and P4 has the features of protocol independence, target independence and reconfigurability.

[0004] However, the prior art defines that the data plane pipeline has poor flexibility in processing network messages. Summary of the invention

[0005] The main purpose of the embodiment of the present invention is to propose a conditional branch logic processing method for network traffic, thereby realizing complex network data processing of programmable plane data.

[0006] One aspect of the present invention provides a method for conditional branch logic processing of network traffic, comprising:

[0007] Acquire a network message processed by a parser to obtain a message body and a first header vector, wherein the first header vector is used to characterize an instruction set based on P4, and the first header vector includes a local area network identifier;

[0008] Performing conditional judgment on the first header vector during processing at the logic stage to obtain a conditional code for conditional processing at the logic stage;

[0009] Extracting the first header vector according to the local area network identifier and the conditional code to obtain a search key;

[0010] Determining, in a table lookup engine, a table lookup range identified by the condition code according to the lookup key carrying the condition code;

[0011] According to the table lookup range matching action table, all logic stage processing is performed in sequence to obtain a second header vector, and the second header vector is assembled with the message body and reverse parsed to complete the processing of the network message.

[0012] According to the conditional branch logic processing method of network traffic, the first header vector is subjected to conditional judgment during processing at the logic stage to obtain a conditional code for conditional processing at the logic stage, including:

[0013] Identifying the network message according to the local area network identifier;

[0014] Obtaining an instruction word indexed by a local area network identifier stored in a variable extraction table, wherein the instruction word includes a plurality of sub-instructions, wherein the instruction word is used to represent an operator, wherein the sub-instructions are used to represent a keyword for extracting the first header vector and placing it in a corresponding position of the first variable group in sequence;

[0015] Extract all variables required for processing the first header vector in the current logic stage according to the instruction word, and store them in corresponding positions of the first variable group to obtain a second variable group formed by sub-instructions;

[0016] The second variable group is processed by arithmetic logic operation through the instruction word to obtain conditional bits, wherein the conditional bits are used to judge the truth of the logical judgment formula in the first header vector, and the conditional bits are used to form the conditional code.

[0017] According to the conditional branch logic processing method of network traffic, the method further includes:

[0018] Identifying a conditional branch of the first header vector to obtain a branch statement;

[0019] If the conditional branches meet the same type and the hardware logic resources are sufficient, the conditional branches of the same type are compiled into the same logic stage for processing;

[0020] If there are multiple branch statements for a conditional branch, the branch statements are assigned to different logic stages for processing.

[0021] According to the conditional branch logic processing method of network traffic, the second variable group is processed by arithmetic logic operation through the instruction word to obtain the conditional bit, including:

[0022] An arithmetic logic operation is performed once with an operator using each of the second variable groups as an input number to obtain a conditional bit, and the conditional bits are combined to obtain the conditional code, where the conditional code is used to represent the statement block to be executed.

[0023] According to the conditional branch logic processing method of network traffic, the method further includes:

[0024] A sub-operation is performed on the two operands according to the operator, and the result of the previous sub-operation is used as the input of the next sub-operation. The sub-operation processing is repeated until the truth or falsehood identification of the conditional bit is completed.

[0025] According to the conditional branch logic processing method of network traffic, the first header vector is extracted according to the local area network identifier and the condition code to obtain a search key, including:

[0026] A key extractor is used to search for an extraction instruction in an extraction table using a combination of the LAN identifier and the conditional code, extracts from the first header vector through the extraction instruction to obtain a search key, attaches the conditional code to the search key, and sends it to a table lookup engine.

[0027] According to the conditional branch logic processing method of network traffic, the table lookup range identified by the condition code is determined in a table lookup engine according to the search key carrying the condition code, including:

[0028] Based on the condition code of the search key, a new condition code field is added, and the query results are distinguished according to the match-action of the search engine through the condition code field.

[0029] The beneficial effects of the present invention are as follows: by adding a simple arithmetic logic operation mechanism based on a tree-shaped computing unit in each pipeline stage, the judgment of the branch statement conditions is realized, and the condition results are matched through a table lookup engine, and the matched actions are executed by the action engine, thereby completing the execution of the statement block in the branch logic, thereby improving the complex logic processing of network traffic. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0031] Figure 1 It is a schematic diagram of the overall architecture of RMT supporting conditional branch logic according to an embodiment of the present invention.

[0032] Figure 2 It is a schematic diagram of the conditional branching logic processing flow of network traffic according to an embodiment of the present invention.

[0033] Figure 3It is a schematic diagram of a conditional judgment flow chart of an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of the conditional identification allocation process of an embodiment of the present invention.

[0035] Figure 5 It is a schematic diagram of a module for conditional judgment according to an embodiment of the present invention.

[0036] Figure 6 It is a schematic diagram of the variable extraction sub-instruction format of an embodiment of the present invention.

[0037] Figure 7 It is a schematic diagram of an ALU computing module according to an embodiment of the present invention.

[0038] Figure 8 It is a schematic diagram of a computing unit according to an embodiment of the present invention.

[0039] Fig. 9 1 is a schematic diagram of a compilation example of conditional branch logic processing of network traffic according to an embodiment of the present invention.

[0040] Fig.10 It is a schematic diagram of a conditional branch logic processing device for network traffic according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In the subsequent description, the use of suffixes such as "module", "component" or "unit" used to represent elements is only for the purpose of facilitating the description of the present invention, and has no specific meaning in itself. Therefore, "module", "component" or "unit" can be used in a mixed manner. "First", "second" and the like are only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the order of the indicated technical features. In this subsequent description, the continuous numbering of the method steps is for the convenience of review and understanding. In combination with the overall technical solution of the present invention and the logical relationship between the various steps, adjusting the implementation order between the steps will not affect the technical effect achieved by the technical solution of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0042] refer to Figure 1 , is a schematic diagram of the overall architecture of the RMT supporting conditional branching logic according to an embodiment of the present invention, which includes adding a conditional judgment module before the key extractor at each stage, and the specific functions of each module are as follows:

[0043] ①Support the recognition of conditional branches, compile the branch statements at the same level to the same stage in sequence, and if there are multiple statements under one condition, they will be allocated to the remaining stages;

[0044] ②Determine the number of bits of the condition code according to the number of conditions that need to be judged in each stage;

[0045] ③ Determine the truth or falsity of the condition represented by each condition code;

[0046] ④Configure the conditional judgment module at each stage, inform it of the location of the variables to be extracted, and the arithmetic and logical operations to be performed between variables, and place the operation results in the corresponding position of the condition code;

[0047] ⑤Configure the keyword extraction table and select the keyword extraction method according to vlan_id (local area network identifier) ​​and condition code;

[0048] ⑥ (not shown) Configure the location of each ALU in the calculation module to obtain the variable from the variable group, as well as the calculation method of each calculation unit.

[0049] In some embodiments, a conditional judgment module is added before the key extractor of each stage to extract the variables required for the conditional judgment of that stage, perform arithmetic logic calculations, judge the conditional statement block that needs to be executed in that stage and form a 4-bit conditional code (4 conditional logic judgments can be implemented in each stage).

[0050] In some embodiments, under the condition that hardware logic resources are sufficient, operations at the same level that have no dependencies on each other are compiled into the same stage.

[0051] In some embodiments, the keyword extractor determines how to extract a field in the PHV (header vector) as a search key by combining the vlan_id and the condition code, and sends the field to the table lookup engine with the condition code.

[0052] In some embodiments, by adding a conditional code to identify the table lookup range in the table lookup engine, it is ensured at the compiler level that the matching-action tables corresponding to different statement blocks will not have resource conflicts caused by duplicate table entries during matching.

[0053] refer to Figure 2 ,in Figure 2 1 is a schematic diagram of a conditional branch logic processing flow of network traffic according to an embodiment of the present invention, which includes but is not limited to steps S100 to S500:

[0054] S100, acquiring a network message processed by a parser, obtaining a message body and a first header vector, wherein the first header vector is used to characterize an instruction set based on P4, and the first header vector includes a local area network identifier.

[0055] S200, performing conditional judgment on the first header vector when processing at the logic stage, and obtaining a conditional code for conditional processing at the logic stage. Performing conditional judgment on the first header vector when processing at the logic stage, and obtaining a conditional code for conditional processing at the logic stage.

[0056] In some embodiments, reference Figure 3 The condition judgment process diagram shown includes but is not limited to steps S210 to S240:

[0057] S210, identifying the network message according to the local area network identifier;

[0058] S220, obtaining an instruction word indexed by a local area network identifier stored in a variable extraction table, wherein the instruction word includes a plurality of sub-instructions, wherein the instruction word is used to represent an operator, wherein the sub-instructions are used to represent a keyword for extracting a first header vector and placing it in a corresponding position of the first variable group in sequence;

[0059] S230, extracting all variables required for processing the first header vector in the current logic stage according to the instruction word, and storing them in corresponding positions of the first variable group, to obtain a second variable group formed by sub-instructions;

[0060] S240, performing arithmetic logic operations on the second variable group through the instruction word to obtain conditional bits, wherein the conditional bits are used to judge the truth of the logic judgment formula in the first header vector, and the conditional bits are used to form a conditional code.

[0061] In some embodiments, reference Figure 4 The condition identification allocation process diagram shown in FIG. 1 includes but is not limited to steps S250 to S260:

[0062] S250, identifying the conditional branch of the first header vector to obtain a branch statement;

[0063] S260, if the conditional branches meet the same type and the hardware logic resources are sufficient, compile the conditional branches of the same type into the same logic stage for processing; if there are multiple branch statements for the conditional branches, assign the branch statements to different logic stages for processing.

[0064] In some embodiments, reference Figure 5 The schematic diagram of a conditional judgment module shown in FIG. 1 includes the following steps:

[0065] The specific process is as follows:

[0066] ①PHV is sent to the condition judgment module as a carrier of variables.

[0067] ② Extract vlan_id according to the position of vlan_id in PHV to identify different message flows.

[0068] ③ The variable extraction table stores instruction words indexed by vlan_id. Each instruction word contains four ALU instructions. Each ALU instruction contains 16 extraction sub-instructions, which are used to instruct how to extract keywords from PHV and put them into the corresponding positions in the variable group in sequence. Figure 6 The variable extraction sub-instruction format diagram shown in the figure has a total of 16 bits, which are divided into two types, distinguished by the indicator bit. The indicator bit is 0 to indicate the extraction operand, and the indicator bit is 1 to indicate that the immediate value has been carried and the immediate value can be written into the variable group.

[0069] ④ Extract all variables needed for conditional judgment in this stage in PHV according to the instruction word and put them into different positions of variable groups. Four sub-instructions form four different variable groups. Each variable group represents all variables needed to calculate a conditional logic judgment expression, which consists of 16 8B fields.

[0070] ⑤ Send the four variable groups to four ALUs for arithmetic and logical operations. ALU supports operations such as “+, -, ×, >, <, =, !, &, |, ~, &&, ||, ^”. The meanings of the operators are shown in Table 1.

[0071] Table 1 Specific meanings of ALU supported operators

[0072]

[0073] ⑥Each ALU eventually forms a conditional bit to indicate the truth or falsehood of a logical judgment. The conditional bits output by the four ALUs are combined to form a conditional code to indicate the conditional branch statement block to be executed. The PHV and conditional code are output to the key extractor.

[0074] In some embodiments, reference Figure 7 A schematic diagram of an ALU computing module shown in FIG. Figure 8A schematic diagram of a computing unit is shown. Four ALUs are placed in the computing module, and each ALU performs a judgment on a conditional statement. Four layers of computing units are placed in each ALU, for a total of 15 computing units. Each computing unit inputs two operands, each operand size is fixed to 8B, and the outputs of the two computing units in the previous layer are used as the inputs of the computing units in the next layer. The operation to be completed by the computing unit is identified by configuring the registers in the computing unit, such as "+, -, ×, >, <, =, &, |, ~". Unused computing units can be configured to output 1, and the computing units of the next layer input are configured as logical "AND operation", which does not affect the calculation results of other computing units. Through the comparison of each layer, the conditional bit is finally obtained to indicate the truth or falsity of the conditional statement. Setting up multiple layers of computing units can realize nested logical judgment. For example, the statement ((x>0)&(y<0))|x<1 requires a total of five basic logical operations to obtain the result. Then input x, 0 into the first computing unit of the first layer and configure it as the “>” operation; input y, 0 into the second computing unit of the first layer and configure it as the “<” operation; input x, 1 into the third computing unit of the first layer and configure it as the “<” operation; configure the first computing unit of the second layer as the “AND” operation; configure the second computing unit of the second layer as the “OR” operation; set the inputs of the remaining computing units to 1 and set them to the “AND” operation. At this time, the bits output by the computing units of the last layer indicate the truth or falsity of the conditional statement.

[0075] S300, extracting the first header vector according to the local area network identifier and the condition code to obtain a search key.

[0076] In some embodiments, the key extractor searches the extraction instruction in the extraction table according to the combination of vlan_id and condition code to determine which fields of the PHV to extract the search key. After the search key is formed, the condition code is attached to the search key and sent to the match-action table for search.

[0077] S400: Determine a table lookup range identified by the condition code in a table lookup engine according to a lookup key carrying the condition code.

[0078] In some embodiments, the match-action table: the match item needs to add a condition code field to distinguish the search results under different conditions. The found instructions are sent to the action execution engine as shown below:

[0079] If(x>0)

[0080] XXXX

[0081] If(y==0&x>1)

[0082] MMMM

[0083] Else if(y<0)

[0084] NNNN

[0085] Else

[0086] AAAA

[0087] Else if(x<0)

[0088] BBBB

[0089] Else

[0090] CCCC

[0091] S500, according to the table lookup range matching action table, all logic stage processing is performed in sequence to obtain a second header vector, the second header vector is assembled with the message body and reverse parsed, thereby completing the processing of the network message.

[0092] In some embodiments, reference Fig. 9 The diagram of the compilation example of the conditional branch logic processing of the network traffic is shown in FIG. 1 , where stage 1 and stage 2 represent two logic processing stages respectively.

[0093] ① For the above P4 program, X, B, C, M, N, and A represent the corresponding statement blocks to be executed under different conditional branch statements, and are mapped in the hardware pipeline to represent the corresponding matching-action table. Figure 8 As shown, through compiler analysis, it is found that XXXX, BBBB and CCCC belong to the statements in the same layer of conditional logic, and can only be executed in one of the three and are not dependent on each other. Therefore, XXXX, BBBB, and CCCC can be compiled to the first stage, and the variable extraction table is configured to extract variable x, and two matching fields are added to the match-action table. If the condition code is 00, the match table of CCCC is executed, 01 executes the match table of BBBB, and 10 executes the match table of XXXX to achieve the isolation of different statement blocks in the same stage; MMMM, NNNN, AAAA have dependencies with XXXX, but no dependencies between each other, so the MMMM, NNNN, and AAAA statements are compiled to the second stage, and the variable extraction table is configured to extract variables x and y, and two matching fields are added to the match-action table. If the condition code is 00, the match table of AAAA is executed, 01 executes the match table of NNNN, and 10 executes the match table of MMMM. The specific compilation method is determined by the compiler according to the resource size.

[0094] ② In the first stage of the pipeline, the conditional judgment module only needs to extract the variable x and use a two-bit conditional code to represent the truth of x>0 and x<0. If the conditional code is 00, CCCC is executed, 01 is executed BBBB, and 10 is executed XXXX.

[0095] ③ In the second stage of the pipeline, the conditional judgment module needs to extract variables x and y, using two-bit conditional codes to represent the truth of y==0&x>1 and y<0. If the conditional code is 00, execute AAAA, 01 executes NNNN, and 10 executes MMMM.

[0096] Fig.10 1 is a diagram of a conditional branch logic processing and analysis device for network traffic according to an embodiment of the present invention. The device includes a first module 1010 , a second module 1020 , a third module 1030 , a fourth module 1040 and a fifth module 1050 .

[0097] Among them, the first module 1010 is used to obtain the network message processed by the parser, obtain the message body and the first header vector, the first header vector is used to represent the instruction set based on P4, and the first header vector includes a local area network identifier; the second module 1020 is used to perform conditional judgment on the first header vector when processing in the logic stage, and obtain the conditional code for executing conditional processing in the logic stage; the third module 1030 is used to extract the first header vector according to the local area network identifier and the conditional code to obtain a search key; the fourth module 1040 is used to determine the table lookup range identified by the conditional code in the table lookup engine according to the search key carrying the conditional code; the fifth module 1050 matches the action table according to the table lookup range, executes all the logic stage processing in sequence, obtains the second header vector, assembles the second header vector with the message body and performs inverse parsing, and then completes the processing of the network message.

[0098] Exemplarily, with the cooperation of the first module 1010, the second module 1020, the third module 1030, the fourth module 1040 and the fifth module 1050 in the device, the embodiment device can implement any of the aforementioned conditional branch logic processing methods for network traffic, that is, obtaining a network message processed by a parser, obtaining a message body and a first header vector, the first header vector is used to characterize an instruction set based on P4, and the first header vector includes a local area network identifier; performing conditional judgment on the first header vector when processing in a logic stage, and obtaining a conditional code for conditional processing in the logic stage; performing conditional judgment on the first header vector when processing in a logic stage, and obtaining a conditional code for conditional processing in the logic stage; extracting the first header vector according to the local area network identifier and the conditional code to obtain a search key; determining a table lookup range identified by the conditional code in a table lookup engine according to the search key carrying the conditional code; matching the action table according to the table lookup range, executing all logic stage processing in sequence, obtaining a second header vector, assembling the second header vector with the message body and performing inverse parsing, and then completing the processing of the network message. The beneficial effects of the present invention are as follows: by adding a simple arithmetic logic operation mechanism based on a tree-shaped computing unit in each pipeline stage, the judgment of the branch statement conditions is realized, and the condition results are matched through a table lookup engine, and the matched actions are executed by the action engine, thereby completing the execution of the statement block in the branch logic, thereby improving the complex logic processing of network traffic.

[0099] An embodiment of the present invention further provides an electronic device, the electronic device comprising a processor and a memory;

[0100] The memory stores a program;

[0101] The processor executes the program to perform the aforementioned conditional branching logic processing method for network traffic; the electronic device has the function of carrying and running the software system for conditional branching logic processing of network traffic provided by an embodiment of the present invention, for example, a personal computer, a minicomputer, a main frame, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or communicating with a charged particle tool or other imaging device, etc.

[0102] An embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a program, and the program is executed by a processor to implement the conditional branch logic processing method of network traffic as described above.

[0103] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0104] The embodiment of the present invention also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device can read the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the aforementioned conditional branch logic processing method of network traffic.

[0105] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0106] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0107] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0108] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0109] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0110] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0111] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0112] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A method for conditional branching logic processing of network traffic, characterized in that: include: Acquire a network message processed by a parser to obtain a message body and a first header vector, wherein the first header vector is used to characterize an instruction set based on P4, and the first header vector includes a local area network identifier; Performing conditional judgment on the first header vector during processing at the logic stage to obtain a conditional code for conditional processing at the logic stage; Extracting the first header vector according to the local area network identifier and the conditional code to obtain a search key; Determining, in a table lookup engine, a table lookup range identified by the condition code according to the lookup key carrying the condition code; According to the table lookup range matching action table, all logic stage processing is performed in sequence to obtain a second header vector, and the second header vector is assembled with the message body and reverse parsed to complete the processing of the network message.

2. The conditional branch logic processing method of network traffic according to claim 1 is characterized in that: The performing conditional judgment on the first header vector during the processing at the logic stage to obtain a conditional code for conditional processing at the logic stage includes: Identifying the network message according to the local area network identifier; Obtaining an instruction word indexed by a local area network identifier stored in a variable extraction table, wherein the instruction word includes a plurality of sub-instructions, wherein the instruction word is used to represent an operator, wherein the sub-instructions are used to represent a keyword for extracting the first header vector and placing it in a corresponding position of the first variable group in sequence; Extract all variables required for processing the first header vector in the current logic stage according to the instruction word, and store them in corresponding positions of the first variable group to obtain a second variable group formed by sub-instructions; The second variable group is processed by arithmetic logic operation through the instruction word to obtain conditional bits, wherein the conditional bits are used to judge the truth of the logical judgment formula in the first header vector, and the conditional bits are used to form the conditional code.

3. The conditional branch logic processing method of network traffic according to claim 2 is characterized in that: The method further comprises: Identifying a conditional branch of the first header vector to obtain a branch statement; If the conditional branches meet the same type and the hardware logic resources are sufficient, the conditional branches of the same type are compiled into the same logic stage for processing; If there are multiple branch statements for a conditional branch, the branch statements are assigned to different logic stages for processing.

4. The conditional branch logic processing method of network traffic according to claim 2 is characterized in that: The step of performing arithmetic logic operations on the second variable group through the instruction word to obtain the conditional bit includes: An arithmetic logic operation is performed once with an operator using each of the second variable groups as an input number to obtain a conditional bit, and the conditional bits are combined to obtain the conditional code, where the conditional code is used to represent the statement block to be executed.

5. The conditional branch logic processing method of network traffic according to claim 4 is characterized in that: The method further comprises: A sub-operation is performed on the two operands according to the operator, and the result of the previous sub-operation is used as the input of the next sub-operation. The sub-operation processing is repeated until the truth or falsehood identification of the conditional bit is completed.

6. The conditional branch logic processing method of network traffic according to claim 1, characterized in that: The extracting the first header vector according to the local area network identifier and the condition code to obtain a search key includes: A key extractor is used to search for an extraction instruction in an extraction table using a combination of the LAN identifier and the conditional code, extracts from the first header vector through the extraction instruction to obtain a search key, attaches the conditional code to the search key, and sends it to a table lookup engine.

7. The conditional branch logic processing method of network traffic according to claim 6, characterized in that: The determining, in a table lookup engine according to the lookup key carrying the condition code, a table lookup range identified by the condition code comprises: Based on the condition code of the search key, a new condition code field is added, and the query results are distinguished according to the match-action of the search engine through the condition code field.

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