Information transmission method and related equipment

Abstract

An information transmission method and related equipment, the information transmission method comprising: a first node receiving first data or a first data signal, the first data signal being obtained by encoding a first data piece, the first data piece being obtained by decomposing the first data; and the first node sends the first data signal to the second node based on a preset time interval, wherein the preset time interval is determined based on the transmission distance between the first node and the second node. By configuring the interval of regularly sending data, the sending rate is further controlled, it is ensured that a receiving end can effectively process data within the time, feedback signals capable of increasing transmission time delay are omitted in asynchronous clock-free communication, and therefore the transmission time delay is reduced, and the system throughput rate is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular, to an information transmission method and related equipment. Background Art

[0002] With the vigorous development of system-on-chip (SoC), the scale of chips is getting larger and larger.

[0003] In order to improve the communication efficiency between chips and within chips, it is necessary to reduce the communication delay. Based on the slowdown in the update of chip manufacturing technology, the performance of existing synchronous circuit design has reached the limit bottleneck. Therefore, an asynchronous clock-free circuit design method is currently adopted. The transmission accuracy is determined by feedback signals. Since it is free from the limitations of the global clock, it can effectively reduce the delay and reduce dynamic power consumption.

[0004] However, in the current asynchronous clock-free circuit design, the control flow is not flexible and reliable enough. Data is not sent during certain time periods when data can be sent, and the feedback signal also takes up communication time, resulting in the problem of large transmission delay. Summary of the invention

[0005] The embodiment of the present application provides an information transmission method for flexibly controlling chip communication and reducing data transmission delay. The embodiment of the present application also provides corresponding communication nodes, communication devices, communication systems, computer-readable storage media, and computer program products.

[0006] In a first aspect, the present application provides an information transmission method, which includes: a first node receives input data, the input data is first data or a first data signal, the first data signal is obtained by encoding a first data slice, and the first data slice is obtained by decomposing the first data; the first node sends the first data signal to a second node based on a preset time interval, and the preset time interval is determined based on a transmission distance between the first node and the second node.

[0007] In the present application, the information transmission method is applied to two nodes, the two nodes can be nodes in the same system or nodes in different systems, the two nodes both include a sending module and a receiving module, and have the same functions. An asynchronous multi-track transmission protocol and a full-duplex communication mode are used between the two nodes, that is, data is transmitted independently and bidirectionally between the two nodes.

[0008] In the present application, the first data is a data packet sent by the synchronization node, and the input data received by the first sending module of the first node can be the first data or the first data signal.

[0009] In the present application, the transmission distance between the first node and the second node can also be understood as the actual line length information of the circuit design. After the preset time interval is set, it can be ensured that under normal circumstances, when the first node sends the first data signal every preset time interval, the second node can just process the previous first data signal and receive the new first data signal to start processing.

[0010] In the first aspect, the first node receives the first data or the first data signal, the first data signal is obtained by encoding the first data slice, and the first data slice is obtained by decomposing the first data; the first node sends the first data signal to the second node based on a preset time interval, and the preset time interval is determined based on the transmission distance between the first node and the second node. By configuring the interval for sending data regularly, the sending rate is controlled to ensure that the receiving end can effectively process the data within the time, and the feedback signal that increases the transmission delay is omitted in asynchronous clock-free communication, thereby reducing the transmission delay and improving the system throughput.

[0011] In a possible implementation manner of the first aspect, the method further includes: the first node sends first control information to the second node based on a preset time interval, and the sending priority of the first control information is higher than the first data signal.

[0012] In this possible implementation, the first node also sends control information to the second node to support control requirements during data transmission. Since the first control information often carries important control flow information, the sending priority of the first control information is higher than the first data signal.

[0013] In a possible implementation of the first aspect, the first control information includes at least one of a first repetition code, a first flow control code, a first parity check code and a first mode code, wherein the first repetition code is used to indicate that there are multiple first data signals with the same content being sent continuously; the first flow control code is used to indicate whether the first node is allowed to receive new data signals; the first parity check code is used to indicate that the first data sending is completed; and the first mode code is used to control the working mode switching of the first node.

[0014] In this possible implementation, the asynchronous multi-track transmission protocol used in the information transmission method adopts 2-of-7 encoding (using 7 transmission lines to represent 4 bits of data, and the encoding contains at most 2 1s). When encoding the first data slice, 16 combinations are used to represent 4 bits of data information, and the remaining 5 combinations are used to represent the first control information. By encoding the newly added control information, other functions of the feedback signal are further realized, thereby improving the flexibility and reliability of data transmission.

[0015] In a possible implementation manner of the first aspect, the method further includes: the first node receives a second data signal sent by the second node, the second data signal is obtained by encoding a second data slice, and the second data slice is obtained by decomposing the second data; the first node outputs the second data signal.

[0016] In this possible implementation, in addition to sending the first data signal to the second node, the first node also receives the second data signal sent by the second node, thereby realizing two-way communication and improving the feasibility of the solution.

[0017] In a possible implementation manner of the first aspect, the method further includes: the first node receiving second control information sent by the second node, and the sending priority of the second control information is higher than the second data signal.

[0018] In this possible implementation, the second node will also send control information to the first node, which improves the feasibility of the solution.

[0019] In a possible implementation of the first aspect, the second control information includes at least one of a second repetition code, a second flow control code, a second parity check code and a second mode code, wherein the second repetition code is used to indicate that there are multiple second data signals with the same content sent continuously; the second flow control code is used to indicate whether the second node is allowed to receive new data signals; the second parity check code is used to indicate that the second data sending is completed; and the second mode code is used to control the working mode switching of the second node.

[0020] In a possible implementation manner of the first aspect, the first node includes a sending module and a receiving module, the receiving module is used to send the second flow control code to the sending module, and the sending module is used to determine whether to continue sending the first data signal to the second node based on the second flow control code.

[0021] In this possible implementation, the sending module and the receiving module of the first node can also communicate with each other to achieve effective feedback of control information, avoid waiting for feedback signals during the sending process, and reduce communication delays. Similarly, the receiving module of the second node can also feedback control information to the sending module.

[0022] In a possible implementation of the first aspect, the above-mentioned step: the first node outputs the second data signal includes: the first node determines whether the second data signals within a preset number of receptions are all data signals obtained based on the second data; if the second data signals within the preset number of receptions are all data signals obtained based on the second data, the first node outputs the second data signal.

[0023] In this possible implementation, the first node uses a completion detection circuit with a self-timing mechanism to determine whether the second data signal has arrived stably, thereby solving the problems of large delay and inflexible coding of the traditional C-unit-based completion detection circuit.

[0024] In a possible implementation manner of the first aspect, the above step: the first node outputs the second data signal includes: the first node analyzes and couples the second data signal to obtain output data; and the first node outputs the output data.

[0025] In this possible implementation, when the first node needs to output the second data signal to the synchronization node, the second data signal needs to be analyzed and coupled, which improves the feasibility of the solution.

[0026] In a possible implementation manner of the first aspect, a transmission channel used by the first node to send a first data signal is a first communication channel, a transmission channel used by the first node to receive a second data signal is a second communication channel, and the first communication channel and the second communication channel are different transmission channels.

[0027] In this possible implementation, the first node and the second node adopt a full-duplex communication mode and transmit through dual channels to avoid data blocking and reduce data delay.

[0028] In a possible implementation manner of the first aspect, the method further includes: when the input data is first data, the first node decomposing the first data into first data slices; and the first node encoding the first data slices into first data signals.

[0029] In this possible implementation, when the input data is the first data input by the synchronization node, the first node also needs to decompose and encode the first data, which improves the feasibility of the solution.

[0030] In a second aspect of the present application, a communication node is provided, which is used to execute the method in the first aspect or any possible implementation of the first aspect. Specifically, the communication node includes a module or unit for executing the method in the first aspect or any possible implementation of the first aspect, such as a sending module and a receiving module.

[0031] The third aspect of the present application provides a communication device, which includes a processor, a memory, and a computer-readable storage medium storing a computer program; the processor is coupled to the computer-readable storage medium, and the computer executes instructions running on the processor. When the computer executes the instructions, the processor executes the method of the first aspect or any possible implementation of the first aspect. Optionally, the communication device may also include an input / output (I / O) interface, and the computer-readable storage medium storing the computer program may be a memory.

[0032] The fourth aspect of the present application provides a communication system, comprising at least two communication nodes, wherein the at least two communication nodes are used to execute a method as described in the first aspect or any possible implementation method of the first aspect to achieve communication, and the communication between the at least two communication nodes can be one-way or two-way.

[0033] The fifth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes a method as described in the first aspect or any possible implementation of the first aspect.

[0034] The sixth aspect of the present application provides a computer program product storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes a method as described in the first aspect or any possible implementation of the first aspect.

[0035] In the seventh aspect of the present application, a chip system is provided, which includes at least one processor and an interface, the interface is used to receive data and / or signals, and at least one processor is used to support a computer device to implement the functions involved in the above-mentioned first aspect or any possible implementation of the first aspect. In one possible design, the chip system may also include a memory, which is used to store program instructions and data necessary for the computer device. The chip system can be composed of chips, or it can include chips and other discrete devices.

[0036] In the embodiment of the present application, the first node receives the first data or the first data signal, the first data signal is obtained by encoding the first data slice, and the first data slice is obtained by decomposing the first data; the first node sends the first data signal to the second node based on a preset time interval, and the preset time interval is determined based on the transmission distance between the first node and the second node. By configuring the interval for sending data regularly, the sending rate is controlled to ensure that the receiving end can effectively process the data within the time, and the feedback signal that increases the transmission delay is omitted in asynchronous clock-free communication, thereby reducing the transmission delay and improving the system throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a scenario architecture diagram for interconnection between core particles;

[0038] Figure 2 This is the architecture diagram of the NoC internal interconnection scenario;

[0039] Figure 3A A schematic diagram of an embodiment of a communication system architecture provided in an embodiment of the present application;

[0040] Figure 3BA schematic diagram of an embodiment of a communication process provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of another embodiment of the information transmission method provided in the embodiment of the present application;

[0042] Figure 5 A schematic diagram of an embodiment of a first sending module provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of an embodiment of a programmable delay unit provided in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of another embodiment of the communication process provided in the embodiment of the present application;

[0045] Figure 8 A schematic diagram of another embodiment of the communication process provided in the embodiment of the present application;

[0046] Fig. 9 A schematic diagram of another embodiment of the first sending module provided in an embodiment of the present application;

[0047] Fig.10 A schematic diagram of an embodiment of a first receiving module provided in an embodiment of the present application;

[0048] Fig.11 A schematic diagram of an embodiment of a completion detection circuit provided in an embodiment of the present application;

[0049] Fig.12 A schematic diagram of another embodiment of the first receiving module provided in an embodiment of the present application;

[0050] Fig.13 A schematic diagram of another embodiment of the communication system architecture provided in an embodiment of the present application;

[0051] Fig.14 A schematic diagram of another embodiment of the communication system architecture provided in an embodiment of the present application;

[0052] Fig.15 A schematic diagram of another embodiment of the communication system architecture provided in an embodiment of the present application;

[0053] Fig.16 A schematic diagram of an embodiment of a communication node provided in an embodiment of the present application;

[0054] Fig.17 A schematic diagram of an embodiment of a communication system provided in an embodiment of the present application;

[0055] Fig.18 A schematic diagram of another embodiment of a communication system provided in an embodiment of the present application;

[0056] Fig.19 A schematic diagram of an embodiment of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only embodiments of a part of the present application, rather than all embodiments. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0058] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0060] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0061] The following is an example of the application scenario involved in the embodiments of the present application.

[0062] With the rapid development of system-on-chip (SoC), the scale of chips is getting larger and larger. In order to improve the communication efficiency between chips and within chips, it is necessary to reduce the communication delay. On the basis of the slowdown of chip manufacturing process update, the performance of existing synchronous circuit design has approached the limit bottleneck. Therefore, the asynchronous clock-free circuit design method is currently used to effectively reduce the delay and reduce dynamic power consumption.

[0063] like Figure 1As shown in the figure, in the scenario of interconnection between chiplets, the distance between chiplets may be far, and long-distance transmission interconnection will lead to large delays and difficulty in converging timing constraints. Figure 2 As shown in the figure, in the scenario of network on chip (NoC) processor, the internal network of NoC includes units such as central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), bridge, etc. The communication between these units requires extremely low latency. In addition, the communication between multiple NoCs also has low latency requirements.

[0064] However, in the current asynchronous clockless circuit design, the control flow is not flexible and reliable enough, and data is not sent during certain periods when data can be sent. In addition, the current asynchronous clockless circuit design also uses feedback signals to ensure the integrity and accuracy of data transmission, but the transmitter will not continue the next transmission until it receives the feedback signal. The waiting time also increases the transmission delay of the system, resulting in the problem of large transmission delay.

[0065] Based on this, the embodiment of the present application provides an information transmission method for flexibly controlling chip communication and reducing data transmission delay. The embodiment of the present application also provides corresponding communication nodes, communication devices, communication systems, computer-readable storage media, and computer program products, etc. The following are detailed descriptions.

[0066] like Figure 3A As shown, an embodiment of the present application provides a communication system architecture for achieving efficient transmission between nodes. The communication system architecture uses asynchronous clock-free signals and does not require feedback signals, thereby achieving the effect of saving power consumption and reducing delays.

[0067] The communication system architecture includes two symmetrical asynchronous communication transceiver nodes: Node A and Node B. Each node contains a transmitting module TX and a receiving module RX. The transmitting module and the receiving module can interact with each other, and the nodes use asynchronous multi-track coding for transmission. Full-duplex communication is used between nodes, that is, two nodes independently transmit data in both directions, each using an asynchronous multi-track coding transmission channel.

[0068] Among them, Figure 3BAs shown, the sending module TX can unpack the input data packet into data slices, and encode the data slices into asynchronous multi-track signals, etc. The receiving module receives the data sent through the asynchronous multi-track coding transmission channel and identifies the valid signal, decodes the valid signal into data slices, and packages the data slices into data packets and sends them to the next stage output.

[0069] Exemplarily, the sending module TX of node A obtains input data, transmits it to the receiving module RX of node B through an asynchronous multi-track coding transmission channel, and the receiving module RX of node B outputs the output data. Similarly, the sending module TX of node B obtains input data, transmits it to the receiving module RX of node A through an asynchronous multi-track coding transmission channel, and the receiving module RX of node A outputs the output data.

[0070] In addition, the sending module TX of node A also transmits control information to the receiving module RX of node B through the asynchronous multi-track coding transmission channel, and the receiving module RX of node B forwards the control information to the sending module TX of node B. Similarly, the sending module TX of node B also transmits control information to the receiving module RX of node A through the asynchronous multi-track coding transmission channel, and the receiving module RX of node A forwards the control information to the sending module TX of node A.

[0071] The communication system architecture can be applied to Figure 1 The scenario of chiplet interconnection shown can also be applied to Figure 2 In the NoC shown, for example, node A is a submodule in core A, and node B is a submodule in core B, thereby achieving low-latency communication between core A and core B. For another example, node A is a CPU in the NoC, and node B is a GPU in the NoC, thereby achieving low-latency communication within the NoC processor.

[0072] The information transmission method provided in the embodiment of the present application is described below in conjunction with the above application scenario.

[0073] like Figure 4 As shown, an embodiment of the information transmission method provided in the embodiment of the present application includes:

[0074] 401. A first node receives input data.

[0075] 402. A first node sends a first data signal to a second node based on a preset time interval.

[0076] In the embodiment of the present application, the information transmission method is applied to Figure 3A In the communication system shown in FIG. 1 , the first node is as follows: Figure 3A In the communication system shown in FIG. 1 , the second node is a node A. Figure 3AAlternatively, the first node is as follows Figure 3A In the communication system shown in FIG. 1 , the second node is a node B. Figure 3A The node A in the communication system shown in the figure has the same functions as the first node and the second node. The embodiment of the present application takes the first node as the node A for illustration.

[0077] The first node includes a first receiving module and a first sending module, and the second node includes a second receiving module and a second sending module. The first sending module of the first node is described in detail below. The input data received by the first sending module of the first node can be the first data or the first data signal, which are described below respectively.

[0078] 1. First Data

[0079] In the embodiment of the present application, the first data is a data packet sent by the synchronization node. When the input data is the first data, the first node decomposes the first data into first data slices and encodes the first data slices into first data signals. Figure 5 As shown, when the input data received by the first sending module is the first data, the first sending module is in form 1, and the first sending module includes an unpacking circuit, an encoding circuit, a programmable delay unit and a control circuit.

[0080] Specifically, the depacketizing circuit is used to depacketize the data packet from the synchronous domain node into a data slice format, which is then encoded into a first data signal (asynchronous transmission signal) by the encoding circuit. The programmable delay unit is a key module of the first sending module. Figure 6 As shown, the programmable delay unit is used to configure the interval of timing data transmission (i.e., the preset time interval) according to the actual line length information of the circuit design (i.e., the transmission distance between the first node and the second node), thereby controlling the transmission rate to ensure that the receiving end (i.e., the second node) can effectively process the data within the time. Since the transmission distance between the first node and the second node is determined, the preset time interval can also be determined based on multiple tests.

[0081] Wherein, after receiving the data slice transmitted by the unpacking circuit, the encoding circuit generates a data valid signal and sends it to the control circuit. After the programmable delay unit receives the start transmission signal from the control circuit, it starts to control the transmission interval, and after reaching the preset time interval, the delayed transmission signal is pulled high. In the control circuit, the data valid signal and the delayed transmission signal sent by the programmable delay unit work together to generate a self-clock signal. In the initial state, the delayed transmission signal is high. When the encoding circuit receives new valid data, the data valid signal is also high, then the self-clock signal is valid, and the self-clock signal is used to drive the transmission of data, for example, allowing the encoding circuit to start sending the first data signal. At this time, the control circuit is also used to pull down the data valid signal and the delayed transmission signal at the same time, and send a start transmission signal to the programmable delay unit to start the programmable delay unit. After a preset time interval, that is, after the first data signal is received by the second receiving module of the second node, the delayed transmission signal will be pulled high again, and wait for the next time to generate a new data valid signal, thereby achieving an event-driven data transmission and reception mechanism. In addition, the control circuit is also used to receive the second control information from the first receiving module of the node (the first node), and control whether to allow the first data signal to be sent based on the second control information.

[0082] Exemplarily, after the first sending module receives the first data, the unpacking circuit disassembles the first data into data slices, converts the synchronous data into asynchronous data, and the data slice is the smallest effective unit of the transmitted data, and the effective data of a data slice can be defined as 4 bits. The transmission protocol adopts asynchronous multi-track encoding, for example, as shown in Table 1, the encoding circuit adopts 2-of-7 encoding (using 7 transmission lines to represent 4-bit data, and the encoding contains at most 2 1s) to encode the data slice to obtain the first data signal, in which 16 combinations are used to represent 4-bit data information.

[0083] Table 1

[0084] Binary Data Reference code Binary Data Reference code 0000 001_0001 1000 100_0001 0001 001_0010 1001 100_0010 0010 001_0100 1010 100_0100 0011 001_1000 1011 100_1000 0100 010_0001 1100 000_0011 0101 010_0010 1101 000_0110 0110 010_0100 1110 000_1100 0111 010_1000 1111 000_1001

[0085] After obtaining the first data signal, the control circuit determines whether to send the first data signal based on the second control information of the first receiving module and the sending signal of the programmable delay unit. The second control information is sent by the second node to the first receiving module. After receiving the second control information, the first receiving module sends the second control information to the first sending module. If the second control information indicates to suspend sending the first data signal, for example, when the cache of the second node is full and cannot accept new data, the first sending module suspends sending the first data signal. When the first sending module receives the second control information from the second node again, the control circuit of the first sending module sends a start sending signal to the programmable delay unit, and the programmable delay unit sends a delayed sending signal to the control circuit. The control circuit controls the encoding circuit to start to continue sending the first data signal, that is, to send the first data signal to the second node after reaching the preset time interval.

[0086] For example, in Figure 3B On the basis of Figure 7 As shown, when the node of the first receiving module of node A (first node) is congested (the cache is full), the first sending module of node A will send the first flow control code to the second receiving module of node B (second node). After the second receiving module of node B receives the first flow control code, it sends the first flow control code to the second sending module of node B. The second sending module receives the first flow control code for the first time, and suspends sending the second data signal, or suspends sending data after sending the second data signal corresponding to a complete data packet in the second data. When the congestion of the first receiving module of node A is relieved, the first flow control code is sent using the same method as above. When the second sending module of node B receives the first flow control code for the second time, the second sending module continues to send the second data signal, or starts to send the second data signal corresponding to the next complete data packet in the second data.

[0087] The same, such as Figure 8 As shown, when the node of the second receiving module of node B (the second node) is congested (the cache is full), the second sending module of node B will send the second flow control code to the first receiving module of node A (the first node). After the first receiving module of node A receives the second flow control code, it sends the second flow control code to the first sending module of node A. The first sending module receives the first flow control code for the first time, and suspends sending the first data signal, or suspends sending data after sending the first data signal corresponding to a complete data packet in the first data. When the congestion of the second receiving module of node B is relieved, the second flow control code is sent using the same method as above. When the first sending module of node A receives the second flow control code for the second time, the first sending module continues to send the first data signal, or starts to send the first data signal corresponding to the next complete data packet in the first data.

[0088] 2. First Data Signal

[0089] In the embodiment of the present application, the first data signal is obtained by encoding the first data slice, and the first data slice is obtained by decomposing the first data. Fig. 9 As shown, when the input data received by the first sending module is the first data signal, the first sending module is form 2, and the first sending module includes a programmable delay unit and a control circuit. At this time, the first data signal is sent by the asynchronous node to the first node, that is, the asynchronous node or the node before the asynchronous node has processed the first data to obtain the first data signal. After the first sending module receives the first data signal, it only needs to control whether to allow the first data signal to be sent based on the second control information and the sending signal, and send the first data signal to the second node when allowed.

[0090] 403. The first node sends first control information to the second node based on a preset time interval.

[0091] In addition to sending the first data signal to the second node, the first node also sends the first control information to the second node. The first control information includes at least one of a first repetition code, a first flow control code, a first parity check code, and a first mode code, wherein the first repetition code is used to indicate that there are multiple first data signals with the same content that are sent continuously; the first flow control code is used to indicate whether the first node is allowed to receive a new data signal; the first parity check code is used to indicate that the first data has been sent; and the first mode code is used to control the working mode switching of the first node.

[0092] Table 2

[0093] Control Information Reference code Repeat code 000_0101 Flow Control Code 000_1010 Odd parity code 101_0000 Even parity code 110_0000 Mode Code 011_0000

[0094] Specifically, in 2-of-7 encoding, a total of 21 combinations can be formed. In addition to the 16 combinations used to represent data information, as shown in Table 2, the remaining 5 combinations are used to represent the first control information. When multiple first data signals with the same content are sent continuously, the first repetition code (repeat) is inserted at intervals in the continuously repeated data slices corresponding to the first data signal. When the first sending module receives the first first flow control code (flow ctrl), the second receiving module representing the second node can no longer receive new data, and the first sending module suspends sending the first data signal. If the first flow control code is received again, it means that the first sending module of this node is allowed to continue sending the first data signal. The first parity check code includes an odd check code (oddEOP) and an even check code (even EOP). The first parity check code is used for odd and even checks. It is generated at the end of a string of complete and valid first data signals to indicate the end of this string of first data signals. The first mode code (mode) is used to control the first node to switch between normal working mode and test mode.

[0095] Since the first control information often carries important control flow information, the sending priority of the first control information is higher than that of the first data signal.

[0096] It should be understood that the execution order of step 403 is not particular, for example, step 403 is executed before step 401, at which time the first node sends the first flow control code to the second node, which is used to indicate that the first node can no longer receive new data. For another example, step 403 is executed simultaneously with step 402, and in the process of the first node sending the first data signal to the second node, the first repetition code is inserted to distinguish the continuous repeated data slices corresponding to the first data signal.

[0097] It should be understood that the structure of the second sending module of the second node, and the methods and functions implemented are the same as those of the first sending module of the first node mentioned above, and the embodiments of the present application will not be repeated here.

[0098] 404. The first node receives a second data signal sent by the second node.

[0099] 405. The first node outputs a second data signal.

[0100] The first receiving module of the first node is described in detail below. The data sent by the second node and received by the first receiving module of the first node is a second data signal, wherein the second data signal is obtained by encoding the second data slice, and the second data slice is obtained by decomposing the second data. It can be the second data signal obtained by the second node processing the second data, or it can be the second data signal obtained by the predecessor node of the second node processing the second data and sending the second data signal to the second node. After receiving the second data signal, the first receiving module outputs the second data signal. The first receiving module may output the second data signal directly to the asynchronous node, or it may process the second data signal into the second data and then output it to the synchronous node, which are described below respectively.

[0101] 1. Second Data

[0102] When the first receiving module needs to output the second data signal to the synchronization node, the first receiving module is in form 1, such as Fig.10 As shown, the first receiving module includes a completion detection circuit, a decoding circuit, a packet assembly circuit and a control circuit.

[0103] After the second data signal is input into the first receiving module, it first passes through the completion detection circuit, such as Fig.11As shown, the completion detection circuit includes a register, an XOR gate, a judgment unit and a self-timing detection circuit. Among them, the register is responsible for outputting a stable signal (second data signal), the register's registration clock signal is given by the self-timing detection circuit, the XOR gate is used to identify whether it is currently in the detection stage or the stabilization stage, the judgment unit starts the detection according to the result of the XOR gate, and detects whether there is new input data. The timing detection circuit determines whether the current input data is stable by judging whether the input data is the same within a certain number of times, and outputs a registration clock signal (registration pulse signal). If it is not the same, it will be re-counted, that is, the first node determines whether the second data signals within the preset number of receptions are all data signals obtained based on the second data. If the second data signals within the preset number of receptions are all data signals obtained based on the second data, the decoding circuit analyzes the second data signal that has been determined to be stable, and sends the analyzed data to the packet assembly circuit. The packet assembly circuit is also used to convert asynchronous data into synchronous data. The control circuit controls the packet assembly circuit to send the coupled output data according to the data valid signal sent by the decoding circuit.

[0104] 2. Second Data Signal

[0105] like Fig.12 As shown, when the first receiving module needs to output the second data signal to the asynchronous node, the first receiving module is in form 2, and the first receiving module includes a completion detection circuit and a control circuit, that is, the first receiving module does not need to parse and package the second data signal, but directly continues to output the second data signal.

[0106] 406. The first node receives second control information sent by the second node.

[0107] In addition to receiving the second data signal sent by the second node, the first node also receives second control information sent by the second node, where the second control information includes at least one of a second repetition code, a second flow control code, a second parity check code and a second mode code, wherein the second repetition code is used to indicate that there are multiple second data signals with the same content sent continuously; the second flow control code is used to indicate whether the second node is allowed to receive a new data signal; the second parity check code is used to indicate that the second data has been sent; and the second mode code is used to control the working mode switching of the second node, that is, the content of the second control information is the same as the first control information, and the sending priority of the second control information is higher than the second data signal.

[0108] Exemplarily, the first receiving module of the first node receives second control information sent by the second node, and the second control information is a second flow control code. At this time, the first receiving module continues to send the second flow control code to the first sending module. When the first sending module receives the second flow control code for the first time, it suspends sending the first data signal to the second node. When the second sending module receives the second flow control code again, the first sending module continues to send the first data signal to the second node.

[0109] It should be understood that the execution order of step 406 is not particular, for example, step 406 is executed before step 404, at which time the first node receives the second flow control code from the second node, which is used to indicate that the second node can no longer receive new data. For another example, step 403 is executed simultaneously with step 402, and in the process of the first node receiving the second data signal from the second node, the first repetition code is inserted into the second data signal to distinguish the continuous repeated data slices corresponding to the second data signal.

[0110] In addition, the execution order of step 404-step 406 is independent of step 401-step 403, that is, the sending and receiving processes of the first node can be performed simultaneously or one after another, and the embodiment of the present application does not limit this.

[0111] It should be understood that the structure of the second receiving module of the second node, and the methods and functions implemented are the same as those of the first receiving module of the first node mentioned above, and the embodiments of the present application will not be repeated here.

[0112] In the embodiment of the present application, the transmission channel used by the first node to send the first data signal is the first communication channel, and the transmission channel used by the first node to receive the second data signal is the second communication channel. The first communication channel and the second communication channel are different transmission channels.

[0113] In the embodiment of the present application, the information transmission method is event-driven, does not work when there is no event, saves circuit dynamic power consumption, and the transmission adopts a self-clocking method, saves global clock tree overhead, and brings power consumption benefits. Secondly, the information transmission method uses a two-phase non-return-to-zero handshake, which reduces the delay by half compared to the four-phase handshake, and there is no feedback signal (such as ack signal), which further reduces the delay and brings power consumption benefits. In addition, the data transmission of the information transmission method has a certain degree of leniency, and does not require the harsh timing requirements required for synchronous node design, which brings flexibility benefits.

[0114] The information transmission method provided in the embodiment of the present application can be applied to a variety of different communication system architectures. The information transmission method provided in the embodiment of the present application is described in detail below with reference to several examples.

[0115] Example 1

[0116] like Fig.13As shown, in the communication system architecture, the synchronization domain includes a synchronization node S1 and a synchronization node S2, and the asynchronous domain includes a first node A1 and a second node A2. When data needs to be transmitted between the synchronization node S1 and the synchronization node S2, the first node A1 and the second node A2 are set between the synchronization node S1 and the synchronization node S2, and the first sending module, the first receiving module, the second sending module and the second receiving module are all in form 1.

[0117] Exemplarily, the first sending module of the first node A1 receives the first data input by the synchronization node S1, processes the first data into a first data signal, and sends it to the second receiving module of the second node A2 through the first communication channel. The second receiving module restores the first data signal to the first data and sends it to the synchronization node S2.

[0118] Similarly, the second sending module of the second node A2 receives the second data input by the synchronization node S2, processes the second data into a second data signal, and sends it to the first receiving module of the first node A1 through the second communication channel. The first receiving module restores the second data signal into second data and sends it to the synchronization node S1.

[0119] In addition, in the first node A1, the first receiving module also receives the second control information sent by the second node A2, and the first receiving module continues to send the second control information to the first sending module. In the second node A1, the second receiving module also receives the first control information sent by the first node A1, and the second receiving module continues to send the first control information to the second sending module.

[0120] It should be understood that Fig.13 The architecture shown can also be understood as a point-to-point networking mode (excluding an asynchronous routing module). This architecture can be adapted and connected to a standard synchronous interface, which can greatly reduce the transmission delay between the synchronous node S1 and the synchronous node S2.

[0121] Example 2

[0122] like Fig.14 As shown, in the communication system architecture, the synchronization domain includes a synchronization node S1, a synchronization node S2, a synchronization node S3 and a synchronization node S4, and the asynchronous domain includes a first node A1, a second node A2, a third node A3, a fourth node A4 and an asynchronous routing module R1. When data needs to be transmitted between the synchronization nodes S1, S2, S3 and S4, the first node A1, the second node A2, the third node A3 and the fourth node A4 are respectively set between the synchronization nodes S1, S2, S3 and S4, wherein the first node A1, the second node A2, the third node A3 and the fourth node A4 can be the first node or the second node described in the above embodiments.

[0123] In addition, an asynchronous routing module R1 is also set between the first node A1, the second node A2, the third node A3 and the fourth node A4. The asynchronous routing module R1 includes a node R1N, a node R1W, a node R1E and a node R1S. The node R1N, the node R1W, the node R1E and the node R1S can respectively be the first node or the second node described in the above embodiments.

[0124] Among them, the sending module and receiving module of the first node A1, the second node A2, the third node A3 and the fourth node A4 are all form 1, which are used to transmit data between synchronous nodes and asynchronous nodes, and the sending module and receiving module in the asynchronous routing module R1 are all form 2, which are used to transmit data between asynchronous nodes.

[0125] It should be understood that Fig.14 The architecture shown can also be understood as a streamlined networking mode (including an asynchronous routing module), which improves the data transmission capacity of the synchronization node S1-synchronization node S4. Secondly, the intermediate routing is also implemented in an asynchronous manner, further improving the efficiency of data forwarding.

[0126] Example 3

[0127] like Fig.15 As shown, based on Example 2, when data needs to be transmitted between synchronization nodes S1, S2, S3, S4, S5, S6, S7 and S8, a first node A1, a second node A2, a third node A3, a fourth node A4, a fifth node A5, a sixth node A6, a seventh node A7 and an eighth node A8 are respectively set between synchronization nodes S1, S2, S3, S4, S5, S6, S7 and S8. The first node A1, the second node A2, the third node A3, the fourth node A4, the fifth node A5, the sixth node A6, the seventh node A7 and the eighth node A8 can be the first node or the second node described in the above embodiments.

[0128] In addition, an asynchronous routing module R1, an asynchronous routing module R2 and an asynchronous routing module R3 are also provided between the first node A1, the second node A2, the third node A3, the fourth node A4, the fifth node A5, the sixth node A6, the seventh node A7 and the eighth node A8. The asynchronous routing module R1 includes a node R1N, a node R1W, a node R1E and a node R1S. The asynchronous routing module R2 includes a node R2N, a node R2W, a node R2E and a node R2S. The asynchronous routing module R3 includes a node R3N, a node R3W, a node R3E and a node R3S. The node R1N, the node R1W, the node R1E, ​​the node R1S, the node R2N, the node R2W, the node R2E, the node R2S, the node R3N, the node R3W, the node R3E and the node R3S can be the first node or the second node described in the above embodiments respectively.

[0129] It should be understood that Fig.15 The architecture shown can also be understood as an elastic networking mode (including asynchronous routing modules, and there is communication between asynchronous routing modules). It can be well expanded in a scale-out (an architectural technology that usually refers to distributing the computing and storage resources in the system to multiple nodes to expand the system's functions and performance) manner, so it is also highly adaptable to large-scale NoC architectures.

[0130] Summarizing the above embodiments, it can be seen that the beneficial effects brought by the information transmission method provided in the embodiments of the present application include but are not limited to the following four points:

[0131] (1) By configuring the interval for sending data at a fixed time, the sending rate is controlled to ensure that the receiving end can effectively process the data within this time. In addition, the feedback signal that increases the transmission delay is eliminated in asynchronous clock-free communication, thereby reducing the transmission delay and improving the system throughput. This solves the problem of inflexible and unreliable control flow in asynchronous transmission systems.

[0132] (2) Repetition codes are used to transmit continuous repeated data to achieve non-return-to-zero transmission. Only when the other end needs feedback information, control information is inserted into the original data transmission channel to achieve feedback, thus achieving no feedback signal, thereby solving the problem of large data detection delay and large area at the receiving end in the asynchronous transmission system.

[0133] (3) By adding the encoding of control information, other functions of the feedback signal are further realized, improving the flexibility and reliability of data transmission.

[0134] (4) A completion detection circuit with a self-timing mechanism is used to determine whether the data has arrived stably, thereby solving the problem of large delay and inflexible coding of the traditional C-unit-based completion detection circuit.

[0135] The above introduces the information transmission method provided in the embodiment of the present application. The following introduces the related equipment provided in the embodiment of the present application in conjunction with the accompanying drawings.

[0136] like Fig.16 As shown, an embodiment of the communication node 1600 provided in the embodiment of the present application includes:

[0137] The sending module 1601 is used to receive input data, where the input data is first data or a first data signal, where the first data signal is obtained by encoding a first data slice, and where the first data slice is obtained by decomposing the first data; the sending module 1601 is used to execute step 401 in the above method embodiment.

[0138] The sending module 1601 is further used to send the first data signal to the second node based on a preset time interval, where the preset time interval is determined based on a transmission distance between the communication node and the second node. The sending module 1601 is also used to execute step 402 in the above method embodiment.

[0139] Optionally, the sending module 1601 is further configured to send first control information to the second node based on a preset time interval, and the sending priority of the first control information is higher than the first data signal.

[0140] Optionally, the first control information includes at least one of a first repetition code, a first flow control code, a first parity check code and a first mode code, wherein the first repetition code is used to indicate that there are multiple first data signals with the same content being sent continuously; the first flow control code is used to indicate whether the first node is allowed to receive new data signals; the first parity check code is used to indicate that the first data sending is completed; and the first mode code is used to control the working mode switching of the first node.

[0141] Optionally, the communication node 1600 also includes a receiving module 1602, which is used to receive a second data signal sent by a second node, where the second data signal is obtained by encoding a second data slice, which is obtained by decomposing the second data; the receiving module 1602 is also used to output the second data signal.

[0142] Optionally, the receiving module 1602 is further configured to receive second control information sent by the second node, and the sending priority of the second control information is higher than the second data signal.

[0143] Optionally, the second control information includes at least one of a second repetition code, a second flow control code, a second parity check code and a second mode code, wherein the second repetition code is used to indicate that there are multiple second data signals with the same content being sent continuously; the second flow control code is used to indicate whether the second node is allowed to receive new data signals; the second parity check code is used to indicate that the second data sending is completed; and the second mode code is used to control the working mode switching of the second node.

[0144] Optionally, the receiving module 1602 is used to send the second flow control code to the sending module, and the sending module 1601 is used to determine whether to continue sending the first data signal to the second node based on the second flow control code.

[0145] Optionally, the receiving module 1602 is specifically used to determine whether the second data signals within a preset number of receptions are all data signals obtained based on the second data; the receiving module 1602 is also specifically used to output the second data signal if the second data signals within the preset number of receptions are all data signals obtained based on the second data.

[0146] Optionally, the receiving module 1602 is specifically used to analyze and couple the second data signal to obtain output data; the receiving module 1602 is also used to output the output data.

[0147] Optionally, the transmission channel used by the sending module 1601 to send the first data signal is the first communication channel, the transmission channel used by the receiving module 1602 to receive the second data signal is the second communication channel, and the first communication channel and the second communication channel are different transmission channels.

[0148] Optionally, the sending module 1601 is further used to decompose the first data into first data slices when the input data is first data; the sending module 1601 is further used to encode the first data slices into first data signals.

[0149] The communication node 1600 provided in the embodiment of the present application can be Figure 1 The core particle A or core particle B or its internal module shown may also be Figure 2 The CPU, NPU, GPU or bridge shown can also be Figure 3A The node A or node B shown can also be Figure 4 The specific implementation of the first node or the second node shown can be understood by referring to the corresponding content of the aforementioned information transmission method embodiment part, and will not be repeated here.

[0150] like Fig.17 As shown, the embodiment of the present application also provides a communication system 1700, the communication system 1700 includes at least two Fig.16 As shown in the communication nodes, at least two communication nodes perform bidirectional communication. Fig.18 As shown, in another possible implementation, the communication system 1800 is used for one-way communication, and one communication node in the communication system 1800 includes only a sending module, and another communication node includes only a receiving module. The sending module can be as follows Figure 5 or Fig. 9 The first sending module shown in FIG. 1 and the receiving module may be as follows: Fig.10 or Fig.12The first receiving module is shown.

[0151] The communication system 1700 and the communication system 1800 may be as follows: Figure 1-Figure 3A , Figure 4 or Figure 13-Figure 15 The communication system architecture shown has the same beneficial effects and will not be repeated here.

[0152] like Fig.19 As shown, an embodiment of the present application also provides a communication device 1900. The communication device 1900 includes: a processor 1901, a communication interface 1902, a memory 1903 and a bus 1904. The processor 1901 may include a CPU, or a CPU and at least one of a GPU, an NPU and other types of processors. The processor 1901, the communication interface 1902 and the memory 1903 are interconnected via the bus 1904. In an embodiment of the present application, the processor 1901 is used to control and manage the actions of the communication device 1900. For example, the processor 1901 is used to execute Figure 4 The communication interface 1902 is used to support the communication device 1900 to communicate. The memory 1903 is used to store program codes and data of the communication device 1900.

[0153] Among them, processor 1901 can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the contents disclosed in this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on. Bus 1904 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.19 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0154] In another embodiment of the present application, a computer-readable storage medium is provided, in which computer-executable instructions are stored. When at least one processor of a device executes the computer-executable instructions, the device executes the information transmission method described in the above embodiment.

[0155] In another embodiment of the present application, a computer program product is also provided, which includes computer execution instructions, which are stored in a computer-readable storage medium; at least one processor of the device can read the computer execution instructions from the computer-readable storage medium, and at least one processor executes the computer execution instructions so that the device executes the information transmission method described in the above embodiment.

[0156] In another embodiment of the present application, a chip system is also provided, the chip system includes at least one processor and an interface, the interface is used to receive data and / or signals, and at least one processor is used to support the information transmission method described in the above embodiment. In one possible design, the chip system may also include a memory, the memory is used to store program instructions and data necessary for the computer device. The chip system can be composed of chips, or it can include chips and other discrete devices.

[0157] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0158] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0159] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0160] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0161] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0162] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.

Claims

1. A method for transmitting information, It is characterized in that include: The first node receives input data, where the input data is first data or a first data signal, where the first data signal is obtained by encoding a first data slice, and where the first data slice is obtained by decomposing the first data; The first node sends the first data signal to the second node based on a preset time interval, and the preset time interval is determined based on a transmission distance between the first node and the second node.

2. The method according to claim 1, It is characterized in that The method further comprises: The first node sends first control information to the second node based on the preset time interval, and the sending priority of the first control information is higher than the first data signal.

3. The method according to claim 2, It is characterized in that The first control information includes at least one of a first repetition code, a first flow control code, a first parity check code, and a first mode code, wherein: The first repetition code is used to indicate that there are multiple first data signals with the same content that are sent continuously; The first flow control code is used to indicate whether the first node is allowed to receive a new data signal; The first parity check code is used to indicate that the first data has been sent; The first mode code is used to control the switching of the working mode of the first node.

4. The method according to any one of claims 1 to 3, It is characterized in that The method further comprises: The first node receives a second data signal sent by the second node, where the second data signal is obtained by encoding a second data slice, and the second data slice is obtained by decomposing the second data; The first node outputs the second data signal.

5. The method according to claim 4, It is characterized in that The method further comprises: The first node receives second control information sent by the second node, and the sending priority of the second control information is higher than the second data signal.

6. The method according to claim 5, It is characterized in that The second control information includes at least one of a second repetition code, a second flow control code, a second parity check code, and a second mode code, wherein: The second repetition code is used to indicate that there are multiple second data signals with the same content that are sent continuously; The second flow control code is used to indicate whether the second node is allowed to receive a new data signal; The second parity check code is used to indicate that the second data has been sent; The second mode code is used to control the switching of the working mode of the second node.

7. The method according to claim 6, It is characterized in that The first node includes a sending module and a receiving module, the receiving module is used to send the second flow control code to the sending module, and the sending module is used to determine whether to continue sending the first data signal to the second node based on the second flow control code.

8. The method according to any one of claims 4 to 7, It is characterized in that The first node outputting the second data signal comprises: Determining, by the first node, whether all of the second data signals received within a preset number of times are data signals obtained based on the second data; If the second data signals received within the preset number of times are all data signals obtained based on the second data, the first node outputs the second data signal.

9. The method according to any one of claims 4 to 8, It is characterized in that The first node outputting the second data signal comprises: The first node analyzes and couples the second data signal to obtain output data; The first node outputs the output data.

10. The method according to any one of claims 4 to 9, It is characterized in that A transmission channel used by the first node to send the first data signal is a first communication channel, a transmission channel used by the first node to receive the second data signal is a second communication channel, and the first communication channel and the second communication channel are different transmission channels.

11. The method according to any one of claims 1 to 10, It is characterized in that The method further comprises: When the input data is the first data, the first node decomposes the first data into the first data slices; The first node encodes the first data slice into the first data signal.

12. A communication node, It is characterized in that include: a sending module, configured to receive input data, wherein the input data is first data or a first data signal, wherein the first data signal is obtained by encoding a first data slice, and the first data slice is obtained by decomposing the first data; The sending module is further used to send the first data signal to the second node based on a preset time interval, and the preset time interval is determined based on a transmission distance between the communication node and the second node.

13. The node according to claim 12, It is characterized in that The sending module is further configured to send first control information to the second node based on the preset time interval, and the sending priority of the first control information is higher than that of the first data signal.

14. The node according to claim 13, It is characterized in that The first control information includes at least one of a first repetition code, a first flow control code, a first parity check code, and a first mode code, wherein: The first repetition code is used to indicate that there are multiple first data signals with the same content that are sent continuously; The first flow control code is used to indicate whether the first node is allowed to receive a new data signal; The first parity check code is used to indicate that the first data has been sent; The first mode code is used to control the switching of the working mode of the first node.

15. A node according to any one of claims 12 to 14, It is characterized in that The node also includes: a receiving module, configured to receive a second data signal sent by the second node, where the second data signal is obtained by encoding a second data slice, where the second data slice is obtained by decomposing the second data; The receiving module is further configured to output the second data signal.

16. The node according to claim 15, It is characterized in that The receiving module is further configured to receive second control information sent by the second node, wherein the sending priority of the second control information is higher than that of the second data signal.

17. The node according to claim 16, It is characterized in that The second control information includes at least one of a second repetition code, a second flow control code, a second parity check code, and a second mode code, wherein: The second repetition code is used to indicate that there are multiple second data signals with the same content that are sent continuously; The second flow control code is used to indicate whether the second node is allowed to receive a new data signal; The second parity check code is used to indicate that the second data has been sent; The second mode code is used to control the switching of the working mode of the second node.

18. The node according to claim 17, It is characterized in that The receiving module is used to send the second flow control code to the sending module, and the sending module is used to determine whether to continue sending the first data signal to the second node based on the second flow control code.

19. A node according to any one of claims 15 to 18, It is characterized in that The receiving module is specifically used to determine whether the second data signals within a preset number of receptions are all data signals obtained based on the second data; the receiving module is also specifically used to output the second data signal if the second data signals within the preset number of receptions are all data signals obtained based on the second data.

20. A node according to any one of claims 15 to 19, It is characterized in that The receiving module is specifically used for analyzing and coupling the second data signal to obtain output data; the receiving module is also used for outputting the output data.

21. A node according to any one of claims 15 to 20, It is characterized in that The transmission channel used by the sending module to send the first data signal is a first communication channel, and the transmission channel used by the receiving module to receive the second data signal is a second communication channel. The first communication channel and the second communication channel are different transmission channels.

22. A node according to any one of claims 12 to 21, It is characterized in that The sending module is further used for decomposing the first data into the first data slices when the input data is the first data; the sending module is further used for encoding the first data slices into the first data signal.

23. A communication device, It is characterized in that The method comprises a processor on which a computer-executable instruction runs. When the computer-executable instruction is executed by the processor, the processor executes the method according to any one of claims 1 to 11.

24. A communication system, It is characterized in that The method comprises at least two communication nodes, wherein the at least two communication nodes are used to execute the method according to any one of claims 1 to 11.

25. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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