Wake-up radio with stacked circuit configuration with ultra-low power consumption

Abstract

In one embodiment, an apparatus includes a wake-up radio to issue a trigger signal in response to detection of a wake-up message in a radio frequency (RF) signal; and a second radio coupled to the wake-up radio, the second radio to wake up in response to receipt of the trigger signal. The wake-up radio may be coupled to a second radio without substantial loading, and may be configured with stacked circuitry to reuse current.

Description

Background Art

[0001] Radios are incorporated into increasingly smaller and evolving types of devices. Current trends extend the use of radios to small, low-cost, low-power devices, including various Internet of Things (IoT) devices.

[0002] Suggestions for reducing power consumption include providing a radio with lower power consumption that can be used for the purpose of triggering the wake-up of the main radio. However, the complexity involved in such a radio (which detects whether there is a request for communication and, if so, enables the main receiver) can still consume high power, resulting in short battery life.

[0003] Available low-power Bluetooth Low Energy (BLE) receivers typically consume about 10 milliwatts (mW) of power. This level of power consumption is quite high for a wake-up receiver. Therefore, it is desirable for the wake-up receiver to have much less power consumption than the main receiver.

[0004] Other solutions provide low-power radio frequency (RF) signal detectors coupled to the input of a low noise amplifier (LNA). However, this technology can only detect the presence of any RF signal in a wideband, not in a specific narrow channel. Summary of the invention

[0005] In one aspect, a device includes a plurality of stacked circuits. A first stacked circuit may include: a low noise amplifier (LNA) for receiving and amplifying a radio frequency (RF) signal; and a voltage controlled oscillator (VCO) coupled to the LNA, the VCO generating at least one clock signal. The first stacked circuit is coupled to a supply voltage node and is to reuse a first current for the LNA and the VCO. A second stacked circuit may be coupled to the first stacked circuit and may include: a local oscillator (LO) generation circuit for generating at least one LO clock signal based at least in part on at least one clock signal; and at least one buffer coupled to the LO generation circuit for buffering at least one LO clock signal and outputting a differential complex clock signal. The second stacked circuit is coupled to a supply voltage node and is to reuse a second current for the LO generation circuit and at least one buffer.

[0006] In one implementation, the device further includes a low dropout regulator coupled to the supply voltage node, the low dropout regulator for providing a regulated voltage to the supply voltage node. The VCO may be an open loop VCO. An automatic frequency control loop may be coupled to the VCO to regulate the VCO at a frequency significantly lower than the clock signal. The VCO is coupled to the supply voltage node, and the LNA is coupled to the reference voltage node, the LNA being coupled to the VCO at a midpoint of the first stacked circuit.

[0007] In an implementation, the device further includes a polyphase filter coupled between the VCO and the LO generation circuit, the polyphase filter for receiving at least one clock signal and outputting a multiphase clock signal. The at least one buffer may include a first buffer for buffering the differential complex clock signal, and the LO generation circuit may be implemented with a duty cycle pulse generator to provide at least one LO clock signal for mixing with the amplified RF signal.

[0008] In an implementation, the device further includes a transimpedance amplifier (TIA) coupled to the second stacked circuit, the TIA for receiving and amplifying an intermediate frequency (IF) signal, the IF signal being based on the RF signal. The device may also include: a peak detector coupled to the TIA, the peak detector for detecting a peak signal of the amplified IF signal; and a comparator for comparing the peak signal with a threshold signal. The peak detector is to self-generate a threshold signal based on the peak signal. The LNA of the first stacked circuit may be configured to provide a low impedance at DC to achieve a stable midpoint voltage for the first stacked circuit.

[0009] In another aspect, an apparatus includes a peak detector for receiving a quadrature IF signal and outputting a maximum signal of the quadrature IF signal at an output node, the peak detector comprising a switched capacitor circuit for storing the maximum signal and generating a threshold signal; and a comparator coupled to the peak detector, the comparator for comparing the maximum signal with the threshold signal.

[0010] In an embodiment, the peak detector is to self-generate a threshold signal. The threshold signal comprises an average value of the maximum signal. The switched capacitor circuit may comprise: a holding circuit for holding the maximum signal with droop, the holding circuit comprising at least one first capacitor and at least one first switch, the at least one first switch being controlled by the first phase signal. The switched capacitor circuit may further comprise: a low pass filter coupled to the holding circuit, wherein the low pass filter is to provide the threshold signal to the comparator circuit.

[0011] In an embodiment, the apparatus further comprises: a second switch controlled by the first phase signal, the second switch for coupling the threshold signal to the comparator circuit; and a third switch controlled by the second phase signal to couple the maximum signal to the comparator circuit.

[0012] In yet another aspect, an apparatus includes a wake-up radio for issuing a trigger signal in response to detection of a wake-up message in an RF signal, and a second radio coupled to the wake-up radio, the second radio for waking up in response to receipt of the trigger signal. The wake-up radio may be coupled to the second radio without substantial loading.

[0013] In an example, a wake-up radio device includes: a low dropout regulator for providing a supply voltage to a supply voltage node; a first stacked circuit coupled to the supply voltage node, and a second stacked circuit coupled to the supply voltage node. The first stacked circuit may include: an amplifier for receiving and amplifying an RF signal; and an oscillator coupled to the amplifier, the oscillator for generating at least one clock signal, wherein the first stacked circuit is to reuse a first current for the amplifier and the oscillator. The second stacked circuit may include: a clock generation circuit for receiving at least one clock signal and outputting a multi-phase clock signal; and at least one buffer coupled to the clock generation circuit to buffer the multi-phase clock signal and output a set of clock signals, wherein the second stacked circuit is to reuse a second current for the clock generation circuit and the at least one buffer.

[0014] The device may further include a TIA coupled to the supply voltage node, the first stack circuit, and the second stack circuit, the TIA for receiving and amplifying an IF signal, the IF signal being based on the RF signal. The device may also include: a peak detector for receiving the IF signal and outputting a maximum signal of the IF signal, the peak detector including a switched capacitor circuit for storing the maximum signal and a threshold signal; and a comparator coupled to the peak detector, the comparator for comparing the maximum signal with the threshold signal and outputting a trigger signal when the maximum signal exceeds the threshold signal

[0015] In an example, the amplifier may include: a plurality of gain slices; and a plurality of dummy load circuits coupled to the plurality of gain slices.

[0016] The apparatus may further include a controller for: controlling a number of the plurality of slices to be enabled based at least in part on the gain control signal; and coupling at least one of the plurality of dummy loads to a midpoint of the first stack circuit when a corresponding slice of the plurality of slices is disabled. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1is a block diagram of a wireless communication environment according to an embodiment.

[0018] Figure 2A is a block diagram illustrating an arrangement of a wake-up packet according to an embodiment.

[0019] Figure 2B is a transmission power spectrum of wake-up communication according to an embodiment.

[0020] Figure 2C is a time domain plot of a MOOK modulated wake-up packet according to an embodiment.

[0021] Figure 3A is a block diagram of a portion of a wake-up receiver according to an embodiment.

[0022] Figure 3B It is a graphic with Figure 3A Timing diagram of the various signals associated with the wake-up radio device.

[0023] Figure 4 is a schematic diagram of a portion of a wake-up radio according to an embodiment.

[0024] Figure 5 is another schematic diagram of a portion of a wake-up radio according to an embodiment.

[0025] Figure 6 is a schematic diagram of a peak detector and a comparator according to an embodiment.

[0026] Figure 7 Depicts many of the waveforms associated with the IF, peak detector, and comparator circuits.

[0027] Figure 8 is a block diagram of a representative integrated circuit incorporating an embodiment.

[0028] Fig. 9 is a high-level diagram of a network according to an embodiment. DETAILED DESCRIPTION

[0029] In various embodiments, a device is provided with multiple radios, including a main radio and a wake-up radio (WuR), which is a low-power radio defined to enable the device to save power by using it to wake up the rest of the device when needed. The embodiments described herein are used in conjunction with a Bluetooth Low Energy (BLE) radio to prevent its use when there is no activity on the device.

[0030] In various embodiments, the wake-up radio can be implemented in a configuration that achieves ultra-low power operation (less than 200 microwatts). Although low power, this wake-up receiver meets or exceeds the BLE standard requirements in terms of sensitivity and interceptor performance. In order to meet this tight power consumption budget, a current reuse architecture is used to stack circuits with similar current consumption between the supply voltage and the ground level.

[0031] In one or more embodiments, a radio frequency (RF) oscillator and a low noise amplifier (LNA), which are the highest current consumption blocks, are stacked together in a first stack circuit. A second stack circuit may in turn include a clock generation circuit system for generating a 25% duty cycle local oscillator (LO) signal and one or more LO buffers. In this configuration, a large portion (e.g., more than 75%) of the power consumption budget is consumed in the RF circuit of the first stack circuit. By stacking these circuits, bias current can be reused, allowing the radio device to meet a tight current consumption budget, which in an implementation is only 110 microamps with a 1.8 volt (V) power supply.

[0032] This wake-up radio device can be implemented as a zero intermediate frequency (IF) receiver that provides channel selectivity while detecting RF signals. In one or more embodiments, the receiver has a very low input capacitive loading (e.g., approximately 30 femtofarads (fF)) and can therefore be directly coupled to the LNA input of the main receiver with minimal impact on the main receiver.

[0033] Thus, in an example, this WuR can be designed and controlled as described herein to achieve a significant improvement in power consumption relative to the main receiver (e.g., a 50x improvement in power consumption (<200 μW)) with a fast wake-up time (<20 ms) while maintaining a sensitivity of -89.5 dBm at a bit error rate (BER) of 0.1%. Although the wake-up receiver may consume 200 μW, by duty cycling the on time, power consumption as low as 2 μW can be achieved at the expense of increased latency. As will be described herein, these power savings can be achieved by design and configuration of the receiver and its control so that the activities of different parts of the receiver are tightly scheduled in a power-conscious manner.

[0034] Reference now Figure 1 , which is a block diagram of a wireless communication environment according to an embodiment. Figure 1As shown in , a wireless communication environment 100 such as a wireless local area network (WLAN) includes various devices such as Internet of Things (IoT) devices, including a transmitter 110 and a receiver 120. Although the embodiments are not limited in this regard, for the purpose of discussion, it is assumed that these components communicate via at least one wireless communication protocol (such as one or more Bluetooth protocols). The components may also be configured to communicate according to other wireless communication protocols (including Wi-Fi, cellular communications (e.g., 5G or higher), etc.). Although only two devices are shown for ease of discussion, additional devices may exist in other embodiments.

[0035] With embodiments, significant power consumption savings can be achieved by keeping at least the main radio circuitry of the receiver 120 in a low power mode (typically it will be completely powered off) unless a given communication is to occur between the devices. To this end, at least the receiver 120 may include a wake-up radio (WuR). More specifically, as shown, in addition to the Bluetooth radio 122 (which may be the main or primary Bluetooth receiver), the receiver 120 also includes a WuR 124. In some embodiments, in addition to the Bluetooth radio 112 (which may be the main or primary Bluetooth transmitter), the transmitter 110 may also include a WuR ( Figure 1 not shown).

[0036] With this arrangement, the main radio component of the device can remain in a low power mode until communication is to occur. When operating in wake-up mode, the transmitter initiates a wake-up event to communicate with the receiver. To initiate the wake-up of the Bluetooth radio 122, the Bluetooth radio 112 transmits a wake-up signal 118, which is to be received by the wake-up radio 124. Upon successful reception and processing of the wake-up signal 118 (which may include a wake-up protocol data unit (PDU) in an embodiment), the wake-up radio 124 transmits a wake-up signal, an interrupt or other notification signal. This signal causes the Bluetooth radio 122 to wake up, thereby enabling it to receive the data packet 115 transmitted from the Bluetooth radio 112.

[0037] During a wake-up event, the wake-up transmitter sends a wake-up message to a specific wake-up receiver or a group of receivers using the addresses of one or more targets. In the case of a successful wake-up request in which a response is expected, the wake-up receiver responds, for example, with an advertising event. In an embodiment, the wake-up receiver does not respond to invalid requests. In one implementation, the wake-up event is considered closed if the wake-up receiver has responded or a given amount of time has passed. If the receiver has not responded yet, the wake-up transmitter can repeat the wake-up event for one or more attempts. If the repeated attempts are unsuccessful, the wake-up procedure can be considered to have failed, and the controller notifies the host. For example, the wake-up receiver can be controlled to enter the WuR scan state within a given scan window duration to listen for packets sent on the wake-up channel, after which the wake-up receiver can enter an idle state until the next wake-up scan window.

[0038] Although shown at this high level for ease of discussion, it is understood that various enhancements are possible in embodiments. For example, it is understood that although discussed above as a "transmitter" and a "receiver", each device can be a complete radio device with transmission and reception capabilities.

[0039] Depending on the implementation, the wake-up packet may be a fixed-length or variable-length packet. Figure 2A , shown is a block diagram illustrating an arrangement of a wake-up packet according to an embodiment. Figure 2A As shown in , the wake-up packet 200 may be modulated with Manchester Encoding (ME) On-Off Keying (MOOK). Using an embodiment, the wake-up packet 200 may be transmitted at a data rate of 125 kilobits per second (Kbps). The MOOK information may be modulated by a Bluetooth low energy 1M Gaussian Frequency Shift Keying (GFSK) physical unit (PHY) circuit using random data (e.g., PRBS9 data). By adding MOOK modulation to such data, a bit rate of 62.5 Kbps may be achieved using 2-chip Manchester encoding.

[0040] In a particular embodiment, WuR data is sent with OOK modulation, where a chip sent with a value of "0" means the absence of a carrier, and a chip sent with a value of "1" means the presence of a carrier. GFSK is used to modulate the carrier to distribute the RF power over a wide frequency band in order to shape the signal spectrum. The mapping of input bits to output chip sequences (in transmission order) is Manchester coded, as shown in Table 1. Table 1 Input Bit Output chip sequence 0 01 1 10

[0041] Although the embodiments are not limited in this regard, in implementations, the wake-up packets may be sent on one or more specific wireless channels. For example, the channels used for wake-up requests may have low interference to minimize retransmissions of wake-up requests. In one embodiment, non-primary advertising BLE channels that do not overlap with frequently used Wi-Fi channels (e.g., channels 1, 6, and 11) and / or channels that are multiples of 16 MHz may be used.

[0042] refer to Figure 2A The packet length of the wake-up packet 200 may be between 104 and 144 bits, corresponding to a duration between 1.664-2.304 milliseconds (ms). Figure 2A As shown in , the wake-up packet 200 is formed by a plurality of fields, namely, a leading field 201 which may be 1 octet (8 bits), a synchronization word field 202 which may be 4 octets, a wake-up mode field 203 which may be 4 bits, a length field 204 which may be 4 bits (to indicate the length of the payload), an address field 205 which may be 2 octets, a token field 206 which may be 4 octets, a payload field 207 which may have a length based on a given wake-up mode and length, and finally a 2 octet cyclic redundancy check (CRC) field 208.

[0043] In an embodiment, the WuR uses the preamble and sync word fields to detect the wake-up message and acquire timing synchronization. In an embodiment, the address field 205 may be 15 bits and is divided into a receiver ID and a group ID. In a specific embodiment, the group ID is a 7-bit value and the receiver ID is an 8-bit value.

[0044] In an embodiment, the wake-up mode field 203 is 4 bits and may be defined as shown in Table 2 below. Table 2

[0045] Token field 206 may be used to identify the wakeup transmitter. The WuR may support multiple stored tokens (e.g., a single token for each supported transmitter). Although embodiments are not limited in this regard, the example payload may be used to provide commands, such as commands to toggle LED states and switch images on the device (e.g., previously transmitted images). CRC field 208 may in turn be a CRC value calculated for the WM, Length, Address, Token, and Payload fields. Of course, while shown with this particular arrangement of wakeup packets, variations are possible in other implementations.

[0046] Reference now Figure 2B , shows the transmission power spectrum of the wake-up communication according to the embodiment. Figure 2B As shown in FIG. 2 , power spectrum 220 includes a Bluetooth Low Energy (BLE) transmission 230 sent using GFSK modulation, i.e., a BLE modulated signal containing random data. Over this, according to an embodiment, a MOOK modulated transmission 240 is sent, which may form at least a portion of a wake-up packet. (Confirmation 240 is required to be a MOOK signal 230 modulating a GFSK signal).

[0047] Reference now Figure 2C , which shows a time domain plot of a MOOK modulation wake-up packet according to an embodiment. Figure 2C As shown in , a wakeup packet 250' is illustrated, and inset 250 zooms in on a portion of the wakeup packet 250'. As illustrated, the amplitude of the base BLE packet is MOOK modulated, and the dense portion 255 (as zoomed in at 250') includes the original BLE modulated data (here, a portion of the zoomed in packet shows a ... 010 ... chip sequence).

[0048] Reference now Figure 3A , which is a block diagram of a portion of a wake-up receiver according to an embodiment. Figure 3A As shown in FIG. , the receiver 300 may be implemented as part of a multi-mode receiver, such as Figure 1 Receiver 120. As shown, an incoming RF signal is received via antenna 316 and provided to RF circuit 318. In various embodiments, RF circuit 318 may be configured to perform various processing on the received RF signal, such as amplification in an LNA, filtering in one or more filters, and so on.

[0049] The resulting RF signal is provided to a mixer 320, which down-converts the RF signal to a lower frequency signal, such as a zero intermediate frequency (ZIF). To this end, the mixer 320 down-converts the received RF signal using a mixed signal received from a local oscillator 322. The resulting down-converted signal passes through a low pass filter (LPF) 325 and is provided to a peak detector 330 (illustrated as a diode) that outputs a peak signal (OUT_PEAK_DETECT). As shown, the peak signal is provided to the positive input of a comparator 335. The peak signal is further filtered in an RC filter formed by a resistor R and a capacitor C, which generates a threshold signal provided to the negative input of the comparator 335.

[0050] The resulting comparison signal (COMP_OUT) is provided to a de-glitch circuit 340 which provides a de-glitched output to a D-type flip-flop 345 which is clocked with a 1 megahertz (MHz) clock signal. The output of flip-flop 345 is in turn provided as a 1-bit digital signal which is output to the digital portion of the wake-up radio (WuR digital circuit 350).

[0051] As will be further described below, the digital circuit 350 is configured to process this input bit stream to detect the presence of a valid wake-up packet. Upon such detection, the digital circuit 350 outputs an interrupt signal or other notification, which can be sent to the energy management unit and / or the main radio circuit. As further shown, the digital circuit 350 can generate a clear signal (wur_peakdata_clear) to clear the threshold signal by discharging the capacitor C. This is so because the threshold may increase undesirably, for example, in the presence of a high power blocker (such as a Wi-Fi blocker signal). Therefore, in the event of an undesirable increase in the threshold due to such a blocker, such a signal causes the threshold signal to be reset. It is understood that although in Figure 3A The embodiments are shown at this high level, but many variations and alternatives are possible.

[0052] Reference now Figure 3B , which shows the diagram and Figure 3A 345 . A timing diagram of various signals associated with a wake-up radio device. In an embodiment, the input RF signal has a MOOK modulation. Using this Manchester-based encoding, the amplitude information is recovered via a peak detector. The resulting peak signal 305 is compared to a threshold 310. As shown, the threshold 310 varies based on the peak signal 305 (according to the RC filter characteristics). Therefore, the resulting comparison output is a single bit sample at the clock rate of the clock driving the trigger (such as trigger 345). A 1 MHz clock signal results in 8 times oversampling. Therefore, this 1-bit signal stream 315 is an input to the digital circuit 350. The digital circuit 350 can perform timing acquisition based on this signal.

[0053] Reference now Figure 4 , which is a schematic diagram of a portion of a wake-up radio device according to an embodiment. Figure 4As shown in , the wake-up radio device 400 includes RF circuitry for receiving and processing an incoming RF signal and down-converting it to a lower frequency signal (e.g., an intermediate frequency (IF), low IF, or zero IF (ZIF) signal). The IF circuitry is in turn coupled to the RF circuitry to receive and process the IF signal to provide an output signal that, when valid, identifies a detected signal exceeding a threshold (wherein this detected signal can then be processed to identify a wake-up communication).

[0054] like Figure 4 As illustrated in , the radio 400 receives an input RF signal (RFin) in an LNA 410 having a coupling capacitor C1 coupled to its input. In an embodiment, the LNA 410 is implemented as a low noise transimpedance amplifier, although other amplifiers may be used in other implementations. Figure 4 At a high level shown in , the resulting amplified RF signal is down-converted by a passive mixer implemented with a plurality of switches S1 - S4 controlled by the LO signal.

[0055] The resulting quadrature IF signal is provided to the corresponding TIA 440 I，Q (Strictly speaking, the TIA 440 consists of an operational amplifier and resistors (e.g., for the TIA 440 I 4 and 5. The peak detector 450 is a device that generates a peak signal from a peak detector 450. The peak signal is converted to a voltage signal by an RC filter (formed by resistors R1, R2) of FIG. 4 for conversion to a voltage signal. As shown, an RC filter is coupled to the TIA 440 (having corresponding resistors R1-R4 and capacitors C4-C7). Input capacitors C2, C3 are coupled in parallel to the differential inputs of the TIA 440. The resulting voltage signal output from the TIA 440 passes through an additional filter (formed by resistors R5-R12 and capacitors C8-C15) and is provided to the peak detector 450.

[0056] Peak detector 450 is configured to identify the maximum value of one of the four phase IF signals. As will be further described below, peak detector 450 can be implemented by using a switched capacitor circuit. The resulting peak signal is provided to comparator 460, where the peak signal is compared with a threshold signal that is self-generated based on filtering the peak signal via a schematic representation of an RC filter formed by resistor R13 and capacitor C16 (and scaled via gain factor 455). In one embodiment, the RC filter is implemented using switched capacitor circuitry. When the peak signal exceeds the threshold, a valid output signal is sent, indicating the receipt of a valid Manchester coded bit (valid communication can only be achieved if the entire packet is checked and the cyclic redundancy checksum (CRC) is valid). Note that the threshold can be locked by control of switch S5 in response to a threshold hold signal sent from the downstream digital circuitry.

[0057] like Figure 4As further shown in FIG. 4 , the quadrature LO signals (ilop, ilom, qlop, qlom) are generated via a clock circuit system that includes a voltage controlled oscillator (VCO) 420, which in turn is coupled to a polyphase filter 425 and a buffer 430. With this arrangement, the use of a phase locked loop (PLL) is avoided, thereby minimizing die area and power consumption.

[0058] In an embodiment, the VCO 420 may be implemented with an open-loop high frequency CMOS LC oscillator configuration with periodically activated automatic frequency control (AFC) to reduce power consumption, complexity, and die area. When open-loop, the AFC circuit 415 is a slowly running control circuit that may be periodically implemented to provide closed-loop frequency control to the VCO 420, albeit at a very low frequency. For example, in an embodiment, the AFC loop 415 may operate at a frequency of 32 kilohertz (kHz) while the VCO operates at a frequency of 2.4 gigahertz (GHz). As will be further described herein, the LNA 410 and VCO 420 may be implemented in a stacked circuit configuration to enable current reuse. Similarly, a 25% duty cycle LO generator circuitry and LO buffer may also be implemented in a stacked circuit configuration to enable current reuse. Although in Figure 4 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0059] Reference now Figure 5 , shows another schematic diagram of a portion of a wake-up radio device according to an embodiment. Figure 5 , a radio 400 is illustrated in a form showing a circuit stack configuration. More specifically, LNA 410 and VCO 420 are coupled in a stack configuration to reuse the current generated by low dropout (LDO) regulator 405 and provided via a regulated voltage (Vdd). MOSFET M1 provides this current, which in an embodiment may be approximately 55 microamperes (uA). With an embodiment, LNA 410 is not saturated when a large blocker is present (e.g., 40 dB at 2 MHz offset). In addition, with this configuration, large voltage swings at the LNA output are avoided before the RF signal current is down-converted by deferring the current-to-voltage conversion to the TIA, where the large current due to the strong blocker is filtered in the IF frequency domain by the frequency response of the TIA.

[0060] Similarly, the duty cycle LO generation circuitry 430B and buffer 430 A1-A4 Coupled in a stacked configuration to reuse the current provided via the regulated voltage. Here, MOSFET M2 provides this current, which in an embodiment may be approximately 22uA.

[0061] Note the presence of capacitor CA coupled to the drain terminal of MOSFET M1 and capacitor CB coupled between the midpoint of the first stacked circuit formed by VCO 420 and LNA 410 and a reference voltage node (e.g., ground). These capacitors reduce supply ripple at the maximum voltage (CA) and at the mid-rail node (CB), thereby providing a stable, low-ripple DC voltage for the VCO and LNA local supply. Note that the DC midpoint is controlled without an explicit servo loop because LNA 410 is self-biased at a PMOS plus NMOS diode drop, thereby forming a low DC impedance.

[0062] As further illustrated, the amplified RF signal output from LNA 410 (shown at circuit node A) is coupled to the RF port of the passive mixer implemented with MOSFETs M3-M6, while the LO signal output from buffer 430B is coupled to the LO port of the passive mixer. The resulting IF signal is in turn provided to TIA 440. The resulting quadrature IF (voltage) signals (ifip, ifim, ifqp, ifqm) output from TIA 440 are in turn provided to the peak detector circuit ( Figure 5 not shown).

[0063] Reference now Figure 6 , which is a schematic diagram of a peak detector and a comparator according to an embodiment. Figure 6 As shown in FIG. 6 , circuit 600, which is also part of a wake-up radio, includes a peak detector 610 and a comparator 620. First, with respect to peak detector 610, an input IF signal (such as output by a TIA such as TIA 440) is received via gate relay terminals of a plurality of MOSFETs M1-M4 and via a differential NMOS pair arrangement, and the maximum signal of these IF signals (such as output by a TIA such as TIA 440) is detected at the output of a switched capacitor circuit. Figure 6 V peak_detect As shown, the switched capacitor circuit includes a plurality of switches S1-S4 that can be switched (in turn controlled by corresponding phase signals θ 1 ,θ 2 ,θ 2D The following four capacitors C1-C4 are used for control. Figure 7 A diagram of the control of these switches is shown in FIG. Figure 6 In the embodiment of , the peak detector 610 thus follows the maximum of the four single-ended IF signals. The switched capacitors C1-C4 implement a hold function (C2), a droop function (C1), and an equivalent RC filter with C3 and C4 and associated switches.

[0064] There are two decay time constants in this implementation: (1) the decay time constant of the peak detector, which detects the peak value of the IF signal and is formed by capacitors C1-C2; and (2) the decay time of the filter, which self-generates the threshold voltage from the peak detector output and is formed by capacitors C3-C4.

[0065] With Figure 3A In contrast to the RC circuit shown in , by using switched capacitors, the RC time constant process variation is eliminated because the decay time constant here depends only on the capacitor ratio and the reference frequency.

[0066] Generally speaking, the switched capacitor circuit includes a holding circuit with droop, a low pass filter, and a switching circuit system for controllably providing a peak signal and a threshold voltage to the comparator 620. Figure 6 In the embodiment of the present invention, a holding circuit with droop is implemented with capacitors C1, C2 and switches S1 and S2, which form a holding function with droop for the peak detector 610. Note that although the droop function is implemented with switched capacitors here, in other implementations, a resistor or a small current source may be used. A low pass filter is also provided to implement the threshold voltage using capacitors C3, C4 and switches S3, S4 (where capacitor C3 and switches S3, S4 implement the equivalent of a resistor). In other implementations, the low pass filter may be formed by an operational amplifier based approach using RC or using switched capacitors.

[0067] Still reference Figure 6 , comparator 620 is implemented as an offset cancellation comparator with three gain stages. Each gain stage is formed with a pair of series coupled NMOS / PMOS devices (collectively referred to as inverters M11 / M12 and M14 / M15 and M16 / M17). During the auto-zero operation of comparator 620, switches S7 and S8 are closed. During this auto-zero operation, switches S5, S7, and S8 are closed. V 阈值 The offset of the inverter M11 / M12 is held on the capacitor C5, and the offset of the inverter M14 / 15 is held on the capacitor C6. The resulting comparison signal is passed through the inverter 630 and the de-burring circuit ( Figure 6 The output of the de-burring circuit is output via a phase signal θ 2D The D-type flip-flop circuit 640 controls sampling.

[0068] The comparator 620 can operate with low power consumption. As shown, the current mirror configuration is composed of a current source I 1and a plurality of MOSFETs M9, M10, M13. In an embodiment, the current source may have a current of about 1 uA, and currents of about 400 nanoamperes (nA) and 200 nA may be provided to the first two gain stages via the MOSFETs M10, M13, respectively.

[0069] Based on switch control, during the comparison phase, the detected peak signal is passed to the comparator 620 via switch S5. The self-generated threshold is in turn passed through switch S6 during the auto-zero phase. In one or more embodiments, the threshold signal is generated by averaging the peak detector output with a time constant of approximately 30 microseconds.

[0070] Reference now Figure 7 , shown are timing diagrams 710-750 illustrating the operation of an IF peak detector and comparator according to an embodiment. Waveforms 710 and 720 respectively illustrate the orthogonal IF signals output from the TIA according to an embodiment. Waveform 730 shows the peak detector output (i.e., the curve with a larger slope change), and the threshold generator output that tracks the peak detector output in a self-generated, filtered manner. Waveform 740 shows the comparator output, which is in turn de-burred by a de-burring circuit to produce an output waveform 750, which can be provided to additional downstream processing circuitry of a demodulator. Although these corresponding waveforms and Figure 7 Embodiments are shown, but many variations and alternatives are possible.

[0071] Embodiments may be incorporated into many different types of wireless systems. Figure 8 , a block diagram of a representative integrated circuit 800 is shown, which includes transceiver circuitry having a stacked circuit arrangement to reuse current as described herein. Figure 8 In the embodiment shown in , the integrated circuit 800 can be, for example, a microcontroller, a wireless transceiver that can operate according to one or more wireless protocols (e.g., WLAN-OFDM, WLAN-DSSS, Bluetooth, IEEE 802.15.4, etc.), or other devices that can be used in various use cases (including sensing, metering, monitoring, embedded applications, communications, applications, etc.), and it can be particularly suitable for use in an Internet of Things device.

[0072] In the embodiment shown, the integrated circuit 800 includes a memory system 810, which in an embodiment may include non-volatile memory such as flash memory and volatile memory such as RAM. In an embodiment, this non-volatile memory may be implemented as a non-transitory storage medium that can store instructions and data.

[0073] The memory system 810 is coupled to a digital core 820, which may include one or more cores and / or microcontrollers that serve as the main processing unit of the integrated circuit, via a bus 850. The digital core 820 may in turn be coupled to a clock generator 830, which may provide one or more phase-locked loops or other clock generator circuitry to generate various clocks for use by the circuitry of the IC (some of which may be implemented in a stacked arrangement as described herein).

[0074] As further illustrated, IC 800 further includes power circuitry 840, which may include one or more voltage regulators or DC-DC converters. Additional circuitry may optionally be present to provide various functionality and interaction with external devices, depending on the specific implementation. Such circuitry may include interface circuitry 860, which may provide interfaces with various off-chip devices, and sensor circuitry 870, which may include various on-chip sensors, including digital and analog sensors used to sense desired signals, such as for metering applications, etc.

[0075] In addition, if Figure 8 As shown in , a transceiver circuit system 880 can be provided to enable transmission and reception of wireless signals according to one or more of a local area or wide area wireless communication scheme. As shown, the transceiver circuit system 880 includes a stacked circuit system 885, which can reuse current as described herein. It is understood that although shown with this high level view, many variations and alternatives are possible.

[0076] Note that ICs such as those described herein may be implemented in a variety of different devices such as an IoT device. This IoT device may be a smart utility meter for use in a smart utility network (e.g., a star or gateway network in which remote communications are in accordance with the IEEE 802.15.4 specification or other such wireless protocols).

[0077] Reference now Fig. 9 , which shows a high-level diagram of a network according to an embodiment. Fig. 9 As shown in , the network 900 includes various devices, including smart devices such as IoT devices, gateways / routers, and remote service providers. Fig. 9 In an embodiment, a mesh network or star network 905 may exist in a network having multiple IoT devices 910 0-nSuch IoT devices can receive and process packets (including wake-up packets as described herein). As shown, at least one IoT device 910 is coupled to one or more gateways 930, which in turn communicate with a remote service provider 960 via a wide area network 950 (e.g., the Internet). In an embodiment, the remote service provider 960 can be a backend server of a utility that handles communications with the IoT device 910. It is understood that although in Fig. 9 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0078] While the present disclosure has been described with respect to a limited number of implementations, those skilled in the art having the benefit of this disclosure will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations.

Claims

1. A device comprising: A first stacking circuit comprises: a low noise amplifier (LNA) for receiving and amplifying a radio frequency (RF) signal; and a voltage controlled oscillator (VCO) coupled to the LNA, the VCO for generating at least one clock signal, wherein the first stacked circuit is coupled to a supply voltage node and a first current is to be reused for the LNA and the VCO; and a second stacked circuit coupled to the first stacked circuit, the second stacked circuit comprising: a local oscillator (LO) generating circuit for generating at least one LO clock signal based at least in part on the at least one clock signal; and at least one buffer coupled to the LO generation circuit for buffering the at least one LO clock signal and outputting a differential complex clock signal, wherein the second stacked circuit is coupled to the supply voltage node and is to reuse a second current for the LO generation circuit and the at least one buffer. 2 . The apparatus of claim 1 , further comprising a low dropout regulator coupled to the supply voltage node, the low dropout regulator for providing a regulated voltage to the supply voltage node.

3. The device according to claim 1, wherein: The VCO includes an open-loop VCO.

4. The apparatus of claim 3, further comprising an automatic frequency control (AFC) loop coupled to the VCO, the AFC loop for adjusting the VCO at a frequency significantly lower than the clock signal.

5. The device according to claim 3, wherein: The VCO is coupled to the supply voltage node, and the LNA is coupled to a reference voltage node, the LNA being coupled to the VCO at a midpoint of the first stack circuit.

6. The apparatus of claim 1, further comprising a polyphase filter coupled between the VCO and the LO generation circuit, the polyphase filter configured to receive the at least one clock signal and output a multiphase clock signal.

7. The device according to claim 6, wherein: The at least one buffer includes a first buffer for buffering the differential complex clock signal, and the LO generation circuit includes a duty cycle pulse generator for providing the at least one LO clock signal for mixing with the amplified RF signal.

8. The apparatus of claim 1, further comprising a transimpedance amplifier (TIA) coupled to the second stacked circuit, the TIA configured to receive and amplify an intermediate frequency (IF) signal, the IF signal being based on the RF signal.

9. The apparatus according to claim 8, further comprising: a peak detector coupled to the TIA, the peak detector configured to detect a peak signal of the amplified IF signal; as well as A comparator is used to compare the peak signal with a threshold signal.

10. The device according to claim 9, wherein: The peak detector is to self-generate the threshold signal based on the peak signal.

11. The device according to claim 1, wherein: The LNA of the first stack circuit is to provide a low impedance at DC to achieve a stable midpoint voltage for the first stack circuit.

12. A device comprising: a peak detector for receiving a quadrature intermediate frequency (IF) signal and outputting a maximum signal of the quadrature IF signal at an output node, the peak detector comprising a switched capacitor circuit for storing the maximum signal and generating a threshold signal; as well as A comparator is coupled to the peak detector, the comparator being configured to compare the maximum signal with the threshold signal.

13. The device according to claim 12, wherein: The peak detector is to self-generate the threshold signal.

14. The device according to claim 13, wherein: The threshold signal comprises an average value of the maximum signal.

15. The apparatus according to claim 12, wherein: The switched capacitor circuit comprises: A holding circuit is provided for holding the maximum signal with droop, the holding circuit comprising at least one first capacitor and at least one first switch, wherein the at least one first switch is controlled by a first phase signal.

16. The device according to claim 15, wherein: The switched capacitor circuit further comprises: A low pass filter is coupled to the holding circuit, wherein the low pass filter is to provide the threshold signal to the comparator circuit.

17. The apparatus of claim 15, further comprising: a second switch controlled by the first phase signal, the second switch being used to couple the threshold signal to the comparator circuit; as well as A third switch is controlled by the second phase signal to couple the maximum signal to the comparator circuit.

18. A device comprising: A wake-up radio for issuing a trigger signal in response to detection of a wake-up message in a radio frequency (RF) signal, the wake-up radio comprising: a low dropout regulator for providing a supply voltage to a supply voltage node; a first stacked circuit coupled to the supply voltage node, the first stacked circuit comprising: an amplifier for receiving and amplifying the RF signal; and an oscillator coupled to the amplifier, the oscillator for generating at least one clock signal, wherein the first stacked circuit is to reuse a first current for the amplifier and the oscillator; and a second stacked circuit coupled to the supply voltage node, the second stacked circuit comprising: a clock generation circuit configured to receive the at least one clock signal and output a multi-phase clock signal; and At least one buffer coupled to the clock generation circuit is used to buffer the multi-phase clock signal and output a set of clock signals, wherein the second stacked circuit is to reuse the second current for the clock generation circuit and the at least one buffer coupled to the clock generation circuit. One less buffer; a transimpedance amplifier (TIA) coupled to the supply voltage node, the first stacked circuit, and the second stacked circuit, the TIA for receiving and amplifying an intermediate frequency (IF) signal, the IF signal being based on the RF signal; a peak detector for receiving the IF signal and outputting a maximum signal of the IF signal, the peak detector comprising a switched capacitor circuit for storing the maximum signal and a threshold signal; and a comparator coupled to the peak detector, the comparator being configured to compare the maximum signal with the threshold signal and output a trigger signal when the maximum signal exceeds the threshold signal; and A second radio is coupled to the wake-up radio, the second radio being operable to wake up in response to receipt of the trigger signal, wherein the wake-up radio is coupled to the second radio without being substantially loaded.

19. The apparatus according to claim 18, wherein: The amplifier comprises: multiple gain slices; and A plurality of dummy load circuits are coupled to the plurality of gain slices.

20. The apparatus of claim 19, further comprising a controller for: controlling a number of the plurality of slices to enable based at least in part on a gain control signal; and At least one of the plurality of dummy loads is coupled to a midpoint of the first stacked circuit when a corresponding slice of the plurality of slices is disabled.

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