Memory array structure and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a storage array structure and a memory, the storage array structure comprises a plurality of basic units, and each basic unit comprises a storage capacitor configured to perform charge interaction with a bit line structure; the first terminal of the switch transistor is connected with the bit line structure, the second terminal is connected with the storage capacitor, and the control end is connected with the word line structure; the switching transistor is configured to be switched on based on an effective level transmitted by the word line structure so as to couple the storage capacitor and the bit line structure; the electric fine tuning structure is coupled with the word line structure and the control end of the switch transistor, and the capacitance of the electric fine tuning structure is a negative value, so that the stability of the storage array structure is improved, and the sub-threshold swing of the transistor is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a storage array structure and a memory. Background Art

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, consisting of many repeated storage units.

[0003] Specifically, each storage unit usually includes a capacitor and a transistor, the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0004] The transistor of the memory cell is usually set as an N-type transistor, that is, when the level transmitted in the word line is greater than the threshold voltage Vth of the N-type transistor, the word line turns on the transistor of the memory cell, and the level in the word line is provided by the row controller (Sub Word line Driver, SWD). However, the row selection signal provided by the row controller may be affected by device pressure, temperature, etc. during the word line transmission process, resulting in the row selection signal that should turn on the transistor being unable to normally turn on the transistor of the memory cell, affecting the stability of the memory.

[0005] In addition, in the case of storage channel leakage of the transistor of the memory cell, a substrate bias voltage Vbb is usually introduced on the substrate to reduce the channel leakage. However, since the sense amplifier circuit SA and the row controller SWD around the memory array share the same substrate with the memory array, the introduction of the substrate bias voltage Vbb will introduce additional substrate leakage (Junction leakage) in the sense amplifier circuit SA and the row controller SWD circuit. Summary of the invention

[0006] The embodiments of the present disclosure provide a memory array structure and a memory to improve the stability of the memory array structure and reduce the subthreshold swing of transistors.

[0007] An embodiment of the present disclosure provides a storage array structure, including multiple basic units, each basic unit including: a storage capacitor, configured to interact with a bit line structure; a switching transistor, a first terminal connected to the bit line structure, a second terminal connected to the storage capacitor, and a control terminal connected to the word line structure; the switching transistor is configured to be turned on based on the effective level transmitted by the word line structure to couple the storage capacitor and the bit line structure; an electrical fine-tuning structure, coupling the word line structure and the control terminal of the switching transistor, wherein the capacitance of the electrical fine-tuning structure is a negative value.

[0008] An electrical fine-tuning structure is provided in each basic unit. By introducing the electrical fine-tuning structure, the actual gate voltage received by the switching transistor in the basic unit is increased to facilitate turning on the switching transistor, thereby improving the stability of the storage array structure. In addition, by introducing the electrical fine-tuning structure, the subthreshold swing of the switching transistor is reduced. By reducing the subthreshold swing, the channel leakage of the transistor can be reduced, thereby avoiding the introduction of a large substrate bias voltage, that is, avoiding the influence of the introduction of additional substrate leakage on the storage array structure.

[0009] Optionally, the electrical fine-tuning structure is disposed in a structure of a switch transistor, and the switch transistor is an embedded transistor.

[0010] Optionally, the switching transistor is embedded in an opening of the substrate, and the switching transistor includes: a first insulating layer, which is arranged on the side walls and bottom of the opening, and the top surface is flush with the surface of the substrate, and the inner surface of the first insulating layer forms a first opening; an electrical fine-tuning structure is arranged on the side walls and bottom of the first opening, and the inner surface of the electrical fine-tuning structure forms a second opening; a first conductive layer, which is arranged in the second opening and is located at the bottom of the second opening; a second conductive layer, which is arranged on the top surface of the first conductive layer; and a second insulating layer, which is arranged on the top of the second conductive layer, and the top surface of the second insulating layer is flush with the top surface of the substrate.

[0011] Optionally, a top surface of the electrical fine tuning structure is flush with the substrate surface.

[0012] Optionally, a top surface of the electrical fine-tuning structure is lower than a surface of the substrate and higher than a top surface of the second conductive layer.

[0013] Optionally, a top surface of the electrical fine-tuning structure is lower than a top surface of the second conductive layer and higher than a top surface of the first conductive layer.

[0014] Optionally, a top surface of the electrical fine-tuning structure is lower than a top surface of the first conductive layer.

[0015] Optionally, in a direction perpendicular to the sidewall of the opening, the thickness of the electrical fine-tuning structure is 2 nm to 20 nm.

[0016] Optionally, in a direction perpendicular to the sidewalls of the opening, the thickness of the electrical fine-tuning structure is less than or equal to the thickness of the first insulating layer.

[0017] Optionally, the material of the electric fine-tuning structure includes: hafnium aluminum oxide HfAlO x 、HfZrO x 、HfYO x 、HfLaO x 、HfSrO x At least one of .

[0018] Optionally, the storage array structure also includes: a contact plug, one end of which is in contact with the second electrical fine-tuning structure and the other end of which is in contact with the word line structure, for receiving a control signal, and the control signal is used to drive the switching transistor; one end of the second electrical fine-tuning structure is in contact with the contact plug and the other end of which is in contact with the control end of the switching transistor, wherein the capacitance of the second electrical fine-tuning structure is a negative value.

[0019] Optionally, the material of the second electrical fine-tuning structure is the same as the material of the electrical fine-tuning structure.

[0020] Optionally, in a connection direction among the contact plug, the second electrical fine-tuning structure and the word line structure, a thickness of the second electrical fine-tuning structure is 2-20 nm.

[0021] Optionally, the storage array structure also includes: a contact plug, one end of which contacts the electrical fine-tuning structure and the other end of which contacts the word line structure, for receiving a control signal, the control signal is used to drive the switching transistor; one end of the electrical fine-tuning structure contacts the contact plug, and the other end of the electrical fine-tuning structure contacts the control end of the switching transistor.

[0022] Another embodiment of the present disclosure further provides a memory, comprising the sensing amplifier circuit structure provided by the above embodiment, so as to improve the stability of the memory array structure and reduce the subthreshold swing of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a storage array structure provided in one embodiment of the present disclosure;

[0025] Figure 2 An embodiment of the present disclosure provides Figure 1A schematic diagram of the structure of the basic unit in the dashed box shown;

[0026] Figure 3 A schematic diagram of the principle of a storage array structure provided by an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of a structure in which a first electric fine-tuning structure provided in an embodiment of the present disclosure is disposed on a switch transistor;

[0028] Figure 5 A schematic diagram of a structure in which a second electrical fine-tuning structure provided in an embodiment of the present disclosure is disposed on a switch transistor;

[0029] Figure 6 A schematic diagram of a structure in which a third electric fine-tuning structure provided in an embodiment of the present disclosure is disposed on a switch transistor;

[0030] Figure 7 A schematic diagram of a structure in which a fourth electric fine-tuning structure provided in an embodiment of the present disclosure is disposed on a switch transistor;

[0031] Figure 8 to Figure 12 When the electrical fine-tuning structure provided in one embodiment of the present disclosure is disposed on a switch transistor, a cross-sectional view and a top view corresponding to each step of manufacturing the switch transistor and the electrical fine-tuning structure;

[0032] Fig.13 A schematic diagram of the structure of a second electrical fine-tuning structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, the transistor of the memory cell is usually set as an N-type transistor, that is, when the level transmitted in the word line is greater than the threshold voltage Vth of the N-type transistor, the word line turns on the transistor of the memory cell, and the level in the word line is provided by the row controller (Sub Word line Driver, SWD). However, the row selection signal provided by the row controller may be affected by device pressure, temperature, etc. during the word line transmission process, resulting in the row selection signal that should turn on the transistor failing to normally turn on the transistor of the memory cell, affecting the stability of the memory.

[0034] In addition, in the case of storage channel leakage of the transistor of the memory cell, a substrate bias voltage Vbb is usually introduced on the substrate to reduce the channel leakage. However, since the sense amplifier circuit SA and the row controller SWD around the memory array share the same substrate with the memory array, the introduction of the substrate bias voltage Vbb will introduce additional substrate leakage (Junction leakage) in the sense amplifier circuit SA and the row controller SWD circuit.

[0035] An embodiment of the present disclosure provides a storage array structure to improve the stability of the storage array structure.

[0036] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0037] Figure 1 A schematic diagram of the storage array structure provided in this embodiment, Figure 2 The embodiment provided Figure 1 The structural diagram of the basic unit in the dashed box is shown. Figure 3 A schematic diagram of the storage array structure provided in this embodiment. Figure 4 A schematic diagram of a structure in which a first electric fine-tuning structure provided in this embodiment is disposed on a switch transistor, Figure 5 A schematic diagram of a structure in which a second electric fine-tuning structure provided in this embodiment is disposed on a switch transistor, Figure 6 A schematic diagram of a structure in which a third electric fine-tuning structure provided in this embodiment is disposed on a switch transistor, Figure 7 A schematic diagram of a structure in which a fourth electric fine-tuning structure provided in this embodiment is disposed on a switch transistor, Figure 8 to Figure 12 When the electrical fine-tuning structure provided in this embodiment is disposed on a switch transistor, a cross-sectional view and a top view corresponding to each step of manufacturing the switch transistor and the electrical fine-tuning structure are provided. Fig.13 This is a schematic diagram of the structure of the second electrical fine-tuning structure provided in an embodiment of the present disclosure. The storage array structure provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0038] refer to Figure 1 The storage array structure includes a plurality of basic cells 100 , wherein the basic cells 100 are connected to a word line structure 201 and a bit line structure 202 , and the basic cells 100 arranged in the same row are connected to the same word line structure 201 , and the basic cells 100 arranged in the same column are connected to the same bit line structure 202 .

[0039] refer to Figure 2 , Figure 2 for Figure 1 The specific structure of the basic unit of the dotted frame 101 is shown, and each basic unit 100 includes:

[0040] The storage capacitor 101 is configured to interact with the bit line structure 202 for electric charge.

[0041] The switch transistor 102 has a first terminal connected to the bit line structure 202, a second terminal connected to the storage capacitor 101, and a control terminal connected to the word line structure 201. Specifically, the first terminal and the second terminal are one and the other of the source and drain of the transistor respectively; Figure 2 In this example, the third terminal of the switch transistor 102 is configured to receive a substrate bias voltage Vbb.

[0042] The switch transistor 102 is configured to be turned on based on the effective level transmitted by the word line structure 201 to couple the storage capacitor 101 and the bit line structure 202. For the "effective level", in this example, the "effective level" is used to turn on the switch transistor 102; in one example, if the switch transistor 102 is an N-type transistor, and the threshold voltage Vth1 of the N-type transistor is 0.7V, then the level greater than 0.7V in the level transmitted by the word line structure 201 is the effective level; in another example, if the switch transistor 102 is a P-type transistor, and the threshold voltage Vth2 of the P-type transistor is 0.5V, then the level less than 0.5V in the level transmitted by the word line structure 201 is the effective level.

[0043] The electrical fine-tuning structure 300 is coupled to the word line structure 201 and the control terminal of the switch transistor 102 , wherein the capacitance of the electrical fine-tuning structure is a negative value.

[0044] Regarding the storage array structure provided in this embodiment, it should be noted that the control end of the switch transistor 102 is connected to the word line structure 201. In a specific setting, the control end of the switch transistor 102, that is, the gate, can be directly formed together with the word line structure 201, that is, the control end of the switch transistor and the word line structure 201 share the same structure.

[0045] for Figure 2 In the circuit shown, specifically, the row controller (SWD) 307 is used to output a row selection signal, and the row selection signal is transmitted in the word line structure 201 to turn on the corresponding switch transistor 102; when the switch transistor 102 is turned on, the source and the drain of the switch transistor 102 are coupled to each other, that is, the first terminal and the second terminal of the switch transistor 102 are electrically connected, and at this time, the storage capacitor 101 and the bit line structure 202 interact with each other.

[0046] Since the bit line structure 202 is charged based on the reference voltage Vref during the pre-charge phase (in the circuit, a level greater than the reference voltage Vref is a high level, and a level less than the reference voltage Vref is a low level), after the storage capacitor 101 interacts with the bit line structure 202, if the data stored in the storage capacitor 101 is "0", that is, a low level, at this time the storage capacitor 101 pulls down the level of the bit line structure 202. After being pulled down, the level of the bit line structure 202 (slightly less than Vref) is amplified by the sense amplifier circuit (SA) 308 and outputs the data "0", that is, a low level; if the data stored in the storage capacitor 101 is "1", that is, a high level, at this time the storage capacitor 101 pulls up the level of the bit line structure 202. After being pulled up, the level of the bit line structure 202 (slightly greater than Vref) is amplified by the sense amplifier circuit 308 and outputs the data "1", that is, a high level.

[0047] For the electrical trimming structure 300, refer to Figure 3 , the switching transistor 102 itself has a capacitance C MOS . After adding the electrical trimming structure 300 to the control terminal of the switching transistor 102, according to the law of conservation of charge, we can get:

[0048] V MOS *C MOS =(V G -V MOS )*C NC (1)

[0049] Among them, C NC is the capacitance of the electrical trimming structure 300, C MOS is the capacitance of the switching transistor 102, V G is the output voltage of the row controller 307, V MOS is the actual coupling control voltage received by the switching transistor 102, that is, the actual gate voltage of the switching transistor 102. Among them, since C NC is a negative capacitance, that is, C NC =-|C NC | (2)

[0050] After organizing (1) and (2), we can get: V MOS *|C MOS |=-(V G -V MOS )*|C NC | (3)

[0051] And the amplification factor of the switching transistor 102: Av = V MOS / V G (4)

[0052] Combining (3) and (4), we can get: V MOS / V G =|CNC 丨 / (丨C NC 丨-丨C MOS 丨) (5)

[0053] As can be seen from Equation (5), after adding the electrical fine-tuning structure 300, the Av of the switching transistor 102 is greater than 1, that is, V MOS is greater than V G , that is, by introducing the electrical fine-tuning structure 300, the actual gate voltage received by the switching transistor 102 is increased to facilitate the turning on of the switching transistor 102. In addition, for the subthreshold swing (SS) of the switching transistor 102, the subthreshold swing

[0054] SS = dV G / dVint * dVint / dψ S * dψ S / dlogI D = dV G / dlogI D (6)

[0055] After adding the electrical fine-tuning structure 300, the actual gate voltage of the switching transistor 102 changes from V G to V MOS , and at this time, the subthreshold swing SS1 of the switching transistor 102 = (V G / V MOS ) * SS (7)

[0056] where SS is the subthreshold swing of the switching transistor 102 when the electrical fine-tuning structure 300 is not added. As can be seen from the previous text, after adding the electrical fine-tuning structure 300, the Av of the switching transistor 102 is greater than 1, that is, V G / V MOS is less than 1, that is, SS1 is less than SS, and the subthreshold swing of the switching transistor 102 decreases.

[0057] As is known from the prior art, in order to limit the channel leakage of the transistor, a substrate bias voltage Vbb is usually introduced on the substrate to reduce the channel leakage. However, since the sense amplifier circuit SA and the row controller SWD around the memory array share the same substrate, the introduction of the substrate bias voltage Vbb will introduce additional substrate leakage (Junction leakage) in the sense amplifier circuit SA and the row controller SWD circuit. By reducing the subthreshold swing, the channel leakage of the transistor can be reduced, thereby avoiding the introduction of a large substrate bias voltage Vbb, that is, avoiding the influence of additional substrate leakage introduced in the sense amplifier circuit SA and the row controller SWD circuit due to the introduction of Vbb.

[0058] In one example, the electrical trimming structure 300 is disposed in the structure of the switch transistor 102 , and the switch transistor 102 is a buried transistor.

[0059] In some embodiments, reference Figure 4 to Figure 7 , the switch transistor 102 is arranged in the opening 420 of the substrate 410, and the switch transistor 102 includes: a first insulating layer 401, which is arranged on the side wall and the bottom of the opening 420, and the top surface is flush with the surface of the substrate 410, and the inner surface of the first insulating layer 401 surrounds the first opening 402; the electrical fine-tuning structure 300 is arranged on the side wall and the bottom of the first opening 402, and the inner surface of the electrical fine-tuning structure 300 surrounds the second opening 403; the first conductive layer 203 is arranged in the second opening 403 and is located at the bottom of the second opening 403; the second conductive layer 404 is arranged on the top surface of the first conductive layer 203; the second insulating layer 405 is arranged on the top of the second conductive layer 404, and the top surface of the second insulating layer 405 is flush with the top surface of the substrate 410.

[0060] In one example, refer to Figure 4 , the top surface of the electrical fine tuning structure 300 is flush with the surface of the substrate 410. In one example, reference Figure 5 , the top surface of the electrical fine tuning structure 300 is lower than the surface of the substrate 410 and higher than the top surface of the second conductive layer 404. In one example, referring to Figure 6 , the top surface of the electrical fine tuning structure 300 is lower than the top surface of the second conductive layer 404 and higher than the top surface of the first conductive layer 203. In one example, referring to Figure 7 , a top surface of the electrical fine tuning structure 300 is lower than a top surface of the first conductive layer 203 .

[0061] refer to Figure 8 to Figure 12 This embodiment also provides a method for forming the above example. Specifically, refer to Figure 8 , providing a substrate 410, and forming an opening 420 at a preset position of the substrate 410; in some embodiments, the substrate 410 can be etched based on an etching process to form the opening 420.

[0062] For the substrate 410, in some embodiments, the material of the substrate 410 includes a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the basic semiconductor includes silicon or germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or III-V semiconductor materials, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, tin germanium, silicon germanium tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate can also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0063] Continue to refer Fig. 9 , a first insulating layer 401 is formed on the sidewall of the opening 420, wherein the first insulating layer 401 serves as a gate oxide layer of the buried transistor. After the first insulating layer 401 is formed, the inner surface of the first insulating layer 401 surrounds the second opening 402; in some embodiments, the first insulating layer 401 can be formed by a chemical vapor deposition (CVD) process; in some embodiments, the opening 420 can be oxidized to form the first insulating layer 401 at the sidewall of the opening 420.

[0064] For the first insulating layer 401, in some embodiments, the material of the first insulating layer 401 includes silicon oxide, hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicate, zirconium oxide or zirconium silicate, etc.; in addition, if the first insulating layer 401 is obtained based on oxidation treatment of the opening 420, the material of the first insulating layer 401 is an oxide corresponding to the material of the substrate 420, such as silicon oxide, germanium oxide, etc.

[0065] Continue to refer Fig.10 , an electrical fine-tuning structure 300 is formed on the sidewall of the first insulating layer 401. In some embodiments, the electrical fine-tuning structure 300 can be formed by a chemical vapor deposition process (chemical vapor deposition, CVD) or an atomic layer deposition process (Atomiclayer deposition, ALD). After the electrical fine-tuning structure 300 is formed, the inner surface of the electrical fine-tuning structure 300 surrounds the third opening 403. It should be noted that the electrical fine-tuning structure 300 formed by the atomic layer deposition process has better coverage and is more conducive to reducing the subthreshold swing of the transistor.

[0066] For the electrical fine tuning structure 300, in some embodiments, the material of the electrical fine tuning structure 300 includes: hafnium aluminum oxide HfAlO x 、HfZrO x 、HfYO x 、HfLaO x 、HfSrO x At least one of; wherein x can be any parameter.

[0067] In some embodiments, the thickness of the electrical fine-tuning structure 300 in a direction perpendicular to the side wall of the opening 420 is 2nm to 20nm; specifically, in practical applications, the thickness of the electrical fine-tuning structure 300 can be set to 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm or 18nm.

[0068] In some embodiments, in a direction perpendicular to the sidewalls of the opening 420 , the thickness of the electrical fine-tuning structure 300 is less than or equal to the thickness of the first insulating layer 401 to prevent the thickness of the electrical fine-tuning structure 300 from being too large and thus affecting the gate oxide thickness of the switching transistor 102 , thereby affecting the performance of the switching transistor 102 .

[0069] Continue to refer Fig.11 and Fig.12 , a first conductive layer 203 is formed in the third opening 403, and the top surface of the first conductive layer 203 is lower than the top surface of the substrate 410; a second conductive layer 404 is formed in the third opening 403 and on the top of the first conductive layer 203, and the top surface of the second conductive layer 404 is lower than the top surface of the substrate 410; a second insulating layer 405 is formed in the third opening 403 and on the top surface of the second conductive layer 404, and the top surface of the second insulating layer 405 is flush with the surface of the substrate 410. In some embodiments, the first conductive layer 203, the second conductive layer 404, and the second insulating layer 405 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0070] For the first conductive layer 203 , in some embodiments, the material of the first conductive layer 203 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, cobalt, titanium or tungsten, and the first conductive layer 203 is used to form a gate conductive layer of the switching transistor 102 .

[0071] For the second conductive layer 404, specifically, the second conductive layer 404 serves as a work function layer; it is understood that the threshold voltage may depend on the flat band voltage, and the flat band voltage may depend on the work function. The work function may be adjusted by various methods, for example, the work function may be adjusted by the material used for the word line, or by the material used between the word line and the channel in the substrate. Adjusting the work function may cause the flat band voltage to shift, a high work function may cause the flat band voltage to shift in a positive direction, and a low work function may cause the flat band voltage to shift in a negative direction. In this way, the threshold voltage may be adjusted by shifting the flat band voltage, and the threshold voltage may be adjusted by shifting the flat band voltage even when the channel doping concentration is reduced or the channel doping is omitted. Therefore, the second conductive layer 404 is conducive to adjusting the threshold voltage of the switch transistor 102.

[0072] In addition, in this example, the second conductive layer 404 is a single-layer structure. In a specific application, the second conductive layer 404 can be configured as a multi-layer work function layer to further adjust the threshold voltage of the switch transistor 102 .

[0073] For the second insulating layer 405, specifically, the second insulating layer 405 is used to isolate the buried gate structure; in some embodiments, the second insulating layer 405 material includes silicon oxide, hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicate, zirconium oxide or zirconium silicate, etc.

[0074] In addition, if the target structure is Figure 5 , that is, the top surface of the electrical fine-tuning structure 300 is lower than the surface of the substrate 410 and higher than the top surface of the second conductive layer 404; before forming the second insulating layer 405, the electrical fine-tuning structure 300 of a certain height needs to be etched by an etching process, and then the deposition of the second insulating layer 405 is completed. If the target structure is Figure 6 , that is, the top surface of the electrical fine-tuning structure 300 is lower than the top surface of the second conductive layer 404 and higher than the top surface of the first conductive layer 203; before forming the second conductive layer 404, the electrical fine-tuning structure 300 of a certain height needs to be etched by an etching process so that the height of the electrical fine-tuning structure 300 is lower than the target height after forming the second conductive layer 404, and then the deposition of the second conductive layer 404 is completed. If the target structure is Figure 7 , that is, the top surface of the electrical fine-tuning structure 300 is lower than the top surface of the first conductive layer 203; before forming the first conductive layer 203, it is necessary to etch part of the height of the electrical fine-tuning structure 300 through an etching process so that the height of the electrical fine-tuning structure 300 is lower than the target height after the first conductive layer 203 is formed, and then the deposition of the first conductive layer 203 is completed.

[0075] refer to Fig.13 In some embodiments, the storage array structure further includes:

[0076] The contact plug 406 has one end connected to the second electrical trimming structure 301 and the other end connected to the word line structure for receiving a control signal for driving the switch transistor 102. Specifically, the other end of the contact plug 406 is coupled to the row controller (SWD) for receiving a control signal provided by the row controller.

[0077] One end of the second electrical fine-tuning structure 301 contacts the contact plug 406 , and the other end contacts the control end of the switch transistor 102 , wherein the capacitance of the second electrical fine-tuning structure 301 is the amplitude.

[0078] for Fig.13 For example, based on the above, the switch transistor 102 is arranged in the substrate 102 based on the buried type, and the word line structure 201 is also arranged in the substrate; in addition, the top of the word line structure 201 also includes other semiconductor structures to realize the related functions of the storage array. Fig.13Although not shown in the figure, those skilled in the art should understand that the contact plug 406 at this time is formed by forming a through hole in the semiconductor structure on the top of the word line structure 201, and then filling the through hole after electrically insulating the through hole to form the contact plug 406.

[0079] It should be noted that the working principle of the second electrical fine tuning structure 301 is the same as that of the electrical fine tuning structure 300. The detailed working principle is referred to the above description, and will not be described in detail in this embodiment. That is, by introducing the second electrical fine tuning structure 301 at the contact position between the contact plug 406 and the control end of the switch transistor 102, the actual gate voltage received by the switch transistor 102 is increased to facilitate turning on the switch transistor 102, and at the same time, the subthreshold swing of the memory array structure is further reduced to reduce the channel leakage of the transistor, thereby avoiding the introduction of a large substrate bias voltage Vbb, that is, avoiding the influence of additional substrate leakage introduced into the sense amplifier circuit SA and the row controller SWD circuit due to the introduction of Vbb.

[0080] For the second electrical fine tuning structure 301, in some embodiments, the material of the second electrical fine tuning structure 301 includes: hafnium aluminum oxide HfAlO x 、HfZrO x 、HfYO x 、HfLaO x 、HfSrO x At least one of; wherein x can be any parameter.

[0081] In some embodiments, the material of the second electrical fine tuning structure 301 is the same as that of the electrical fine tuning structure 300 , that is, the electrical fine tuning structure 300 and the second electrical fine tuning structure 301 are formed using the same forming process.

[0082] In some embodiments, in the connection direction of the contact plug 406, the second electrical fine-tuning structure 301 and the word line structure 201, the thickness of the second electrical fine-tuning structure 301 is 2-20nm; specifically, in practical applications, the thickness of the second electrical fine-tuning structure 300 can be set to 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm or 18nm.

[0083] In some embodiments, the thickness of the second electrical fine tuning structure 301 is the same as the thickness of the electrical fine tuning structure 300 .

[0084] It should be noted that the second electrical fine-tuning structure 301 can be independently arranged in the storage array structure, that is, the storage array structure only includes the second electrical fine-tuning structure 301 but does not include the electrical fine-tuning structure 300, that is, at this time, the electrical fine-tuning structure and the switching transistor 102 are independently arranged, that is, the storage array structure, including: a contact plug, one end of which is in contact with the electrical fine-tuning structure; the other end is in contact with the word line structure for receiving a control signal, and the control signal is used to drive the switching transistor 102, wherein one end of the electrical fine-tuning structure is in contact with the contact plug, and the other end is in contact with the control end of the switching transistor 102.

[0085] At this time, for Fig.13 For example, at this time, the switch transistor can be buried in the substrate or on the top surface of the substrate. Correspondingly, the word line structure 201 can also be set in the substrate or on the top of the substrate. In addition, the top of the word line structure 201 also includes other semiconductor structures to realize the related functions of the storage array. Fig.13 Although not shown in the figure, those skilled in the art should understand that the contact plug 406 at this time is formed by forming a through hole in the semiconductor structure on the top of the word line structure 201, and then filling the through hole after electrically insulating the through hole to form the contact plug 406.

[0086] For the storage array structure provided in the present embodiment, an electrical fine-tuning structure 300 is provided in each basic unit 100. By introducing the electrical fine-tuning structure 300, the actual gate voltage received by the switch transistor 102 in the basic unit 100 is increased, so as to turn on the switch transistor 102, thereby improving the stability of the storage array structure. In addition, by introducing the electrical fine-tuning structure 300, the subthreshold swing of the switch transistor 102 is reduced. By reducing the subthreshold swing, the channel leakage of the transistor can be reduced, thereby avoiding the introduction of a large substrate bias voltage Vbb, that is, avoiding the influence of the introduction of additional substrate leakage on the storage array structure in the sensing amplifier circuit SA and the row controller SWD circuit, and further improving the stability of the storage array structure.

[0087] It should be noted that the features disclosed in the storage array structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new storage array structure embodiment.

[0088] Another embodiment of the present disclosure provides a memory, including the sensing amplifier circuit structure provided by the above embodiment, so as to improve the stability of the memory array structure and reduce the subthreshold swing of the transistor.

[0089] Specifically, for the electrical fine-tuning structure 300, refer to Figure 3 , the switch transistor 102 itself has a capacitor C MOS, after adding the electrical trimming structure 300 to the control terminal of the switching transistor 102, according to the law of conservation of charge, we can obtain:

[0090] V MOS *C MOS =(V G -V MOS )*C NC (1)

[0091] Among them, C NC is the capacitance of the electrical trimming structure 300, C MOS is the capacitance of the switching transistor 102, V G is the output voltage of the row controller 307, V MOS is the actual coupling control voltage received by the switching transistor 102, that is, the actual gate voltage of the switching transistor 102. Among them, since C NC is a negative capacitance, that is, C NC =-丨C NC 丨 (2)

[0092] By arranging (1) and (2), we can obtain: V MOS *丨C MOS 丨=-(V G -V MOS )*丨C NC 丨 (3)

[0093] And the amplification factor of the switching transistor 102: Av=V MOS / V G (4)

[0094] Combining (3) and (4), we can obtain: V MOS / V G =丨C NC 丨 / (丨C NC 丨-丨C MOS 丨) (5)

[0095] It can be seen from equation (5) that after adding the electrical trimming structure 300, the Av of the switching transistor 102 is greater than 1, that is, V MOS is greater than V G , that is, by introducing the electrical trimming structure 300, the actual gate voltage received by the switching transistor 102 is increased to facilitate the turning on of the switching transistor 102. In addition, for the subthreshold swing (SS) of the switching transistor 102, the subthreshold swing

[0096] SS=dV G / dVint*dVint / dψ S * dψ S / dlogI D = dVG / dlogI D (6)

[0097] After adding the electrical trimming structure 300, the actual gate voltage of the switch transistor 102 is changed from V G Change to V MOS At this time, the subthreshold swing SS1 of the switch transistor 102 is (V G / V MOS )*SS(7)

[0098] Wherein, SS is the subthreshold swing of the switch transistor 102 when the electrical fine-tuning structure 300 is not added. As can be seen from the above, after the electrical fine-tuning structure 300 is added, Av of the switch transistor 102 is greater than 1, that is, V G / V MOS is less than 1, that is, SS1 is less than SS, and the subthreshold swing of the switching transistor 102 is reduced.

[0099] It is known from the prior art that in order to limit the channel leakage of the transistor, a substrate bias voltage Vbb is usually introduced on the substrate to reduce the channel leakage. However, since the sensing amplifier circuit SA and the row controller SWD around the memory array share the same substrate with the memory array, the introduction of the substrate bias voltage Vbb will introduce additional substrate leakage (Junction leakage) in the sensing amplifier circuit SA and the row controller SWD circuit. By reducing the subthreshold swing, the channel leakage of the transistor can be reduced, thereby avoiding the introduction of a large substrate bias voltage Vbb, that is, avoiding the influence of additional substrate leakage introduced into the sensing amplifier circuit SA and the row controller SWD circuit due to the introduction of Vbb.

[0100] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0101] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A storage array structure, It is characterized in that It comprises a plurality of basic units, each of which comprises: A storage capacitor configured to interact with the bit line structure; A switch transistor, a first terminal connected to the bit line structure, a second terminal connected to the storage capacitor, and a control terminal connected to the word line structure; The switch transistor is configured to be turned on based on the effective level transmitted by the word line structure to couple the storage capacitor and the bit line structure; An electrical fine-tuning structure is coupled to the word line structure and the control end of the switch transistor, wherein the capacitance of the electrical fine-tuning structure is a negative value.

2. The storage array structure according to claim 1, It is characterized in that The electrical fine-tuning structure is disposed in the structure of the switch transistor, and the switch transistor is an embedded transistor.

3. The storage array structure according to claim 2, It is characterized in that The switch transistor is embedded in the opening of the substrate, and the switch transistor comprises: A first insulating layer, disposed on the sidewalls and bottom of the opening, with a top surface flush with the substrate surface, and an inner surface of the first insulating layer enclosing a first opening; The electrical fine-tuning structure is disposed on the sidewall and the bottom of the first opening, and the inner surface of the electrical fine-tuning structure surrounds a second opening; A first conductive layer is disposed in the second opening and is located at the bottom of the second opening; A second conductive layer, disposed on a top surface of the first conductive layer; The second insulating layer is disposed on the top of the second conductive layer, and the top surface of the second insulating layer is flush with the top surface of the substrate.

4. The storage array structure according to claim 3, It is characterized in that The top surface of the electrical fine-tuning structure is flush with the substrate surface.

5. The storage array structure according to claim 3, It is characterized in that A top surface of the electrical fine-tuning structure is lower than a surface of the substrate and higher than a top surface of the second conductive layer.

6. The storage array structure according to claim 3, It is characterized in that A top surface of the electrical fine-tuning structure is lower than a top surface of the second conductive layer and higher than a top surface of the first conductive layer.

7. The storage array structure according to claim 3, It is characterized in that A top surface of the electrical fine-tuning structure is lower than a top surface of the first conductive layer.

8. The storage array structure according to claim 3, It is characterized in that In a direction perpendicular to the sidewall of the opening, the thickness of the electrical fine-tuning structure is 2 nm to 20 nm.

9. The storage array structure according to claim 3, It is characterized in that In a direction perpendicular to the sidewall of the opening, the thickness of the electrical fine-tuning structure is less than or equal to the thickness of the first insulating layer.

10. The storage array structure according to claim 3, It is characterized in that The material of the electric fine-tuning structure includes: hafnium aluminum oxide HfAlO x 、HfZrO x 、HfYO x 、HfLaO x 、HfSrO x At least one of .

11. The storage array structure according to any one of claims 2 to 10, It is characterized in that Also includes: A contact plug, one end of which is in contact with the second electrical fine-tuning structure and the other end of which is in contact with the word line structure, and is used to receive a control signal, wherein the control signal is used to drive the switch transistor; One end of the second electrical fine-tuning structure is in contact with the contact plug, and the other end is in contact with the control end of the switch transistor, wherein the capacitance of the second electrical fine-tuning structure is a negative value.

12. The storage array structure according to claim 11, It is characterized in that The material of the second electrical fine-tuning structure is the same as that of the electrical fine-tuning structure.

13. The storage array structure according to claim 11, It is characterized in that In the connection direction of the contact plug, the second electrical fine-tuning structure and the word line structure, the thickness of the second electrical fine-tuning structure is 2-20 nm.

14. The storage array structure according to claim 1, It is characterized in that Also includes: A contact plug, one end of which is in contact with the electrical fine-tuning structure and the other end of which is in contact with the word line structure, and is used to receive a control signal, wherein the control signal is used to drive the switch transistor; One end of the electrical fine-tuning structure is in contact with the contact plug, and the other end is in contact with the control end of the switch transistor.

15. A memory, It is characterized in that It comprises the storage array structure as described in any one of claims 1 to 14.

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