Display device and method of manufacturing same

Abstract

The invention provides a display device and a manufacturing method thereof. The display device includes: a substrate; a connection electrode on the substrate; a light emitting element on the connection electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a third direction; and an insulating layer covering the connection electrode and the light emitting element. The insulating layer has openings spaced apart from each other and exposing the second semiconductor layer of the light emitting element, and the second semiconductor layer has a plurality of grooves corresponding to the openings in the insulating layer.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0003] Embodiments of the present disclosure provide a display device and a method of manufacturing the same, the display device exhibiting improved light emitting efficiency of light emitted from a light emitting element by forming a concavo-convex pattern on one surface of the light emitting element from which light is emitted.

[0004] An embodiment of the present disclosure also provides a method for manufacturing a display device, which exhibits improved process efficiency and reduced cost by performing a process of forming a concave-convex pattern of a light-emitting element together with (or simultaneously with) a process of forming a pixel circuit area after the light-emitting element is disposed on a substrate.

[0005] However, the aspects and features of the present disclosure are not limited to the above-mentioned aspects and features, and they may be variously extended without departing from the spirit and scope of the present disclosure.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate; a connecting electrode on the substrate; a light emitting element on the connecting electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a third direction; and an insulating layer covering the connecting electrode and the light emitting element. The insulating layer has openings of the second semiconductor layer spaced apart from each other and exposing the light emitting element, and the second semiconductor layer has a plurality of grooves corresponding to the openings.

[0007] According to an embodiment, each of the plurality of grooves may overlap with the opening in a plan view.

[0008] According to an embodiment, the plurality of grooves may extend through a portion of the second semiconductor layer.

[0009] According to an embodiment, the opening in the insulating layer and the plurality of grooves of the second semiconductor layer may form a concavo-convex pattern.

[0010] According to an embodiment, the display device may further include a first transistor on the substrate and spaced apart from the light emitting element in a first direction intersecting the third direction.

[0011] According to an embodiment, the display device may further include: a first pixel electrode on the insulating layer and electrically connected to the first semiconductor layer of the light emitting element through the connecting electrode; and a second pixel electrode. The insulating layer may have a contact opening exposing a portion of the second semiconductor layer in which the plurality of grooves are not provided, and the second pixel electrode may be electrically connected to the second semiconductor layer of the light emitting element through the contact opening.

[0012] According to an embodiment, the first pixel electrode may be between the first transistor and the light emitting element in the first direction.

[0013] According to an embodiment, the first pixel electrode may not overlap the light emitting element in a plan view, and the second pixel electrode may be on the insulating layer and may cover at least one side surface of the light emitting element.

[0014] According to an embodiment, the display device may further include a second power supply line which is in the same layer as the connection electrode and to which the second driving power is applied.

[0015] According to an embodiment, the display device may further include: a first via layer covering the first transistor and the second power line; and a second conductive pattern on the first via layer and connected to the first transistor.

[0016] According to an embodiment, the display device may further include: a second via layer on the first via layer and covering the second conductive pattern; and a third conductive pattern on the second via layer. The third conductive pattern may include a first power line to which the first driving power is applied.

[0017] According to an embodiment, a cross-sectional shape of an inner surface of each of the plurality of grooves may be a tapered shape.

[0018] According to an embodiment, the display device may further include a conductive adhesive member between the connection electrode and the light emitting element in the third direction.

[0019] According to another embodiment of the present disclosure, a method for manufacturing a display device includes: providing a substrate defining a display element region and a pixel circuit region; forming a first transistor on the substrate in the pixel circuit region; forming a connection electrode on the substrate in the display element region; forming a light emitting element by sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on the connection electrode; forming an insulating layer covering the first transistor, the connection electrode, and the light emitting element; forming an opening partially exposing the second semiconductor layer of the light emitting element by etching the insulating layer; forming a first conductive layer on the first transistor; and forming a first conductive pattern by etching the first conductive layer. Etching the first conductive layer may include forming a first groove in the second semiconductor layer exposed by the opening.

[0020] According to an embodiment, etching the insulating layer may include forming a first contact hole and a second contact hole for respectively exposing a source electrode and a drain electrode of the first transistor by etching the insulating layer.

[0021] According to an embodiment, the method may further include: forming a contact opening exposing the second semiconductor layer of the light emitting element by etching the insulating layer. The first conductive pattern may include: a first pixel electrode electrically connected to the first semiconductor layer of the light emitting element through the connecting electrode; and a second pixel electrode electrically connected to the second semiconductor layer of the light emitting element through the contact opening.

[0022] According to an embodiment, the method may further include: forming a first via layer on the first conductive pattern; forming a second conductive layer on the first via layer; and forming a second conductive pattern by etching the second conductive layer. Etching the second conductive layer may include forming a second groove in the second semiconductor layer exposed by the opening, the first groove may have a first etching depth, and the second groove may have a second etching depth deeper than the first etching depth.

[0023] According to an embodiment, forming the first conductive pattern may include etching the first conductive layer by using an etching gas, and forming the second conductive pattern may include etching the second conductive layer by using an etching gas.

[0024] According to an embodiment, the etching gas may include boron trichloride (BCl 3 ) and chlorine (CL 2 ).

[0025] According to an embodiment, the second conductive pattern may include a 2-1st conductive pattern and a 2-2nd conductive pattern, and the 2-1st conductive pattern may include a scan line.

[0026] According to an embodiment, the method may further include: forming a second via layer on the first via layer; forming a third conductive layer on the second via layer; and forming a third conductive pattern by etching the third conductive layer using an etching gas. Etching the third conductive layer may include forming a third groove in the second semiconductor layer exposed by the opening, and the third groove may have a third etching depth deeper than the second etching depth.

[0027] According to an embodiment, the third conductive pattern may include a first power line to which the first driving power is applied, and the third conductive pattern may be electrically connected to the first terminal of the first transistor through a 2-2 conductive pattern.

[0028] According to an embodiment of the present disclosure, a display device and a method of manufacturing the display device can improve light extraction efficiency by forming a concavo-convex pattern on a surface of a light emitting element from which light is emitted.

[0029] In addition, the concavo-convex pattern formed on one surface of the light-emitting element from which light is emitted may not be formed in a separate process step, but may be formed in a process of forming a pixel circuit. Therefore, since a separate process step (including time conditions and process conditions) for forming the concavo-convex pattern may be omitted, process efficiency may be improved and manufacturing process costs may be reduced.

[0030] However, the aspects and features of the present disclosure are not limited to the above-mentioned aspects and features, and they may be variously extended without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic plan view showing a display device according to an embodiment of the present disclosure;

[0032] Figure 2 The embodiment of the present disclosure includes Figure 1 A circuit diagram of a sub-pixel in a display device shown in ;

[0033] Figure 3 The embodiment of the present disclosure includes Figure 2 A cross-sectional view of a light-emitting element in a sub-pixel shown in FIG.

[0034] Figure 4 According to an embodiment of the present disclosure, Figure 3 A cross-sectional view of a sub-pixel of a light-emitting element shown in ;

[0035] Figure 5 The present invention is a diagram showing an embodiment of the present invention. Figure 4 an enlarged view of region A; and

[0036] Figures 6 to 17 2 is a schematic cross-sectional view illustrating steps of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0038] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may also be present. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled to or directly connected to the second element, or the first element may be indirectly coupled to or indirectly connected to the second element via one or more intervening elements.

[0039] In the accompanying drawings, the sizes of various elements, layers, etc. may be exaggerated for clarity of explanation. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. In addition, the use of "may" when describing the embodiments of the present disclosure relates to "one or more embodiments of the present disclosure". Expressions such as "at least one of ..." and "any of ...", when before the list of elements, modify the elements of the entire list rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" indicates: only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the term "use" may be considered synonymous with the term "utilize", respectively. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms rather than as degree terms, and are intended to explain the inherent variation of measured values ​​or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0040] It will be understood that although the terms first, second, third, etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the exemplary embodiments, the first element, component, region, layer or part discussed below can be referred to as a second element, component, region, layer or part.

[0041] For ease of description, spatially relative terms such as "below," "below," "down," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another (additional) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the elements described as being "below" or "below" other elements or features will then be oriented "above" or "on" the other elements or features. Therefore, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] The terms used herein are used for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are intended to also include the plural forms. It will also be understood that the terms "include", "comprise", "include", and / or "comprises", when used in this specification, specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0043] Figure 1 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0044] refer to Figure 1 The display panel DP (or display device DD) may be provided in various shapes, for example, a rectangular plate shape having two pairs of sides parallel to each other, but is not limited thereto. When the display panel DP has a rectangular plate shape, one of the two pairs of sides may be longer than the other pair of sides.

[0045] At least a portion of the display panel DP may be flexible and may be folded at the flexible portion, but is not limited thereto.

[0046] The display panel DP can display an image. The display panel DP can be a display panel capable of (or configured for) self-emission (for example, it can be a self-emitting display panel), such as an organic light-emitting diode (OLED) display panel (or OLED panel) using an organic light-emitting diode as a light-emitting element, an ultra-small light-emitting diode display panel (micro-LED or nano-LED display panel) using an ultra-small light-emitting diode as a light-emitting element, and a quantum dot organic light-emitting display panel (QD OLED panel) using quantum dots and organic light-emitting diodes. In addition, the display panel DP can be a non-emitting (or non-self-emitting) display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel) and an electrowetting display panel (EWD panel). When the display panel DP is a non-emitting display panel, the display device DD may include a backlight unit for supplying light to the display panel DP. However, the present disclosure is not limited thereto, and the display panel DP may include an inorganic light-emitting element having an inorganic semiconductor.

[0047] The display panel DP may include a substrate SUB and pixels PXL disposed on the substrate SUB.

[0048] The substrate SUB may include a transparent insulating material that transmits light. The substrate SUB may be a rigid substrate or a flexible substrate. The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0049] The flexible substrate may be one of a film substrate and a plastic substrate including a polymerized organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0050] The display device DD may have various shapes. For example, the display device DD may have a rectangular shape, but is not limited thereto. For example, the display device DD may have a circular shape or an elliptical shape. In addition, the display device DD may include right angles and / or rounded corners. Figure 1 In FIG. 1 , a display device DD having a rectangular plate shape is shown as an example. Figure 1 , an extending direction (eg, a horizontal direction) of a short side of the display device DD is indicated as a first direction DR1, and an extending direction (eg, a vertical direction) of a long side is indicated as a second direction DR2.

[0051] The substrate SUB (and the display device DD) may have a display area DA for displaying an image and a peripheral area PA (or non-display area) excluding the display area DA (except the display area DA). The substrate SUB may have (or may define) a display area DA including a pixel area in which each pixel PXL is disposed and a peripheral area PA disposed around the display area DA (or disposed adjacent to the display area DA).

[0052] The peripheral area PA may be located adjacent to the display area DA. The peripheral area PA may be disposed on at least one side of the display area DA. For example, the peripheral area PA may surround the periphery (or edge or periphery) of the display area DA. In an embodiment, the peripheral area PA may be a frame area of ​​the display device DD.

[0053] The pixel PXL may be disposed in the display area DA on the substrate SUB. The peripheral area PA may be disposed around the display area DA. The peripheral area PA may have a structure for protecting the pixel PXL and related components disposed in the display area DA, but is not limited thereto. For example, a line unit connected to each pixel PXL and a driver connected to the line unit and driving the pixel PXL may be disposed in the peripheral area PA.

[0054] The pixel PXL may include a plurality of pixels (or sub-pixels). For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged in a first direction DR1. However, the present disclosure is not limited thereto, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged in a second direction DR2 intersecting the first direction DR1.

[0055] The first sub-pixel SPX1 to the third sub-pixel SPX3 may emit light having different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel for emitting red light, the second sub-pixel SPX2 may be a green sub-pixel for emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel for emitting blue light. However, the color, type, number, etc. of the pixels (or sub-pixels) configuring the pixel PXL are not particularly limited. For example, the color of light emitted from each of the first sub-pixel SPX1 to the third sub-pixel SPX3 may be variously changed.

[0056] Hereinafter, when the first to third subpixels SPX1 to SPX3 are collectively named, the first to third subpixels SPX1 to SPX3 are referred to as pixels PXL.

[0057] A plurality of pixels PXL may be provided, and the plurality of pixels PXL may be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR2. The arrangement form of the pixels PXL is not particularly limited, and when a plurality of pixels PXL are provided, the plurality of pixels PXL may be provided to have different areas (or sizes). For example, in an embodiment where the pixels PXL (or sub-pixels) emit light of different colors, the pixels PXL (or sub-pixels) may be provided with different areas (or sizes), or may have different shapes for each color.

[0058] The driver may control driving of the pixels PXL by supplying a signal and power (eg, a predetermined signal and a predetermined power) to each pixel PXL through a line unit.

[0059] Figure 2 The embodiment of the present disclosure includes Figure 1 Circuit diagram of a sub-pixel in a display device shown in .

[0060] Figure 2 The sub-pixel SPX shown in FIG. 1 may be Figure 1 Any one of the sub-pixels SPX1 to SPX3 shown in FIG. 1 , and each of the sub-pixels SPX1 to SPX3 arranged in the display area DA of the display device DD may be configured substantially the same as or similar to each other.

[0061] exist Figure 2 , for convenience, a sub-pixel SPX positioned in an i-th pixel row (or i-th horizontal row) and a j-th pixel column (where i and j are natural numbers greater than 0) is shown.

[0062] refer to Figure 2 The sub-pixel SPX may include a light emitting unit EMU that generates light having brightness corresponding to the data signal. In addition, the sub-pixel SPX may further selectively include a pixel circuit PXC for driving the light emitting unit EMU.

[0063] The light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 is connected to a first driving power source VDD and a voltage of the first driving power source VDD is applied to the first power line PL1, and the second power line PL2 is connected to a second driving power source VSS and a voltage of the second driving power source VSS is applied to the second power line PL2. For example, the light emitting unit EMU may include a first pixel electrode ELT1, a second pixel electrode ELT2, and a plurality of light emitting elements LD, the first pixel electrode ELT1 is connected to the first driving power source VDD via a pixel circuit PXC and the first power line PL1, the second pixel electrode ELT2 is connected to the second driving power source VSS via the second power line PL2, and the plurality of light emitting elements LD are connected in parallel between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the same direction. In an embodiment, the first pixel electrode ELT1 may be an anode, and the second pixel electrode ELT2 may be a cathode.

[0064] Each of the light emitting elements LD included in the light emitting unit EMU may have one end connected to the first driving power source VDD through the first pixel electrode ELT1 and the other end connected to the second driving power source VSS through the second pixel electrode ELT2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. During the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be greater than or equal to the threshold voltage of the light emitting element LD.

[0065] As described above, each of the light emitting elements LD connected in parallel between the first pixel electrode ELT1 and the second pixel electrode ELT2 to which voltages of different powers are supplied may configure each effective light source.

[0066] In an embodiment, the light emitting element LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit PXC. For example, during each frame period, a driving current corresponding to the grayscale value of the corresponding frame data of the pixel circuit PXC may be supplied to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may be divided and may flow to each of the light emitting elements LD. Therefore, when each light emitting element LD emits light having a brightness corresponding to the current flowing therethrough, the light emitting unit EMU may emit light having a brightness corresponding to the driving current.

[0067] In the above-described embodiment, both ends of the light-emitting element LD are connected between the first driving power source VDD and the second driving power source VSS in the same direction, but the present disclosure is not limited thereto. According to an embodiment, in addition to the light-emitting element LD configuring each effective light source, the light-emitting unit EMU may further include at least one invalid light source, such as a reverse light-emitting element LDr. The reverse light-emitting element LDr may be connected in parallel between the first pixel electrode ELT1 and the second pixel electrode ELT2 together with the light-emitting element LD configuring the effective light source, and may be connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the opposite direction to the light-emitting element LD. Even if a driving voltage (e.g., a forward driving voltage) is applied between the first pixel electrode ELT1 and the second pixel electrode ELT2, the reverse light-emitting element LDr remains in a disabled state, and therefore, current substantially does not flow through the reverse light-emitting element LDr.

[0068] The pixel circuit PXC may be connected to the scan line SLi and the data line DLj of the pixel PXL. In addition, the pixel circuit PXC may be connected to the control line CLi and the sensing line SENLj of the pixel PXL. For example, when the pixel PXL is disposed in the i-th row and the j-th column in the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line SLi, the j-th data line DLj, the i-th control line CLi, and the j-th sensing line SENLj.

[0069] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0070] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the first driving power source VDD and the light emitting unit EMU. The first terminal of the first transistor T1 may be connected to (or accessed to) the first driving power source VDD through the first power line PL1, the second terminal of the first transistor T1 may be connected to the second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current applied from the first driving power source VDD to the light emitting unit EMU through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but the present disclosure is not limited thereto. According to an embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0071] In an embodiment, the first transistor T1 may further selectively include a bottom metal layer BML (or a back gate electrode). The bottom metal layer BML and the gate electrode of the first transistor T1 may overlap each other with a gate insulating layer interposed therebetween. In an embodiment, the bottom metal layer BML may be connected to an electrode, such as a source electrode of the first transistor T1.

[0072] In an embodiment where the first transistor T1 includes a bottom metal layer BML, a reverse bias technique (or synchronization technique) for shifting a threshold voltage of the first transistor T1 in a negative direction or a positive direction by applying a reverse bias voltage to the bottom metal layer BML of the first transistor T1 may be applied. In addition, when the bottom metal layer BML is disposed under a semiconductor pattern configuring (or forming) a channel of the first transistor T1 to block light incident on the semiconductor pattern, the operating characteristics of the first transistor T1 may be stabilized.

[0073] The second transistor T2 may be a switching transistor that selects the pixel PXL in response to the scan signal and activates the pixel PXL, and may be connected between the data line DLj and the first node N1. The first terminal of the second transistor T2 may be connected to the data line DLj, the second terminal of the second transistor T2 may be connected to the first node N1, and the gate electrode of the second transistor T2 may be connected to the scan line SLi. The first terminal and the second terminal of the second transistor T2 may be different terminals, and for example, when the first terminal is a drain electrode, the second terminal may be a source electrode.

[0074] When a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the scan line SLi, the second transistor T2 may be turned on to electrically connect the data line DLj and the first node N1. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0075] The third transistor T3 can obtain a sensing signal through the sensing line SENLj by connecting the first transistor T1 to the sensing line SENLj, and can detect the characteristics of the pixel PXL including the threshold voltage of the first transistor T1 by using the sensing signal. Information about the characteristics of the pixel PXL can be used to convert image data so that the characteristic deviation between the pixels PXL can be compensated. The second terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sensing line SENLj, and the gate electrode of the third transistor T3 can be connected to the control line CLi. In addition, the first terminal of the third transistor T3 can be connected to an initialization power supply. The third transistor T3 can be an initialization transistor capable of initializing the second node N2, and can be turned on when a sensing control signal is supplied from the control line CLi to transmit the voltage of the initialization power to the second node N2. Therefore, the second storage electrode of the storage capacitor Cst connected to the second node N2 can be initialized.

[0076] A first storage electrode of the storage capacitor Cst may be connected to the first node N1, and a second storage electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst may charge a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Thus, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0077] exist Figure 2 , an embodiment in which all light emitting elements LD of the light emitting unit EMU are connected in parallel is shown, but the present disclosure is not limited thereto. According to an embodiment, the light emitting unit EMU may be configured to include at least one series stage (or stage) including a plurality of light emitting elements LD connected in parallel to each other. That is, the light emitting unit EMU may be configured in a series / parallel hybrid structure.

[0078] exist Figure 2 In the embodiment, all transistors T1 to T3 included in the pixel circuit PXC are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the transistors T1 to T3 may be changed to a P-type transistor.

[0079] In addition, the structure and driving method of the sub-pixel SPX can be changed in various ways. Figure 2 In addition to the embodiment shown in , the pixel circuit PXC may be configured as a pixel circuit PXC having various suitable structures and / or driving methods.

[0080] Figure 3 The embodiment of the present disclosure includes Figure 2 A cross-sectional view of a light-emitting element in a sub-pixel shown in FIG.

[0081] refer to Figure 3 The light emitting element LD is configured to emit light. For example, the light emitting element LD may be a light emitting diode including an inorganic material.

[0082] The light emitting element LD may include a first semiconductor layer SEC1, an active layer AL, a second semiconductor layer SEC2, and an electrode layer EL. For example, when the extension direction (e.g., the third direction DR3) of the light emitting element LD is the length direction, the electrode layer EL, the first semiconductor layer SEC1, the active layer AL, and the second semiconductor layer SEC2 may be implemented as a light emitting stack (or stacking pattern) sequentially stacked in the length direction.

[0083] The light emitting element LD may have a shape extending in one direction. The light emitting element LD may have a first end EP1 and a second end EP2 along a length direction. The first semiconductor layer SEC1 may be adjacent to the first end EP1 of the light emitting element LD, and the second semiconductor layer SEC2 may be adjacent to the second end EP2.

[0084] The light emitting element LD may have various shapes. Figure 1 As shown in , the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is longer in the length direction (e.g., having an aspect ratio greater than 1). In another embodiment, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is shorter in the length direction (e.g., having an aspect ratio less than 1). In another embodiment, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape with an aspect ratio of 1.

[0085] The light emitting element LD may include, for example, a light emitting diode (LED) manufactured to have an ultra-small size having a diameter and / or a length of approximately nanometer level (or nanometer) to micrometer level (or micrometer).

[0086] When the light emitting element LD is relatively long in the length direction (i.e., has an aspect ratio greater than 1), the diameter of the light emitting element LD may be in the range of 0.5 μm to 6 μm, and the length thereof may be in the range of 1 μm to 10 μm. However, the diameter and length of the light emitting element LD are not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or self-luminous display device to which the light emitting element LD is applied.

[0087] In an embodiment, the electrode layer EL may include a metal or a conductive metal oxide, and for example, the electrode layer EL may be formed of a transparent electrode material such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or alloy thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like, alone or in combination. The electrode layer EL may be substantially transparent. Therefore, light generated from the light emitting element LD may pass through the electrode layer EL and may be emitted to the outside of the light emitting element LD.

[0088] In an embodiment, the electrode layer EL may have an upper surface on which the first semiconductor layer SEC1 is disposed and a lower surface (also referred to as a first surface) exposed to the outside in a length direction. The electrode layer EL may define a first end EP1 (eg, a lower end) of the light emitting element LD.

[0089] The first semiconductor layer SEC1 may include, for example, at least one P-type semiconductor layer. For example, the first semiconductor layer SEC1 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a first conductive type dopant (such as Mg). The first semiconductor layer SEC1 may have a lower surface exposed to the outside along the length direction of the light emitting element LD and an upper surface contacting the active layer AL. The lower surface of the first semiconductor layer SEC1 may face the first end EP1 of the light emitting element LD.

[0090] The active layer AL may be disposed between the first semiconductor layer SEC1 and the second semiconductor layer SEC2, and may have a single quantum well structure or a multiple quantum well structure. For example, when the active layer AL is formed as a multiple quantum well structure, in the active layer AL, the barrier layer QB and the well layer QW may be periodically and repeatedly stacked as a unit. A strain enhancement layer may also be included between the barrier layer QB and the well layer QW. The lattice constant of the strain enhancement layer may be smaller than the lattice constant of the barrier layer QB to further enhance the strain (e.g., compressive strain) applied to the well layer QW. However, the structure of the active layer AL is not limited to the above-described embodiments.

[0091] A cladding layer doped with a conductive dopant and / or a tensile strain barrier reduction (TSBR) layer may also be included on and / or below the active layer AL. For example, the cladding layer may be formed of an AlGaN layer or an AlInGaN layer. The TSBR layer may be a strain relief layer disposed between semiconductor layers having different lattice structures, and may act as a buffer for reducing the lattice constant difference. The TSBR layer may be configured as a P-type semiconductor layer, such as p-GaInP, p-AlInP, and p-AlGaInP, but is not limited thereto.

[0092] The active layer AL may emit light having a wavelength in the range of 400 nm to 900 nm and may have a double heterostructure. The active layer AL may have a first surface contacting the first semiconductor layer SEC1 and a second surface contacting the second semiconductor layer SEC2.

[0093] The color (or emission color) of the light emitting element LD may be determined according to the wavelength of light emitted from the active layer AL. The color of the light emitting element LD may determine the color of the pixel corresponding thereto. For example, the light emitting element LD may emit red light, green light, or blue light.

[0094] When an electric field of a reference (or predetermined) voltage or higher voltage is applied to both ends of the light emitting element LD, the light emitting element LD emits light when electron-hole pairs are recombined in the active layer AL. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source (or light emitting source) of various light emitting devices including pixels of a display device.

[0095] In an embodiment, the second semiconductor layer SEC2 may include, for example, at least one N-type semiconductor layer. The second semiconductor layer SEC2 may include any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and may include an N-type semiconductor layer doped with a second conductive type dopant (such as Si, Ge or Sn). However, the material used to form the second semiconductor layer SEC2 is not limited thereto, and the second semiconductor layer SEC2 may be formed of various suitable materials. The second semiconductor layer SEC2 may have a lower surface contacting the active layer AL along the length direction of the light emitting element LD and an upper surface exposed to the outside. The upper surface of the second semiconductor layer SEC2 may define the second end EP2 of the light emitting element LD.

[0096] In an embodiment, the second end EP2 of the light emitting element LD may be a surface through which light is emitted from the active layer AL. The upper surface of the second semiconductor layer SEC2 may have a plurality of grooves EH. The plurality of grooves EH may be arranged spaced apart from each other in the radial direction of the light emitting element LD. The upper surface of the second semiconductor layer SEC2 exposed to the outside may have a concave-convex pattern formed by the plurality of grooves EH to increase the light extraction efficiency of the light emitting element LD.

[0097] Figure 4 According to an embodiment of the present disclosure, Figure 3 sectional view of a sub-pixel of a light-emitting element shown in FIG.

[0098] refer to Figure 4 , the display device DD may include a display area (eg, Figure 1The display area DA shown in FIG. 1 may include a substrate SUB. The sub-pixel SPX may be disposed in the display area DA. The sub-pixel SPX may include a pixel circuit area PCA and a display element area DPA.

[0099] The substrate SUB may configure (or may be) a base member of the display device DD. The substrate SUB may be a rigid or flexible substrate or film, but is not limited thereto. According to an example, the substrate SUB may include polyimide. The substrate SUB may be provided as a base surface and may include a pixel circuit area PCA and a display element area DPA.

[0100] Circuit elements (e.g. Figure 2 The first transistor T1 to the third transistor T3 shown in FIG. 1 and the signal line electrically connected to the circuit element may be disposed in the pixel circuit area PCA. Hereinafter, for the convenience of description, the present disclosure is described based on the first transistor T1 among the first transistor T1 to the third transistor T3 described above.

[0101] The display element area DPA may be surrounded by the pixel circuit area PCA (e.g., may be surrounded along its periphery). A light emitting element LD for emitting light may be provided in the display element area DPA. The light emitting element LD may be, for example, an inorganic light emitting element including an inorganic light emitting material or a light emitting element that emits light by changing the wavelength of the emitted light using quantum dots, but is not limited thereto.

[0102] The first transistor T1 may be disposed in the pixel circuit area PCA. The first transistor T1 may be disposed on one side of the light emitting element LD. The first transistor T1 may be disposed in a direction intersecting with the third direction DR3 (eg, Figure 1 In an example, the first transistor T1 may include a gate electrode GE, an active layer ACT, first and second terminals TE1 and TE2, and a bottom metal layer BML.

[0103] The bottom metal layer BML may be disposed on the substrate SUB and may be covered by the buffer layer BFL. A portion of the bottom metal layer BML may overlap with other configurations of the first transistor T1. The bottom metal layer BML may include a conductive material and may provide a path through which an electrical signal provided to the pixel circuit area PCA and the display element area DPA moves. For example, the bottom metal layer BML may include any one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0104] The buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may prevent impurities from diffusing from the outside. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiOx ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) is at least one of the metal oxides.

[0105] The active layer ACT may be disposed on the buffer layer BFL. For example, the active layer ACT may include any one of polycrystalline silicon, low temperature polycrystalline silicon (LTPS), amorphous silicon, and an oxide semiconductor. The active layer ACT may be a semiconductor layer. The active layer ACT may have a first contact region contacting the first terminal TE1 and a second contact region contacting the second terminal TE2. The first contact region and the second contact region may be semiconductor patterns doped with impurities. The region between the first contact region and the second contact region may be a channel region. The channel region may be an intrinsic semiconductor pattern not doped with impurities.

[0106] In an embodiment, the first terminal TE1 may be electrically connected to the first power line PL1 through the 1-2 conductive pattern BRP1b and the 2-2 conductive pattern BRP2b. The second terminal TE2 may be electrically connected to the light emitting element LD through the first pixel electrode ELT1 and the connection electrode CNE. In an example, the first terminal TE1 may be a source electrode, and the second terminal TE2 may be a drain electrode.

[0107] The gate electrode GE may be disposed on the gate insulating layer GI. The position of the gate electrode GE may correspond to (e.g., may be aligned with) the position of the channel region of the active layer ACT. For example, the gate electrode GE may be disposed on the active layer ACT in a region overlapping the channel region of the active layer ACT, with the gate insulating layer GI interposed therebetween. According to an example, the gate electrode GE may include any one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo). The gate insulating layer GI may be disposed on the active layer ACT.

[0108] In an embodiment, the first to third insulating layers INS1 to INS3 may be disposed directly on the buffer layer BFL. In an example, the first to third insulating layers INS1 to INS3 may be sequentially disposed in a direction crossing the third direction DR3.

[0109] In an embodiment, the first insulating layer INS1 and the third insulating layer INS3 may be disposed in the pixel circuit area PCA, and the second insulating layer INS2 may be disposed in the display element area DPA. In an example, the gate insulating layer GI may be disposed between the first insulating layer INS1 and the second insulating layer INS2 in a direction intersecting the third direction DR3. The second insulating layer INS2 may be disposed between the gate insulating layer GI and the third insulating layer INS3 in a direction intersecting the third direction DR3.

[0110] One electrode (eg, the upper electrode UE) of the storage capacitor Cst may be disposed on the first insulating layer INS1.

[0111] The connection electrode CNE may be disposed on the second insulating layer INS2. The connection electrode CNE may be disposed in a region corresponding to the display element region DPA. That is, the connection electrode CNE may be disposed between the second insulating layer INS2 and the light emitting element LD. The connection electrode CNE may include a metal material having excellent reflectivity. For example, the connection electrode CNE may be formed of a material such as aluminum (Al), silver (Ag), a silver alloy (Ag alloy), copper (Cu), or a magnesium-silver alloy (Mg-Ag), but is not limited thereto.

[0112] The third insulating layer INS3 may be disposed in the pixel circuit area PCA adjacent to the display element area DPA. The second power line PL2 may be disposed on the third insulating layer INS3. The second power line PL2 may include a second driving power source (eg, Figure 2 A power line for a voltage of a second driving power source VSS) shown in FIG.

[0113] The light emitting element LD may be disposed on the connection electrode CNE. The light emitting element LD may be disposed and / or provided in the display element region DPA. The light emitting element LD may be bonded to the connection electrode CNE by a conductive adhesive member PST. The conductive adhesive member PST may include a conductive paste. The conductive paste may include silver.

[0114] The light emitting element LD may include an electrode layer EL, a first semiconductor layer SEC1, an active layer AL, and a second semiconductor layer SEC2. The electrode layer EL, the first semiconductor layer SEC1, the active layer AL, and the second semiconductor layer SEC2 may be sequentially stacked and arranged in a third direction DR3. In an example, light emitted from the active layer AL may pass through the second semiconductor layer SEC2 and may be emitted in the third direction DR3. The second semiconductor layer SEC2 may have a surface having a plurality of grooves EH for increasing extraction efficiency of light generated in the active layer AL.

[0115] The insulating layer ILD may cover one electrode of the storage capacitor Cst, the first transistor T1, the second power line PL2, and the light emitting element LD throughout the entire areas of the pixel circuit area PCA and the display element area DPA.

[0116] In an embodiment, the insulating layer ILD may be disposed on a surface of the light emitting element LD disposed in the display element region DPA. The insulating layer ILD may be disposed and / or formed to surround the outer peripheral surface of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL.

[0117] In an embodiment, the insulating layer ILD may have first to fifth contact holes (e.g., contact openings) CH1 to CH5, an opening OP, and a contact opening CNT. The first to fifth contact holes CH1 to CH5 may be disposed and / or formed in the insulating layer ILD disposed in the pixel circuit area PCA. The opening OP and the contact opening CNT may be disposed and / or formed in the insulating layer ILD disposed in the display element area DPA.

[0118] In an embodiment, the insulating layer ILD may cover the first transistor T1. The first to third contact holes CH1 to CH3 may be contact holes (eg, contact openings) that pass through the insulating layer ILD to expose the first transistor T1.

[0119] The insulating layer ILD may have a first contact hole CH1 exposing the first terminal TE1. The first terminal TE1 may be connected to the 1-2 th conductive pattern BRP1b through the first contact hole CH1. The insulating layer ILD may have a second contact hole CH2 exposing the second terminal TE2. The second terminal TE2 may be electrically connected to the first pixel electrode ELT1 through the second contact hole CH2. The insulating layer ILD may have a third contact hole CH3 exposing the gate electrode GE. The 1-1 th conductive pattern BRP1a may be electrically connected to the gate electrode GE through the third contact hole CH3. The 1-1 th conductive pattern BRP1a may include a data line DL providing a data signal.

[0120] In an embodiment, the insulating layer ILD may cover the connection electrode CNE not overlapping the light emitting element LD. The fourth contact hole CH4 may be a contact hole (eg, a contact opening) exposing the connection electrode CNE. The connection electrode CNE may be electrically connected to the first pixel electrode ELT1 through the fourth contact hole CH4.

[0121] In an embodiment, the insulating layer ILD may cover one side surface of the light emitting element LD and the second power line PL2. The fifth contact hole CH5 may be a contact hole (e.g., a contact opening) exposing the second power line PL2. The second pixel electrode ELT2 may be electrically connected to the second power line PL2 through the fifth contact hole CH5 to receive the second driving power (e.g., Figure 2 The contact opening CNT may be an opening that exposes the second semiconductor layer SEC2 to electrically connect the second pixel electrode ELT2 and the light emitting element LD. The contact opening CNT may be filled with the second pixel electrode ELT2. The second driving power VSS may be applied to the second semiconductor layer SEC2 through the second pixel electrode ELT2.

[0122] In an embodiment, the insulating layer ILD may cover the side surface and the upper surface of the light emitting element LD. The insulating layer ILD may have an opening OP exposing the second semiconductor layer SEC2 of the light emitting element LD. In an example, a plurality of grooves EH of the second semiconductor layer SEC2 may be exposed to the outside through the opening OP in the insulating layer ILD. That is, each of the plurality of grooves EH may overlap with the opening OP in the third direction DR3 (or in a plan view). Each of the plurality of grooves EH may extend through a portion of the second semiconductor layer SEC2.

[0123] In an embodiment, the opening OP may be formed in the same process as the first to fifth contact holes CH1 to CH5 .

[0124] In an embodiment, after the light emitting element LD is disposed in the display element area DPA, the plurality of grooves EH may be formed in a process of forming circuit elements in the pixel circuit area PCA.

[0125] According to an embodiment of the present disclosure, the display device DD may have a concavo-convex pattern (eg, Figure 5 ). Therefore, light emitted from the active layer AL may pass through the concavo-convex pattern CCP in a set direction (eg, in an emission direction), thereby improving light emitting efficiency of the light emitting element LD.

[0126] The insulating layer ILD may include a transparent insulating material. For example, the insulating layer ILD may include a material selected from silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), hafnium oxide (HfO x ), titanium strontium oxide (SrTiO x ), cobalt oxide (Co x O y )、MgO、ZnO x ), ruthenium oxide (RuO x ), nickel oxide (NiO), tungsten oxide (WO x ), tantalum oxide (TaO x ), gadolinium oxide (GdO x ), zirconium oxide (ZrO x ), gallium oxide (GaO x ), vanadium oxide (V x O y)、ZnO:Al、ZnO:B、InxOy:H、NbO x O y ), magnesium fluoride (MgF x ), aluminum fluoride (AlF x ), aluminum cone polymer film (eg, organic-inorganic hybrid polymer film), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN x ), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN) and vanadium nitride (VN), but the present disclosure is not limited thereto, and various suitable materials with insulating properties can be used as the material of the insulating layer ILD.

[0127] In an embodiment, the first to third conductive layers SD1 to SD3 may be disposed in the pixel circuit area PCA.

[0128] In an embodiment, the first conductive layer SD1 may be disposed on the insulating layer ILD. The first conductive layer SD1 may include a first pixel electrode ELT1, a second pixel electrode ELT2, and a first bridge pattern BRP1. The first pixel electrode ELT1, the second pixel electrode ELT2, and the first bridge pattern BRP1 may be disposed in the same layer.

[0129] The first pixel electrode ELT1 may be disposed between the first transistor T1 and the connection electrode CNE (or the light emitting element LD) in a direction intersecting the third direction DR3. The first pixel electrode ELT1 may not overlap the light emitting element LD in the third direction DR3 (or in a plan view). The first pixel electrode ELT1 may be disposed in the second contact hole CH2 and the fourth contact hole CH4. The first pixel electrode ELT1 may receive an anode signal from the second terminal TE2 through the second contact hole CH2. The first pixel electrode ELT1 may transmit the anode signal to the first end portion (e.g., Figure 3 The first end EP1 is shown in FIG.

[0130] The second pixel electrode ELT2 may be disposed on the side surface of the light emitting element LD and on the fifth contact hole CH5. The second pixel electrode ELT2 may receive the cathode signal through the fifth contact hole CH5. The second pixel electrode ELT2 may transmit the cathode signal to the second end portion (e.g., Figure 3 The second end EP2 shown in FIG.

[0131] In an embodiment, the first bridge pattern BRP1 may include a 1-1st conductive pattern BRP1a, a 1-2nd conductive pattern BRP1b, and a 1-3rd conductive pattern BRP1c. The 1-1st conductive pattern BRP1a may be disposed on the gate electrode GE and may be electrically connected to the gate electrode GE through the third contact hole CH3. The 1-1st conductive pattern BRP1a may include a data line DL to which a data signal is applied. The 1-2nd conductive pattern BRP1b may be disposed on the first terminal TE1 and may be electrically connected to the first terminal TE1 through the first contact hole CH1. The 1-3rd conductive pattern BRP1c may overlap one electrode of the storage capacitor Cst and may be disposed on the insulating layer ILD.

[0132] In an embodiment, the first via layer VIA1 may be disposed on the first conductive layer SD1. The first via layer VIA1 may be formed of an organic material to flatten the step difference at the lower portion. For example, the first via layer VIA1 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not limited thereto, and the first via layer VIA1 may include an organic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) of various suitable types of inorganic materials.

[0133] In an embodiment, the second conductive layer SD2 may be disposed on the first via layer VIA1. The second conductive layer SD2 may include a second bridge pattern BRP2. The second bridge pattern BRP2 may include a 2-1st conductive pattern BRP2a and a 2-2nd conductive pattern BRP2b. The 2-1st conductive pattern BRP2a and the 2-2nd conductive pattern BRP2b may be disposed in the same layer and may be disposed spaced apart from each other on the first via layer VIA1. In an example, the 2-1st conductive pattern BRP2a may overlap with the 1-3rd conductive pattern BRP1c in the third direction DR3 (or in a plan view). The 2-1st conductive pattern BRP2a may include a scan line SL for supplying a scan signal. The 2-2nd conductive pattern BRP2b may be electrically connected to the 1-2nd conductive pattern BRP1b through a sixth contact hole CH6 passing through the first via layer VIA1.

[0134] In an embodiment, the second via layer VIA2 may be disposed on the first via layer VIA1. The second via layer VIA2 may cover the second conductive layer SD2. The second via layer VIA2 may be formed of an organic material to flatten the step difference at the lower portion. However, the present disclosure is not limited thereto, and the second via layer VIA2 may include various suitable types of inorganic materials.

[0135] In an embodiment, the third conductive layer SD3 may be disposed on the second via layer VIA2. The third conductive layer SD3 may include a third bridge pattern BRP3. The third bridge pattern BRP3 may be electrically connected to the 2-2nd conductive pattern BRP2b through the seventh contact hole CH7 passing through the second via layer VIA2. The third bridge pattern BRP3 may include a first driving power supply (e.g., Figure 1 The third bridge pattern BRP3 may supply the voltage of the first driving power source VDD to the first terminal TE1 through the 2-2nd conductive pattern BRP2b and the 1-2nd conductive pattern BRP1b.

[0136] In an embodiment, a protective layer PVX may be disposed on the second via layer VIA2. The protective layer PVX may be formed of an organic material to flatten the step difference at the lower portion, but is not limited thereto, and may include various suitable types of inorganic materials. The protective layer PVX may have an opening exposing the light emitting element LD.

[0137] Figure 5 The present invention is a diagram showing an embodiment of the present invention. Figure 4 Magnified view of area A.

[0138] refer to Figure 5 , the first semiconductor layer SEC1 can be electrically connected to the first pixel electrode ELT1, and therefore, the anode signal can be applied to the first semiconductor layer SEC1. The second semiconductor layer SEC2 can be electrically connected to the second pixel electrode ELT2 through the contact opening CNT in the insulating layer ILD, and therefore, the cathode signal can be applied to the second semiconductor layer SEC2. When an electric field having a reference (or predetermined) voltage or higher is applied to both ends of the light emitting element LD, when electron-hole pairs are recombined in the active layer AL, light can be emitted. The light emitted from the active layer AL can pass through the second semiconductor layer SEC2 and can be emitted in the third direction DR3.

[0139] The exposed surface of the second semiconductor layer SEC2 may have a concavo-convex shape formed by a plurality of grooves EH. The plurality of grooves EH may be exposed to the outside corresponding to (e.g., by aligning with) the opening OP in the insulating layer ILD. The cross-sectional shape of the inner surface of each of the plurality of grooves EH may have a conical shape. In an example, the side surface and the protruding portion of the second semiconductor layer SEC2 other than the plurality of grooves EH may be covered by the insulating layer ILD.

[0140] Since the display device DD according to an embodiment of the present disclosure may have the concavo-convex pattern CCP formed of the plurality of grooves EH and the openings OP, the display device DD may minimize (or improve) loss of a portion of light emitted from the active layer AL.

[0141] Figures 6 to 17 2 is a schematic cross-sectional view illustrating steps of a method of manufacturing a display device according to an embodiment of the present disclosure.

[0142] The method of manufacturing a display device according to an embodiment of the present disclosure may include: forming a first transistor T1 and a connection electrode CNE (see, for example, Figure 6 ); forming a light emitting element LD' (see, for example, FIG. 1 ) on the connection electrode CNE, including a first semiconductor layer SEC1, an active layer AL and a second semiconductor layer SEC2 sequentially arranged in the third direction DR3; Figure 7 ); forming an insulating layer ILD covering the first transistor T1, the connection electrode CNE and the light emitting element LD (see, for example Figure 8 ); forming an opening OP exposing the second semiconductor layer SEC2 of the light emitting element LD by etching the insulating layer ILD (see, for example, Fig. 9 ); forming a first conductive layer SD1 on the first transistor T1 (see, for example, Fig.10 ); and forming a first conductive pattern including a first pixel electrode ELT1, a second pixel electrode ELT2 and a first bridge pattern BRP1 by etching the first conductive layer SD1 (see, for example, Fig.11 ). Etching the first conductive layer SD1 may include forming a first groove EH1 in the second semiconductor layer SEC2 exposed through the opening OP.

[0143] refer to Figure 6 , a first transistor T1 and a connection electrode CNE may be formed in the display area DA on the substrate SUB. The first transistor T1 may be formed in the pixel circuit area PCA. The connection electrode CNE may be formed in the display element area DPA.

[0144] In an embodiment, a bottom metal layer BML may be formed on a substrate SUB. A buffer layer BFL may be formed on the substrate SUB to cover the bottom metal layer BML. An active layer ACT may be formed on the buffer layer BFL and may overlap the bottom metal layer BML in a third direction DR3 (or in a plan view).

[0145] In an embodiment, the gate insulating layer GI may be formed on the active layer ACT. The first to third insulating layers INS1 to INS3 may be spaced apart from each other and may be disposed on the buffer layer BFL. The first insulating layer INS1 and the second insulating layer INS2 may be formed on both sides of the gate insulating layer GI. The third insulating layer INS3 may be formed on one side of the second insulating layer INS2. In an example, the gate insulating layer GI and the first to third insulating layers INS1 to INS3 may be formed of the same material in the same process.

[0146] In an embodiment, one electrode (e.g., upper electrode UE) of the storage capacitor Cst may be formed on the first insulating layer INS1. The gate electrode GE may be formed on the gate insulating layer GI. The connection electrode CNE may be formed on the second insulating layer INS2. The second power line PL2 may be formed on the third insulating layer INS3. In an example, one electrode (e.g., upper electrode UE) of the storage capacitor Cst, the gate electrode GE, the connection electrode CNE, and the second power line PL2 may be formed of the same material in the same process. One electrode (e.g., upper electrode UE) of the storage capacitor Cst, the gate electrode GE, the connection electrode CNE, and the second power line PL2 may include a conductive material.

[0147] refer to Figure 7 , a light emitting element LD' may be formed on the connection electrode CNE.

[0148] The light emitting element LD' may include a first semiconductor layer SEC1, an active layer AL and a second semiconductor layer SEC2. The first semiconductor layer SEC1, the active layer AL and the second semiconductor layer SEC2 may be sequentially stacked in the third direction DR3. The light emitting element LD' may include a second semiconductor layer SEC2 having a flat upper surface exposed in the third direction DR3.

[0149] The display area DA may include an emission area EMA and a non-emission area NEA. The emission area EMA may correspond to a region where the light emitting element LD' is disposed. The non-emission area NEA may correspond to a region where the light emitting element LD' is not disposed.

[0150] The display element area DPA may be an area where the light emitting element LD' is formed. The pixel circuit area PCA may be an area surrounding the display element area DPA (eg, surrounding the periphery of the display element area DPA).

[0151] refer to Figure 8 , an insulating layer ILD may be formed on the buffer layer BFL to cover the first transistor T1 , the connection electrode CNE, and the light emitting element LD.

[0152] In an embodiment, the insulating layer ILD may be entirely formed throughout the pixel circuit area PCA and the display element area DPA.

[0153] refer to Fig. 9 , the insulating layer ILD may be etched, and thus, an opening OP and a contact opening CNT of the second semiconductor layer SEC2 partially exposing the light emitting element LD may be formed. In the example, a region of the insulating layer ILD corresponding to the first to fifth contact holes CH1 to CH5, the opening OP, and the contact opening CNT may be etched by using the first mask PM1. The insulating layer ILD may be etched, and thus, the first to fifth contact holes CH1 to CH5, the opening OP, and the contact opening CNT may be formed. The opening OP, the contact opening CNT, and the first to fifth contact holes CH1 to CH5 may be formed in the same process.

[0154] The first terminal TE1 (e.g., source electrode) and the second terminal TE2 (e.g., drain electrode) of the first transistor T1 may be exposed through the first contact hole CH1 and the second contact hole CH2 passing through the insulating layer ILD. The gate electrode GE may be exposed through the third contact hole CH3. The connection electrode CNE may be exposed through the fourth contact hole CH4. The second power line PL2 may be exposed through the fifth contact hole CH5.

[0155] The second semiconductor layer SEC2 may be partially exposed through the opening OP and the contact opening CNT passing through the insulating layer ILD. The opening OP may define a plurality of grooves (eg, Figure 4 The contact opening CNT may define an area where the second pixel electrode (eg, Figure 4 The area of ​​the second pixel electrode ELT2) shown in FIG.

[0156] refer to Fig.10 , a first conductive layer SD1 (or a first conductive pattern) may be formed in the pixel circuit area PCA. The first conductive layer SD1 may be formed on an insulating layer ILD disposed in the pixel circuit area PCA.

[0157] refer to Fig.11 , the first conductive layer SD1 may be etched, and thus, a first conductive pattern including the first pixel electrode ELT1, the second pixel electrode ELT2, and the first bridge pattern BRP1 may be formed.

[0158] In an embodiment, one region of the first conductive layer SD1 may be etched by exposing the one region of the first conductive layer SD1 to an etching gas GAS_EC disposed above the one region of the first conductive layer SD1 and passing through the second mask PM2. A portion of the first conductive layer SD1 corresponding to the one region of the first conductive layer SD1 exposed to the etching gas GAS_EC may be removed. When the first conductive layer SD1 is etched, first and second pixel electrodes ELT1 and ELT2 and a first bridge pattern BRP1 may be formed.

[0159] In an embodiment, the first pixel electrode ELT1 may be formed on the second contact hole CH2 and the fourth contact hole CH4. The second pixel electrode ELT2 may be formed on the contact opening CNT and the fifth contact hole CH5. The first bridge pattern BRP1 may include a 1-1st conductive pattern BRP1a, a 1-2nd conductive pattern BRP1b, and a 1-3rd conductive pattern BRP1c. The 1-1st conductive pattern BRP1a may be formed on the third contact hole CH3. The 1-2nd conductive pattern BRP1b may be formed on the first contact hole CH1. The 1-3rd conductive pattern BRP1c may be formed on one electrode (e.g., the upper electrode UE) of the storage capacitor Cst.

[0160] In an embodiment, first grooves EH1 may be formed in one surface of the second semiconductor layer SEC2 corresponding to the opening OP. In an example, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC. The second semiconductor layer SEC2 exposed to the etching gas GAS_EC may be etched, and thus the first grooves EH1 may be formed. In an example, each of the first grooves EH1 may have a first etching depth.

[0161] In an embodiment, the first conductive pattern including the first pixel electrode ELT1, the second pixel electrode ELT2, and the first bridge pattern BRP1 and the first groove EH1 may be formed in the same process. In the process of etching the first conductive layer SD1 to form the first conductive pattern including the first pixel electrode ELT1, the second pixel electrode ELT2, and the first bridge pattern BRP1, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC.

[0162] refer to Fig.12 , a first via layer VIA1 may be formed on the first conductive pattern including the first pixel electrode ELT1, the second pixel electrode ELT2 and the first bridge pattern BRP1. The first via layer VIA1 may be provided to flatten the step difference at the lower portion. In an example, a sixth contact hole CH6 may be formed through the first via layer VIA1.

[0163] refer to Fig.13 , a second conductive layer SD2 may be formed on the first via layer VIA1. In an example, the second conductive layer SD2 may overlap the first transistor T1 in the third direction DR3 (or in a plan view).

[0164] refer to Fig.14 , the second conductive layer SD2 may be etched, and thus, a second conductive pattern including a second bridge pattern BRP2 may be formed. In an embodiment, the second bridge pattern BRP2 may also be referred to as a second conductive pattern BRP2.

[0165] In an embodiment, when a region of the second conductive layer SD2 is exposed to the etching gas GAS_EC through the third mask PM3, a region of the second conductive layer SD2 may be etched. A portion of the second conductive layer SD2 corresponding to the region of the second conductive layer SD2 exposed to the etching gas GAS_EC may be removed. When the second conductive layer SD2 is etched, a second bridge pattern BRP2 may be formed.

[0166] In an embodiment, the second bridge pattern BRP2 may include a 2-1st conductive pattern BRP2a and a 2-2nd conductive pattern BRP2b. The 2-1st conductive pattern BRP2a may be formed on the first via layer VIA1 and may overlap the 1-3rd conductive pattern BRP1c. The 2-1st conductive pattern BRP2a may include a scan line SL for supplying a scan signal. The 2-2nd conductive pattern BRP2b may be formed on the first via layer VIA1 and overlap the sixth contact hole CH6. The 2-2nd conductive pattern BRP2b may be electrically connected to the 1-2nd conductive pattern BRP1b through the sixth contact hole CH6.

[0167] In an embodiment, a second groove EH2 may be formed on a surface of the second semiconductor layer SEC2 corresponding to the opening OP. In an example, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC. The second semiconductor layer SEC2 exposed to the etching gas GAS_EC may be etched, and thus the second groove EH2 may be formed. In an example, when the first groove EH1 is exposed to the etching gas GAS_EC, the surface of the first groove EH1 may be etched, and thus the second groove EH2 may be formed. Each of the second grooves EH2 may have a second etching depth. The second etching depth may be greater than the first groove EH1 (see, for example, Fig.11 ) has a first etching depth that is deep.

[0168] In an embodiment, the second conductive pattern BRP2 and the second groove EH2 may be formed in the same process. In the process of etching the second conductive layer SD2 to form the second conductive pattern BRP2, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC.

[0169] refer to Fig.15 , a second via layer VIA2 may be formed on the second conductive pattern BRP2. The second via layer VIA2 may be provided to planarize the step difference at the lower portion. In an example, a seventh contact hole CH7 may be formed through the second via layer VIA2.

[0170] In embodiments, a first via layer VIA1 and a second via layer VIA2 may be formed in the pixel circuit area PCA.

[0171] refer to Fig.16 , a third conductive layer SD3 may be formed on the second via layer VIA2. In an example, the third conductive layer SD3 may be formed in the pixel circuit area PCA and may overlap the first transistor T1 and the 2-1st conductive pattern BRP2a in the third direction DR3 (or in a plan view).

[0172] refer to Fig.17 , the third conductive layer SD3 may be etched, and thus a third conductive pattern including a third bridge pattern BRP3 may be formed.

[0173] In an embodiment, when one region of the third conductive layer SD3 is exposed to the etching gas GAS_EC passing through the fourth mask PM4, one region of the third conductive layer SD3 may be etched. A portion of the third conductive layer SD3 corresponding to the one region of the third conductive layer SD3 exposed to the etching gas GAS_EC may be removed. When the third conductive layer SD3 is etched, a third conductive pattern including a third bridge pattern BRP3 may be formed.

[0174] In an embodiment, the third bridge pattern BRP3 may be referred to as a third conductive pattern BRP3, and the third conductive pattern BRP3 may include a first driving power source (eg, Figure 1 The third conductive pattern BRP3 may be formed on the second via layer VIA2 and may overlap with the seventh contact hole CH7. The third conductive pattern BRP3 may be electrically connected to the 2-2nd conductive pattern BRP2b through the seventh contact hole CH7. The third conductive pattern BRP3 may transmit the anode signal to the first terminal TE1 of the first transistor T1 through the 2-2nd conductive pattern BRP2b and the 1-2nd conductive pattern BRP1b.

[0175] In an embodiment, a third groove EH3 may be formed on one surface of the second semiconductor layer SEC2 corresponding to the opening OP. In an example, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC. The second semiconductor layer SEC2 exposed to the etching gas GAS_EC may be etched, and thus the third groove EH3 may be formed. In an example, when the second groove EH2 is exposed to the etching gas GAS_EC, the surface of the second groove EH2 may be etched, and thus the third groove EH3 may be formed. In an example, each of the third grooves EH3 may have a third etching depth. The third etching depth may be greater than the second groove EH2 (see, for example Fig.14 ) has a second etching depth that is deeper.

[0176] In an embodiment, the third conductive pattern BRP3 and the third groove EH3 may be formed in the same process. In the process of etching the third conductive layer SD3 to form the third conductive pattern BRP3, the second semiconductor layer SEC2 exposed through the opening OP may be exposed to the etching gas GAS_EC.

[0177] In an embodiment, in the process of etching the first to third conductive layers SD1 to SD3, the second semiconductor layer SEC2 exposed through the opening OP in the insulating layer ILD may be exposed to the etching gas GAS_EC, and thus, a third groove EH3 (or a third groove EH4) may be formed in the second semiconductor layer SEC2 corresponding to the opening OP. Figure 4 Multiple grooves EH) shown in FIG.

[0178] refer to Fig.11 , Fig.14 and Fig.17 , the etching gas GAS_EC may be used in the process of etching the first conductive layer SD1 to the third conductive layer SD3. In an example, the etching gas GAS_EC may include boron trichloride (BCl 3 ) and chlorine (CL 2 ), but not limited thereto. In an example, the second semiconductor layer SEC2 of the light emitting element LD may be etched by using the etching gas GAS_EC. That is, since the second semiconductor layer SEC2 exposed through the opening OP is also exposed to the etching gas GAS_EC in the process of etching the first to third conductive layers SD1 to SD3, the second semiconductor layer SEC2 may be etched. The first to third grooves EH1 to EH3 may be formed in the second semiconductor layer SEC2 exposed to the etching gas GAS_EC.

[0179] According to the method of manufacturing a display device according to an embodiment of the present disclosure, a concave-convex pattern CCP can be formed by an opening OP and a first groove EH1 to a third groove EH3 formed along a path of light generated in an active layer AL (or emitted from an active layer AL) in a process of etching an insulating layer ILD and first to third conductive layers SD1 to SD3 (as a process of a pixel circuit PXC), without forming the concave-convex pattern CCP in a separate process, thereby ensuring process efficiency and improving the light-emitting efficiency of the light-emitting element LD.

[0180] Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as described in the claims and their equivalents.

Claims

1. Display device, include: substrate; connecting electrodes on the substrate; a light emitting element, on the connection electrode and comprising a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a third direction; as well as an insulating layer covering the connection electrode and the light emitting element, the insulating layer having openings spaced apart from each other and exposing the second semiconductor layer of the light emitting element, and The second semiconductor layer has a plurality of grooves corresponding to the openings in the insulating layer.

2. The display device according to claim 1, in, Each of the plurality of grooves overlaps the opening in a plan view and extends through a portion of the second semiconductor layer.

3. The display device according to claim 1, in, The opening in the insulating layer and the plurality of grooves in the second semiconductor layer form a concavo-convex pattern.

4. The display device according to claim 1, further comprising: include: a first transistor on the substrate and spaced apart from the light emitting element in a first direction intersecting the third direction; a first pixel electrode, on the insulating layer and electrically connected to the first semiconductor layer of the light emitting element through the connecting electrode; as well as a second pixel electrode, wherein the insulating layer has a contact opening exposing a portion of the second semiconductor layer where the plurality of grooves are not formed, and The second pixel electrode is electrically connected to the second semiconductor layer of the light emitting element through the contact opening.

5. The display device according to claim 4, in, The first pixel electrode is between the first transistor and the light emitting element in the first direction, wherein the first pixel electrode does not overlap with the light emitting element in a plan view, and The second pixel electrode is on the insulating layer and covers at least one side surface of the light emitting element.

6. The display device according to claim 4, further comprising: include: a second power supply line in the same layer as the connection electrode and to which a second driving power is applied; a first via layer, covering the first transistor and the second power line; a second conductive pattern on the first via layer and connected to the first transistor; a second via layer, on the first via layer and covering the second conductive pattern; as well as a third conductive pattern, on the second via layer, Wherein, the third conductive pattern includes a first power line to which a first driving power is applied.

7. The display device according to claim 1, in, A cross-sectional shape of an inner surface of each of the plurality of grooves is a tapered shape.

8. A method for manufacturing a display device, the method include: Providing a substrate defining a display element region and a pixel circuit region; forming a first transistor on the substrate in the pixel circuit region; forming a connection electrode on the substrate in the display element region; forming a light emitting element by sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on the connection electrode; forming an insulating layer covering the first transistor, the connection electrode and the light emitting element; forming an opening partially exposing the second semiconductor layer of the light emitting element by etching the insulating layer; forming a first conductive layer on the first transistor; as well as forming a first conductive pattern by etching the first conductive layer, Wherein, etching the first conductive layer includes: forming a first groove in the second semiconductor layer exposed by the opening.

9. The method according to claim 8, further comprising: include: forming a contact opening exposing the second semiconductor layer of the light emitting element by etching the insulating layer, The etching of the insulating layer comprises: forming a first contact hole and a second contact hole respectively exposing a source electrode and a drain electrode of the first transistor by etching the insulating layer; Wherein, the first conductive pattern comprises: a first pixel electrode electrically connected to the first semiconductor layer of the light emitting element through the connecting electrode; and The second pixel electrode is electrically connected to the second semiconductor layer of the light emitting element through the contact opening.

10. The method according to claim 8, further comprising: include: forming a first via layer on the first conductive pattern; forming a second conductive layer on the first via layer; as well as forming a second conductive pattern by etching the second conductive layer, Wherein, etching the second conductive layer comprises: forming a second groove in the second semiconductor layer exposed by the opening, wherein the first groove has a first etching depth, and The second groove has a second etching depth that is deeper than the first etching depth.

11. The method according to claim 10, in, Forming the first conductive pattern includes: etching the first conductive layer by using an etching gas, Wherein, forming the second conductive pattern comprises: etching the second conductive layer by using the etching gas, Wherein, the etching gas includes boron trichloride and chlorine, The second conductive pattern includes a 2-1 conductive pattern and a 2-2 conductive pattern, and Wherein, the 2-1st conductive pattern includes a scan line.

12. The method according to claim 11, further comprising: include: forming a second via layer on the first via layer; forming a third conductive layer on the second via layer; as well as forming a third conductive pattern by etching the third conductive layer using the etching gas, Wherein, etching the third conductive layer comprises: forming a third groove in the second semiconductor layer exposed by the opening, and The third groove has a third etching depth deeper than the second etching depth.

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