Display panel and display device

Abstract

The invention discloses a display panel and a display device, and generally relates to the technical field of display equipment. The display panel comprises a substrate comprising a display area and a peripheral area surrounding the display area: a plurality of sub-pixels located on one side of the substrate and located in the display area; the first dielectric medium layer is located in the peripheral area and surrounds the multiple first binding bonding pads, the first dielectric medium layer comprises a first area and a second area, the first dielectric medium layer in the first area surrounds the multiple first binding bonding pads, and the first dielectric medium layer in the second area surrounds the first dielectric medium layer in the first area; the middle dielectric layer is located on the side, away from the substrate, of the first dielectric layer of the second area and covers a boundary structure of the junction of the first dielectric layer of the first area and the first dielectric layer of the second area; and the first protection layer at least partially covers the edges, close to the first binding bonding pads, of the intermediate dielectric layer and the boundary structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display devices, and in particular to a display panel and a display apparatus. Background Art

[0002] With the continuous development of display panels, increasing the available area of ​​display panels has become a mainstream trend.

[0003] In order to maximize the available area of ​​the display panel, extremely narrow borders are often used.

[0004] However, in the above process, the driver chip (driver IC) needs to be bonded to the border area of ​​the display panel (PNL) and bent to the back of the display panel (PNL), so it is easy for some film layers of the PNL to crack. Summary of the invention

[0005] In view of the above defects or deficiencies in the related art, it is desired to provide a display panel and a display device that can solve the problem that the film layer of the PNL is easily cracked due to excessive pressure during the binding process of the driving chip above the PNL, thereby improving the stability and reliability of the display panel.

[0006] In a first aspect, a display panel is provided, the display panel comprising:

[0007] A substrate, comprising a display area and a peripheral area surrounding the display area:

[0008] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0009] a plurality of data lines, located in the display area and the peripheral area, electrically connected to the plurality of sub-pixels, and configured to transmit data signals to the plurality of sub-pixels;

[0010] A plurality of first binding pads are located in the peripheral area on one side of the display area, and some of the plurality of first binding pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driving chip;

[0011] A plurality of second binding pads, located on the substrate and on a side of the plurality of first binding pads away from the display area, the plurality of second binding pads being configured to be bound to a circuit board;

[0012] A first dielectric layer is located in the peripheral area and surrounds the plurality of first binding pads, the first dielectric layer includes a first region and a second region, the first dielectric layer in the first region surrounds the plurality of first binding pads, and the first dielectric layer in the second region surrounds the first dielectric layer in the first region;

[0013] An intermediate dielectric layer, located at a side of the first dielectric layer in the second region away from the substrate and covering a boundary structure at a junction of the first dielectric layer in the first region and the first dielectric layer in the second region;

[0014] The first protection layer at least partially covers the edge of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

[0015] In the present application, the display panel includes a substrate, which includes a display area and a peripheral area surrounding the display area; also includes a plurality of sub-pixels, the plurality of sub-pixels are located on one side of the substrate and in the above-mentioned display area; also includes a plurality of data lines, the plurality of data lines are located in the display area and the peripheral area, and are electrically connected to the plurality of sub-pixels, and are configured to transmit data signals to the plurality of sub-pixels; also includes a plurality of first binding pads, the plurality of first binding pads are located in the peripheral area on one side of the display area, and some of the plurality of first pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driving chip; also includes a plurality of second binding pads, which are located on the substrate and on a side of the plurality of binding pads away from the above-mentioned display area, and the plurality of The second binding pad is configured to be bound to the circuit board; it also includes a first dielectric layer, which is located in the above-mentioned peripheral area and surrounds the above-mentioned multiple first binding pads, the above-mentioned first dielectric layer includes a first area and a second area, the dielectric layer of the above-mentioned first area surrounds the above-mentioned multiple first binding pads, and the first dielectric layer of the above-mentioned second area surrounds the first dielectric layer of the above-mentioned first area; it also includes an intermediate dielectric layer, which is located on the side of the first dielectric layer of the above-mentioned second area away from the above-mentioned substrate and covers the boundary structure at the junction of the first dielectric layer of the above-mentioned first area and the dielectric layer of the above-mentioned second area; it also includes a first protective layer, which at least partially covers the edge of the above-mentioned intermediate dielectric layer close to the above-mentioned multiple first binding pads and the above-mentioned boundary structure. In this way, by covering the first protective layer at the edge and the boundary structure, it can be ensured that the shape of the boundary structure is a relatively regular structure, and then when it is necessary to continue to cover the film layer above the boundary structure in the future, there will be no abnormal morphology of the upper film layer, and then it is ensured that the first binding pad will not cause the film layer to crack during the binding process with the upper film layer.

[0016] In a second aspect, a display device is provided, comprising the display panel described in the first aspect.

[0017] In a third aspect, a method for manufacturing a display panel is provided.

[0018] The display panel comprises: a substrate, comprising a display area and a peripheral area surrounding the display area; a plurality of sub-pixels, located on one side of the substrate and located in the display area; a plurality of data lines, located in the display area and the peripheral area, and electrically connected to the plurality of sub-pixels, and configured to transmit data signals to the plurality of sub-pixels; a plurality of first binding pads, located in the peripheral area on one side of the display area, and some of the plurality of first binding pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driver chip; a plurality of second binding pads, located on the substrate and located between the plurality of first binding pads The bonding pad is away from the side of the display area, and the plurality of second binding pads are configured to be bound to the circuit board; a first dielectric layer is located in the peripheral area and surrounds the plurality of first binding pads, the first dielectric layer includes a first area and a second area, the first dielectric layer of the first area surrounds the plurality of first binding pads, and the first dielectric layer of the second area surrounds the first dielectric layer of the first area; an intermediate dielectric layer is located on the side of the first dielectric layer of the second area away from the substrate and covers the boundary structure at the junction of the first dielectric layer of the first area and the first dielectric layer of the second area;

[0019] The method comprises:

[0020] An intermediate dielectric layer is coated on a side of the display panel away from the base substrate; the intermediate dielectric layer is patterned in the peripheral area through a composition process to form a step portion; when a step portion is formed between the boundary structure of the first dielectric layer and the edge of the intermediate dielectric layer close to the plurality of first binding pads, a first protective layer is covered on at least a portion of the step portion.

[0021] In a fourth aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the third aspect is implemented.

[0022] In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that when the program is executed by a processor, the method described in the third aspect is implemented.

[0023] In a sixth aspect, a computer program product is provided, wherein the computer program product includes instructions, and the instructions are executed by a processor to implement the method described in the third aspect.

[0024] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0026] Figure 1 One of the schematic diagrams of the overall top view structure of the display area and the peripheral area of ​​the display panel provided in the embodiment of the present application;

[0027] Figure 2 A schematic diagram of a partial structure of a first binding pad in a peripheral area of ​​a display panel provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a partial structure of a data connection in a first binding pad provided in an embodiment of the present application;

[0029] Figure 4 A schematic side cross-sectional view of a display area of ​​a display panel provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of a top view structure of a first binding pad, a second binding pad and a protective layer in a peripheral area of ​​a display panel provided in an embodiment of the present application;

[0031] Figure 6 for Figure 5 The middle shows a side view of the position of panel EE;

[0032] Figure 7 Provided for the embodiments of this application Figure 5 A side cross-sectional schematic diagram showing a groove structure at position EE of the display panel;

[0033] Figure 8 A schematic top view of a peripheral area having a hole structure in a display panel provided in an embodiment of the present application;

[0034] Fig. 9 A schematic top view of a peripheral area of ​​a display panel having a surrounding groove structure provided in an embodiment of the present application

[0035] Fig.10 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0038] In recent years, with the advancement of science and technology, display panels have become an indispensable and important role in people's life, work, leisure and entertainment, and various types of display panels have been developing significantly. For example, the active matrix organic light emitting diode (AMLED) display panel is one of the various display panels and has received great attention from the industry. It has the advantages of light weight, high luminous efficiency, low power consumption, self-luminescence, good low temperature characteristics, and bendability.

[0039] Extremely narrow bezels are the main popular trend of display panels nowadays, which can make the effective display area of ​​the display panel account for as large a proportion of the entire display panel as possible. In order to narrow the lower bezel, the pads of the display panel are often set in the bezel area and bound to the driver chip (driver IC), that is, the chip on panel (COP) design. Taking advantage of the bendability of the display panel (PNL), the pads of the display panel bound to the driver IC are set on one side of the display panel (non-light-emitting side) through a bending process, thereby reducing the bezel area of ​​the lower bezel and forming a narrow bezel.

[0040] However, in the above process, the PNL needs to be etched. During the etching process, due to the inconsistency between the materials of the PNL film layer PVX and the TLD film layer, the etching speed is also different, which makes it easy to over-etch during the etching process, resulting in the subsequent TLD film layer covering the PVX film layer and prone to abnormal film morphology. In the subsequent process of bonding the driver IC to the pad of the display panel, cracks are likely to appear on the TLD film layer.

[0041] Specifically, one side of the substrate in the display panel is a stacked structure, including a dielectric layer ILD layer and other stacked structures, an intermediate dielectric layer PVX on the side of the ILD dielectric layer away from the substrate, and an uppermost dielectric layer (TLD) covering the side of the intermediate dielectric layer PVX away from the substrate. In the process of preparing the display panel, the intermediate dielectric layer PVX and the dielectric layer ILD adjacent thereto are etched, and then the TLD is covered on the side of the display panel away from the substrate after etching (that is, the side of the PVX and the dielectric layer away from the substrate).

[0042] However, since the material of PVX may be different from that of ILD, different etching lengths of PVX and ILD may occur during the etching process of PVX and ILD, which is called an undercut structure. In this way, when the TLD film layer is subsequently covered (for example, the TLD film layer is covered on the PVX and ILD by deposition), the TLD film layer is no longer completely flat, but has an abnormal morphology, and the pressure during the subsequent pad bonding process is likely to cause cracks in the TLD.

[0043] Based on this, the present application proposes a display panel and a display device, which can solve the problem that the film layer of the PNL is easily cracked due to pressure during the process of binding the driver IC, and improve the stability and reliability of the display panel.

[0044] Figures 1 to 9 It is a structural schematic diagram of a display panel provided by an embodiment of the present application, and the display panel includes: a base substrate, including a display area and a peripheral area surrounding the above-mentioned display area; a plurality of sub-pixels, located on one side of the above-mentioned base substrate and in the above-mentioned display area; a plurality of data lines, located in the above-mentioned display area and the above-mentioned peripheral area, and electrically connected to the above-mentioned plurality of sub-pixels, and configured to transmit data signals to the above-mentioned plurality of sub-pixels; a plurality of first binding pads, located in the above-mentioned peripheral area on one side of the above-mentioned display area, and some of the above-mentioned plurality of first binding pads are electrically connected to the above-mentioned plurality of data lines, and the above-mentioned plurality of first binding pads are configured to be bound to a driving chip (driving IC); a plurality of second binding pads, located on the above-mentioned base substrate and on a side of the above-mentioned plurality of first binding pads away from the above-mentioned display area, and the above-mentioned plurality of second binding pads are configured to be bound to a circuit board.

[0045] In the embodiment of the present application, the display panel is composed of multiple film layers, and the base substrate is one or more of the multiple film layers. The other film layers are all arranged on one side of the base substrate.

[0046] In the embodiment of the present application, the display panel includes a display area and a peripheral area, the display area is an area for display, and the peripheral area is a non-display area. The peripheral area can also be called a frame area.

[0047] For example, Figure 1 As shown, the display panel 100 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 1 The middle peripheral area BB is arranged around the display area AA. The peripheral area BB is an area where no image is displayed, and the peripheral area BB is configured to set a display driving circuit, for example, a scanning driving circuit and a source driving circuit.

[0048] Exemplarily, the display panel 100 may include a base substrate 10 and a plurality of sub-pixels 20 , each of which includes a pixel circuit 21 and a light-emitting element 22 , wherein the pixel circuit 21 is used to drive the light-emitting element 22 to emit light.

[0049] exist Figure 1 In the embodiment, a base substrate 10 is provided, and the base substrate 10 may be a flexible substrate 10 or a rigid substrate 10. The material used for the base substrate 10 may include polymer resin or glass.

[0050] Exemplarily, the substrate 10 may be flexible, and the material used by the substrate 10 includes a polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formic acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the substrate 10 may be rigid, and the material used by the substrate 10 includes glass containing SiO2 as a main component.

[0051] Exemplarily, the plurality of sub-pixels 20 are located on one side of the base substrate 10 , and the plurality of sub-pixels 20 are located in the display area AA. Each sub-pixel 20 includes at least one transistor 21 and at least one capacitor 22 .

[0052] The plurality of sub-pixels 20 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which is not specifically limited in the embodiments of the present disclosure.

[0053] For example, Figure 1As shown, the plurality of sub-pixels 20 may be arranged in a plurality of rows and columns, each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0054] For example, Figure 1 As shown, the peripheral area BB includes a first binding area BB1, and the first binding area BB1 is located at one side of the display area AA along the second direction Y. The first binding area BB1 is used to arrange the above-mentioned driving chip.

[0055] It is understandable that if Figure 1 As shown, the peripheral area BB further includes a second binding area BB2, which is located on a side of the first binding area BB1 away from the display area AA. The second binding area BB2 is used to set a plurality of second binding pads 60 for binding an external circuit board.

[0056] For example, you can compare Figure 2 , Figure 2 is a partial enlarged view of the first binding area BB1, Figure 2 Combination Figure 1 The display panel 100 includes a plurality of first binding pads 50 , which are located on one side of the base substrate 10 and in the first binding area BB1 , and are configured to be bound and connected to the driving chip of the display panel.

[0057] For example, Figure 1 As shown, the display panel 100 further includes a second binding pad 60. A plurality of second binding pads 60 are located on the base substrate 10, and a plurality of second binding pads 60 are located in the second binding area BB2. The plurality of second binding pads 60 are connected to the first binding pad 50, and the second binding pads 60 are configured to be bound and connected to an external circuit board.

[0058] For example, Figure 3 It can be seen that the plurality of first bonding pads 50 include a plurality of first sub-pads 51 and a plurality of second sub-pads 52. The plurality of first sub-pads 51 are located on one side of the plurality of second sub-pads 52 close to the display area AA. The plurality of first sub-pads 51 are electrically connected to the sub-pixels 20, and the plurality of first sub-pads 51 are electrically connected to the sub-pixels 20. Figure 2 As shown, a plurality of second sub-pads 52 are connected to the second binding pad 60. Exemplarily, the length of the first sub-pad 51 along the second direction Y is smaller than the length of the second sub-pad 52 along the second direction Y.

[0059] For example, Figure 2As shown, a plurality of first sub-pads 51 may be arranged in a plurality of rows and columns, each row of first sub-pads 51 includes at least two first sub-pads 51 arranged along a first direction X, and each column of first sub-pads 51 includes at least two first sub-pads 51 arranged along a second direction Y. The shape of the middle first sub-pad 51 is roughly rectangular, and the shape of the edge first sub-pads 51 is roughly parallelogram and tilted toward the middle. A plurality of second sub-pads 52 may be arranged in a row, the shape of the middle second sub-pad 52 is roughly rectangular, and the shape of the edge second sub-pads 52 is roughly parallelogram and tilted toward the middle.

[0060] For example, Figure 1 and Figure 3 As shown, Figure 3 for Figure 2 The display panel 100 further includes a plurality of data lines 70, which are located in the display area AA and extend to the first binding area BB1. The plurality of data lines 70 are electrically connected to the plurality of first sub-pads 51 and the sub-pixels 20. Figure 1 As shown, the display panel provides a signal through an external circuit board bound to a plurality of second binding pads 60, and transmits the signal through a plurality of connecting wires 71 ( Figure 1 In the figure, only one connection line 71 is marked with a reference numeral, and multiple connection lines located between the first sub-pad 51 and the second sub-pad 52 are the same as the connection line 71 and are used to transmit signals) to the second sub-pad 52, and after the driver chip converts the signal, it is transmitted to multiple data lines 70 through multiple first sub-pads 51, and then transmitted to the pixel circuit 21 through the data line 70. Figure 1 Only the way in which the data line is connected to part of the first binding pads is shown. In actual application, the data line 70 will be connected to part of the first binding pads. The data line 70 includes multiple data lines, and one sub-pad in the first binding pad is connected to one data line).

[0061] It should be noted that among the plurality of first binding pads 50 , some of the first binding pads 50 are electrically connected to the plurality of data lines 70 .

[0062] Exemplarily, the data lines 70 extend along the second direction Y to the first binding area BB1 , each data line 70 is connected to a column of pixel circuits 21 , and one data line 70 is connected to one first sub-pad 51 .

[0063] In the embodiment of the present application, the film layer of the display panel is Figure 4 Take this as an example to illustrate: Figure 4 for Figure 1A cross-sectional side view of a sub-pixel 20 at a CC position in FIG. Each sub-pixel includes at least one transistor 23 and at least one capacitor 24. The transistor 23 may be a low temperature polysilicon thin film transistor.

[0064] Further, in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a base substrate 10, and a circuit structure layer 120, a light emitting structure layer 130, and an encapsulation structure layer 140 sequentially arranged on the base substrate 10. The circuit structure layer 120 may include at least: a pixel circuit of a plurality of sub-pixels, each of which may include at least one transistor and at least one capacitor. The light emitting structure layer 130 may include at least: a light emitting element of a plurality of sub-pixels. In other examples, a touch structure layer may be provided on a side of the encapsulation structure layer 140 away from the base substrate 10 to integrate a touch function.

[0065] like Figure 4 As shown, the circuit structure layer 120 of the display area may include: a shielding layer 200 arranged on the base substrate 10, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source-drain metal layer) and a fourth conductive layer (also referred to as a second source-drain metal layer). A first insulating layer (also called a buffer layer) 101 may be provided between the blocking layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be provided between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be provided between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be provided between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first flat layer) 106 may be provided between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 may be located on a side of the fifth insulating layer 105 away from the base substrate 10; a seventh insulating layer (also called a second flat layer) 107 may be provided on a side of the fourth conductive layer away from the base substrate 10. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105 may be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, the fifth insulating layer may be omitted between the third conductive layer and the fourth conductive layer, and only the sixth insulating layer may be provided between the third conductive layer and the fourth conductive layer.

[0066] In some examples, such as Figure 4As shown, the semiconductor layer of the display area may include: an active layer 230 of the transistor 23 of the pixel circuit. The active layer 230 of the transistor 23 may include: a first area 2301, a second area 2302, and a channel area 2300 located between the first area 2301 and the second area 2302. The first conductive layer may include: a first gate 233 of the transistor 23, and a first electrode 241 of the capacitor 24. The orthographic projection of the first gate 233 of the transistor 23 on the substrate 10 may cover the orthographic projection of the channel area 2300 of the active layer 230 on the substrate 10. The second conductive layer may include: a second electrode 242 of the capacitor 24. The orthographic projections of the second electrode 242 and the first electrode 241 of the capacitor 24 on the substrate 10 may at least partially overlap, for example, the two may coincide.

[0067] Further, such as Figure 4 As shown, the third conductive layer of the display area may include: a first source 231 and a first drain 232 of the transistor 23. The first source 231 of the transistor 23 may be electrically connected to the first area 2301 of the active layer 230, and the first drain 232 may be electrically connected to the second area 2302 of the first active layer 230. The fourth conductive layer may include at least: a first anode transition electrode 451. The first anode transition electrode 451 may be electrically connected to the first drain 232 of the transistor 23 of the pixel circuit through a via hole provided in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element may be realized through the first anode transition electrode 451.

[0068] Further, such as Figure 4 As shown, the light emitting structure layer 130 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the seventh insulating layer 107, and electrically connected to the first anode switching electrode 451 through a via hole provided in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the organic light emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0069] In some examples, the organic light-emitting layer 132 of the light-emitting element may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0070] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0071] In some examples, such as Figure 4As shown, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display substrate, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0072] In the embodiment of the present application, the display panel further comprises: a first dielectric layer located in the peripheral area BB. The first dielectric layer is located in the peripheral area and surrounds the plurality of first binding pads 50 .

[0073] like Figure 1 , Figure 5 and Figure 6 As shown, Figure 1 As mentioned above, this is a top view of the display panel. Figure 5 for Figure 1 The top view after the middle and lower border is enlarged ( Figure 5 FIG. 4 shows the connection between some of the plurality of connection lines 71 and the first binding pad and the second binding pad). Further, Figure 6 for Figure 5 A side view showing the position of panel EE is shown in FIG. Figure 1 , Figure 5 and Figure 6 It can be seen that the first dielectric layer 32 is located in the peripheral area BB and surrounds the plurality of first binding pads 50 , and the plurality of first binding pads 50 are located in the first binding area BB1 .

[0074] Combination Figure 6 As shown, Figure 6 The substrate 10 and the first dielectric layer 32 are included.

[0075] In the embodiment of the present application, the first dielectric layer includes a first region 321 and a second region 322, the first dielectric layer in the first region surrounds the plurality of first binding pads, and the first dielectric layer in the second region surrounds the first dielectric layer in the first region. Figure 1 and Figure 5It can be seen that the second region 322 is arranged around the BB1 ​​region where the plurality of first binding pads are located. Figure 6 As shown, in Figure 6 In the embodiment, the first dielectric layer 32 includes a first region 321 and a second region 322 , and the second region 322 surrounds the plurality of first bonding pads 50 .

[0076] In the embodiment of the present application, the display panel further includes: an intermediate dielectric layer 33, which is a boundary structure located at a side of the first dielectric layer in the second region away from the base substrate and covers the junction of the first dielectric layer in the first region and the first dielectric layer in the second region.

[0077] It is understandable that an intermediate dielectric layer, such as a PVX layer, is disposed on the side of the second region away from the substrate. Figure 6 As shown, Figure 6 In the embodiment, an intermediate dielectric layer 33 is disposed on a side of the first dielectric layer 32 away from the base substrate 10 .

[0078] like Figure 6 As described above, a boundary structure 34 (framed by a dotted line) is formed at the boundary between the first region 321 and the second region 322 . The intermediate dielectric layer 33 covers the side of the boundary structure 34 away from the substrate 10 .

[0079] In an embodiment of the present application, the display panel further includes: a first protective layer, at least partially covering an edge of one side of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

[0080] It is understandable that the first protective layer may cover the edge of one side of the intermediate dielectric layer 33 close to the first binding pads 50 and the boundary structure, or may partially cover the edge of one side of the intermediate dielectric layer 33 close to the first binding pads 50 and the boundary structure.

[0081] In the embodiment of the present application, a side of the boundary structure away from the substrate is covered with a first protective layer.

[0082] Exemplarily, the first protective layer is a buffer structure.

[0083] In one example, the buffer structure is an obtuse-angle structure or a curved surface structure.

[0084] Exemplarily, the first protective layer is a structure that gently bulges toward a side away from the substrate.

[0085] like Figure 1 and Figure 6 As shown, Figure 1 is a top view of the display panel. Figure 6 for Figure 5 The corresponding cross-sectional view of the section at EE is Figure 5 and Figure 6 It can be seen that the coverage area corresponding to the first protection layer 38 substantially includes the protruding structure formed by the boundary structure 34 and the intermediate dielectric layer 33, and is close to the edge of the plurality of first binding pads BB1.

[0086] It should be noted that in Figure 6 In the display panel, the display panel further includes a plurality of peripheral insulating layers, specifically, a peripheral first insulating layer 11, a peripheral second insulating layer 12, and a peripheral third insulating layer 13. It can be understood that in the manufacturing process of the display panel, the film layer of the display area and the film layer corresponding to the peripheral area (i.e., the non-display area) are usually formed by the same manufacturing process, that is, the above Figure 6 The several film layers shown in the figure are the insulating layers of the peripheral area. The peripheral first insulating layer 11 and the first insulating layer 101 are prepared by the same preparation process and the same layer; the peripheral second insulating layer 12 and the second insulating layer 102 are prepared by the same preparation process and the same layer; the peripheral third insulating layer 13 and the third insulating layer 103 are prepared by the same preparation process and the same layer.

[0087] Optionally, in the embodiment of the present application, the first protection layer is a closed ring structure covering a side edge of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

[0088] like Figure 1 and Figure 5 As shown, in Figure 1 and Figure 5 In the embodiment, the first protective layer 38 is a closed ring structure that surrounds and covers the edge of the intermediate dielectric layer close to the plurality of first bonding pads 50, the boundary structure 34, and the edge of the intermediate dielectric layer close to the boundary structure.

[0089] It can be understood that the boundary structure includes a step portion consisting of a vertical surface and a parallel surface. Figure 6 As shown, the boundary structure is a step portion composed of a parallel surface and a vertical surface 30 at the intersection of the first area 321 and the second area 322, and on the side of the step portion away from the substrate 10, it also includes an intermediate dielectric layer 33 that is not aligned with the vertical surface 30 intersecting between the first area 321 and the second area 322. The intermediate dielectric layer 33 also forms a step portion, and the vertical surface of the step portion is a vertical surface 35. The vertical surface 30 and the vertical surface 35 are staggered with each other, that is, the step portion is a protruding structure compared to the boundary structure.

[0090] Furthermore, in the case where the vertical plane 30 and the vertical plane 35 are staggered with each other, if the second dielectric layer away from the intermediate dielectric layer 33 is directly covered on the boundary structure 34 and the protruding structure formed by the intermediate dielectric layer 33, it is easy to form an abnormal structure during the deposition process, for example, a structure with a sharp concave angle. Therefore, the boundary structure 34 and the protruding structure formed by the intermediate dielectric layer 33 can be completely covered by the first protective layer 38 with a buffering effect, thereby avoiding the situation in which the morphological abnormality is caused at the protruding structure formed by the boundary structure 34 and the intermediate dielectric layer 33 when the second dielectric layer is prepared later.

[0091] like Figure 6 As shown, the first protective layer 38, that is, the first protective layer completely covers the entire boundary structure 34 and the edge side of the intermediate dielectric layer close to the boundary structure, and is in a closed ring shape. In this way, when the first dielectric layer and the intermediate dielectric layer continue to cover other film layers on the side away from the substrate, there will be no abnormal morphology of other film layers.

[0092] Optionally, in an embodiment of the present application, the first dielectric layer and the intermediate dielectric layer are made of different materials.

[0093] It is understandable that, when the first dielectric layer and the middle dielectric layer are made of different materials, after the etching process, the first dielectric layer and the middle dielectric layer are etched at different speeds, and thus the etched volumes are also different.

[0094] like Figure 6 As shown, the first dielectric layer 32 and the intermediate dielectric layer 33 corresponding to the first region 321 (framed by a dotted line) and the second region 321 (framed by a dotted line) of the first dielectric layer 32 are made of different materials, so the etching boundary 30 after the first dielectric layer 32 is etched and the etching boundary 35 after the intermediate dielectric layer 33 is etched do not overlap. The etching boundary 30 of the first dielectric layer 32 is used as a dividing line for dividing the first region 321 and the second region 322 in the first dielectric layer 32.

[0095] In one example, the material of the intermediate dielectric layer 33 is silicon oxide, and the material of the first dielectric layer 32 is silicon nitride. After the intermediate dielectric layer 33 is etched by gas, since the etching speed of the first dielectric layer 32 made of silicon nitride is greater than the etching speed of the intermediate dielectric layer 33 made of silicon oxide, the etching boundaries of the first dielectric layer 32 and the intermediate dielectric layer 33 after etching do not overlap, and the etched area of ​​the first dielectric layer 32 is larger than that of the intermediate dielectric layer 33. In this case, the orthographic projection of the second area 322 on the substrate is within the orthographic projection of the intermediate dielectric layer 33 on the substrate 10.

[0096] Optionally, in an embodiment of the present application, the orthographic projection of the intermediate dielectric layer on the base substrate covers the orthographic projection of the boundary structure on the base substrate.

[0097] like Figure 6 As shown, the orthographic projection of the second region 322 on the substrate is within the orthographic projection of the intermediate dielectric layer 33 on the base substrate.

[0098] like Figure 6 As shown, the orthographic projection of the boundary line 30 between the first region 321 and the second region 322 on the base substrate 10 and the orthographic projection of the edge 35 of the intermediate dielectric layer 33 close to the first region 321 on the base substrate do not overlap.

[0099] Optionally, in an embodiment of the present application, the thickness of the first dielectric layer in the first region in a direction perpendicular to the substrate is smaller than the thickness of the first dielectric layer in the second region in a direction perpendicular to the substrate, and the boundary structure at the junction of the first region and the second region is a step portion.

[0100] It can be understood that, in the embodiment of the present application, in order to generate the above-mentioned first region surrounding the first binding pad 30, the intermediate dielectric layer needs to be etched, for example, by etching the intermediate dielectric layer with a gas.

[0101] In one example, during the etching process, the etching sometimes exceeds the intermediate dielectric layer and then etches to the film layer on the side of the intermediate dielectric layer close to the substrate, that is, the first dielectric layer is etched. In this case, the first dielectric layer can be divided into a first area and a second area by the etching line, and the thickness of the second area perpendicular to the substrate direction is different from the thickness of the first area perpendicular to the substrate direction.

[0102] It can be understood that, when the thickness of the second region is different from that of the first region, the boundary structure at the junction of the first region and the second region will be a step portion.

[0103] As described above, after etching the intermediate dielectric layer, it is sometimes over-etched, and a portion of the intermediate dielectric layer and the first dielectric layer are etched away. Since the intermediate dielectric layer and the first dielectric layer are made of different materials, the etching rates are different, which results in the projection of the remaining intermediate dielectric layer on the substrate after etching covering the projection of the second area of ​​the first dielectric layer on the substrate.

[0104] In one example, when a portion of the intermediate dielectric layer and the first dielectric layer are etched away, a boundary structure including at least two parallel surfaces and one vertical surface is formed, so that a step portion is formed between the first region and the second region. The parallel surface refers to the parallel surface of the intermediate dielectric layer away from the substrate, and the surface of the intermediate dielectric layer close to the substrate and not directly attached to the first dielectric layer; the vertical surface refers to the etched surface in the vertical direction after the first dielectric layer is etched. Figure 5 As shown, the parallel planes are the planes indicated by the dotted lines 36 and 37 , and the vertical plane is the plane indicated by the dotted line 30 .

[0105] Exemplarily, the vertical surface and the parallel surface constitute a step portion.

[0106] Optionally, in the embodiment of the present application, a second dielectric layer is provided on a side of the first protective layer and the intermediate dielectric layer away from the substrate.

[0107] Exemplarily, the orthographic projection of the second dielectric layer on the base substrate at least covers the orthographic projection of the first protective layer on the base substrate.

[0108] In an example, the second dielectric layer may be a touch insulating layer, that is, a TLD layer, which covers the first dielectric layer and the middle dielectric layer on a side away from the substrate.

[0109] like Figure 6 As shown, the first protective layer 38 completely covers the entire boundary structure 34 and the edge of the intermediate dielectric layer close to the boundary structure, and is in a closed ring shape. This can avoid the abnormal morphology of the TLD layer when the TLD layer is subsequently covered on the side of the first dielectric layer and the intermediate dielectric layer away from the substrate.

[0110] Optionally, in an embodiment of the present application, the first protective layer includes: an organic material film layer.

[0111] For example, the organic film layer may be Figure 4 The pixel definition layer 134 in the embodiment is located in the same layer, or is located in the same layer as any one of the second planar layer 106 and the third planar layer 107 .

[0112] The display panel provided in the embodiment of the present application includes a base substrate, which includes a display area and a peripheral area surrounding the display area; also includes a plurality of sub-pixels, the plurality of sub-pixels are located on one side of the base substrate and located in the above-mentioned display area; also includes a plurality of data lines, the plurality of data lines are located in the display area and the peripheral area, and are electrically connected to the plurality of sub-pixels, and are configured to transmit data signals to the plurality of sub-pixels; also includes a plurality of first binding pads, the plurality of first binding pads are located in the peripheral area on one side of the display area, and some of the plurality of first pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driving chip; also includes a plurality of second binding pads, which are located on the base substrate and located on a side of the plurality of binding pads away from the above-mentioned display area, The above-mentioned multiple second binding pads are configured to be bound to the circuit board; further comprising a first dielectric layer, located in the above-mentioned peripheral area and surrounding the above-mentioned multiple first binding pads, the above-mentioned first dielectric layer includes a first area and a second area, the dielectric layer of the above-mentioned first area surrounds the above-mentioned multiple first binding pads, and the first dielectric layer of the above-mentioned second area surrounds the first dielectric layer of the above-mentioned first area; further comprising an intermediate dielectric layer, located on the side of the first dielectric layer of the above-mentioned second area away from the above-mentioned substrate substrate and covering the boundary structure at the junction of the first dielectric layer of the above-mentioned first area and the dielectric layer of the above-mentioned second area; further comprising a first protective layer, the first protective layer at least partially covers the edge of the above-mentioned intermediate dielectric layer close to the above-mentioned multiple first binding pads and the above-mentioned boundary structure. In this way, by covering the first protective layer at the edge and the boundary structure, it can be ensured that the shape of the boundary structure is a relatively regular structure, and then when it is necessary to continue to cover the film layer above the boundary structure in the future, the upper film layer will not have an abnormal shape, and then it is ensured that the first binding pad will not cause the film layer to crack during the binding process with the upper film layer.

[0113] Optionally, in an embodiment of the present application, at least one groove structure is provided on a side of the intermediate dielectric layer close to the plurality of first binding pads.

[0114] Exemplarily, the at least one groove structure is arranged in a region of the intermediate dielectric layer corresponding to the first protective layer, and the region is close to one side of the plurality of first binding pads. The corresponding region refers to a region in the intermediate dielectric layer that will be covered by the first protective layer.

[0115] Further, an orthographic projection of at least one groove structure on the base substrate is within the orthographic projection range of the first protective layer on the base substrate.

[0116] Exemplarily, the groove structure may be a surrounding groove structure, or a discontinuous groove structure, or a hole structure, which is not limited in the embodiments of the present application, and please refer to the subsequent description for details.

[0117] Exemplarily, the depth of the groove structure is the same as the thickness of the intermediate dielectric layer.

[0118] It can be understood that after a number of groove structures with the same depth as the intermediate dielectric layer are set in the area corresponding to the intermediate dielectric layer and the above-mentioned first protective layer, the exposed area of ​​the first dielectric layer can be increased. Due to the presence of the grooves, in the subsequent process of using gas to etch the intermediate dielectric layer to generate a boundary structure, the etching gas density in the groove area is smaller than the etching gas density outside the groove area, thereby reducing the depth of etching the film layer outside the intermediate dielectric layer, that is, the first dielectric layer.

[0119] In this way, on the basis of the groove structure, the side of the boundary structure away from the substrate and the edge side of the intermediate dielectric layer close to the multiple first binding pads are covered with the first protective layer, which can ensure that the shape of the boundary structure is a relatively regular structure, and then when it is necessary to continue to cover the film layer above the first dielectric layer and the intermediate dielectric layer in the future, there will be no abnormal morphology of the upper film layer, thereby ensuring that the film layer will not crack during the binding process of the multiple first binding pads 50 with the driver chip.

[0120] Optionally, in an embodiment of the present application, the at least one groove structure includes a plurality of groove structures, and the plurality of groove structures are uniformly or non-uniformly distributed in the intermediate dielectric layer;

[0121] Exemplarily, the at least one groove structure is at least one annular groove structure, and the at least one annular groove structure is arranged around the plurality of first binding pads.

[0122] Exemplarily, the at least one annular groove structure means that the annular groove structures may be distributed in a single row or in multiple rows.

[0123] like Figure 7 and Figure 8 As shown, Figure 8 for Figure 5 A top view of the display panel including the groove structure, Figure 7 for Figure 5 Side view of the EE position. Figure 8 As shown, in the case where the groove structure is a plurality of hole structures 81, the plurality of hole structures 81 are non-uniformly distributed at the edge of one side of the intermediate dielectric layer close to the plurality of first binding pads, and the hole structures are distributed in a single row. Figure 7 It can be seen that the depth of the hole structure 81 is the same as the depth of the intermediate dielectric layer 33 .

[0124] It should be noted that if Figure 8 As shown, Figure 8In the embodiment, a first protective layer 38 is included, which is shown as a boundary line of the first protective layer in the top view, and also includes a first binding pad 50 in the first region, wherein the first binding pad includes a first sub-pad 51 and a first sub-pad 51. Figure 8 It is shown in Figure 6 The edge line 30 between the first region 321 and the second region 322 of the first dielectric layer 32 is indicated by a dotted line, and the edge line 30 overlaps with the hole structure 81. Figure 8 The cross-sectional view of the FF position is Figure 6 Consistent with Figure 8 Only shown in Figure 6 The edge line in 30)

[0125] like Figures 7 to 9 As shown, Figure 7 is a side view of the display panel. Fig. 9 is a top view of the display panel. Fig. 9 As shown, in the case where the groove structure is two surrounding closed groove structures 91, the multiple surrounding closed groove structures 91 are distributed on one side of the intermediate dielectric layer close to the multiple first binding pads, and the surrounding closed groove structure is a single row. Figure 7 It can be seen that the depth of the surrounding closed groove structure 91 is the same as the depth of the intermediate dielectric layer 33 .

[0126] It should be noted that if Fig. 9 As shown, Fig. 9 In the embodiment, a first protective layer 38 is included, which is displayed as a boundary line of the first protective layer in the top view, and also includes a first binding pad in the first region, wherein the first binding pad includes a first sub-pad 51 and a second sub-pad 52. Fig. 9 It is shown in Figure 6 The edge line 30 between the first region 321 and the second region 322 of the first dielectric layer 32 is indicated by a dotted line, and the edge line 30 is covered by the groove structure 91. Fig. 9 The cross-sectional view of the GG position is Figure 6 Consistent with Figure 8 Only shown in Figure 6 The edge line in 30)

[0127] Optionally, in an embodiment of the present application, the display panel includes a circuit structure layer arranged on one side of the base substrate and a light-emitting structure layer located on a side of the circuit structure layer away from the base substrate, the circuit structure layer includes: at least one thin film transistor, at least one capacitor, an interlayer insulating layer and a passivation layer; the light-emitting structure layer includes at least one light-emitting element.

[0128] Exemplarily, the at least one thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the at least one capacitor comprises a first capacitor electrode and a second capacitor electrode; Figure 4 The interlayer insulation 104 is between the second capacitor electrode and the drain, the passivation layer 105 is located on the side of the source and the drain away from the substrate, and the at least one light emitting element is electrically connected to the source or the drain through a via in the passivation layer.

[0129] Exemplarily, the first dielectric layer and the interlayer insulating layer 104 are located in the same layer, and the intermediate dielectric layer 33 and the passivation layer 105 are located in the same layer.

[0130] It can be understood that, from the above content, the display panel is composed of a plurality of film layers. When the display panel includes a display area and a peripheral area, most of the film layers will have a part of the area belonging to the display area, and the rest of the area belongs to the peripheral area. In the process of manufacturing the display panel, assuming that the same film layer includes the display area and the peripheral area, it is very likely to be manufactured at the same time, rather than first manufacturing the display area portion corresponding to the film layer, and then manufacturing the peripheral area portion corresponding to the film layer. In this case, the first dielectric medium layer and the intermediate dielectric layer in the above peripheral area in the embodiment of the present application correspond to part of the film layer in the display area, respectively, and belong to the same film layer.

[0131] For example, in the display area of ​​the display panel, the light-emitting elements of the display area need to be set through the light-emitting structure layer, and the circuit structure layer needs to provide the light-emitting structure layer with timing signals and electrical signals, so that the light-emitting elements of the light-emitting structure layer emit light according to the timing signals.

[0132] Exemplarily, in the embodiments of the present application, combined with Figure 4 and Figure 6 The first dielectric layer 32 and the interlayer insulating layer 104 are located in the same layer, and the intermediate dielectric layer 33 and the passivation layer 105 are located in the same layer.

[0133] Furthermore, in the process of manufacturing the interlayer insulating layer 104 in the display area of ​​the display panel, the first dielectric layer in the peripheral area of ​​the display panel is also manufactured. Figure 4 Accordingly, in the process of manufacturing the passivation layer 105 of the display area of ​​the display panel, an intermediate dielectric layer of the peripheral area of ​​the display panel is also manufactured, that is, Figure 4 The intermediate dielectric layer 33 in the.

[0134] For example, the above Figure 6 The first insulating layer 11 and the Figure 4 The first insulating layer (also referred to as a buffer layer) 101 in the above Figure 6 The second insulating layer around Figure 4 The second insulating layer (also referred to as the first gate insulating layer) 102 in the same layer is located. Figure 6 The third insulating layer 13 and the Figure 4 The third insulating layer (also referred to as the second gate insulating layer) 103 is located in the same layer. Figure 6 The base substrate 10 and Figure 4 The base substrate 100 is prepared by the same process, for example, the base substrate 10 and the base substrate 100 are located in the same layer.

[0135] Optionally, in an embodiment of the present application, the light-emitting structure layer further includes a pixel defining layer, the at least one light-emitting element includes an anode and a light-emitting layer, the pixel defining layer covers the edge of the anode and exposes the surface of the anode away from the substrate through a pixel opening, and the light-emitting layer is located in the opening. Exemplarily, the circuit structure layer further includes at least one planarization layer located on the side of the passivation layer away from the substrate, and the at least one light-emitting element is electrically connected to the source or the drain through vias in the passivation layer and the at least one planarization layer. Exemplarily, the first protective layer 38 is located in the same layer as the planarization layer, or the first protective layer 38 is located in the same layer as the pixel defining layer. It can be understood that in an embodiment of the present application, the first protective layer 38 is an organic material film layer, which can be either a pixel defining layer (PDL organic material film layer) or at least one planarization layer (PLN organic material film layer) during the manufacturing process, and both organic material film layers can serve as the first protective layer. It can be understood that in the above Figure 4 In the embodiment, the pixel definition layer is the pixel definition layer 134. The planarization layer is the Figure 4 Furthermore, in the process of manufacturing the first flat layer 106 in the display area of ​​the display panel, the first protective layer in the peripheral area of ​​the display panel is also manufactured. Figure 4 or, in the process of manufacturing the pixel definition layer 134 of the display area of ​​the display panel, substantially also manufacturing Figure 4 The first protective layer 38 in the embodiment of the present application further provides a display device, which includes the above-mentioned display panel.

[0136] Fig.10The present invention provides a flow chart of a method for manufacturing a display panel, wherein the display panel comprises: a substrate, comprising a display area and a peripheral area surrounding the display area; a plurality of sub-pixels, located on one side of the substrate and located in the display area; a plurality of data lines, located in the display area and the peripheral area, and electrically connected to the plurality of sub-pixels, and configured to transmit data signals to the plurality of sub-pixels; a plurality of first binding pads, located in the peripheral area on one side of the display area, and some of the plurality of first binding pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driver chip; a plurality of second binding pads, located on the substrate The first dielectric layer is located on the substrate and is located on a side of the plurality of first binding pads away from the display area, and the plurality of second binding pads are configured to be bound to the circuit board; a first dielectric layer is located in the peripheral area and surrounds the plurality of first binding pads, the first dielectric layer includes a first area and a second area, the first dielectric layer of the first area surrounds the plurality of first binding pads, and the first dielectric layer of the second area surrounds the first dielectric layer of the first area; an intermediate dielectric layer is located on a side of the first dielectric layer of the second area away from the substrate and covers a boundary structure at a junction of the first dielectric layer of the first area and the first dielectric layer of the second area;

[0137] The above method includes the following step 301:

[0138] Step 301: coating a middle dielectric layer on a side of the display panel away from the base substrate;

[0139] Step 302: patterning the intermediate dielectric layer in the peripheral area by a composition process to form a step portion;

[0140] Step 303: When a step portion is formed between the boundary structure of the first dielectric layer and the edge of the intermediate dielectric layer close to the plurality of first binding pads, cover at least a portion of the step portion with a first protection layer.

[0141] Exemplarily, the first protection layer is a closed ring structure covering the edge of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

[0142] Exemplarily, the orthographic projection of the intermediate dielectric layer on the base substrate covers the orthographic projection of the boundary structure on the base substrate.

[0143] Exemplarily, the thickness of the first dielectric layer in the first region in a direction perpendicular to the substrate is smaller than the thickness of the first dielectric layer in the second region in a direction perpendicular to the substrate, and the boundary structure at the junction of the first region and the second region is a step portion.

[0144] Exemplarily, a second dielectric layer is disposed on a side of the first protective layer and the intermediate dielectric layer away from the substrate, and an orthographic projection of the second dielectric layer on the substrate at least covers an orthographic projection of the first protective layer on the substrate.

[0145] Exemplarily, the first dielectric layer and the intermediate dielectric layer are made of different materials.

[0146] Exemplarily, the first protective layer includes: an organic material film layer.

[0147] In another embodiment of the present application, a specific implementation method of setting a groove structure is also provided. Exemplarily, before the aforementioned “when a step portion is formed between the boundary structure of the first dielectric layer and the edge of the intermediate dielectric layer close to the plurality of first binding pads, at least a portion of the step portion is covered with a first protective layer”, the specific implementation includes:

[0148] Step 304: Dispose at least one groove structure on a side of the intermediate dielectric layer close to the plurality of first bonding pads.

[0149] Exemplarily, the depth of the groove structure is the same as the thickness of the intermediate dielectric layer.

[0150] Exemplarily, the at least one groove structure includes a plurality of groove structures, and the plurality of groove structures are evenly or unevenly distributed in the intermediate dielectric layer; the at least one groove structure is at least one annular groove structure, and the at least one annular groove structure is arranged around the plurality of first binding pads.

[0151] Exemplarily, the display panel includes a circuit structure layer arranged on one side of the base substrate and a light-emitting structure layer located on a side of the circuit structure layer away from the base substrate, the circuit structure layer includes: at least one thin film transistor, at least one capacitor, an interlayer insulating layer and a passivation layer; the light-emitting structure layer includes at least one light-emitting element; the at least one thin film transistor includes an active layer located on the base substrate, a gate located on a side of the active layer away from the base substrate, and a source and a drain located on a side of the gate away from the base substrate; the at least one capacitor includes a first capacitor electrode and a second capacitor electrode; the interlayer insulating layer is located between the second capacitor electrode and the drain, the passivation layer is located on a side of the source and the drain away from the base substrate, and the at least one light-emitting element is electrically connected to one of the source or the drain through a via in the passivation layer; the first dielectric layer and the interlayer insulating layer are located on the same layer, and the intermediate dielectric layer and the passivation layer are located on the same layer.

[0152] Exemplarily, the light-emitting structure layer also includes a pixel defining layer, the at least one light-emitting element includes an anode and a light-emitting layer, the pixel defining layer covers the edge of the anode and exposes the surface of the anode away from the substrate through a pixel opening, and the light-emitting layer is located in the opening; the circuit structure layer also includes at least one planarization layer located on the side of the passivation layer away from the substrate, and the at least one light-emitting element is electrically connected to one of the source or the drain through vias in the passivation layer and the at least one planarization layer; the first protective layer and the planarization layer are located on the same layer, or the first protective layer and the pixel defining layer are located on the same layer.

[0153] The present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the training rule determination method described in the present application is implemented. For example, the following can be executed: Fig.10 The individual steps of the method are shown.

[0154] The present invention provides a computer program product, which includes instructions that are executed by a processor when the processor executes the instructions. Fig.10 The individual steps of the method are shown.

[0155] It should be noted that although the operations of the method of the present invention are described in a particular order in the drawings, this does not require or imply that the operations must be performed in this particular order or that all illustrated operations must be performed to achieve desired results.

[0156] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A display panel, characterized in that: include: A substrate, comprising a display area and a peripheral area surrounding the display area: A plurality of sub-pixels are located on one side of the base substrate and in the display area; a plurality of data lines, located in the display area and the peripheral area, electrically connected to the plurality of sub-pixels, and configured to transmit data signals to the plurality of sub-pixels; A plurality of first binding pads are located in the peripheral area on one side of the display area, and some of the plurality of first binding pads are electrically connected to the plurality of data lines, and the plurality of first binding pads are configured to be bound to a driving chip; A plurality of second binding pads, located on the substrate and on a side of the plurality of first binding pads away from the display area, the plurality of second binding pads being configured to be bound to a circuit board; A first dielectric layer is located in the peripheral area and surrounds the plurality of first binding pads, the first dielectric layer includes a first region and a second region, the first dielectric layer in the first region surrounds the plurality of first binding pads, and the first dielectric layer in the second region surrounds the first dielectric layer in the first region; An intermediate dielectric layer, located at a side of the first dielectric layer in the second region away from the substrate and covering a boundary structure at a junction of the first dielectric layer in the first region and the first dielectric layer in the second region; The first protection layer at least partially covers the edge of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

2. The display panel according to claim 1, characterized in that: The first protection layer is a closed ring structure covering the edge of the intermediate dielectric layer close to the plurality of first binding pads and the boundary structure.

3. The display panel according to claim 1, characterized in that: The orthographic projection of the intermediate dielectric layer on the base substrate covers the orthographic projection of the boundary structure on the base substrate.

4. The display panel according to claim 1, characterized in that: The thickness of the first dielectric layer in the first region in a direction perpendicular to the substrate is smaller than the thickness of the first dielectric layer in the second region in a direction perpendicular to the substrate, and the boundary structure at the junction of the first region and the second region is a step portion.

5. The display panel according to claim 1, characterized in that: A second dielectric layer is disposed on a side of the first protective layer and the intermediate dielectric layer away from the substrate, and an orthographic projection of the second dielectric layer on the substrate at least covers an orthographic projection of the first protective layer on the substrate.

6. The display panel according to claim 1, characterized in that: The first dielectric layer and the intermediate dielectric layer are made of different materials.

7. The display panel according to claim 1, characterized in that: The first protective layer includes: an organic material film layer.

8. The display panel according to claim 1, characterized in that: At least one groove structure is disposed on one side of the intermediate dielectric layer close to the plurality of first binding pads, and the depth of the groove structure is the same as the thickness of the intermediate dielectric layer.

9. The display panel according to claim 8, characterized in that: The at least one groove structure comprises a plurality of groove structures, and the plurality of groove structures are evenly or non-evenly distributed in the intermediate dielectric layer; The at least one groove structure is at least one annular groove structure, and the at least one annular groove structure is arranged around the plurality of first binding pads.

10. The display panel according to claim 1, characterized in that: The display panel comprises a circuit structure layer arranged on one side of the base substrate and a light emitting structure layer located on a side of the circuit structure layer away from the base substrate, wherein the circuit structure layer comprises: at least one thin film transistor, at least one capacitor, an interlayer insulating layer and a passivation layer; the light emitting structure layer comprises at least one light emitting element; The at least one thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the at least one capacitor comprises a first capacitor electrode and a second capacitor electrode; the interlayer insulating layer is located between the second capacitor electrode and the drain, the passivation layer is located on a side of the source and the drain away from the substrate, and the at least one light emitting element is electrically connected to one of the source or the drain through a via in the passivation layer; The first dielectric layer and the interlayer insulating layer are located in the same layer, and the intermediate dielectric layer and the passivation layer are located in the same layer.

11. The display panel according to claim 10, characterized in that: The light emitting structure layer further comprises a pixel defining layer, the at least one light emitting element comprises an anode and a light emitting layer, the pixel defining layer covers the edge of the anode and exposes the surface of the anode away from the substrate through a pixel opening, and the light emitting layer is located in the opening; The circuit structure layer further comprises at least one planarization layer located on a side of the passivation layer away from the base substrate, and the at least one light emitting element is electrically connected to one of the source electrode or the drain electrode through via holes in the passivation layer and the at least one planarization layer; The first protection layer and the planarization layer are located in the same layer, or the first protection layer and the pixel defining layer are located in the same layer.

12. A display device, characterized in that: The device comprises the display panel according to claims 1-11.

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