Display device

Abstract

There is provided a display device including an element layer including a light emitting element located in an emission area and a circuit layer, the circuit layer including: a light emitting pixel driver; a data line electrically connected to the light emitting pixel driver; a first auxiliary line extending in a first direction crossing the data line; the circuit layer includes a first auxiliary line extending in a first direction, and a second auxiliary line extending in a second direction crossing the first direction, where the first auxiliary line includes a first bypass auxiliary line, where the second auxiliary line includes a second bypass auxiliary line, where the circuit layer further includes: a first connection auxiliary electrode spaced apart from the first bypass auxiliary line; a first connection line connecting the first bypass auxiliary line to the first connection auxiliary electrode; and a first auxiliary protruding electrode protruding from the second bypass auxiliary line and electrically connected to the first connection auxiliary electrode through the auxiliary connection hole.

Description

Technical Field

[0001] Aspects of the present disclosure relate to a display device. Background Art

[0002] As information-oriented society develops, more and more demands are placed on display devices that display images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device including a micro-light-emitting element.

[0004] An organic light emitting display device displays images using light emitting elements, each of which includes a light emitting layer made of an organic light emitting material. As described above, an organic light emitting display device can display images using self-luminous elements, and therefore, compared with other display devices, can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0005] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area as a periphery of the display area. An emission area emitting light having various brightness and colors may be arranged in the display area.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] Aspects of embodiments of the present disclosure are directed to a display device including a data supply line that is disposed in a non-display area and electrically connects a data line to a display driving circuit.

[0008] As the number of data lines increases due to the demand for high resolution, the number of data supply lines disposed in the non-display area also increases, which poses a limitation on reducing the width of the non-display area.

[0009] Aspects of the present disclosure provide a display device capable of reducing the width of a non-display area.

[0010] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate, comprising a display area in which an emission area is arranged and a non-display area located around the display area; a circuit layer, on the substrate; and an element layer, on the circuit layer and comprising a light-emitting element located in the emission area, wherein the circuit layer comprises: a light-emitting pixel driver, electrically connected to the light-emitting element; a data line, electrically connected to the light-emitting pixel driver; a first auxiliary line, extending in a first direction intersecting the data line and located in the light-emitting pixel driver; and a second auxiliary line, extending in a second direction intersecting the first direction and parallel to the data line, the second auxiliary line being paired with a corresponding one of the data lines, wherein the first auxiliary line comprises an electrically A first bypass auxiliary line connected to a first data line among the data lines, the first data line being adjacent to a non-display area in a first direction, wherein the second auxiliary line includes a second bypass auxiliary line paired with a second data line among the data lines, the second data line being spaced farther from the non-display area than the first data line in the first direction, wherein the circuit layer further includes: a first connection auxiliary electrode adjacent to an intersection between the first bypass auxiliary line and the second bypass auxiliary line and spaced apart from the first bypass auxiliary line; a first connection line connecting the first bypass auxiliary line to the first connection auxiliary electrode; and a first auxiliary protruding electrode protruding from the second bypass auxiliary line and electrically connected to the first connection auxiliary electrode through one of the auxiliary connection holes.

[0011] In some embodiments, the circuit layer further includes: a data connection electrode adjacent to a crossing point between the data line and the first auxiliary line and spaced apart from the first auxiliary line; and a data protrusion electrode protruding from the data line and electrically connected to the data connection electrode through the data connection hole.

[0012] In some embodiments, the circuit layer further includes a second connection line connecting one of the data connection electrodes adjacent to a crossing point between the first data line and the first bypass auxiliary line to the first bypass auxiliary line.

[0013] In some embodiments, the circuit layer also includes: a first power line and a second power line, which are in the non-display area and respectively transmit the first power and the second power for driving the light-emitting element; and a first power line, which is electrically connected between the light-emitting pixel driver and the first power line, wherein the first auxiliary line also includes a second power auxiliary horizontal line electrically connected to the second power line, wherein the second auxiliary line also includes a second power auxiliary vertical line electrically connected to the second power auxiliary horizontal line and the second power line.

[0014] In some embodiments, the circuit layer further includes: a second connection auxiliary electrode adjacent to an intersection between the second power assisting vertical line and the second power assisting horizontal line; and a second auxiliary protruding electrode protruding from the second power assisting vertical line and electrically connected to the second connection auxiliary electrode through an auxiliary connection hole.

[0015] In some embodiments, one of the second power assist horizontal lines is electrically connected to at least one of the second power assist vertical lines, and the circuit layer also includes at least one third connection line, which connects at least one of the second connection assisting electrodes to one of the second power assisting horizontal lines, and at least one second connection assisting electrode is adjacent to the intersection between one of the second power assisting horizontal lines and at least one of the second power assisting vertical lines.

[0016] In some embodiments, the circuit layer also includes: a third connection auxiliary electrode, adjacent to the intersection between the second power assisting vertical line and the first bypass auxiliary line; a third auxiliary protruding electrode, protruding from the second power assisting vertical line and electrically connected to the third connection auxiliary electrode through an auxiliary connection hole; a fourth connection auxiliary electrode, adjacent to the intersection between the second bypass auxiliary line and the second power assisting horizontal line; and a fourth auxiliary protruding electrode, protruding from the second bypass auxiliary line and electrically connected to the fourth connection auxiliary electrode through the auxiliary connection hole.

[0017] In some embodiments, the display device also includes a display driving circuit configured to transmit a data signal of a light-emitting pixel driver to a data line, wherein the circuit layer also includes a data supply line in a non-display area and electrically connected between the data line and the display driving circuit, wherein the bypass area on one side of the display area includes: a central bypass middle area; a first bypass side area, parallel to the central bypass middle area in a first direction and in contact with the non-display area; and a second bypass side area, between the central bypass middle area and the first bypass side area, wherein the first data line is in the first bypass side area, wherein the second data line is in the second bypass side area, wherein a first data supply line that transmits a data signal of the first data line among the data supply lines is electrically connected to the first data line through a first bypass auxiliary line and a second bypass auxiliary line, and wherein a second data supply line that transmits a data signal of the second data line among the data supply lines is directly electrically connected to the second data line.

[0018] In some embodiments, one of the light-emitting elements is electrically connected between one of the light-emitting pixel drivers and a second power line, and one of the light-emitting pixel drivers includes: a first transistor, which is configured to generate a driving current for driving one of the light-emitting elements; a second transistor, which is electrically connected between one of the data lines and a first electrode of the first transistor; a third transistor, which is electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor; a fourth transistor, which is electrically connected between the gate electrode of the first transistor and a first initialization power line configured to transmit a first initialization power; a fifth transistor, which is electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor, which is electrically connected between the second electrode of the first transistor and one of the light-emitting elements; a seventh transistor, which is electrically connected between one of the light-emitting elements and a second initialization power line configured to transmit a second initialization power; and an eighth transistor, which is electrically connected between the first electrode of the first transistor and a bias power line configured to transmit a bias power.

[0019] In some embodiments, the circuit layer includes: a buffer layer covering the light blocking layer on the substrate; a first semiconductor layer on the buffer layer; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; a first planarizing layer covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarizing layer; and a second planarizing layer covering the second source-drain conductive layer, wherein the channel portion, source portion and drain portion of each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are in the first semiconductor layer, and wherein the channel portion, source portion and drain portion of each of the third transistor and the fourth transistor are as part of the second semiconductor layer.

[0020] In some embodiments, the gate electrode of the fourth transistor is electrically connected to a scan initialization line constructed to transmit a scan initialization signal, wherein the first initialization power line is spaced apart from the scan initialization line and serves as another part of the second semiconductor layer, wherein the scan initialization line is in a third gate conductive layer, wherein the first auxiliary line, the connection auxiliary electrode, and the data connection electrode are in a first source-drain conductive layer, wherein the data line, the second auxiliary line, the auxiliary protruding electrode, the data protruding electrode, and the first power line are in a second source-drain conductive layer, wherein each of the auxiliary connection hole and the data connection hole penetrates the first planarization layer, and wherein the first auxiliary line and the connection auxiliary electrode overlap with the first initialization power line and are spaced apart from the scan initialization line.

[0021] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate comprising a display area in which an emission area is arranged and a non-display area around the display area; a circuit layer on the substrate; and an element layer on the circuit layer and comprising a light-emitting element located in the emission area, wherein the circuit layer comprises: a light-emitting pixel driver electrically connected to the light-emitting element; a data line electrically connected to the light-emitting pixel driver; a first auxiliary line extending in a first direction intersecting the data line and located in the light-emitting pixel driver; a second auxiliary line extending in a second direction intersecting the first direction and parallel to the data line, the second auxiliary line being paired with a corresponding data line in the data lines; a connecting auxiliary electrode adjacent to an intersection between the first auxiliary line and the second auxiliary line and spaced apart from the first auxiliary line; and an auxiliary protruding electrode protruding from the second auxiliary line and electrically connected to the connecting auxiliary electrode through an auxiliary connection hole.

[0022] In some embodiments, the circuit layer further includes: a data connection electrode adjacent to an intersection between the data line and the first auxiliary line and spaced apart from the first auxiliary line and the connection auxiliary electrode; and data protrusion electrodes protruding from the data line and electrically connected to the data connection electrodes through the data connection holes, respectively.

[0023] In some embodiments, the connection auxiliary electrode faces one side of the first auxiliary line in the second direction, the data connection electrode faces the other side of the first auxiliary line in the second direction, and the connection auxiliary electrode and the data connection electrode are spaced apart from each other in an oblique direction intersecting the first direction and the second direction.

[0024] In some embodiments, the display device also includes a display driving circuit configured to transmit a data signal of a light-emitting pixel driver to a data line, wherein the circuit layer also includes a data supply line in the non-display area and electrically connected between the data line and the display driving circuit, wherein the bypass area on one side of the display area includes: a central bypass middle area; a first bypass side area, parallel to the central bypass middle area in a first direction and in contact with the non-display area; and a second bypass side area, between the central bypass middle area and the first bypass side area, wherein the data line includes a first data line in the first bypass side area and a second data line in the second bypass side area, wherein the first auxiliary line includes a first bypass auxiliary line electrically connected to the first data line, wherein the second auxiliary line includes a second bypass auxiliary line paired with the second data line and electrically connected to the first bypass auxiliary line, wherein a first data supply line that transmits a data signal of the first data line among the data supply lines is electrically connected to the first data line through the first bypass auxiliary line and the second bypass auxiliary line, and wherein a second data supply line that transmits a data signal of the second data line among the data supply lines is directly electrically connected to the second data line.

[0025] In some embodiments, the circuit layer also includes: a first connecting line, connecting a first connecting auxiliary electrode among the connecting auxiliary electrodes to the first bypass auxiliary line, the first connecting auxiliary electrode being adjacent to the intersection between the first bypass auxiliary line and the second bypass auxiliary line; and a second connecting line, connecting a data connecting electrode among the data connecting electrodes adjacent to the intersection between the first bypass auxiliary line and the first data line to the first bypass auxiliary line, wherein the second bypass auxiliary line is electrically connected to the first bypass auxiliary line through an auxiliary protruding electrode among the auxiliary protruding electrodes overlapping with one of the connecting auxiliary electrodes, one of the connecting auxiliary electrodes, and the first connecting line, wherein the first data line is electrically connected to the first bypass auxiliary line through a data protruding electrode among the data protruding electrodes overlapping with one of the data connection electrodes, one of the data connection electrodes, and the second connecting line.

[0026] In some embodiments, the circuit layer also includes: a first power line and a second power line, which are in the non-display area and transmit the first power and the second power for driving the light-emitting element respectively; and a first power line, which is electrically connected between the light-emitting pixel driver and the first power line, wherein one of the light-emitting elements is electrically connected between one of the light-emitting pixel drivers and the second power, wherein one of the light-emitting pixel drivers in the light-emitting pixel driver includes: a first transistor, which is configured to generate a driving current for driving one of the light-emitting elements; a second transistor, which is electrically connected between one of the data lines and the first electrode of the first transistor; a third transistor, which is electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor, which is electrically connected between the gate electrode of the first transistor and the first initialization power line configured to transmit the first initialization power; a fifth transistor, which is electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor, which is electrically connected between the second electrode of the first transistor and one of the light-emitting elements; a seventh transistor, which is electrically connected between one of the light-emitting elements and the second initialization power line configured to transmit the second initialization power; and an eighth transistor, which is electrically connected between the first electrode of the first transistor and the bias power line configured to transmit the bias power.

[0027] In some embodiments, the circuit layer includes: a buffer layer covering the light blocking layer on the substrate; a first semiconductor layer on the buffer layer; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; a first planarizing layer covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarizing layer; and a second planarizing layer covering the second source-drain conductive layer, wherein the channel portion, source portion and drain portion of each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are in the first semiconductor layer, and wherein the channel portion, source portion and drain portion of each of the third transistor and the fourth transistor are as part of the second semiconductor layer.

[0028] In some embodiments, the gate electrode of the fourth transistor is electrically connected to a scan initialization line constructed to transmit a scan initialization signal, wherein the first initialization power line is spaced apart from the scan initialization line and serves as another part of the second semiconductor layer, wherein the scan initialization line is in a third gate conductive layer, wherein the first auxiliary line, the connection auxiliary electrode and the data connection electrode are in a first source-drain conductive layer, wherein the data line, the second auxiliary line, the auxiliary protruding electrode, the data protruding electrode and the first power line are in a second source-drain conductive layer, wherein each of the auxiliary connection hole and the data connection hole penetrates the first planarization layer, wherein the first auxiliary line and the connection auxiliary electrode overlap with the first initialization power line and are spaced apart from the scan initialization line.

[0029] In some embodiments, the first auxiliary line also includes a second power assist horizontal line electrically connected to the second power line, wherein the second auxiliary line also includes a second power assist vertical line electrically connected to the second power assist horizontal line and the second power line, wherein one of the second power assist horizontal lines is electrically connected to at least one of the second power assist vertical lines, wherein the circuit layer also includes at least one third connecting line, at least one third connecting line connects at least one connecting auxiliary electrode to one of the second power assist horizontal lines, and at least one connecting auxiliary electrode is adjacent to an intersection between one of the second power assist horizontal lines and at least one of the second power assist vertical lines.

[0030] That is, according to some embodiments, the circuit layer includes: a connection auxiliary electrode adjacent to an intersection (e.g., an intersection) between a first auxiliary line and a second auxiliary line and spaced apart from the first auxiliary line; and an auxiliary protruding electrode protruding from the second auxiliary line and electrically connected to the connection auxiliary electrode through an auxiliary connection hole, respectively. Here, the connection auxiliary electrode may include: a first connection auxiliary electrode adjacent to an intersection (e.g., an intersection) between a first bypass auxiliary line and a second bypass auxiliary line; a second connection auxiliary electrode adjacent to an intersection between a second power auxiliary horizontal line and a second power auxiliary vertical line; and a third connection auxiliary electrode adjacent to an intersection (e.g., an intersection) between the first bypass auxiliary line and the second power auxiliary vertical line.

[0031] As described above, according to some embodiments, all of the connection auxiliary electrodes adjacent to the intersection (e.g., intersection) between the first auxiliary line and the second auxiliary line may be electrically connected to the auxiliary protruding electrodes through the auxiliary connection holes, respectively. That is, all of the connection auxiliary electrodes may overlap with the auxiliary connection holes.

[0032] Therefore, it is possible to prevent visibility of the connection auxiliary electrode and visibility of intersections (eg, junctions) between first and second auxiliary lines adjacent to the connection auxiliary electrode from being increased due to the arrangement of the auxiliary connection holes.

[0033] Therefore, it is possible to reduce the degradation of the display quality of the display device due to the first and second auxiliary lines for reducing the width of the non-display area.

[0034] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0036] Figure 1 is a perspective view showing a display device according to some embodiments of the present disclosure;

[0037] Figure 2 is a diagram showing some embodiments of the present disclosure Figure 1 A plan view of a display device;

[0038] Figure 3 According to some embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line AA';

[0039] Figure 4 is a diagram showing some embodiments of the present disclosure Figure 2 A layout diagram of area B;

[0040] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 An equivalent circuit diagram of a light-emitting pixel driver;

[0041] Figure 6 is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of a light emitting element and a first transistor, a second transistor, a fourth transistor and a sixth transistor;

[0042] Figure 7 is a diagram showing some embodiments of the present disclosure Figure 3 A plan view of the base;

[0043] Figure 8 is a diagram showing some embodiments of the present disclosure Figure 7 A layout diagram of area B';

[0044] Fig. 9 is a diagram showing some embodiments of the present disclosure Figure 7A layout diagram of area C;

[0045] Fig.10 According to some embodiments of the present disclosure, Figure 8 A cross-sectional view taken along line D-D';

[0046] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 are respectively shown according to some embodiments of the present disclosure Figure 8 Region E, Region F, Region G and Region H and Fig. 9 plan views of parts I and J of the

[0047] Fig.17 and Fig.18 are respectively shown according to some other embodiments of the present disclosure Figure 8 a plan view of area E and area F; and

[0048] Fig.19 , Fig. 20 and Fig.21 are diagrams showing some other embodiments according to the present disclosure. Figure 8 Area E and Area F and Fig. 9 Floor plan of Section I. DETAILED DESCRIPTION

[0049] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0050] Some of the parts not related to the description may not be provided to describe some embodiments of the present disclosure.

[0051] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0052] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "superimposed" or "superimposed" means that the first object can be above, below and / or on the side of the second object, and / or vice versa. In addition, the term "superimposed" may include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-superimposed" may include meanings such as "spaced apart" or "separated" or "offset" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is placed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0053] For ease of description, spatially relative terms such as "below", "under", "below", "above", "on", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, where the device shown in the drawings is flipped, a device that is "below" or "below" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be otherwise oriented, so that the spatially relative terms may be interpreted differently depending on the positioning.

[0054] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "having," "including," and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0055] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate description and explanation thereof. For example, when a "first element" is discussed in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be named in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0056] As used herein, the term "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0057] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or". When expressions such as "one or more (kinds / persons) of ... " and "at least one (kind / person) of ... " are located after a column of elements, the entire column of elements is modified without modifying the individual elements in the column. For example, the expressions "one or more (kinds / persons) of A, B, and C", "at least one (kind / person) of A, B, and C", and "at least one (kind / person) selected from the group consisting of A, B, and C" represent only A, only B, only C, both A and B, both A and C, both B and C, or all of A, B, and C.

[0058] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0059] Hereinafter, some embodiments will be described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view showing a display device according to some embodiments of the present disclosure. Figure 2 is a diagram showing some embodiments of the present disclosure Figure 1 A plan view of a display device. Figure 3 According to some embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line AA'. Figure 4 is a diagram showing some embodiments of the present disclosure Figure 2 Layout diagram of area B.

[0061] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying a moving image or a still image. The display device 100 can be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0062] The display device 100 may be a light-emitting display device such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro-light-emitting display using a micro-light-emitting diode (LED) or a nano-light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto and may be applied to a display device including an organic insulating material, an organic light-emitting material, and / or a metal material.

[0063] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be flexibly formed so that it may be curved, bent, folded, or curled.

[0064] like Figure 1 , Figure 2 and Figure 3 As shown in , the display device 100 includes a substrate 110 .

[0065] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0066] like Figure 2 As shown in FIG, the main area MA may include a display area DA disposed at most of the center thereof and a non-display area NDA disposed around the display area DA.

[0067] In a plan view, the display area DA may have a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. An angle at which the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded (rounded) to have a predetermined curvature, or may be a right angle. The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, an elliptical shape, or any other suitable shape. In addition, the elements of the display device 100 may be defined from a third direction DR3 intersecting the first direction DR1 and the second direction DR2.

[0068] The non-display area NDA may be disposed at an edge of the main area MA to surround the display area DA.

[0069] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA to one side in the second direction DR2 .

[0070] Since a portion of the sub-area SBA is transformed to be bent, another portion of the sub-area SBA may be disposed on the rear surface of the display device 100 .

[0071] Figure 2 and Figure 3 The display device 100 is shown with a portion of the sub-area SBA being in a bent state.

[0072] Reference Figure 3 , the display device 100 according to some embodiments includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0073] The display device 100 according to some embodiments may further include an encapsulation layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0074] In addition, the display device 100 according to some embodiments further includes a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0075] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate, which may be bent, folded, or rolled.

[0076] In some examples, substrate 110 may be formed of an insulating material such as glass.

[0077] The substrate 110 may include a main area MA and a sub area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0078] Figure 4 It is shown Figure 2 Layout diagram of area B.

[0079] Reference Figure 4 , the display area DA of the display device 100 according to some embodiments may include the emission area EA. In addition, the display area DA may further include a non-emission area NEA disposed in a gap between the emission areas EA.

[0080] The light-emitting pixel drivers EPD corresponding to the emission area EA may be arranged in parallel with each other in the display area DA in the first direction DR1 and the second direction DR2. The light-emitting pixel drivers EPD may be electrically connected to the light-emitting elements LE of the element layer 130 disposed in the emission area EA, respectively (see, for example, Figure 5 ).

[0081] The emission area EA may have a rhombus planar shape or a rectangular planar shape. However, this is only an example, and the planar shape of the emission area EA according to some embodiments is not limited to Figure 4 The emission area EA may have a planar shape as shown in FIG, and may have any suitable shape. For example, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular shape or an elliptical shape including curved edges.

[0082] The emission area EA may include a first emission area EA1 emitting a first color light in a predetermined band, a second emission area EA2 emitting a second color light in a band lower than the first color, and a third emission area EA3 emitting a third color light in a band lower than the second color.

[0083] For example, the first color may be red having a wavelength of about 600 nm to about 750 nm, the second color may be green having a wavelength of about 480 nm to about 560 nm, and the third color may be blue having a wavelength of about 370 nm to about 460 nm.

[0084] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0085] The second emission regions EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0086] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in oblique directions DR4 and DR5 intersecting the first direction DR1 and the second direction DR2.

[0087] The pixel PX displaying its own brightness and color may be provided by the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 adjacent to each other among the emission areas EA.

[0088] In other words, the pixel PX may be a basic unit for displaying various suitable colors including white at a predetermined brightness.

[0089] Each of the pixels PX may include at least one of the first emission areas EA1, at least one of the second emission areas EA2, and at least one of the third emission areas EA3 that are adjacent to each other. Therefore, each of the pixels PX may display various suitable colors by mixing the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 that are adjacent to each other.

[0090] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 Equivalent circuit diagram of the light-emitting pixel driver.

[0091] Reference Figure 5 , one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power line VSL.

[0092] That is, the anode electrode 131 of the light emitting element LE (see, for example, Figure 6 ) is electrically connected to the light-emitting pixel driver EPD, the cathode electrode 134 of the light-emitting element LE (see, for example Figure 6 ) may be applied with a second power ELVSS lower than the first power ELVDD.

[0093] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0094] The circuit layer 120 may further include a first power line VDL for transmitting the first power ELVDD, a first initialization power line VIL for transmitting the first initialization power VINT, a second initialization power line VAIL for transmitting the second initialization power VAINT, and a bias power line VBL for transmitting the bias power VBS.

[0095] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0096] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1 , and at least one capacitor PC1 .

[0097] The first transistor T1 and the light emitting element LE are connected in series between the first power ELVDD and the second power ELVSS.

[0098] That is, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0099] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0100] A gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1 .

[0101] That is, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0102] Therefore, the potential of the gate electrode of the first transistor T1 can maintain the voltage charged in the first power line VDL.

[0103] In addition, when the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be the voltage difference between the first power ELVDD and the data signal Vdata.

[0104] At this time, when the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (ie, the gate-source voltage difference) is higher than the threshold voltage, the first transistor T1 may be turned on to generate a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0105] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the driving current of the light emitting element LE.

[0106] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0107] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0108] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of the gate control line GCL.

[0109] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the first initialization power line VIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0110] Each of the third transistor T3 and the fourth transistor T4 may be implemented as an N-type MOSFET.

[0111] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0112] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0113] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the light emitting control line ECL.

[0114] The seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the second initialization power line VAIL. The seventh transistor T7 may be turned on by a bias control signal GB of a bias control line GBL.

[0115] The eighth transistor T8 may be connected between the first electrode of the first transistor T1 and the bias power line VBL.

[0116] The eighth transistor T8 may be turned on by a bias control signal GB of a bias control line GBL.

[0117] Among the first to eighth transistors T1 to T8 , each of the transistors T1 , T2 , and T5 to T8 excluding the third and fourth transistors T3 and T4 may be implemented as a P-type MOSFET.

[0118] That is, although each of the third transistor T3 and the fourth transistor T4 among the first to eighth transistors T1 to T8 included in the light-emitting pixel driver EPD is implemented as an N-type MOSFET, each of the remaining transistors T1, T2 and T5 to T8 except these two transistors can be implemented as a P-type MOSFET.

[0119] Therefore, according to some embodiments, each of the third transistor T3 and the fourth transistor T4 may include a channel portion, a source portion, and a drain portion formed of a semiconductor layer different from those of the other transistors T1 , T2 , and T5 to T8 .

[0120] Figure 6 is a diagram showing some embodiments of the present disclosure Figure 5 A cross-sectional view of a light emitting element and a first transistor, a second transistor, a fourth transistor and a sixth transistor.

[0121] Reference Figure 6 According to some embodiments, the circuit layer 120 of the display device 100 may include: a buffer layer 121, covering the first light blocking layer LB1 on the substrate 110; first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6, which are arranged on the buffer layer 121; a first gate insulating layer 122, covering the first semiconductor layers CH1, S1, D1, CH2, S2, D2, CH6, S6 and D6; first gate conductive layers G1, G2 and G6, which are arranged on the first gate insulating layer 122; a second gate insulating layer 123, covering the first gate conductive layers G1, G2 and G6; second gate conductive layers CPE and LB2, which are arranged on the second gate insulating layer 123; a first interlayer insulating layer 124, covering the second gate conductive layers layer CPE and LB2; second semiconductor layers CH4, S4 and D4 are arranged on the first interlayer insulating layer 124; a third gate insulating layer 125 covers the second semiconductor layers CH4, S4 and D4; a third gate conductive layer G4 is arranged on the third gate insulating layer 125; a second interlayer insulating layer 126 covers the third gate conductive layer G4; a first source-drain conductive layer ANCE1, DCE, GCNE and VIL are arranged on the second interlayer insulating layer 126; a first planarizing layer 127 covers the first source-drain conductive layer ANCE1, DCE, GCNE and VIL; a second source-drain conductive layer ANCE2 and DL are arranged on the first planarizing layer 127; and a second planarizing layer 128 covers the second source-drain conductive layer ANCE2 and DL.

[0122] The first transistor T1 may include a channel portion CH1 , a source portion S1 , and a drain portion D1 formed of a first semiconductor layer on the buffer layer 121 , and a gate electrode G1 disposed in a first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH1 .

[0123] A channel portion CH1 of the first transistor T1 may overlap the first light blocking layer LB1 on the substrate 110 .

[0124] The second transistor T2 may include a channel portion CH2 , a source portion S2 , and a drain portion D2 formed of a first semiconductor layer on the buffer layer 121 , and a gate electrode G2 disposed in the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0125] The sixth transistor T6 may include a channel portion CH6 , a source portion S6 , and a drain portion D6 formed of the first semiconductor layer on the buffer layer 121 , and a gate electrode G6 disposed in the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0126] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through the data connection electrode DCE.

[0127] The data connection electrode DCE can be set in the first source-drain conductive layer on the second interlayer insulating layer 126, and can be electrically connected to the source portion S2 of the second transistor T2 through the data connection auxiliary hole DCAH penetrating the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123 and the first gate insulating layer 122.

[0128] The data line DL may be disposed in the second source-drain conductive layer on the first planarization layer 127 , and may be electrically connected to the data connection electrode DCE through a data connection hole DCH3 penetrating the first planarization layer 127 .

[0129] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1 .

[0130] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6 .

[0131] The drain portion D6 of the sixth transistor T6 may be electrically connected to the anode electrode 131 through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2 .

[0132] The first anode connection electrode ANCE1 can be set in the first source-drain conductive layer on the second interlayer insulating layer 126, and is electrically connected to the drain portion D6 of the sixth transistor T6 through the first anode connection hole ANCH1 penetrating the second interlayer insulating layer 126, the third gate insulating layer 125, the first interlayer insulating layer 124, the second gate insulating layer 123 and the first gate insulating layer 122.

[0133] The second anode connection electrode ANCE2 may be disposed in the second source-drain conductive layer on the first planarization layer 127 and electrically connected to the first anode connection electrode ANCE1 through a second anode connection hole ANCH2 penetrating the first planarization layer 127 .

[0134] The anode electrode 131 may be disposed on the second planarization layer 128 , and may be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3 penetrating the second planarization layer 128 .

[0135] The first capacitor PC1 may be provided by an overlapped region between a capacitor electrode CPE in a second gate conductive layer disposed on the second gate insulating layer 123 and a gate electrode G1 of the first transistor T1 .

[0136] The fourth transistor T4 may include: a channel portion CH4, a source portion S4 and a drain portion D4, formed by the second semiconductor layer on the first interlayer insulating layer 124; a gate electrode G4, disposed in the third gate conductive layer on the third gate insulating layer 125; and a gate auxiliary electrode G4' disposed in the second gate conductive layer on the second gate insulating layer 123.

[0137] Each of the gate electrode G4 and the gate auxiliary electrode G4 ′ may overlap the channel portion CH4 of the fourth transistor T4 .

[0138] The source portion S4 of the fourth transistor T4 may be electrically connected to the first initialization power line VIL on the second interlayer insulating layer 126 through a first initialization power hole VICH penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0139] The drain portion D4 of the fourth transistor T4 may be electrically connected to the gate electrode G1 of the first transistor T1 through the gate connection electrode GCNE disposed in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0140] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate connection hole GCH1 penetrating the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0141] The gate connection electrode GCNE may be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate connection hole GCH2 penetrating the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , and the second gate insulating layer 123 .

[0142] Since the third transistor T3 has a structure similar to that of the fourth transistor T4 , and the fifth and seventh transistors T5 and T7 have structures similar to those of the second and sixth transistors T2 and T6 , redundant descriptions may be omitted below.

[0143] The circuit layer 120 of the display device 100 according to some embodiments may include a first auxiliary line ASL1 (see, for example, Figure 8 ) and a second auxiliary line ASL2 (see e.g. Figure 8 ) to reduce the width of the non-display area NDA.

[0144] Figure 7 is a diagram showing some embodiments of the present disclosure Figure 3 A plan view of the base.

[0145] Reference Figure 7 , the substrate 110 of the display device 100 according to some embodiments includes a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0146] The main area MA may include a display area DA disposed at a large part of the center and a non-display area NDA disposed at the periphery to surround the display area DA.

[0147] The display area DA may include a bypass area DEA disposed at one side adjacent to the sub area SBA and a general area GA disposed in the remaining area except the bypass area DEA.

[0148] The bypass area DEA may include: a bypass middle area MDDA, which is arranged at the center in the first direction DR1; a first bypass side area SDA1, which is parallel to the bypass middle area MDDA in the first direction DR1 and contacts the non-display area NDA; and a second bypass side area SDA2, which is arranged between the bypass middle area MDDA and the first bypass side area SDA1.

[0149] The first bypass side area SDA1 may be disposed adjacent to a bending corner of the substrate 110 compared to the bypass middle area MDDA and the second bypass side area SDA2 .

[0150] The first and second bypass side areas SDA1 and SDA2 may be disposed between the bypass middle area MDDA and the non-display area NDA at both sides of the bypass middle area MDDA in the first direction DR1 .

[0151] The general area GA may include: a general middle area GMA, a bypass middle area MDDA connected to the bypass area DEA in the second direction DR2; a first general side area GSA1, a first bypass side area SDA1 connected to the bypass area DEA in the second direction DR2; and a second general side area GSA2, a second bypass side area SDA2 connected to the bypass area DEA in the second direction DR2.

[0152] The non-display area NDA may include a gate driving circuit area GDRA where a gate driving circuit is disposed.

[0153] The gate driving circuit area GDRA may be disposed in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0154] The gate drive circuit of the gate drive circuit area GDRA can sequentially transmit the gate signal to the gate line. Here, the gate line may include: a scan write line GWL (see, for example Figure 5 ), transmits a scan write signal GW (see for example Figure 5 ); scan initialization line GIL (see e.g. Figure 5 ), transmission scanning initialization signal GI (see for example Figure 5 ); gate control line GCL (see for example Figure 5 ), transmits a gate control signal GC (see for example Figure 5 ); bias control line GBL (see e.g. Figure 5 ), transmission bias control signal GB (see e.g. Figure 5 ); and emission control line ECL (see e.g. Figure 5 ), transmits a transmission control signal EC (see e.g. Figure 5 ).

[0155] The sub-region SBA may include a bending region BA transformed into a bent shape, a first sub-region SB1 disposed between one side of the bending region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bending region BA.

[0156] When the bending area BA is transformed into a bent shape, the second sub-area SB2 is disposed under the substrate 110 and overlaps the main area MA.

[0157] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0158] A signal pad (or referred to as “pad” or “soldering pad”) SPD coupled to the circuit board 300 may be disposed at one edge of the second sub-region SB2 . In addition, driving chips 400 and 500 may be disposed on the circuit board 300 .

[0159] Figure 8 It is shown Figure 7 Layout diagram of area B'. Fig. 9 is a diagram showing some embodiments of the present disclosure Figure 7 Layout diagram of area C. Fig.10 According to some embodiments of the present disclosure, Figure 8 A cross-sectional view taken along line D-D'.

[0160] Reference Figure 8 and Fig. 9 According to some embodiments, the circuit layer 120 of the display device 100 may include: light-emitting pixel drivers EPD, respectively electrically connected to the light-emitting elements LE of the element layer 130; photosensitive pixel drivers (not shown), respectively electrically connected to the photosensitive elements (not shown) of the element layer 130; data lines DL, electrically connected to the light-emitting pixel drivers EPD and transmitting data signals Vdata; first auxiliary lines ASL1, extending in a first direction DR1 crossing the data lines DL; second auxiliary lines ASL2, respectively extending parallel to the data lines DL and paired with the data lines DL.

[0161] The data line DL and the second auxiliary line ASL2 may extend in the second direction DR2.

[0162] Among the data lines DL, two data lines DL adjacent to each other in the first direction DR1 may be disposed between two second auxiliary lines ASL2 paired therewith to face each other in the first direction DR1.

[0163] According to some embodiments, the first auxiliary lines ASL1 may overlap the light emitting pixel driver EPD of the display area DA. That is, the number of the first auxiliary lines ASL1 may be equal to the number of columns of the emission area EA in the first direction DR1.

[0164] According to some embodiments, the circuit layer 120 further includes a data supply line DSPL disposed in the non-display area NDA and electrically connected to the display driving circuit 200 and the data line DL.

[0165] The data lines DL may include a first data line DL1 disposed in the first bypass side area SDA1 and a second data line DL2 disposed in the second bypass side area SDA2.

[0166] The first auxiliary line ASL1 may include a first bypass auxiliary line TASL1 electrically connected to the first data line DL1 of the first bypass side area SDA1.

[0167] The second auxiliary line ASL2 may include a second bypass auxiliary line TASL2 paired with the second data line DL2 of the second bypass side area SDA2 and electrically connected to the first bypass auxiliary line TASL1 .

[0168] The data supply lines DSPL may include a first data supply line DSPL1 transmitting a data signal of the first data line DL1 and a second data supply line DSPL2 transmitting a data signal of the second data line DL2 .

[0169] According to some embodiments, the data supply line DSPL may extend to the second bypass side area SDA2 and the bypass middle area MDDA.

[0170] Therefore, the first data supply line DSPL1 may extend to the second bypass auxiliary line TASL2 of the second bypass side area SDA2 and may be electrically connected to the first data line DL1 through the second bypass auxiliary line TASL2 and the first bypass auxiliary line TASL1.

[0171] The second data supply line DSPL2 may extend to the second bypass side area SDA2 and may be directly electrically connected to the second data line DL2 .

[0172] In this way, since the first data supply line DSPL1 does not extend to the first data line DL1 of the first bypass side area SDA1 but extends to the second bypass auxiliary line TASL2 of the second bypass side area SDA2, the extension length of the first data supply line DSPL1 can be shortened. As a result, the width of the area for arranging the data supply line DSPL can be reduced, so that the width of the non-display area NDA can be reduced.

[0173] In addition, since the data supply line DSPL is not disposed in a portion of the non-display area NDA between the bent corner of the substrate 110 and the first bypass side area SDA1 , the width of the non-display area NDA may be further reduced.

[0174] The data lines DL may further include a third data line DL3 disposed in the bypass middle area MDDA. In addition, the data supply line DSPL may further include a third data supply line DSPL3 transmitting a data signal of the third data line DL3.

[0175] The third data supply line DSPL3 may extend to the bypass middle area MDDA and may be directly electrically connected to the third data line DL3 .

[0176] The first bypass auxiliary line TASL1 extends from the second bypass auxiliary line TASL2 to the first data line DL1.

[0177] The second bypass auxiliary line TASL2 extends from the first data supply line DSPL1 of the non-display area NDA to the first bypass auxiliary line TASL1.

[0178] In this way, since the first and second bypass auxiliary lines TASL1 and TASL2 are confinedly arranged in the bypass area DEA, the ends of the first and second bypass auxiliary lines TASL1 and TASL2 are regularly arranged. Therefore, the first and second bypass auxiliary lines TASL1 and TASL2 may become more visible.

[0179] To prevent this, the first auxiliary line ASL1 may include not only the first bypass auxiliary line TASL1 but also the second power assist horizontal line VSAHL. In addition, the second auxiliary line ASL2 may include not only the second bypass auxiliary line TASL2 but also the second power assist vertical line VSAVL.

[0180] Two of the second power auxiliary horizontal lines VSAHL may extend from both ends of the first bypass auxiliary line TASL1 to the non-display area NDA.

[0181] One of the second power auxiliary vertical lines VSAVL may extend from one end of the second bypass auxiliary line TASL2 to the non-display area NDA in a direction away from the sub-area SBA.

[0182] Therefore, a portion of each second data line DL2 is paired with the second bypass auxiliary line TASL2, and another portion of the second data line DL2 may be paired with one second power auxiliary vertical line VSAVL extending from one end of the second bypass auxiliary line TASL2.

[0183] Since the second bypass auxiliary line TASL2 is disposed only in the second bypass side area SDA2 , the first data line DL1 of the first bypass side area SDA1 may be paired with the second power auxiliary vertical line VSAVL.

[0184] The third data line DL3 bypassing the middle area MDDA may be paired with the second power auxiliary vertical line VSAVL.

[0185] like Fig. 9 As shown in FIG. 1 , among the first auxiliary lines ASL1 , the first bypass auxiliary line TASL1 may be disposed in the first and second bypass side areas SDA1 and SDA2 of the bypass area DEA, and the second power auxiliary horizontal line VSAHL may be disposed in the bypass middle area MDDA of the bypass area DEA.

[0186] In addition, if Fig.10 As shown in FIG. 1 , the second power assist horizontal line VSAHL and the second power assist vertical line VSAVL may be disposed in the general area GA.

[0187] like Figure 8As shown in FIG. 1 , the circuit layer 120 may further include a first power line VDSPL and a second power line VSSPL that transmit a first power ELVDD and a second power ELVSS for driving the light emitting element LE, respectively.

[0188] The first power line VDSPL and the second power line VSSPL may be disposed in the non-display area NDA and may extend to the sub-area SBA.

[0189] The first power line VDSPL may be electrically connected to a first power pad for transmitting the first power ELVDD among the signal pads SPD disposed in the second sub-region SB2 .

[0190] The second power line VSSPL may be electrically connected to a second power pad for transmitting the second power ELVSS among the signal pads SPD provided in the second sub-region SB2 .

[0191] The second power auxiliary horizontal line VSAHL may be electrically connected to the second power supply line VSSPL.

[0192] The second power assist vertical line VSAVL may be electrically connected to the second power assist horizontal line VSAHL and the second power supply line VSSPL.

[0193] According to some embodiments, the circuit layer 120 further includes a first power line VDL electrically connected between the light emitting pixel driver EPD and the first power line VDSPL.

[0194] The first power line VDL may be disposed between two second auxiliary lines ASL2 adjacent to each other in the first direction DR1.

[0195] Reference Fig.10 The data line DL, the second auxiliary line ASL2, and the first power line VDL may be disposed on the first planarization layer 127 covering the first auxiliary line ASL1.

[0196] That is, the first auxiliary line ASL1 may be disposed in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0197] The data line DL, the second auxiliary line ASL2 , and the first power line VDL may be disposed in the second source-drain conductive layer on the first planarization layer 127 .

[0198] The second bypass auxiliary line TASL2 may be electrically connected to the first bypass auxiliary line TASL1 through a first auxiliary connection hole ASCH1 penetrating the first planarization layer 127 .

[0199] The first data line DL1 may be electrically connected to the first bypass auxiliary line TASL1 through a second auxiliary connection hole ASCH2 penetrating the first planarization layer 127 .

[0200] According to some embodiments, in order to prevent signals of lines adjacent to the first bypass auxiliary line TASL1 from being distorted due to differential coupling (e.g., poor signal coupling) with the data signal of the first bypass auxiliary line TASL1 extending in the first direction DR1, the first bypass auxiliary line TASL1 overlaps the first initialization power line VIL.

[0201] According to some embodiments, the first auxiliary line ASL1 including the first bypass auxiliary line TASL1 overlaps the first initialization power line VIL. With this configuration, the influence of the data signal of the first bypass auxiliary line TASL1 on the gate control signal GC of the gate control line GCL or the scan initialization signal GI of the scan initialization line GIL can be reduced.

[0202] In order to sequentially arrange the first bypass auxiliary lines TASL1 in the bypass area DEA, the first data lines DL1 of the first bypass side area SDA1 may be electrically connected to the first bypass auxiliary lines TASL1 having a longer length since they are positioned away from the second bypass side area SDA2. Therefore, since the ends of the first bypass auxiliary lines TASL1 are arranged in the oblique direction, the first bypass auxiliary lines TASL1 may become more visible.

[0203] In addition, since the auxiliary connection holes ASCH for electrically connecting each of the data line DL and the second auxiliary line ASL2 to the first auxiliary line ASL1 penetrate the first planarization layer 127 , they may be arranged with a relatively wide width.

[0204] Since the auxiliary connection hole ASCH is disposed at each of the end portions of the first bypass auxiliary line TASL1 , the first bypass auxiliary line TASL1 may become more visible due to the arrangement of the auxiliary connection hole ASCH.

[0205] Hereinafter, various embodiments for reducing the visibility of the first bypass auxiliary line TASL1 will be described.

[0206] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 are respectively shown according to some embodiments of the present disclosure Figure 8 Region E, Region F, Region G and Region H and Fig. 9 Plan views of Section I and Section J.

[0207] Reference Fig.11According to some embodiments, the circuit layer 120 of the display device 100 may also include: a first connection auxiliary electrode ASCE1, which is adjacent to an intersection (e.g., a junction) between the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2 and is spaced apart from the first bypass auxiliary line TASL1; a first connection line CL1, which connects the first bypass auxiliary line TASL1 to the first connection auxiliary electrode ASCE1; and a first auxiliary protruding electrode ASPE1, which protrudes from the second bypass auxiliary line TASL2 and is electrically connected to the first connection auxiliary electrode ASCE1 through an auxiliary connection hole ASCH.

[0208] The first connection auxiliary electrode ASCE1 and the first connection line CL1 may be disposed at (eg, in) the same layer as the first bypass auxiliary line TASL1 , ie, in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0209] The first connection auxiliary electrode ASCE1 may face one side of the first bypass auxiliary line TASL1 in the second direction DR2.

[0210] The first bypass auxiliary line TASL1 extends in the first direction DR1, and may include a bent shape to surround a portion of an edge of the first connection auxiliary electrode ASCE1.

[0211] The first connection line CL1 may extend between the first bypass auxiliary line TASL1 and the first connection auxiliary electrode ASCE1.

[0212] As an example, the first connection line CL1 may extend in the second direction DR2. However, this is only an example, and the extending direction of the first connection line CL1 is not limited to Fig.11 Directions shown in .

[0213] The first connection auxiliary electrode ASCE1 has an island shape (eg, a rectangular shape) spaced apart from the first bypass auxiliary line TASL1 and may be electrically connected to the first bypass auxiliary line TASL1 through a first connection line CL1.

[0214] The first auxiliary protrusion electrode ASPE1 may protrude in the first direction DR1 from the second bypass auxiliary line TASL2 extending in the second direction DR2 .

[0215] The first auxiliary protrusion electrode ASPE1 may be electrically connected to the first connection auxiliary electrode ASCE1 through the auxiliary connection hole ASCH.

[0216] Therefore, the second bypass auxiliary line TASL2 may be electrically connected to the first bypass auxiliary line TASL1 through the first auxiliary protrusion electrode ASPE1 , the first connection auxiliary electrode ASCE1 , and the first connection line CL1 .

[0217] like Fig.12 , Fig.14 , Fig.15 and Fig.16 As shown in, according to some embodiments, the circuit layer 120 also includes: a second connection auxiliary electrode ASCE2, adjacent to an intersection (e.g., a junction) between the second power assist horizontal line VSAHL and the second power assist vertical line VSAVL; and a second auxiliary protruding electrode ASPE2, protruding from the second power assist vertical line VSAVL and electrically connected to the second connection auxiliary electrode ASCE2 through auxiliary connection holes ASCH, respectively.

[0218] The second connection auxiliary electrode ASCE2 may be disposed at (eg, in) the same layer as the first auxiliary line ASL1 including the second power auxiliary horizontal line VSAHL, that is, in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0219] The second connection assisting electrode ASCE2 may face one side of the second power assisting horizontal line VSAHL in the second direction DR2 .

[0220] According to some embodiments, the second connection auxiliary electrode ASCE2 has an island shape (eg, a rectangular shape) spaced apart from the second power auxiliary horizontal line VSAHL.

[0221] Therefore, even if the second auxiliary protruding electrode ASPE2 protruding from the second power assisting vertical line VSAVL is electrically connected to the second connection auxiliary electrode ASCE2 through the auxiliary connection hole ASCH, the electrical connection between the second power assisting horizontal line VSAHL and the second power assisting vertical line VSAVL cannot be achieved only through the second connection auxiliary electrode ASCE2 and the second auxiliary protruding electrode ASPE2.

[0222] As above Figure 6 As described above, the second transistor T2 of the light emitting pixel driver EPD may be electrically connected to the data line DL through the data connection electrode DCE.

[0223] like Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 As shown in FIG. 1 , according to some embodiments, the data connection electrode DCE is connected to the data line DL and the first auxiliary line (in Figure 8 The first auxiliary line ASL1 may be adjacent to a cross point (eg, a junction point) between the first auxiliary line ASL1 and the second auxiliary line ASL2.

[0224] In addition, the data protruding electrodes DPE protruding from the data lines DL may be electrically connected to the data connection electrodes DCE through the data connection holes DCH, respectively.

[0225] That is, according to some embodiments, the circuit layer 120 may include: a data connection electrode DCE, and a first auxiliary line (in Figure 8 A cross point (eg, a junction point) between the data lines ASL1 including TASL1 and VSAHL and spaced apart from the first auxiliary line ASL1; and a data protruding electrode DPE protruding from the data lines DL and electrically connected to the data connection electrodes DCE through the data connection holes DCH, respectively.

[0226] The data link electrode DCE may face the other side (eg, the opposite side) of the first auxiliary line ASL1 including the first bypass auxiliary line TASL1 and the second power auxiliary horizontal line VSAHL in the second direction DR2 .

[0227] like Fig.12 As shown in , the circuit layer 120 according to some embodiments also includes a second connection line CL2 that connects a data connection electrode DCE among the data connection electrodes DCE adjacent to an intersection (e.g., a junction) between the first data line DL1 and the first bypass auxiliary line TASL1 to the first bypass auxiliary line TASL1.

[0228] The second connection line CL2 may be disposed at (eg, in) the same layer as the first bypass auxiliary line TASL1 and the data link electrode DCE, ie, in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0229] The second link line CL2 may extend between the first bypass auxiliary line TASL1 and one data link electrode DCE.

[0230] For example, the second connection line CL2 may extend in the second direction DR2. However, this is only an example, and the extending direction of the second connection line CL2 is not limited to Fig.12 Directions shown in .

[0231] One data link electrode DCE adjacent to a crossing point (eg, a junction point) between the first data line DL1 and the first bypass auxiliary line TASL1 may be electrically connected to the first bypass auxiliary line TASL1 through a second connection line CL2 .

[0232] One digital protrusion electrode DPE overlapped with one data link electrode DCE adjacent to a crossing point (eg, a junction point) between the first data line DL1 and the first bypass auxiliary line TASL1 may protrude from the first data line DL1 in the first direction DR1.

[0233] One data protruding electrode DPE may be electrically connected to one data connection electrode DCE through the data connection hole DCH.

[0234] Therefore, the first data line DL1 may be electrically connected to the first bypass auxiliary line TASL1 through one data protruding electrode DPE, one data link electrode DCE, and the second link line CL2.

[0235] like Fig.12 and Fig.13 As shown in, the circuit layer 120 according to some embodiments also includes: a third connection auxiliary electrode ASCE3, adjacent to an intersection (e.g., a junction) between the second power auxiliary vertical line VSAVL and the first bypass auxiliary line TASL1; and a third auxiliary protruding electrode ASPE3, protruding from the second power auxiliary vertical line VSAVL and electrically connected to the third connection auxiliary electrode ASCE3 through auxiliary connection holes ASCH, respectively.

[0236] The third connection auxiliary electrode ASCE3 may be disposed at (eg, in) the same layer as the first bypass auxiliary line TASL1 , ie, in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0237] The third connection auxiliary electrode ASCE3 may face one side of the first bypass auxiliary line TASL1 in the second direction DR2.

[0238] According to some embodiments, each of the third connection auxiliary electrodes ASCE3 has an island shape (eg, a rectangular shape) spaced apart from the first bypass auxiliary line TASL1 .

[0239] Therefore, even if the third auxiliary protruding electrode ASPE3 protruding from the second power assisting vertical line VSAVL is electrically connected to the third connection assisting electrode ASCE3 through the auxiliary connection hole ASCH, the electrical connection between the first bypass auxiliary line TASL1 and the second power assisting vertical line VSAVL is achieved through both the third connection assisting electrode ASCE3 and the third auxiliary protruding electrode ASPE3.

[0240] In addition, if Fig.11As shown in, according to some embodiments, the circuit layer 120 also includes: a fourth connection auxiliary electrode ASCE4, adjacent to an intersection (e.g., a junction) between the second bypass auxiliary line TASL2 and the second power auxiliary horizontal line VSAHL; and a fourth auxiliary protruding electrode ASPE4, protruding from the second power auxiliary horizontal line VSAHL and electrically connected to the fourth connection auxiliary electrode ASCE4 through auxiliary connection holes ASCH, respectively.

[0241] The fourth connection assisting electrode ASCE4 may be disposed at (eg, in) the same layer as the second power assisting horizontal line VSAHL, ie, in the first source-drain conductive layer on the second interlayer insulating layer 126 .

[0242] The fourth connection auxiliary electrode ASCE4 may face one side of the second power auxiliary horizontal line VSAHL in the second direction DR2 .

[0243] According to some embodiments, each of the fourth connection auxiliary electrodes ASCE4 has an island shape (eg, a rectangular shape) spaced apart from the second power auxiliary horizontal line VSAHL.

[0244] Therefore, even if the fourth auxiliary protruding electrode ASPE4 protruding from the second bypass auxiliary line TASL2 is electrically connected to the fourth connection auxiliary electrode ASCE4 through the auxiliary connection hole ASCH, the electrical connection between the second power auxiliary horizontal line VSAHL and the second bypass auxiliary line TASL2 is achieved through both the fourth connection auxiliary electrode ASCE4 and the fourth auxiliary protruding electrode ASPE4.

[0245] A third connection line CL3 (see, for example, FIG. 4 ) for electrically connecting the second power assist horizontal line VSAHL to the second power assist vertical line VSAVL. Fig.15 and Fig.16 ) can be set in the general area GA.

[0246] That is, in the general area GA, one of the second power assist horizontal lines VSAHL may be electrically connected to at least one of the second power assist vertical lines VSAVL.

[0247] like Fig.15 and Fig.16 As shown in, according to some embodiments, the circuit layer 120 also includes at least one third connection line CL3, which connects at least one second connection auxiliary electrode ASCE2 adjacent to an intersection (e.g., a junction) between a second power auxiliary horizontal line VSAHL and at least one second power auxiliary vertical line VSAVL to a second power auxiliary horizontal line VSAHL.

[0248] Therefore, at least one second power assisting vertical line VSAVL can be electrically connected to a second power assisting horizontal line VSAHL through at least one auxiliary protruding electrode ASPE2, at least one second connection auxiliary electrode ASCE2 and at least one third connection line CL3, wherein the at least one auxiliary protruding electrode ASPE2 protrudes from the at least one second power assisting vertical line VSAVL and overlaps with the at least one second connection auxiliary electrode ASCE2.

[0249] As described above, according to some embodiments, the circuit layer 120 includes: a connecting auxiliary electrode ASCE, which is adjacent to an intersection (e.g., a junction) between the first auxiliary line ASL1 and the second auxiliary line ASL2 and is spaced apart from the first auxiliary line ASL1; and an auxiliary protruding electrode ASPE, which protrudes from the second auxiliary line ASL2 and is electrically connected to the connecting auxiliary electrode ASCE through auxiliary connection holes ASCH, respectively.

[0250] In addition, according to some embodiments, the circuit layer 120 also includes: a data connection electrode DCE, which is adjacent to an intersection (e.g., a junction) between the data line DL and the first auxiliary line ASL1 and is spaced apart from the first auxiliary line ASL1 and the connection auxiliary electrode ASCE; and a data protruding electrode DPE, which protrudes from the data line DL and is electrically connected to the data connection electrode DCE through the data connection holes DCH, respectively.

[0251] The connection auxiliary electrode ASCE may face one side of the first auxiliary line ASL1 in the second direction DR2 , and the data link electrode DCE may face the other side (eg, opposite sides) of the first auxiliary line ASL1 in the second direction DR2 .

[0252] That is, the first auxiliary line ASL1 may be disposed between the connection auxiliary electrode ASCE and the data link electrode DCE.

[0253] In addition, because the connection auxiliary electrode ASCE is adjacent to the second auxiliary line ASL2 and the data link electrode DCE is adjacent to the data line DL, the connection auxiliary electrode ASCE and the data link electrode DCE may be spaced apart from each other in an oblique direction crossing the first and second directions DR1 and DR2.

[0254] The connection auxiliary electrode ASCE may include: a first connection auxiliary electrode ASCE1, which is adjacent to an intersection (e.g., an intersection) between the second bypass auxiliary line TASL2 and the first bypass auxiliary line TASL1; a second connection auxiliary electrode ASCE2, which is adjacent to an intersection (e.g., an intersection) between the second power assist vertical line VSAVL and the second power assist horizontal line VSAHL; and a third connection auxiliary electrode ASCE3, which is adjacent to an intersection (e.g., an intersection) between the second power assist vertical line VSAVL and the first bypass auxiliary line TASL1.

[0255] According to some embodiments, since all of the connection auxiliary electrodes ASCE disposed in the display area DA overlap with the corresponding auxiliary connection holes ASCH, the visibility due to the arrangement of the auxiliary connection holes ASCH is greatly reduced (e.g., completely eliminated). Therefore, it is possible to prevent the visibility of the end of the first bypass auxiliary line TASL1 from increasing due to the arrangement of the auxiliary connection holes ASCH.

[0256] Furthermore, according to some embodiments, each of the connection auxiliary electrodes ASCE has an island shape (eg, a rectangular shape) spaced apart from the first auxiliary line ASL1. Therefore, even if all of the connection auxiliary electrodes ASCE overlap the corresponding auxiliary connection holes ASCH, this does not affect electrical connection.

[0257] like Fig.11 , Fig.12 , Fig.15 and Fig.16 As shown in, according to some embodiments, for the purpose of selective electrical connection, the circuit layer 120 also includes: a first connecting line CL1, used to electrically connect the second bypass auxiliary line TASL2 to the first bypass auxiliary line TASL1; a second connecting line CL2, used to electrically connect the first data line DL1 to the first bypass auxiliary line TASL1; and a third connecting line CL3, used to electrically connect the second power auxiliary vertical line VSAVL to the second power auxiliary horizontal line VSAHL.

[0258] Fig.17 and Fig.18 are respectively shown according to some other embodiments of the present disclosure Figure 8 Plan view of area E and area F.

[0259] like Fig.17 and Fig.18As shown in FIG. 1 , except that the first connection auxiliary electrode ASCE1′ adjacent to the intersection (e.g., intersection) between the second bypass auxiliary line TASL2 and the first bypass auxiliary line TASL1 and the third connection auxiliary electrode ASCE3′ adjacent to the intersection (e.g., intersection) between the second power auxiliary vertical line VSAVL and the first bypass auxiliary line TASL1 protrude from the first bypass auxiliary line TASL1, and the third connection auxiliary electrode ASCE3′ does not overlap with the auxiliary connection hole ASCH, the circuit layer 120 of the display device 100 according to some other embodiments is not overlapped with the auxiliary connection hole ASCH. Figures 11 to 16 The circuit layer 120 of the display device 100 of the embodiment shown in FIG. 1 is substantially the same. As such, a redundant description of the circuit layer 120 may not be repeated below.

[0260] According to some other embodiments, the first connection auxiliary electrode ASCE1' and the third connection auxiliary electrode ASCE3' are disposed to protrude from the first bypass auxiliary line TASL1 in the second direction DR2. That is, since the first connection auxiliary electrode ASCE1' is formed as a part of the first bypass auxiliary line TASL1, the first connection line CL1 for electrically connecting the first connection auxiliary electrode ASCE1' to the first bypass auxiliary line TASL1 is not required.

[0261] In addition, since the first connection auxiliary electrode ASCE1' and the third connection auxiliary electrode ASCE3' protrude from the first bypass auxiliary line TASL1, if the first connection auxiliary electrode ASCE1' and the third connection auxiliary electrode ASCE3' overlap with the auxiliary connection hole ASCH, selective electrical connection with the first bypass auxiliary line TASL1 is impossible. As a solution, according to some other embodiments, by setting the auxiliary connection hole ASCH only in the first connection auxiliary electrode ASCE1' among the first connection auxiliary electrode ASCE1' and the third connection auxiliary electrode ASCE3', the electrical connection between the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2 is selectively achieved.

[0262] Fig.19 , Fig. 20 and Fig.21 are diagrams showing some other embodiments according to the present disclosure. Figure 8 Area E and Area F and Fig. 9 Floor plan of Section I.

[0263] Reference Fig.19 , Fig. 20 and Fig.21In addition to the second connection auxiliary electrode ASCE2′ adjacent to the intersection (e.g., intersection) between the second power assist horizontal line VSAHL and the second power assist vertical line VSAVL and the fourth connection auxiliary electrode ASCE4′ adjacent to the intersection (e.g., intersection) between the second power assist horizontal line VSAHL and the second bypass auxiliary line TASL2 protruding from the second power assist horizontal line VSAHL, the circuit layer 120 of the display device 100 according to still other embodiments is connected to the circuit layer 120 of the display device 100. Figures 11 to 16 The circuit layer 120 of the display device 100 of the embodiment shown in FIG. 1 is substantially the same. As such, the description of the circuit layer 120 may not be repeated below.

[0264] According to still other embodiments, the second connection auxiliary electrode ASCE2' and the fourth connection auxiliary electrode ASCE4' are arranged to protrude from the second power assist horizontal line VSAHL in the second direction DR2. That is, because the second connection auxiliary electrode ASCE2' and the fourth connection auxiliary electrode ASCE4' are formed as a part of the second power assist horizontal line VSAHL, the third connection line CL3 for electrically connecting the second power assist horizontal line VSAHL and the second power assist vertical line VSAVL can be omitted (for example, the third connection line CL3 for electrically connecting the second power assist horizontal line VSAHL and the second power assist vertical line VSAVL is not necessary).

[0265] Furthermore, since the second and fourth connection auxiliary electrodes ASCE2 ′ and ASCE4 ′ protrude from the second power assisting horizontal line VSAHL, if the second and fourth connection auxiliary electrodes ASCE2 ′ and ASCE4 ′ overlap the auxiliary connection hole ASCH, selective electrical connection with the second power assisting horizontal line VSAHL is impossible.

[0266] As a solution, according to still other embodiments, by providing auxiliary connection holes ASCH only in some of the second connection auxiliary electrodes ASCE2' among the second connection auxiliary electrodes ASCE2' and the fourth connection auxiliary electrodes ASCE4', the electrical connection between the second power auxiliary horizontal line VSAHL and the second power auxiliary vertical line VSAVL is selectively implemented. For example, some of the second connection auxiliary electrodes ASCE2' overlapped with the auxiliary connection holes ASCH may be provided in the general area GA.

[0267] It should be understood that the embodiments described herein should be considered in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display device, the display device include: a substrate including a display area in which an emission area is arranged and a non-display area around the display area; a circuit layer on the substrate; as well as an element layer, on the circuit layer, and including a light emitting element located in the emission region, The circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting element; a data line electrically connected to the light-emitting pixel driver; a first auxiliary line extending in a first direction intersecting the data line and located in the light-emitting pixel driver; and a second auxiliary line extending in a second direction intersecting the first direction and parallel to the data line, the second auxiliary line being paired with a corresponding one of the data lines. The first auxiliary line includes a first bypass auxiliary line electrically connected to a first data line among the data lines, and the first data line is adjacent to the non-display area in the first direction. The second auxiliary line includes a second bypass auxiliary line paired with a second data line among the data lines, and the second data line is farther away from the non-display area than the first data line in the first direction. Among them, the circuit layer also includes: a first connecting auxiliary electrode, adjacent to the intersection between the first bypass auxiliary line and the second bypass auxiliary line, and spaced apart from the first bypass auxiliary line; a first connecting line, connecting the first bypass auxiliary line to the first connecting auxiliary electrode; and a first auxiliary protruding electrode, protruding from the second bypass auxiliary line and electrically connected to the first connecting auxiliary electrode through one of the auxiliary connection holes.

2. The display device according to claim 1, in, The circuit layer also includes: a data link electrode adjacent to a crossing point between the data line and the first auxiliary line and spaced apart from the first auxiliary line; and A data protrusion electrode protrudes from the data line and is electrically connected to the data connection electrode through a data connection hole.

3. The display device according to claim 2, in, The circuit layer further includes a second connection line connecting one of the data connection electrodes adjacent to a crossing point between the first data line and the first bypass auxiliary line to the first bypass auxiliary line.

4. The display device according to claim 3, in, The circuit layer also includes: a first power line and a second power line in the non-display area and transmitting a first power and a second power for driving the light emitting element, respectively; and a first power line electrically connected between the light-emitting pixel driver and the first power line, wherein the first auxiliary line further comprises a second power auxiliary horizontal line electrically connected to the second power line, and Wherein, the second auxiliary line further includes a second power auxiliary vertical line electrically connected to the second power auxiliary horizontal line and the second power line.

5. The display device according to claim 4, in, The circuit layer also includes: a second connection assisting electrode adjacent to a cross point between the second power assisting vertical line and the second power assisting horizontal line; and A second auxiliary protruding electrode protrudes from the second power assisting vertical line and is electrically connected to the second connection assisting electrode through the auxiliary connection hole.

6. The display device according to claim 5, in, One of the second power-assist horizontal lines is electrically connected to at least one of the second power-assist vertical lines, and Wherein, the circuit layer also includes at least one third connecting line, which connects at least one second connection auxiliary electrode among the second connection auxiliary electrodes to the one second power auxiliary horizontal line among the second power auxiliary horizontal lines, and the at least one second connection auxiliary electrode is adjacent to the intersection between the one second power auxiliary horizontal line among the second power auxiliary horizontal lines and the at least one second power auxiliary vertical line among the second power auxiliary vertical lines.

7. The display device according to claim 4, in, The circuit layer also includes: a third connection auxiliary electrode adjacent to a cross point between the second power auxiliary vertical line and the first bypass auxiliary line; a third auxiliary protruding electrode protruding from the second power auxiliary vertical line and electrically connected to the third connection auxiliary electrode through the auxiliary connection hole; a fourth connection auxiliary electrode adjacent to a cross point between the second bypass auxiliary line and the second power auxiliary horizontal line; and A fourth auxiliary protruding electrode protrudes from the second bypass auxiliary line and is electrically connected to the fourth connection auxiliary electrode through the auxiliary connection hole.

8. The display device according to claim 4, further comprising a display driving circuit configured to transmit the data signal of the light-emitting pixel driver to the data line, in, The circuit layer further includes a data supply line in the non-display area and electrically connected between the data line and the display driving circuit. The bypass area on one side of the display area includes: a central bypass middle area; a first bypass side area, which is parallel to the central bypass middle area in the first direction and contacts the non-display area; and a second bypass side area, which is between the central bypass middle area and the first bypass side area. Wherein, the first data line is in the first bypass side area, Wherein, the second data line is in the second bypass side area, wherein a first data supply line for transmitting a data signal of the first data line among the data supply lines is electrically connected to the first data line through the first bypass auxiliary line and the second bypass auxiliary line, and Among the data supply lines, a second data supply line transmitting a data signal of the second data line is directly electrically connected to the second data line.

9. The display device according to claim 4, in, One of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power line, and Wherein, the one of the light-emitting pixel drivers comprises: a first transistor configured to generate a driving current for driving the one of the light emitting elements; a second transistor electrically connected between one of the data lines and the first electrode of the first transistor; a third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor electrically connected between the gate electrode of the first transistor and a first initialization power line configured to transmit a first initialization power; a fifth transistor electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the one of the light emitting elements; a seventh transistor electrically connected between the one of the light emitting elements and a second initialization power line configured to transmit a second initialization power; and An eighth transistor is electrically connected between the first electrode of the first transistor and a bias power line configured to transmit bias power.

10. The display device according to claim 9, in, The circuit layer comprises: a buffer layer covering the light blocking layer on the substrate; a first semiconductor layer on the buffer layer; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer, covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer, covering the second semiconductor layer; a third gate conductive layer, on the third gate insulating layer; A second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; a first planarization layer, covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarization layer; and a second planarization layer, covering the second source-drain conductive layer, wherein a channel portion, a source portion, and a drain portion of each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are in the first semiconductor layer, wherein a channel portion, a source portion, and a drain portion of each of the third transistor and the fourth transistor serve as a portion of the second semiconductor layer, wherein a gate electrode of the fourth transistor is electrically connected to a scan initialization line configured to transmit a scan initialization signal, wherein the first initialization power line is spaced apart from the scanning initialization line and serves as another part of the second semiconductor layer, Wherein, the scan initialization line is in the third gate conductive layer, Wherein, the first auxiliary line, the connecting auxiliary electrode and the data connecting electrode are in the first source-drain conductive layer, wherein the data line, the second auxiliary line, the auxiliary protruding electrode, the data protruding electrode and the first power line are in the second source-drain conductive layer, wherein each of the auxiliary connection hole and the data connection hole penetrates the first planarization layer, and The first auxiliary line and the connection auxiliary electrode overlap with the first initialization power line and are spaced apart from the scan initialization line.

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