Display device

Abstract

A display device is provided. The display device includes: a first voltage line supplying a high potential voltage; a data line supplying a data voltage; a first capacitor electrode disposed between the first voltage line and the data line; a buffer layer disposed on the first voltage line; a second capacitor electrode disposed on the buffer layer and the first capacitor electrode to overlap the first capacitor electrode; a first transistor disposed on the buffer layer and connected to the data line; an interlayer insulating layer disposed on the second capacitor electrode; and a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, in which the first connection pattern is connected to the second capacitor electrode through a first contact hole formed through the interlayer insulating layer and connected to the first transistor through a second contact hole formed through the interlayer insulating layer, and the first capacitor electrode overlaps the first connection pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms increases. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element including, for example, an inorganic semiconductor, and a micron light-emitting display device or a nano light-emitting display device including a micron light-emitting element or a nano light-emitting element. Summary of the invention

[0004] Aspects of the present disclosure provide a display device capable of ensuring capacitance in high-resolution pixels.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to aspects of the present disclosure, a display device includes: a first voltage line, which is arranged on a substrate and supplies a high potential voltage; a data line, which is spaced apart from the first voltage line and supplies a data voltage; a first capacitor electrode, which is arranged between the first voltage line and the data line; a buffer layer, which is arranged on the first voltage line, the data line and the first capacitor electrode; a second capacitor electrode, which is arranged on the buffer layer and the first capacitor electrode to overlap with the first capacitor electrode in a plan view; a first transistor, which is arranged on the buffer layer and connected to the data line; an interlayer insulating layer, which is arranged on the second capacitor electrode and the first transistor; and a first connection pattern, which is arranged on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, wherein the first connection pattern is connected to the second capacitor electrode through a first contact hole formed through the interlayer insulating layer, and is connected to the first transistor through a second contact hole formed through the interlayer insulating layer, and the first capacitor electrode overlaps with the first connection pattern.

[0007] In an embodiment, the first capacitor electrode overlaps the first contact hole and does not overlap the second contact hole.

[0008] In an embodiment, the first capacitor electrode does not overlap the first contact hole and overlaps the second contact hole.

[0009] In an embodiment, a capacitor is formed between the first capacitor electrode and the source electrode of the first transistor.

[0010] In an embodiment, the first capacitor electrode overlaps the first contact hole and the second contact hole.

[0011] In an embodiment, the display device further includes: a second transistor disposed on the buffer layer; and a second connection pattern overlapping the second transistor and disposed on the interlayer insulating layer, wherein the second transistor is electrically connected to the first voltage line.

[0012] In an embodiment, the display device further includes: a first via layer disposed on the first connection pattern and the second connection pattern; and a first connection electrode disposed on the first via layer and connected to the second connection pattern through a third contact hole formed through the first via layer.

[0013] In an embodiment, the first connection pattern, the first connection electrode, and the first capacitor electrode overlap each other in a plan view, and a capacitor is formed between the first connection pattern and the first connection electrode.

[0014] In an embodiment, the second connection pattern is connected to the second transistor through a fourth contact hole formed through the interlayer insulating layer, and is connected to the first capacitor electrode through a fifth contact hole formed through the interlayer insulating layer and the buffer layer.

[0015] In an embodiment, a capacitor is formed between the first capacitor electrode and the second capacitor electrode and between the second capacitor electrode and the second connection pattern.

[0016] According to aspects of the present disclosure, a display device includes: a first voltage line, which is disposed on a substrate and supplies a high potential voltage; a data line, which is spaced apart from the first voltage line and supplies a data voltage; a first capacitor electrode, which is disposed between the first voltage line and the data line; a buffer layer, which is disposed on the first voltage line, the data line, and the first capacitor electrode; a second capacitor electrode, which is disposed on the buffer layer to overlap with the first capacitor electrode; a first transistor disposed on the buffer layer and connected to the data line, and a second transistor disposed on the buffer layer and connected to the first voltage line; an interlayer insulating layer, which is disposed on the second capacitor electrode, the first transistor, and the second transistor; a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, and a second connection pattern disposed on the interlayer insulating layer A second connection pattern on the interlayer insulating layer and connected to the first capacitor electrode and the second transistor; a passivation layer, arranged on the first connection pattern and the second connection pattern; a first through-hole layer, arranged on the passivation layer; and a first connection electrode, arranged on the first through-hole layer and connected to the second connection pattern through a third contact hole formed through the passivation layer and the first through-hole layer, wherein the first connection pattern is connected to the second capacitor electrode through the first contact hole formed through the interlayer insulating layer and is connected to the first transistor through the second contact hole formed through the interlayer insulating layer, the first through-hole layer includes an opening, the opening is arranged in a region corresponding to at least one of the first contact hole and the second contact hole in a plan view, and the first connection electrode is arranged on the first through-hole layer to cover the opening.

[0017] In an embodiment, an opening of the first via layer is formed through the first via layer to expose an upper surface of the passivation layer, and the first connection electrode extends from the upper surface of the first via layer to the upper surface of the passivation layer.

[0018] In an embodiment, the first connection electrode and the first connection pattern overlap each other in a plan view, and a capacitor is formed between the first connection electrode and the first connection pattern.

[0019] In an embodiment, the opening of the first via layer is not disposed in a region overlapping the first capacitor electrode in a plan view.

[0020] In an embodiment, in a plan view, the first capacitor electrode overlaps with the first contact hole, and the opening of the first via layer is disposed in a region corresponding to the first contact hole and the first capacitor electrode.

[0021] In an embodiment, the first capacitor electrode overlaps the first contact hole and the second contact hole, and the opening of the first via layer is disposed in a region corresponding to the first contact hole, the second contact hole, and the first capacitor electrode.

[0022] In an embodiment, in a plan view, the first capacitor electrode overlaps with the second contact hole, and the opening of the first via layer overlaps with the second contact hole and the first capacitor electrode.

[0023] According to aspects of the present disclosure, a display device includes: a first voltage line, which supplies a high potential voltage and extends in a first direction; a data line, which supplies a data voltage and extends in the first direction; a first transistor, which is electrically connected to the first voltage line; a first connection pattern, which is connected to the first transistor; a first capacitor electrode, which is electrically connected to the first connection pattern to receive a high potential voltage; a second transistor, which is electrically connected to the data line; a second connection pattern, which is connected to the second transistor; a second capacitor electrode, which is connected to the second connection pattern to receive the data voltage; an interlayer insulating layer, which is arranged between the first transistor and the first connection pattern and between the second transistor and the second connection pattern; and a buffer layer, which is arranged between the first voltage line, the first capacitor electrode and the data line and the first transistor and the second transistor, wherein the second connection pattern is connected to the second capacitor electrode and the second transistor through a contact hole formed in the interlayer insulating layer, and the first capacitor electrode overlaps with the first transistor and the second capacitor electrode in a plan view and overlaps with at least one of the contact holes in a plan view.

[0024] In an embodiment, the second capacitor electrode completely overlaps the first capacitor electrode in plan view.

[0025] In an embodiment, at least a portion of the second connection pattern and the first capacitor electrode overlap each other in a plan view.

[0026] In an embodiment, the display device further includes: a passivation layer disposed on the first connection pattern and the second connection pattern; a first through-hole layer disposed on the passivation layer; and a first connection electrode disposed on the first through-hole layer and electrically connected to the first connection pattern through a contact hole formed in the passivation layer and the first through-hole layer, wherein the first connection electrode overlaps with the second connection pattern in a plan view.

[0027] In an embodiment, the display device further includes: a second through hole layer disposed on the first connection electrode; a pixel electrode disposed on the second through hole layer and electrically connected to the first connection electrode; an organic layer disposed on the pixel electrode; and a common electrode disposed on the organic layer.

[0028] The display device according to the embodiment can increase capacitance by increasing the overlap area between the first capacitor electrode and the second capacitor electrode. In addition, the first connection electrode can be further formed to form a capacitor between the first connection electrode and the third connection pattern, thereby increasing capacitance.

[0029] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those of ordinary skill in the art to which the embodiments pertain by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a plan view of a display device according to an embodiment;

[0032] Figure 2 Schematic diagram of pixels and circuits of a display device according to an embodiment;

[0033] Figure 3 is a circuit diagram of a pixel of a display device according to an embodiment;

[0034] Figure 4 is a plan view of a thin film transistor layer of a display device according to an embodiment;

[0035] Figure 5 yes Figure 4 A plan view of a first metal layer of a thin film transistor layer;

[0036] Figure 6 yes Figure 4 A plan view of a first metal layer, an active layer, and a second metal layer of a thin film transistor layer;

[0037] Figure 7 yes Figure 4 A plan view of a first metal layer, an active layer, a second metal layer and a third metal layer of a thin film transistor layer;

[0038] Figure 8 is along Figure 4 A cross-sectional view taken along line Q1-Q1';

[0039] Fig. 9 yes Figure 4 A diagram of a first capacitor of a thin film transistor layer;

[0040] Fig.10 is a plan view of a thin film transistor layer of a display device according to an embodiment;

[0041] Fig.11 yes Fig.10 A plan view of a first metal layer of a thin film transistor layer;

[0042] Fig.12 is along Fig.10 A cross-sectional view taken along line Q2-Q2';

[0043] Fig.13 yes Fig.10 A diagram of a first capacitor of a thin film transistor layer;

[0044] Fig.14 is a plan view of a thin film transistor layer of a display device according to an embodiment;

[0045] Fig.15 yes Fig.14 A plan view of a first metal layer of a thin film transistor layer;

[0046] Fig.16 is along Fig.14 A cross-sectional view taken along line Q3-Q3';

[0047] Fig.17 is a plan view of a thin film transistor layer of a display device according to an embodiment;

[0048] Fig.18 yes Fig.17 A plan view of a fourth metal layer of a thin film transistor layer;

[0049] Fig.19 is along Fig.17 A cross-sectional view taken along line Q4-Q4';

[0050] Fig. 20 yes Fig.17 A diagram of a first capacitor of a thin film transistor layer;

[0051] Fig.21 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment;

[0052] Fig. 22 yes Fig.21 A diagram of a first capacitor of a thin film transistor layer;

[0053] Fig.23 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment;

[0054] Fig.24 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment;

[0055] Fig.25 is a diagram of a capacitor in a region where a third contact hole is provided;

[0056] Fig.26 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment;

[0057] Fig. 27 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment;

[0058] Fig.28 is a plan view of a display device according to an embodiment; and

[0059] Fig.29 is along Fig.28 A cross-sectional view taken along line Q5-Q5'. DETAILED DESCRIPTION

[0060] The inventive concept will now be described more fully below with reference to the accompanying drawings in which preferred embodiments of the inventive concept are shown. However, the inventive concept may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0061] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0062] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element may also be referred to as the first element.

[0063] The various features of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and various interlocks and drives in technology are possible. The various embodiments may be implemented independently of each other, or may be implemented together in association.

[0064] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 is a plan view of a display device 10 according to the embodiment.

[0066] In this specification, "above", "top" and "upper surface" refer to the direction from the display device 10 upward, that is, the Z-axis direction, and "below", "bottom" and "lower surface" refer to the direction from the display device 10 downward, that is, the direction opposite to the Z-axis direction. In addition, "left", "right", "upper" and "lower surface" refer to directions when the display device 10 is viewed in a plan view. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Y-axis direction, and "lower" refers to the direction opposite to the Y-axis direction.

[0067] refer to Figure 1The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs), and display screens in various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0068] The display device 10 may include a display panel 100 , a flexible film 210 , a display driver 220 , a circuit board 230 , a timing controller 240 , a power supply 250 , and a gate driver 260 .

[0069] The display panel 100 may be rectangular in a plan view. For example, the display panel 100 may be shaped like a rectangular plane having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction). Each corner where a long side extending in a first direction (X-axis direction) intersects a short side extending in a second direction (Y-axis direction) may be a right angle, or may be rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may also be other polygonal shapes, a circular shape, or an elliptical shape. For example, the display panel 100 may be formed to be flat, but the present disclosure is not limited thereto. As another example, the display panel 100 may be formed to be curved with a predetermined curvature.

[0070] The display panel 100 may include a display area DA and a non-display area NDA.

[0071] The display area DA may be an area for displaying an image, and may be defined as a central area of ​​the display panel 100. The display area DA may include a pixel SP, a gate line GL, a data line DL, an initialization voltage line VIL, a first voltage line VDL, a vertical voltage line VVSL, and a second voltage line VSL. The pixel SP may be formed in a pixel area where the data line DL and the gate line GL intersect, respectively. The pixel SP may include first to third pixels SP1 to SP3. Each of the first to third pixels SP1 to SP3 may be connected to the gate line GL and the data line DL. Each of the first to third pixels SP1 to SP3 may be defined as a minimum unit area for outputting light.

[0072] Each of the first to third pixels SP1 to SP3 may include an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0073] The first pixel SP1 may emit light of a first color or red light, the second pixel SP2 may emit light of a second color or green light, and the third pixel SP3 may emit light of a third color or blue light. The pixel circuits of the second pixel SP2, the first pixel SP1, and the third pixel SP3 may be arranged in a direction opposite to the second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0074] The gate lines GL may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction). The gate lines GL may receive a gate signal from the gate driver 260 and supply the gate signal to the first auxiliary gate line BGL1 and the second auxiliary gate line BGL2. The first auxiliary gate line BGL1 and the second auxiliary gate line BGL2 may extend from the gate line GL to supply the gate signal to the first to third pixels SP1 to SP3.

[0075] The data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The data lines DL may include first to third data lines DL1 to DL3. The first to third data lines DL1 to DL3 may supply data voltages to the first to third pixels SP1 to SP3, respectively.

[0076] The initialization voltage lines VIL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The initialization voltage lines VIL may supply the initialization voltage received from the display driver 220 to the pixel circuits of the first to third pixels SP1 to SP3. The initialization voltage lines VIL may receive sensing signals from the pixel circuits of the first to third pixels SP1 to SP3 and supply the sensing signals to the display driver 220.

[0077] The first voltage lines VDL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The first voltage lines VDL may supply a driving voltage or a high potential voltage received from the power supply 250 to the first to third pixels SP1 to SP3.

[0078] The vertical voltage lines VVSL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The vertical voltage lines VVSL may be connected to the second voltage lines VSL. The vertical voltage lines VVSL may supply the low potential voltage received from the power supply 250 to the second voltage lines VSL.

[0079] The second voltage lines VSL may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). The second voltage lines VSL may supply a low potential voltage to the first to third pixels SP1 to SP3.

[0080] The connection relationship among the pixels SP, the gate lines GL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL, the vertical voltage lines VVSL and the second voltage lines VSL may be designed and changed according to the number and arrangement of the pixels SP.

[0081] The non-display area NDA may be defined as an area other than the display area DA in the display panel 100. For example, the non-display area NDA may include an area in which a fan-out line connecting the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driver 220 is disposed, and may include an area in which a gate driver 260 and a pad unit (not shown) connected to the flexible film 210 are disposed.

[0082] The flexible film 210 may be connected to a pad unit disposed on the lower side of the non-display area NDA. An input terminal disposed on one side of the flexible film 210 may be attached to the circuit board 230 by a film attachment process, and an output terminal disposed on the other side of the flexible film 210 may be attached to the pad unit by a film attachment process. For example, each of the flexible films 210 may be bent and may be a tape carrier package or a chip on film. The flexible film 210 may be bent toward the bottom of the display panel 100 to reduce the frame area of ​​the display device 10.

[0083] The display driver 220 may be mounted on the flexible film 210. For example, the display driver 220 may be implemented as an integrated circuit (IC). The display driver 220 may receive digital video data and a data control signal from the timing controller 240, convert the digital video data into an analog data voltage according to the data control signal, and supply the analog data voltage to the data line DL through the fan-out line.

[0084] The timing controller 240 and the power supply 250 may be provided on the circuit board 230, and may supply signals and power to the display driver 220. For example, the circuit board 230 may supply the signal supplied from the timing controller 240 and the power supply voltage supplied from the power supply 250 to the flexible film 210 and the display driver 220 to display an image on each pixel SP. To this end, a signal line and a power line may be provided on the circuit board 230.

[0085] The timing controller 240 may be mounted on the circuit board 230, and may receive image data and a timing synchronization signal from a display driving system or a graphics device (not shown) through a connector (not shown) provided on the circuit board 230. The timing controller 240 may generate digital video data by arranging the image data according to the pixel arrangement structure based on the timing synchronization signal, and supply the generated digital video data to the display driver 220. The timing controller 240 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 240 may control the supply timing of the data voltage of the display driver 220 based on the data control signal, and may control the supply timing of the gate signal of the gate driver 260 based on the gate control signal.

[0086] The power supply 250 may be provided on the circuit board 230 to supply a power supply voltage to the flexible film 210 and the display driver 220. For example, the power supply 250 may generate a driving voltage or a high potential voltage and supply the driving voltage or the high potential voltage to the first voltage line VDL, may generate a low potential voltage and supply the low potential voltage to the vertical voltage line VVSL, and may generate an initialization voltage and supply the initialization voltage to the initialization voltage line VIL.

[0087] The gate driver 260 may be disposed on the left and right sides of the non-display area NDA. The gate driver 260 may generate a gate signal based on a gate control signal supplied from the timing controller 240. The gate control signal may include, but is not limited to, a start signal, a clock signal, and a power supply voltage. The gate driver 260 may sequentially supply the gate signal to the gate line GL according to a predetermined order.

[0088] Figure 2 Pixels and lines of the display device 10 according to the embodiment are illustrated.

[0089] refer to Figure 2 , the pixel SP may include first to third pixels SP1 to SP3. The pixel circuit of the second pixel SP2, the pixel circuit of the first pixel SP1, and the pixel circuit of the third pixel SP3 may be arranged in a direction opposite to the second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0090] Each of the first to third pixels SP1 to SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a second voltage line VSL, a gate line GL, and a data line DL.

[0091] The first voltage line VDL may extend in the second direction (Y-axis direction). The first voltage line VDL may be disposed on the left side of the pixel circuits of the first to third pixels SP1 to SP3. The first voltage line VDL may supply a driving voltage or a high potential voltage to the pixel circuits of the first to third pixels SP1 to SP3.

[0092] The initialization voltage line VIL may extend in the second direction (Y-axis direction). The initialization voltage line VIL may be disposed on the left side of the second auxiliary gate line BGL2. The initialization voltage line VIL may be disposed between the vertical voltage line VVSL and the second auxiliary gate line BGL2. The initialization voltage line VIL may supply the initialization voltage to the pixel circuits of the first to third pixels SP1 to SP3. The initialization voltage line VIL may receive a sensing signal from the pixel circuits of the first to third pixels SP1 to SP3, and supply the sensing signal to the display driver 220.

[0093] The vertical voltage line VVSL may extend in the second direction (Y-axis direction). The vertical voltage line VVSL may be disposed on the left side of the initialization voltage line VIL. The vertical voltage line VVSL may be connected between the power supply 250 and the second voltage line VSL. The vertical voltage line VVSL may supply the low potential voltage supplied from the power supply 250 to the second voltage line VSL.

[0094] The second voltage line VSL may extend in the first direction (X-axis direction). The second voltage line VSL may be disposed under the gate line GL disposed in the k-th row ROWk, where k is Except zero The second voltage line VSL may supply the low potential voltage received from the vertical voltage line VVSL to the pixel circuits of the first to third pixels SP1 to SP3.

[0095] The gate line GL may extend in the first direction (X-axis direction). The gate line GL may be arranged below the pixel circuit of the third pixel SP3. Each of the gate lines GL may supply the gate signal received from the gate driver 260 to the first auxiliary gate line BGL1 and the second auxiliary gate line BGL2. The first auxiliary gate line BGL1 and the second auxiliary gate line BGL2 may extend from each of the gate lines GL in the second direction (Y-axis direction). Each of the first auxiliary gate lines BGL1 may be arranged on the right side of the pixel circuit of the first to third pixels SP1 to SP3, and each of the second auxiliary gate lines BGL2 may be arranged on the left side of the pixel circuit of the first to third pixels SP1 to SP3. Each of the first auxiliary gate lines BGL1 and the second auxiliary gate lines BGL2 may supply the gate signal received from the gate line GL to the pixel circuit of the first to third pixels SP1 to SP3.

[0096] The data lines DL may extend in the second direction (Y-axis direction). The data lines DL may supply data voltages to the pixels SP. The data lines DL may include first to third data lines DL1 to DL3.

[0097] The first data line DL1 may extend in the second direction (Y-axis direction). The first data line DL1 may be disposed on the right side of the second data line DL2. The first data line DL1 may supply a data voltage received from the display driver 220 to a pixel circuit of the first pixel SP1.

[0098] The second data line DL2 may extend in the second direction (Y-axis direction). The second data line DL2 may be disposed on the left side of the first data line DL1. The second data line DL2 may supply a data voltage received from the display driver 220 to a pixel circuit of the second pixel SP2.

[0099] The third data line DL3 may extend in the second direction (Y-axis direction). The third data line DL3 may be disposed on the left side of the second data line DL2. The third data line DL3 may supply a data voltage received from the display driver 220 to a pixel circuit of the third pixel SP3.

[0100] Figure 3 is a circuit diagram of a pixel SP of the display device 10 according to the embodiment.

[0101] refer to Figure 3 , each of the pixels SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a gate line GL, and a vertical voltage line VVSL.

[0102] Each of the first to third pixels SP1 to SP3 may include a pixel circuit and a light emitting element ED. The pixel circuit of each of the first to third pixels SP1 to SP3 may include first to third transistors ST1 to ST3 and a first capacitor C1.

[0103] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The first transistor ST1 may have a gate electrode connected to the first node N1, a drain electrode connected to the first voltage line VDL, and a source electrode connected to the second node N2. The first transistor ST1 may control a drain-source current (or a drive current) based on a data voltage applied to the gate electrode.

[0104] The light emitting element ED may emit light in response to the driving current. The amount of light emitted from the light emitting element ED or the brightness of the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0105] A first electrode of the light emitting element ED may be connected to the second node N2, and a second electrode of the light emitting element ED may be connected to the vertical voltage line VVSL. The first electrode of the light emitting element ED may be connected to the source electrode of the first transistor ST1, the drain electrode of the third transistor ST3, and the second capacitor electrode of the first capacitor C1 through the second node N2.

[0106] The second transistor ST2 may be turned on by a gate signal of the gate line GL (or the first auxiliary gate line BGL1) to electrically connect the data line DL and the first node N1 which is the gate electrode of the first transistor ST1. The second transistor ST2 may be turned on in response to the gate signal to supply the data voltage to the first node N1. The second transistor ST2 may have a gate electrode connected to the gate line GL, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the gate electrode of the first transistor ST1 and the first capacitor electrode of the first capacitor C1 through the first node N1.

[0107] The third transistor ST3 may be turned on by a gate signal of the gate line GL (or the second auxiliary gate line BGL2) to electrically connect the initialization voltage line VIL and the second node N2 which is the source electrode of the first transistor ST1. The third transistor ST3 may be turned on in response to the gate signal to supply the initialization voltage to the second node N2. The third transistor ST3 may be turned on in response to the gate signal to supply the sensing signal to the initialization voltage line VIL. The third transistor ST3 may have a gate electrode connected to the gate line GL, a drain electrode connected to the second node N2, and a source electrode connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode of the first transistor ST1, the second capacitor electrode of the first capacitor C1, and the first electrode of the light emitting element ED through the second node N2.

[0108] Figure 4 is a plan view of a thin film transistor layer of the display device 10 according to the embodiment. Figure 5 yes Figure 4 1 is a plan view of a first metal layer MTL1 of a thin film transistor layer. Figure 6 yes Figure 4 1 is a plan view of a first metal layer MTL1, an active layer ACTL and a second metal layer MTL2 of a thin film transistor layer. Figure 7 yes Figure 4 1 is a plan view of a first metal layer MTL1, an active layer ACTL, a second metal layer MTL2 and a third metal layer MTL3 of a thin film transistor layer. Figure 8 is along Figure 4 A cross-sectional view taken along line Q1-Q1'. Fig. 9 yes Figure 4 FIG. 1 is a diagram of a first capacitor C1 of a thin film transistor layer.

[0109] Figure 8 A cross-sectional structure of the first transistor ST1 , the first capacitor C1 , and the second transistor ST2 of the first pixel SP1 is illustrated.

[0110] refer to Figures 4 to 7 , the display area DA may include first to third pixels SP1 to SP3 , a first voltage line VDL, an initialization voltage line VIL, a gate line GL, first and second auxiliary gate lines BGL1 and BGL2 , and a data line DL.

[0111] The pixel SP may include first to third pixels SP1 to SP3. The pixel circuits of the second pixel SP2, the first pixel SP1, and the third pixel SP3 may be arranged in a direction opposite to the second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0112] The first metal layer MTL1, the second metal layer MTL2, and the third metal layer MTL3 may be disposed on the substrate SUB. The first metal layer MTL1 may include a first voltage line VDL, a second capacitor electrode CPE2, first to third data lines DL1 to DL3, and an initialization voltage line VIL. The second metal layer MTL2 may include first and second auxiliary gate lines BGL1 and BGL2 and a first capacitor electrode CPE1. The third metal layer MTL3 may include first to ninth connection patterns CE1 to CE9 and first and second auxiliary electrodes AUE1 and AUE2. The active layer ACTL may include active regions ACT1 to ACT3, source electrodes SE1 to SE3 of first to third transistors ST1 to ST3 of each of the first to third pixels SP1 to SP3, and drain electrodes DE1 to DE3.

[0113] The first voltage line VDL may be disposed on the left side of the pixel circuit of the first to third pixels SP1 to SP3. The first voltage line VDL may overlap the first auxiliary electrode AUE1 of the third metal layer MTL3. The second metal layer MTL2 may be disposed on the gate insulating layer GI covering the active layer ACTL, and the third metal layer MTL3 may be disposed on the interlayer insulating layer ILD covering the second metal layer MTL2. The passivation layer PV may cover the third metal layer MTL3. The first auxiliary electrode AUE1 may be connected to the first voltage line VDL through a contact hole. The first voltage line VDL may be connected to the first auxiliary electrode AUE1 to reduce wiring resistance.

[0114] The first auxiliary electrode AUE1 may be connected to the drain electrode DE1 of the first transistor ST1 of each of the first to third pixels SP1 to SP3. Thus, the first voltage line VDL may supply a driving voltage to the first transistor ST1 of each of the first to third pixels SP1 to SP3 through the first auxiliary electrode AUE1.

[0115] The initialization voltage line VIL may be disposed on the left side of the first voltage line VDL. The initialization voltage line VIL may overlap the second auxiliary electrode AUE2 of the third metal layer MTL3 and may be connected to the second auxiliary electrode AUE2 through a contact hole. The initialization voltage line VIL may be connected to the second auxiliary electrode AUE2 to reduce wiring resistance.

[0116] The second auxiliary electrode AUE2 may be connected to the source electrode SE3 of the third transistor ST3 of each of the first to third pixels SP1 to SP3. Therefore, the initialization voltage line VIL may supply the initialization voltage to the third transistor ST3 of each of the first to third pixels SP1 to SP3 through the second auxiliary electrode AUE2, and may receive a sensing signal from the third transistor ST3.

[0117] The gate line GL may be disposed under the pixel circuit of the third pixel SP3 . The gate line GL may be connected to the first and second auxiliary gate lines BGL1 and BGL2 , and may supply a gate signal received from the gate driver 260 to the first and second auxiliary gate lines BGL1 and BGL2 .

[0118] The first auxiliary gate line BGL1 may protrude from the gate line GL in the second direction (Y-axis direction). The first auxiliary gate line BGL1 may be disposed on the right side of the pixel circuit of the first to third pixels SP1 to SP3. The first auxiliary gate line BGL1 may supply a gate signal received from the gate line GL to the second transistor ST2 of each of the first to third pixels SP1 to SP3.

[0119] The second auxiliary gate line BGL2 may protrude from the gate line GL in the second direction (Y-axis direction). The second auxiliary gate line BGL2 may be disposed between the initialization voltage line VIL and the first voltage line VDL. The second auxiliary gate line BGL2 may supply a gate signal received from the gate line GL to the third transistor ST3 of each of the first to third pixels SP1 to SP3.

[0120] The first data line DL1 may be disposed on the right side of the second data line DL2. The second connection pattern CE2 may electrically connect the first data line DL1 and the drain electrode DE2 of the second transistor ST2 of the first pixel SP1. Therefore, the first data line DL1 may supply a data voltage to the second transistor ST2 of the first pixel SP1 through the second connection pattern CE2.

[0121] The second data line DL2 may be disposed on the left side of the first data line DL1. The fifth connection pattern CE5 may electrically connect the second data line DL2 and the drain electrode DE2 of the second transistor ST2 of the second pixel SP2. Therefore, the second data line DL2 may supply the data voltage to the second transistor ST2 of the second pixel SP2 through the fifth connection pattern CE5.

[0122] The third data line DL3 may be disposed on the right side of the first auxiliary gate line BGL1. The eighth connection pattern CE8 may electrically connect the third data line DL3 and the drain electrode DE2 of the second transistor ST2 of the third pixel SP3. Therefore, the third data line DL3 may supply a data voltage to the second transistor ST2 of the third pixel SP3 through the eighth connection pattern CE8.

[0123] The pixel circuit of the first pixel SP1 may include first to third transistors ST1 to ST3. The first transistor ST1 of the first pixel SP1 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may overlap with the gate electrode GE1 of the first transistor ST1. The active layer ACTL may be disposed on the buffer layer BF covering the first metal layer MTL1.

[0124] The gate electrode GE1 of the first transistor ST1 may be a part of the first capacitor electrode CPE1 of the first capacitor C1. The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be given conductivity in the etching process of the gate electrode GE1. The drain electrode DE1 and the source electrode SE1 may be regions of the active layer that are given conductivity by converting the active layer into an N-type semiconductor, but the present disclosure is not limited thereto. The drain electrode DE1 of the first transistor ST1 may be electrically connected to the first voltage line VDL through the first auxiliary electrode AUE1. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL.

[0125] The source electrode SE1 of the first transistor ST1 may be connected to the first connection pattern CE1. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1.

[0126] The first connection pattern CE1 may be electrically connected to the light emitting element ED of the first pixel SP1. Thus, the first connection pattern CE1 may supply a driving current received from the pixel circuit of the first pixel SP1 to the light emitting element ED.

[0127] The second transistor ST2 of the first pixel SP1 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may overlap with the gate electrode GE2 of the second transistor ST2.

[0128] The gate electrode GE2 of the second transistor ST2 may be a part of the first auxiliary gate line BGL1. The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be given conductivity in the etching process of the gate electrode GE2. The drain electrode DE2 of the second transistor ST2 may be electrically connected to the first data line DL1 through the second connection pattern CE2. Therefore, the first data line DL1 may supply the data voltage to the second transistor ST2 of the first pixel SP1 through the second connection pattern CE2. The source electrode SE2 of the second transistor ST2 may be electrically connected to the first capacitor electrode CPE1 of the first capacitor C1 through the third connection pattern CE3.

[0129] The third transistor ST3 of the first pixel SP1 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode GE3 of the third transistor ST3.

[0130] The gate electrode GE3 of the third transistor ST3 may be a part of the second auxiliary gate line BGL2. The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be given conductivity in the etching process of the gate electrode GE3. The drain electrode DE3 of the third transistor ST3 may be connected to the extended portion of the first connection pattern CE1. The drain electrode DE3 of the third transistor ST3 may be electrically connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2 of the first capacitor C1 through the first connection pattern CE1.

[0131] The source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0132] The pixel circuit of the second pixel SP2 may include first to third transistors ST1 to ST3. The first transistor ST1 of the second pixel SP2 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may overlap with the gate electrode GE1 of the first transistor ST1.

[0133] The gate electrode GE1 of the first transistor ST1 may be a part of the first capacitor electrode CPE1 of the first capacitor C1. The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be given conductivity in the etching process of the gate electrode GE1. The drain electrode DE1 and the source electrode SE1 may be regions of the active layer that are given conductivity by converting the active layer into an N-type semiconductor, but the present disclosure is not limited thereto. The drain electrode DE1 of the first transistor ST1 may be electrically connected to the first voltage line VDL through the first auxiliary electrode AUE1. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL.

[0134] The source electrode SE1 of the first transistor ST1 may be connected to the fourth connection pattern CE4. The fourth connection pattern CE4 may be connected to the second capacitor electrode CPE2. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the fourth connection pattern CE4.

[0135] The fourth connection pattern CE4 may be electrically connected to the light emitting element ED of the second pixel SP2. Therefore, the fourth connection pattern CE4 may supply a driving current received from the pixel circuit of the second pixel SP2 to the light emitting element ED.

[0136] The second transistor ST2 of the second pixel SP2 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may overlap with the gate electrode GE2 of the second transistor ST2.

[0137] The gate electrode GE2 of the second transistor ST2 may be a part of the first auxiliary gate line BGL1. The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be given conductivity in the etching process of the gate electrode GE2. The drain electrode DE2 of the second transistor ST2 may be electrically connected to the second data line DL2 through the fifth connection pattern CE5. Therefore, the second data line DL2 may supply the data voltage to the second transistor ST2 of the second pixel SP2 through the fifth connection pattern CE5. The source electrode SE2 of the second transistor ST2 may be electrically connected to the first capacitor electrode CPE1 of the first capacitor C1 through the sixth connection pattern CE6.

[0138] The third transistor ST3 of the second pixel SP2 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode GE3 of the third transistor ST3.

[0139] The gate electrode GE3 of the third transistor ST3 may be a part of the second auxiliary gate line BGL2. The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be given conductivity in the etching process of the gate electrode GE3. The drain electrode DE3 of the third transistor ST3 may be connected to the extended portion of the fourth connection pattern CE4. The drain electrode DE3 of the third transistor ST3 may be electrically connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2 of the first capacitor C1 through the fourth connection pattern CE4.

[0140] The source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0141] The pixel circuit of the third pixel SP3 may include first to third transistors ST1 to ST3. The first transistor ST1 of the third pixel SP3 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may overlap with the gate electrode GE1 of the first transistor ST1.

[0142] The gate electrode GE1 of the first transistor ST1 may be a part of the first capacitor electrode CPE1 of the first capacitor C1. The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be given conductivity in the etching process of the gate electrode GE1. The drain electrode DE1 and the source electrode SE1 may be regions of the active layer that are given conductivity by converting the active layer into an N-type semiconductor, but the present disclosure is not limited thereto. The drain electrode DE1 of the first transistor ST1 may be electrically connected to the first voltage line VDL through the first auxiliary electrode AUE1. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL.

[0143] The source electrode SE1 of the first transistor ST1 may be connected to the seventh connection pattern CE7. The seventh connection pattern CE7 may be connected to the second capacitor electrode CPE2. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the seventh connection pattern CE7.

[0144] The seventh connection pattern CE7 may be electrically connected to the light emitting element ED of the third pixel SP3. Therefore, the seventh connection pattern CE7 may supply a driving current received from the pixel circuit of the third pixel SP3 to the light emitting element ED.

[0145] The second transistor ST2 of the third pixel SP3 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may overlap with the gate electrode GE2 of the second transistor ST2.

[0146] The gate electrode GE2 of the second transistor ST2 may be a part of the first auxiliary gate line BGL1. The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be given conductivity in the etching process of the gate electrode GE2. The drain electrode DE2 of the second transistor ST2 may be electrically connected to the third data line DL3 through the eighth connection pattern CE8. Therefore, the third data line DL3 may supply the data voltage to the second transistor ST2 of the third pixel SP3 through the eighth connection pattern CE8. The source electrode SE2 of the second transistor ST2 may be electrically connected to the first capacitor electrode CPE1 of the first capacitor C1 through the ninth connection pattern CE9.

[0147] The third transistor ST3 of the third pixel SP3 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode GE3 of the third transistor ST3.

[0148] The gate electrode GE3 of the third transistor ST3 may be a part of the second auxiliary gate line BGL2. The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be given conductivity in the etching process of the gate electrode GE3. The drain electrode DE3 of the third transistor ST3 may be connected to the extended portion of the seventh connection pattern CE7. The drain electrode DE3 of the third transistor ST3 may be electrically connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2 of the first capacitor C1 through the seventh connection pattern CE7.

[0149] The source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0150] refer to Figure 8 and Fig. 9 , the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1.

[0151] Specifically, the source electrode SE1 of the first transistor ST1 may be connected to the first connection pattern CE1. The first connection pattern CE1 may be connected to the source electrode SE1 of the first transistor ST1 through a first contact hole CT1 formed through the interlayer insulating layer ILD. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2 through a second contact hole CT2 formed through the buffer layer BF and the interlayer insulating layer ILD.

[0152] The source electrode SE2 of the second transistor ST2 may be connected to the third connection pattern CE3. The third connection pattern CE3 may be connected to the source electrode SE2 of the second transistor ST2 through a third contact hole CT3 formed through the interlayer insulating layer ILD. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1 through a fourth contact hole CT4 formed through the interlayer insulating layer ILD.

[0153] The second capacitor electrode CPE2, the first capacitor electrode CPE1, and the first connection pattern CE1 described above may overlap each other in a plan view. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1.

[0154] The second capacitor electrode CPE2 may overlap the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected. That is, in a plan view, the second capacitor electrode CPE2 may overlap the first capacitor electrode CPE1 on which the fourth contact hole CT4 is formed in the interlayer insulating layer ILD, thereby increasing the capacitance of the first capacitor C1.

[0155] Fig.10 is a plan view of a thin film transistor layer of a display device according to an embodiment. Fig.11 yes Fig.10 1 is a plan view of a first metal layer MTL1 of a thin film transistor layer. Fig.12 is along Fig.10 A cross-sectional view taken along line Q2-Q2'. Fig.13 yes Fig.10 FIG. 1 is a diagram of a first capacitor C1 of a thin film transistor layer.

[0156] refer to Figures 10 to 13 , the current embodiment and Figures 4 to 9 The embodiment of FIG. 1 is different in that the second capacitor electrode CPE2 overlaps the third contact hole CT3. Descriptions of the same elements and features as those of the embodiment described above will be omitted below, and the differences will be described.

[0157] The second capacitor electrode CPE2 of the first metal layer MTL1 may be disposed on the substrate SUB. The second capacitor electrode CPE2 may extend from under the first transistor ST1 to under the second transistor ST2. For example, the second capacitor electrode CPE2 may overlap the gate electrode GE1 and the source electrode SE1 of the first transistor ST1 and the source electrode SE2 of the second transistor ST2. In addition, in a plan view, the second capacitor electrode CPE2 may overlap the first connection pattern CE1 and the third connection pattern CE3 of the third metal layer MTL3.

[0158] The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 , between the first capacitor electrode CPE1 and the first connection pattern CE1 , and between the second capacitor electrode CPE2 and the source electrode SE2 of the second transistor ST2 .

[0159] Specifically, the source electrode SE1 of the first transistor ST1 may be connected to the first connection pattern CE1. The first connection pattern CE1 may be connected to the source electrode SE1 of the first transistor ST1 through a first contact hole CT1 formed through the interlayer insulating layer ILD. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2 through a second contact hole CT2 formed through the buffer layer BF and the interlayer insulating layer ILD.

[0160] The source electrode SE2 of the second transistor ST2 may be connected to the third connection pattern CE3. The third connection pattern CE3 may be connected to the source electrode SE2 of the second transistor ST2 through a third contact hole CT3 formed through the interlayer insulating layer ILD. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1 through a fourth contact hole CT4 formed through the interlayer insulating layer ILD.

[0161] The second capacitor electrode CPE2, the first capacitor electrode CPE1, and the first connection pattern CE1 described above may overlap each other in a plan view. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1.

[0162] The second capacitor electrode CPE2 may overlap with the third contact hole CT3 exposing the source electrode SE2 of the second transistor ST2. Specifically, the second capacitor electrode CPE2 may not overlap with the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected, and may overlap with the third connection pattern CE3 and the third contact hole CT3 through which the source electrode SE2 of the second transistor ST2 is connected.

[0163] The second capacitor electrode CPE2 may overlap with the source electrode SE2 of the second transistor ST2. The second capacitor electrode CPE2 may not overlap with the gate electrode GE2 of the second transistor ST2. The source electrode SE2 of the second transistor ST2 may be given conductivity to serve as a conductive layer. Therefore, the second capacitor electrode CPE2 may serve as a lower electrode of the first capacitor C1, and the source electrode SE2 of the second transistor ST2 may serve as an upper electrode of the first capacitor C1.

[0164] In the current embodiment, since the second capacitor electrode CPE2 further forms a capacitor with the source electrode SE2 of the second transistor ST2 , the capacitance of the first capacitor C1 may be increased.

[0165] Fig.14 is a plan view of a thin film transistor layer of a display device according to an embodiment. Fig.15 yes Fig.14 1 is a plan view of a first metal layer MTL1 of a thin film transistor layer. Fig.16 is along Fig.14 A cross-sectional view taken along line Q3-Q3'.

[0166] refer to Figures 14 to 16 , the current embodiment and Figures 4 to 13 The embodiment of the present invention is different in that the second capacitor electrode CPE2 extends to overlap the third contact hole CT3 and the fourth contact hole CT4. Descriptions of the same elements and features as those of the embodiment described above will be omitted below, and the differences will be described.

[0167] The second capacitor electrode CPE2 of the first metal layer MTL1 may be disposed on the substrate SUB. The second capacitor electrode CPE2 may extend from under the first transistor ST1 to under the second transistor ST2. For example, in a plan view, the second capacitor electrode CPE2 may overlap the gate electrode GE1 and the source electrode SE1 of the first transistor ST1 and the source electrode SE2 of the second transistor ST2. In addition, in a plan view, the second capacitor electrode CPE2 may overlap the first connection pattern CE1 and the third connection pattern CE3 of the third metal layer MTL3.

[0168] The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 , between the first capacitor electrode CPE1 and the first connection pattern CE1 , and between the second capacitor electrode CPE2 and the source electrode SE2 of the second transistor ST2 .

[0169] Specifically, the source electrode SE1 of the first transistor ST1 may be connected to the first connection pattern CE1. The first connection pattern CE1 may be connected to the source electrode SE1 of the first transistor ST1 through a first contact hole CT1 formed through the interlayer insulating layer ILD. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2. The first connection pattern CE1 may be connected to the second capacitor electrode CPE2 through a second contact hole CT2 formed through the buffer layer BF and the interlayer insulating layer ILD.

[0170] The source electrode SE2 of the second transistor ST2 may be connected to the third connection pattern CE3. The third connection pattern CE3 may be connected to the source electrode SE2 of the second transistor ST2 through a third contact hole CT3 formed through the interlayer insulating layer ILD. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1. The third connection pattern CE3 may be connected to the first capacitor electrode CPE1 through a fourth contact hole CT4 formed through the interlayer insulating layer ILD.

[0171] The second capacitor electrode CPE2, the first capacitor electrode CPE1, and the first connection pattern CE1 described above may overlap each other in a plan view. Therefore, the first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1.

[0172] The second capacitor electrode CPE2 may overlap with the third contact hole CT3 and the fourth contact hole CT4 respectively exposing the source electrode SE2 of the second transistor ST2 and the first capacitor electrode CPE1. Specifically, the second capacitor electrode CPE2 may overlap with the fourth contact hole CT4 exposing the first capacitor electrode CPE1, and may overlap with the third contact hole CT3 exposing the source electrode SE2 of the second transistor ST2. The third connection pattern CE3 may connect the first capacitor electrode CPE1 and the source electrode SE2 of the second transistor ST2 through the third contact hole CT3 and the fourth contact hole CT4.

[0173] In the current embodiment, the second capacitor electrode CPE2 may extend to overlap with the fourth contact hole CT4 and increase the overlapping area with the first capacitor electrode CPE1, thereby increasing the capacitance of the first capacitor C1. In addition, since the second capacitor electrode CPE2 further forms a capacitor with the source electrode SE2 of the second transistor ST2, the capacitance of the first capacitor C1 may be further increased.

[0174] Fig.17 is a plan view of a thin film transistor layer of a display device according to an embodiment. Fig.18 yes Fig.17 1 is a plan view of a fourth metal layer MTL4 of a thin film transistor layer. Fig.19 is along Fig.17 A cross-sectional view taken along line Q4-Q4'. Fig. 20 yes Fig.17 FIG. 1 is a diagram of a first capacitor C1 of a thin film transistor layer.

[0175] refer to Figures 17 to 20 , the current embodiment and Figures 4 to 16 The embodiment of the present invention is different in that the thin film transistor layer further includes a first via layer VIA1 and a fourth metal layer MTL4, and the first via layer VIA1 includes first to third openings OP1 to OP3. The description of the same elements and features as those of the embodiment described above will be omitted below, and the differences will be described.

[0176] The second capacitor electrode CPE2 may overlap with the first capacitor electrode CPE1, but may not overlap with the third connection pattern CE3. The second capacitor electrode CPE2 may not overlap with the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected. The second capacitor electrode CPE2 may not overlap with the third connection pattern CE3 and the third contact hole CT3 through which the source electrode SE2 of the second transistor ST2 is connected.

[0177] The thin film transistor layer may further include a first via layer VIA1 and a fourth metal layer MTL4. The first via layer VIA1 may be disposed on the passivation layer PV to flatten a step under the passivation layer PV.

[0178] The fourth metal layer MTL4 may be disposed on the first through-hole layer VIA1. The fourth metal layer MTL4 may include first to fourth connection electrodes CNE1 to CNE4. The first connection electrode CNE1 may be disposed in the first pixel SP1 and may overlap the first to third transistors ST1 to ST3 of the first pixel SP1. The first connection electrode CNE1 may overlap the first connection pattern CE1 and may be connected to the first connection pattern CE1 through a fifth contact hole CT5 formed through the passivation layer PV and the first through-hole layer VIA1. The second connection electrode CNE2 may be disposed in the second pixel SP2 and may overlap the first to third transistors ST1 to ST3 of the second pixel SP2. The second connection electrode CNE2 may overlap the fourth connection pattern CE4 and may be connected to the fourth connection pattern CE4 through a sixth contact hole CT6 formed through the passivation layer PV and the first through-hole layer VIA1. The third connection electrode CNE3 may be disposed in the third pixel SP3 and may overlap the first to third transistors ST1 to ST3 of the third pixel SP3. The third connection electrode CNE3 may overlap the seventh connection pattern CE7 and may be connected to the seventh connection pattern CE7 through a seventh contact hole CT7 formed through the passivation layer PV and the first via layer VIA1. The fourth connection electrode CNE4 may overlap the initialization voltage line VIL and the data line DL and extend parallel to the initialization voltage line VIL.

[0179] The first connection electrode CNE1 may overlap with the third connection pattern CE3 to form a capacitor. For example, the first connection electrode CNE1 may serve as an upper electrode of the capacitor, and the third connection pattern CE3 may serve as a lower electrode of the capacitor. Therefore, the first connection electrode CNE1 and the third connection pattern CE3 may form a capacitor.

[0180] In an embodiment, the first through hole layer VIA1 may include first to third openings OP1 to OP3. The first opening OP1 may overlap with the third connection pattern CE3 of the first pixel SP1 in a plan view, the second opening OP2 may overlap with the sixth connection pattern CE6 of the second pixel SP2 in a plan view, and the third opening OP3 may overlap with the ninth connection pattern CE9 of the third pixel SP3 in a plan view. The planar shapes and sizes of the first to third openings OP1 to OP3 may be the same as the shapes and sizes of the third connection pattern CE3, the sixth connection pattern CE6, and the ninth connection pattern CE9, respectively. However, the present disclosure is not limited thereto, and the planar sizes of the first to third openings OP1 to OP3 may also be larger than the planar sizes of the third connection pattern CE3, the sixth connection pattern CE6, and the ninth connection pattern CE9.

[0181] Taking the first opening OP1 of the first pixel SP1 as an example, the first opening OP1 may expose the passivation layer PV disposed under the first opening OP1. However, the present disclosure is not limited thereto, and the first opening OP1 may also be a region in which the first through-hole layer VIA1 is partially removed so as not to expose the passivation layer PV disposed under the first through-hole layer VIA1. The first opening OP1 may overlap the third contact hole CT3 and the fourth contact hole CT4. The first connection electrode CNE1 of the fourth metal layer MTL4 may extend from the upper surface of the first through-hole layer VIA1 to the passivation layer PV exposed through the first opening OP1, and may directly contact the passivation layer PV.

[0182] In the region where the first opening OP1 of the first through hole layer VIA1 is provided, a structure in which the third connection pattern CE3, the passivation layer PV, and the first connection electrode CNE1 are sequentially stacked may be formed. That is, the first through hole layer VIA1 between the third connection pattern CE3 and the first connection electrode CNE1 may be removed. Therefore, since the first through hole layer VIA1 is removed, only the passivation layer PV may be provided between the third connection pattern CE3 and the first connection electrode CNE1, thereby increasing the capacitance of the capacitor formed by the third connection pattern CE3 and the first connection electrode CNE1. In addition, the capacitance of the capacitor between the sixth connection pattern CE6 and the second connection electrode CNE2 of the second pixel SP2 and the capacitance of the capacitor between the ninth connection pattern CE9 and the third connection electrode CNE3 of the third pixel SP3 may be increased.

[0183] In the current embodiment, the first opening OP1 of the first via layer VIA1 overlaps the entirety of the third connection pattern CE3, but the present disclosure is not limited thereto. In some embodiments, the first opening OP1 of the first via layer VIA1 may overlap a portion of the third connection pattern CE3 overlapping the fourth contact hole CT4, or may overlap another portion of the third connection pattern CE3 overlapping the third contact hole CT3.

[0184] Fig.21 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment. Fig. 22 yes Fig.21 FIG. 1 is a diagram of a first capacitor C1 of a thin film transistor layer. Fig.21 The diagram goes through the Figure 8 The parts are cut in the same way as the parts of the structure.

[0185] refer to Fig.21 and Fig. 22 , the current embodiment and Figure 8The difference of the embodiment is that the thin film transistor layer further includes a first via layer VIA1 and a fourth metal layer MTL4. The structures of the first via layer VIA1 and the fourth metal layer MTL4 may correspond to those described above. Fig.17 and Fig.19 The structure in which the first to third openings OP1 to OP3 are not formed.

[0186] The first via layer VIA1 may be entirely disposed on the passivation layer PV. The first connection electrode CNE1 of the fourth metal layer MTL4 may be disposed on the first via layer VIA1 and may be connected to the first connection pattern CE1 through a fifth contact hole CT5 formed through the passivation layer PV and the first via layer VIA1.

[0187] In the current embodiment, the first connection electrode CNE1 of the fourth metal layer MTL4 may be further formed to form a capacitor with the third connection pattern CE3 overlapping the first connection electrode CNE1. For example, the first connection electrode CNE1 may be used as an upper electrode of the capacitor, and the third connection pattern CE3 may be used as a lower electrode of the capacitor. Therefore, the first connection electrode CNE1 and the third connection pattern CE3 may form a capacitor.

[0188] The first capacitor C1 of the first pixel SP1 may be formed not only between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1, but also between the first connection electrode CNE1 and the third connection pattern CE3. Therefore, the capacitance of the first capacitor C1 of each of the pixels SP1, SP2, and SP3 may be increased.

[0189] Fig.23 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment. Fig.23 The diagram goes through the Figure 8 The parts are cut in the same way as the parts of the structure.

[0190] refer to Fig.23 , the current embodiment and Figure 8 The difference of the embodiment is that the thin film transistor layer further includes a first through hole layer VIA1 and a fourth metal layer MTL4. Since the arrangement of the first to third openings OP1 to OP3 of the first through hole layer VIA1 and the fourth metal layer MTL4 is the same as that described above Figures 17 to 20 The arrangement is the same as in , and thus the current embodiment will be described using the first opening OP1 as an example.

[0191] Specifically, the second capacitor electrode CPE2 may overlap a portion of the third connection pattern CE3. For example, the second capacitor electrode CPE2 may overlap the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected. The second capacitor electrode CPE2 may not overlap the third connection pattern CE3 and the third contact hole CT3 through which the source electrode SE2 of the second transistor ST2 is connected.

[0192] The first via layer VIA1 may include a first opening OP1 overlapping the third connection pattern CE3. The first opening OP1 may overlap the third and fourth contact holes CT3 and CT4. The first connection electrode CNE1 of the fourth metal layer MTL4 may directly contact the passivation layer PV exposed through the first opening OP1.

[0193] The first capacitor C1 of the first pixel SP1 may be formed not only between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 and between the first capacitor electrode CPE1 and the first connection pattern CE1, but also between the first connection electrode CNE1 and the third connection pattern CE3. Therefore, the capacitance of the first capacitor C1 of each of the pixels SP1, SP2, and SP3 may be increased.

[0194] Furthermore, since the first via layer VIA1 is removed from the region where the first opening OP1 is disposed, only the passivation layer PV may be disposed between the third connection pattern CE3 and the first connection electrode CNE1, thereby further increasing the capacitance of the capacitor formed by the third connection pattern CE3 and the first connection electrode CNE1.

[0195] Fig.24 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment. Fig.25 is a diagram of a capacitor in a region where the third contact hole CT3 is provided. Fig.24 The diagram goes through the Fig.12 The parts are cut in the same way as the parts of the structure.

[0196] refer to Fig.24 and Fig.25 , the current embodiment and Fig.12 and Fig.13 The difference of the embodiment is that the thin film transistor layer further includes a first via layer VIA1 and a fourth metal layer MTL4. The structures of the first via layer VIA1 and the fourth metal layer MTL4 may correspond to those described above. Fig.21 structure.

[0197] The second capacitor electrode CPE2 may extend from under the first transistor ST1 to under the second transistor ST2. For example, the second capacitor electrode CPE2 may overlap the gate electrode GE1 and the source electrode SE1 of the first transistor ST1 and the source electrode SE2 of the second transistor ST2. In addition, the second capacitor electrode CPE2 may overlap the first connection pattern CE1 and the third connection pattern CE3 of the third metal layer MTL3.

[0198] The second capacitor electrode CPE2 may overlap with the third contact hole CT3 exposing the source electrode SE2 of the second transistor ST2. Specifically, the second capacitor electrode CPE2 may not overlap with the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected, and may overlap with the third connection pattern CE3 and the third contact hole CT3 through which the source electrode SE2 of the second transistor ST2 is connected.

[0199] The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 , between the first capacitor electrode CPE1 and the first connection pattern CE1 , and between the second capacitor electrode CPE2 and the source electrode SE2 of the second transistor ST2 .

[0200] The first via layer VIA1 may be entirely disposed on the passivation layer PV. The first connection electrode CNE1 of the fourth metal layer MTL4 may be disposed on the first via layer VIA1 and may be connected to the first connection pattern CE1 through a fifth contact hole CT5 formed through the passivation layer PV and the first via layer VIA1.

[0201] In the current embodiment, the first connection electrode CNE1 of the fourth metal layer MTL4 may be further formed to form a capacitor with the third connection pattern CE3 overlapping the first connection electrode CNE1 in a plan view. For example, the first connection electrode CNE1 may be used as an upper electrode of the capacitor, and the third connection pattern CE3 may be used as a lower electrode of the capacitor. Therefore, the first connection electrode CNE1 and the third connection pattern CE3 may form a capacitor.

[0202] The first capacitor C1 of the first pixel SP1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, between the first capacitor electrode CPE1 and the first connection pattern CE1, between the second capacitor electrode CPE2 and the source electrode SE2 of the second transistor ST2, and between the first connection electrode CNE1 and the third connection pattern CE3. Thus, the capacitance of the first capacitor C1 of each of the pixels SP1, SP2, and SP3 may be increased.

[0203] Fig.26 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment. Fig.26 The diagram goes through the Fig.24 The parts are cut in the same way as the parts of the structure.

[0204] refer to Fig.26 , the current embodiment and Fig.24 The difference of the embodiment is that the first through hole layer VIA1 of the thin film transistor layer includes the first to third openings OP1 to OP3. Since the arrangement of the first to third openings OP1 to OP3 is the same as that described above Figures 17 to 20 The arrangement is the same as in , and thus the current embodiment will be described using the first opening OP1 as an example.

[0205] The first via layer VIA1 may include a first opening OP1 overlapping the third connection pattern CE3. The first opening OP1 may expose the passivation layer PV disposed under the first opening OP1. The first opening OP1 may overlap the third contact hole CT3 and the fourth contact hole CT4. The first connection electrode CNE1 of the fourth metal layer MTL4 may directly contact the passivation layer PV exposed through the first opening OP1.

[0206] In the region where the first opening OP1 of the first via layer VIA1 is provided, a structure in which the third connection pattern CE3, the passivation layer PV, and the first connection electrode CNE1 are sequentially stacked may be formed. Since the first via layer VIA1 is removed from the region where the first opening OP1 of the first via layer VIA1 is provided, only the passivation layer PV may be provided between the third connection pattern CE3 and the first connection electrode CNE1, thereby further increasing the capacitance of the capacitor formed by the third connection pattern CE3 and the first connection electrode CNE1.

[0207] Fig. 27 is a cross-sectional view of a thin film transistor layer of a display device according to an embodiment. Fig. 27 The diagram goes through the Fig.16 The parts are cut in the same way as the parts of the structure.

[0208] refer to Fig. 27 , the current embodiment and Figures 14 to 16 The difference of the embodiment is that the thin film transistor layer further includes a first through hole layer VIA1 and a fourth metal layer MTL4. Since the arrangement of the first to third openings OP1 to OP3 of the first through hole layer VIA1 and the fourth metal layer MTL4 is the same as that described above Figures 17 to 20 The arrangement is the same as in , and thus the current embodiment will be described using the first opening OP1 as an example.

[0209] The second capacitor electrode CPE2 may overlap the gate electrode GE1 and the source electrode SE1 of the first transistor ST1 and the source electrode SE2 of the second transistor ST2. In addition, in a plan view, the second capacitor electrode CPE2 may overlap the first connection pattern CE1 and the third connection pattern CE3 of the third metal layer MTL3. The second capacitor electrode CPE2 may overlap the third contact hole CT3 and the fourth contact hole CT4 through which the third connection pattern CE3 connects the first capacitor electrode CPE1 and the source electrode SE2 of the second transistor ST2. Specifically, the second capacitor electrode CPE2 may overlap the third connection pattern CE3 and the fourth contact hole CT4 through which the first capacitor electrode CPE1 is connected, and may overlap the third contact hole CT3 through which the third connection pattern CE3 and the source electrode SE2 of the second transistor ST2 are connected.

[0210] The second capacitor electrode CPE2 may extend to overlap with the fourth contact hole CT4 and increase the overlapping area with the first capacitor electrode CPE1, thereby increasing the capacitance of the first capacitor C1. In addition, since the second capacitor electrode CPE2 further forms a capacitor with the source electrode SE2 of the second transistor ST2, the capacitance of the first capacitor C1 may be further increased.

[0211] The first via layer VIA1 may include a first opening OP1 overlapping the third connection pattern CE3 in a plan view. The first opening OP1 may overlap the third and fourth contact holes CT3 and CT4. The first connection electrode CNE1 of the fourth metal layer MTL4 may directly contact the passivation layer PV exposed through the first opening OP1.

[0212] The first capacitor C1 of the first pixel SP1 may be formed not only between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, between the first capacitor electrode CPE1 and the first connection pattern CE1, and between the second capacitor electrode CPE2 and the source electrode SE2 of the second transistor ST2, but also between the first connection electrode CNE1 and the third connection pattern CE3. Therefore, the capacitance of the first capacitor C1 of each of the pixels SP1, SP2, and SP3 may be increased. In addition, since the first through hole layer VIA1 is removed from the region where the first opening OP1 of the first through hole layer VIA1 is provided, only the passivation layer PV may be provided between the third connection pattern CE3 and the first connection electrode CNE1, thereby further increasing the capacitance of the capacitor formed by the third connection pattern CE3 and the first connection electrode CNE1.

[0213] Fig.28 is a plan view of a display device according to an embodiment. Fig.29 is along Fig.28 A cross-sectional view taken along line Q5-Q5'. Fig.28 Further shown is a pixel electrode layer ANEL, and Fig.29 A second via layer VIA2 , a pixel electrode layer ANEL, a pixel defining layer PDL, an organic layer ORL and a common electrode CE are further shown.

[0214] refer to Fig.28 and Fig.29 , the display device according to the embodiment may further include a second via layer VIA2 , a pixel defining layer PDL, and a light emitting element layer EML.

[0215] The second via layer VIA2 may be disposed on the first via layer VIA1 and the first to fourth connection electrodes CNE1 to CNE4 of the fourth metal layer MTL4. The second via layer VIA2 flattens a step under the second via layer VIA2 so that the light emitting element layer EML may be easily formed.

[0216] The light emitting element layer EML may be disposed on the second through hole layer VIA2. The light emitting element layer EML may include a pixel electrode layer ANEL, an organic layer ORL, and a common electrode CE. The pixel electrode layer ANEL may include first to third pixel electrodes ANE1 to ANE3 and a pixel auxiliary electrode ANEC. The first pixel electrode ANE1 may be connected to a pixel circuit of a first pixel SP1 through a first contact portion CTD1. For example, the first pixel electrode ANE1 may be connected to a first connection electrode CNE1 through a first contact portion CTD1. The second pixel electrode ANE2 may be connected to a pixel circuit of a second pixel SP2 through a second contact portion CTD2. For example, the second pixel electrode ANE2 may be connected to a second connection electrode CNE2 through a second contact portion CTD2. The third pixel electrode ANE3 may be connected to a pixel circuit of a third pixel SP3 through a third contact portion CTD3. For example, the third pixel electrode ANE3 may be connected to a third connection electrode CNE3 through a third contact portion CTD3. The pixel auxiliary electrode ANEC may be connected to a fourth connection electrode CNE4 through a fourth contact portion CTD4.

[0217] The pixel defining layer PDL may be disposed on the pixel electrode layer ANEL and the second via layer VIA2 to define pixels. For example, the pixel defining layer PDL may expose a portion of each of the pixel electrodes ANE1 to ANE3 to define an emission region of each of the pixels SP1 to SP3.

[0218] The organic layer ORL may be disposed on each of the pixel electrodes ANE1 to ANE3. The organic layer ORL may include at least an organic light emitting layer and may emit light of first to third colors. For example, the first pixel SP1 may emit light of a first color or red light, the second pixel SP2 may emit light of a second color or green light, and the third pixel SP3 may emit light of a third color or blue light.

[0219] The common electrode CE may be disposed on the pixel defining layer PDL and the organic layer ORL. The common electrode CE may be disposed in the entire display area DA to apply a common voltage (or the low potential voltage described above) to each of the pixels SP1 to SP3.

[0220] The display device according to the embodiment can increase capacitance by increasing the overlap area between the first capacitor electrode and the second capacitor electrode. In addition, the first connection electrode can be further formed to form a capacitor between the first connection electrode and the third connection pattern, thereby increasing capacitance.

[0221] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the inventive concept. Therefore, the preferred embodiments of the disclosed inventive concept are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, include: A first voltage line, disposed on the substrate and supplying a high potential voltage; a data line spaced apart from the first voltage line and supplying a data voltage; A first capacitor electrode is disposed between the first voltage line and the data line; a buffer layer, disposed on the first voltage line, the data line and the first capacitor electrode; a second capacitor electrode disposed on the buffer layer and the first capacitor electrode to overlap the first capacitor electrode in a plan view; A first transistor, disposed on the buffer layer and connected to the data line; an interlayer insulating layer disposed on the second capacitor electrode and the first transistor; and a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, The first connection pattern is connected to the second capacitor electrode through a first contact hole formed through the interlayer insulating layer, and is connected to the first transistor through a second contact hole formed through the interlayer insulating layer, and the first capacitor electrode overlaps the first connection pattern.

2. The display device according to claim 1, in, The first capacitor electrode overlaps the first contact hole and does not overlap the second contact hole.

3. The display device according to claim 1, in, The first capacitor electrode does not overlap the first contact hole and overlaps the second contact hole.

4. The display device according to claim 3, in, A capacitor is formed between the first capacitor electrode and a source electrode of the first transistor.

5. The display device according to claim 1, in, The first capacitor electrode overlaps the first contact hole and the second contact hole.

6. The display device according to any one of claims 1 to 5, further comprising: include: A second transistor is disposed on the buffer layer; and a second connection pattern overlapping the second transistor and disposed on the interlayer insulating layer, Wherein, the second transistor is electrically connected to the first voltage line.

7. The display device according to claim 6, further comprising: include: a first through hole layer, disposed on the first connection pattern and the second connection pattern; and A first connection electrode is disposed on the first via layer and connected to the second connection pattern through a third contact hole formed through the first via layer.

8. The display device according to claim 7, in, The first connection pattern, the first connection electrode, and the first capacitor electrode overlap each other in the plan view, and a capacitor is formed between the first connection pattern and the first connection electrode.

9. The display device according to claim 6, in, The second connection pattern is connected to the second transistor through a fourth contact hole formed through the interlayer insulating layer, and is connected to the first capacitor electrode through a fifth contact hole formed through the interlayer insulating layer and the buffer layer.

10. The display device according to claim 9, in, A capacitor is formed between the first capacitor electrode and the second capacitor electrode and between the second capacitor electrode and the second connection pattern.

11. A display device, include: A first voltage line, disposed on the substrate and supplying a high potential voltage; a data line spaced apart from the first voltage line and supplying a data voltage; A first capacitor electrode is disposed between the first voltage line and the data line; a buffer layer, disposed on the first voltage line, the data line and the first capacitor electrode; a second capacitor electrode disposed on the buffer layer to overlap the first capacitor electrode; A first transistor, disposed on the buffer layer and connected to the data line; a second transistor disposed on the buffer layer and connected to the first voltage line; an interlayer insulating layer disposed on the second capacitor electrode, the first transistor, and the second transistor; a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor; a second connection pattern disposed on the interlayer insulating layer and connected to the first capacitor electrode and the second transistor; a passivation layer, disposed on the first connection pattern and the second connection pattern; A first through-hole layer, disposed on the passivation layer; and a first connection electrode disposed on the first via layer and connected to the second connection pattern through a third contact hole formed through the passivation layer and the first via layer, wherein the first connection pattern is connected to the second capacitor electrode through a first contact hole formed through the interlayer insulating layer and is connected to the first transistor through a second contact hole formed through the interlayer insulating layer, the first through-hole layer includes an opening, the opening is arranged in a region corresponding to at least one of the first contact hole and the second contact hole in a plan view, and the first connection electrode is arranged on the first through-hole layer to cover the opening.

12. The display device according to claim 11, in, The opening of the first via layer is formed through the first via layer to expose an upper surface of the passivation layer, and the first connection electrode extends from the upper surface of the first via layer to the upper surface of the passivation layer.

13. The display device according to claim 11, in, The first connection electrode and the first connection pattern overlap each other in the plan view, and a capacitor is formed between the first connection electrode and the first connection pattern.

14. The display device according to claim 11, in, In the plan view, the opening of the first via layer is not provided in a region overlapping with the first capacitor electrode.

15. The display device according to claim 11, in, In the plan view, the first capacitor electrode overlaps with the first contact hole, and the opening of the first via layer is disposed in a region corresponding to the first contact hole and the first capacitor electrode.

16. The display device according to claim 11, in, The first capacitor electrode overlaps the first contact hole and the second contact hole, and the opening of the first via layer is disposed in a region corresponding to the first contact hole, the second contact hole, and the first capacitor electrode.

17. The display device according to claim 11, in, In the plan view, the first capacitor electrode overlaps with the second contact hole, and the opening of the first via layer overlaps with the second contact hole and the first capacitor electrode.

18. A display device, include: a first voltage line that supplies a high potential voltage and extends in a first direction; a data line supplying a data voltage and extending in the first direction; a first transistor electrically connected to the first voltage line; a first connection pattern connected to the first transistor; a first capacitor electrode electrically connected to the first connection pattern to receive the high potential voltage; a second transistor electrically connected to the data line; a second connection pattern connected to the second transistor; a second capacitor electrode connected to the second connection pattern to receive the data voltage; an interlayer insulating layer, provided between the first transistor and the first connection pattern and between the second transistor and the second connection pattern; and a buffer layer disposed between the first voltage line, the first capacitor electrode, the data line, and the first transistor and the second transistor, The second connection pattern is connected to the second capacitor electrode and the second transistor through a contact hole formed in the interlayer insulating layer, and the first capacitor electrode overlaps with the first transistor and the second capacitor electrode in a plan view and overlaps with at least one of the contact holes in the plan view.

19. The display device according to claim 18, in, The second capacitor electrode completely overlaps the first capacitor electrode in the plan view.

20. The display device according to claim 18, in, At least a portion of the second connection pattern and the first capacitor electrode overlap each other in the plan view.

21. The display device according to claim 18, further comprising: include: a passivation layer, disposed on the first connection pattern and the second connection pattern; A first through-hole layer, disposed on the passivation layer; and a first connection electrode disposed on the first via layer and electrically connected to the first connection pattern through a contact hole formed in the passivation layer and the first via layer, Wherein, the first connection electrode overlaps with the second connection pattern in the plan view.

22. The display device according to claim 21, further comprising: include: A second through hole layer, arranged on the first connecting electrode; a pixel electrode, disposed on the second through hole layer and electrically connected to the first connection electrode; An organic layer, disposed on the pixel electrode; and The common electrode is arranged on the organic layer.

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