Display substrate, preparation method thereof and display device

Abstract

The invention provides a display substrate which comprises a substrate body, a plurality of pixel units and a plurality of pixel units. The conductive wiring layer is positioned on one side of the substrate and comprises a plurality of fan-out lines; the driving function layer is located on the side, away from the substrate, of the conductive wiring layer and comprises a plurality of sub-pixel driving circuits and a plurality of signal supply lines used for providing signals for the sub-pixel driving circuits, and at least part of the signal supply lines are coupled with the corresponding fan-out lines. The invention further provides a preparation method of the display substrate and a display device.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display products are widely used due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility, and high luminous efficiency. As the OLED display market gradually expands, the demand for OLED special-shaped display products is also growing.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0005] substrate;

[0006] a conductive wiring layer, located on one side of the substrate, comprising a plurality of fan-out lines;

[0007] The driving function layer is located on the side of the conductive wiring layer away from the substrate, and includes: a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits, at least some of the signal supply lines are coupled to the corresponding fan-out lines.

[0008] In some embodiments, the driving function layer includes: a buffer layer, an active layer located on a side of the buffer layer away from the base substrate, and a first source-drain conductive layer located on a side of the active layer away from the base substrate; the sub-pixel driving circuit includes a plurality of transistors, active patterns of the transistors are located on the active layer, and the signal supply line is located on the first source-drain conductive layer;

[0009] The conductive wiring layer is located between the buffer layer and the base substrate.

[0010] In some embodiments, the fan-out line contacts the buffer layer.

[0011] In some embodiments, an orthographic projection of the fan-out line on the substrate does not overlap with an orthographic projection of the active pattern of the transistor on the substrate.

[0012] In some embodiments, the conductive wiring layer further includes a plurality of first connection terminals corresponding to the plurality of fan-out lines, and one end of the fan-out line is connected to the corresponding signal supply line through the corresponding first connection terminal.

[0013] In some embodiments, the base substrate includes: a display area and a first peripheral area and a second peripheral area located around the display area, the first peripheral area and the second peripheral area are located on opposite sides of the display area in a first direction, and the second peripheral area includes a binding area;

[0014] The first connecting terminal is located in the first peripheral area.

[0015] In some embodiments, the signal supply line extends along the first direction.

[0016] In some embodiments, the fan-out line is made of a metal material, and the melting point of the metal material is greater than 580°C.

[0017] In some embodiments, the sheet resistance of the fan-out line is less than or equal to 0.05Ω / □.

[0018] In some embodiments, the thickness of the fan-out line comprises:

[0019] In some embodiments, the plurality of signal supply lines include a plurality of data lines;

[0020] The plurality of fan-out lines include: a plurality of data fan-out lines, and the data fan-out lines are coupled to corresponding data lines.

[0021] In some embodiments, the plurality of signal supply lines include a plurality of reference signal lines;

[0022] The plurality of fan-out lines include a plurality of reference fan-out lines, wherein the reference fan-out lines are coupled to corresponding reference signal lines.

[0023] In some embodiments, the sub-pixel driving circuit includes: a driving sub-circuit and a light emitting control sub-circuit coupled to each other;

[0024] The plurality of sub-pixel driving circuits are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group including two sub-pixel driving circuits arranged along a first direction, the two sub-pixel driving circuits in the same sub-pixel driving circuit group reuse the same light emitting control sub-circuit, and the light emitting control sub-circuit is used to control the two coupled driving sub-circuits to respectively output corresponding driving signals;

[0025] The plurality of signal supply lines include a plurality of data lines, and the data lines extend along the first direction.

[0026] In some embodiments, the two driving sub-circuits in the same sub-pixel driving circuit group are arranged axially symmetrically, and the axis of symmetry extends along a second direction, and the second direction intersects the first direction.

[0027] In some embodiments, the base substrate includes: a display area, the sub-pixel driving circuit is located in the display area;

[0028] The two sub-pixel driving circuits in the same sub-pixel driving circuit group are adjacent to each other in the first direction;

[0029] The fan-out line includes: at least one first portion located in the display area and extending along a first direction, wherein an orthographic projection of the first portion on the driving function layer is located between two adjacent sub-pixel driving circuit groups in a second direction.

[0030] In some embodiments, at least part of the fan-out line further includes: at least one second portion located in the display area and extending along the second direction, the orthographic projection of the second portion on the driving function layer being located between two adjacent sub-pixel driving circuit groups in the first direction.

[0031] In some embodiments, the driving subcircuit includes: a first transistor, a second transistor, a third transistor, a storage capacitor, and a driving transistor, and the light emitting control subcircuit includes: a light emitting control transistor;

[0032] The control electrode of the first transistor is coupled to the first scan line, the first electrode of the first transistor is coupled to the data line, and the second electrode of the first transistor is coupled to the control electrode of the driving transistor;

[0033] The control electrode of the second transistor is coupled to the second scan line, the first electrode of the second transistor is coupled to the reference signal line, and the second electrode of the second transistor is coupled to the control electrode of the driving transistor;

[0034] A control electrode of the third transistor is coupled to the third scan line, a first electrode of the third transistor is coupled to the initialization signal line, and a second electrode of the third transistor is coupled to the second electrode of the driving transistor;

[0035] The control electrode of the light emitting control transistor is coupled to the light emitting control signal line, the first electrode of the light emitting control transistor is coupled to the power line, and the second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor;

[0036] The second electrode of the driving transistor is coupled to the anode pattern of the corresponding light emitting element;

[0037] The first electrode of the storage capacitor is coupled to the control electrode of the driving transistor, and the second electrode of the storage capacitor is coupled to the second electrode of the driving transistor.

[0038] In some embodiments, the display substrate further comprises:

[0039] a second planarization layer, located on a side of the driving function layer away from the base substrate;

[0040] The light-emitting element layer and the pixel defining layer are located on the side of the second planarization layer away from the base substrate. The light-emitting element layer includes: a plurality of light-emitting elements. The pixel defining layer is provided with a plurality of sub-pixel accommodating holes corresponding to the light-emitting elements one by one. The light-emitting elements are located in the corresponding sub-pixel accommodating holes. The anode pattern of the light-emitting element is coupled to the corresponding sub-pixel driving circuit.

[0041] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: the display substrate provided in the first aspect above.

[0042] In a third aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0043] providing a substrate;

[0044] forming a conductive wiring layer on one side of the base substrate, wherein the conductive wiring layer includes a plurality of fan-out lines;

[0045] A driving function layer is formed on a side of the conductive wiring layer away from the base substrate, and the driving function layer includes: a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits, at least some of the signal supply lines are coupled to the corresponding fan-out lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0047] FIG1A is a schematic top view of a display substrate according to an embodiment of the present disclosure;

[0048] FIG1B is a schematic cross-sectional view showing a portion of a substrate in an embodiment of the present disclosure;

[0049] FIG2 is a schematic diagram of a circuit structure of a sub-pixel driving circuit in an embodiment of the present disclosure;

[0050] FIG3 is a schematic diagram of a circuit structure of a sub-pixel driving circuit group according to an embodiment of the present disclosure;

[0051] FIG4 is a schematic diagram of a layout of area S in FIG1A ;

[0052] FIG5 is a schematic diagram of a layout of a conductive wiring layer in an embodiment of the present disclosure;

[0053] FIG6 is a schematic diagram of a layout of an active layer in an embodiment of the present disclosure;

[0054] FIG7 is a schematic diagram of a layout of the first gate conductive layer in an embodiment of the present disclosure;

[0055] FIG8 is a schematic diagram of a layout of the second gate conductive layer in an embodiment of the present disclosure;

[0056] FIG9 is a schematic diagram of a layout of the first source-drain conductive layer in an embodiment of the present disclosure;

[0057] FIG10 is a schematic diagram of a layout of the second source-drain conductive layer in an embodiment of the present disclosure;

[0058] FIG11 is a schematic diagram of a layout of a conductive wiring layer and an active layer in a disclosed embodiment;

[0059] FIG12 is a schematic diagram of a layout of an anode pattern layer in a disclosed embodiment;

[0060] FIG13 is a schematic diagram of a layout of a pixel definition layer according to an embodiment of the present disclosure;

[0061] FIG14 is a schematic flow chart of a method for preparing a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the technical solution of the present invention, a display substrate, a preparation method thereof, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0063] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register unit, a gate driving circuit, a display panel, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0064] The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "include" or "comprise" and similar terms mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "coupled" or "connected" and similar terms are not limited to physical or mechanical coupling, but may include electrical connections, whether direct or indirect.

[0065] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the coupling methods of the drain and source of each transistor can be interchangeable. Therefore, there is actually no difference between the drain and source of each transistor in the embodiments of the present disclosure. Here, only to distinguish the two poles of the transistor other than the control pole (i.e., the gate), one of the poles is called the drain and the other pole is called the source. The thin film transistor used in the embodiments of the present disclosure can be an N-type transistor or a P-type transistor. In the embodiments of the present disclosure, when an N-type thin film transistor is used, its first pole can be the source and the second pole can be the drain. In the following embodiments, the thin film transistor is an N-type transistor as an example for description.

[0066] In this disclosure, an "active-level signal" refers to a signal that, when input to the control electrode of a transistor, can turn the transistor on; an "inactive-level signal" refers to a signal that, when input to the control electrode of a transistor, can turn the transistor off. For N-type transistors, a high-level signal is an active-level signal, and a low-level signal is an inactive-level signal. For P-type transistors, a low-level signal is an active-level signal, and a high-level signal is an inactive-level signal.

[0067] In the following description, an N-type transistor is used as an example. In this case, an active level signal refers to a high level signal, and an inactive level signal refers to a low level signal. It is conceivable that when a P-type transistor is used, the timing of the control signal needs to be adjusted accordingly. The specific details are not detailed here, but are intended to be within the scope of this disclosure.

[0068] In addition, the light-emitting element in the embodiment of the present disclosure is a current-driven light-emitting element, and the light-emitting element is an organic light-emitting diode as an example for illustrative description in the embodiment of the present disclosure.

[0069] To achieve narrow or ultra-narrow bezels, a related art design called "Fanout in Active Area" (FIA) has been proposed. This design places the fanout lines used to transmit signals to the signal supply lines located in the active area (AA area). The FIA ​​design is particularly suitable for anisotropic displays, such as hexagonal, circular, and heart-shaped displays.

[0070] In related art, fan-out lines (also known as fanout lines) are designed between a sub-pixel driver circuit and a light-emitting element layer, which includes multiple light-emitting elements. Specifically, a second source-drain conductive layer and a second planarization layer are provided between the sub-pixel driver circuit and the light-emitting element layer. The second planarization layer is located between the second source-drain conductive layer and the light-emitting element layer. The second source-drain conductive layer includes conductive connections for connecting the sub-pixel driver circuit and the light-emitting elements, and the fanout lines are located in the second source-drain conductive layer.

[0071] Based on the above, it can be seen that there is only one second planarization layer between the fanout lines and the anode pattern layer (including the anode patterns of multiple light-emitting elements), making it difficult to achieve planarization using this second planarization layer. In particular, in locations where fanout lines are relatively dense, the portion of the second planarization layer covering the densely distributed fanout lines exhibits a noticeable upward bulge. In this case, the flatness of the anode pattern in the anode pattern layer located above the second planarization layer is also poor. For example, different anode patterns may be located in different planes, and different locations on the surface of the same anode pattern on the side away from the substrate may have different steps perpendicular to the substrate. The poor flatness of the anode pattern in the anode pattern layer can lead to significant metallic reflections in the anode pattern layer and uneven display across the light-emitting element layer.

[0072] In order to effectively improve the above-mentioned technical problem of poor flatness of the anode pattern layer caused by the fanout line, the present disclosure provides a corresponding solution.

[0073] Figure 1A is a schematic top view of a display substrate according to an embodiment of the present disclosure. Figure 1B is a schematic cross-sectional view of a portion of a display substrate according to an embodiment of the present disclosure. Figure 2 is a schematic circuit structure diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure. Figure 3 is a schematic circuit structure diagram of a sub-pixel driving circuit group according to an embodiment of the present disclosure. Figure 4 is a schematic layout diagram of area S in Figure 1A. Figure 5 is a schematic layout diagram of a conductive wiring layer according to an embodiment of the present disclosure. Figure 6 is a schematic layout diagram of an active layer according to an embodiment of the present disclosure. Figure 7 is a schematic layout diagram of a first gate conductive layer according to an embodiment of the present disclosure. Figure 8 is a schematic layout diagram of a second gate conductive layer according to an embodiment of the present disclosure. Figure 9 is a schematic layout diagram of a first source and drain conductive layer according to an embodiment of the present disclosure. Figure 10 is a schematic layout diagram of a second source and drain conductive layer according to an embodiment of the present disclosure. Figure 11 is a schematic layout diagram of a conductive wiring layer and an active layer according to an embodiment of the present disclosure. Figure 12 is a schematic layout diagram of an anode pattern layer according to an embodiment of the present disclosure. Figure 13 is a schematic layout diagram of a pixel defining layer according to an embodiment of the present disclosure. As shown in Figures 1A to 13, the display substrate includes: a base substrate 1, a conductive wiring layer 2, and a driving function layer 1000.

[0074] The base substrate 1 can be a flexible substrate (such as a resin substrate) or a rigid substrate (such as a glass substrate). The shape of the base substrate 1 can be a conventional rectangle or a special shape, such as

[0075] The conductive wiring layer 2 is located on one side of the base substrate 1, and the conductive wiring layer 2 includes a plurality of fan-out lines 20. The number and position distribution of the fan-out lines 20 can be designed and adjusted accordingly according to actual needs.

[0076] The driving function layer 1000 is located on the side of the conductive wiring layer 2 away from the base substrate 1, and includes: multiple sub-pixel driving circuits 100 and multiple signal supply lines for providing signals to the sub-pixel driving circuits 100, at least some of the signal supply lines are coupled to the corresponding fan-out lines 20.

[0077] In an embodiment of the present disclosure, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a coupled sub-pixel driving circuit 100 and a light-emitting element OLED. The sub-pixel driving circuit is used to provide a driving signal to the corresponding light-emitting element OLED to drive the light-emitting element OLED to emit light. The present disclosure does not limit the specific circuit structure of the sub-pixel driving circuit 100; for example, the 5T1C mentioned later (including 5 transistors and 1 capacitor) can be used, or other circuit structures can be used. The 5T1C mentioned later is only an optional implementation scheme in the embodiment of the present disclosure, and it does not limit the technical solution of the present disclosure.

[0078] In the embodiment of the present disclosure, the sub-pixel driving circuit located in the driving function layer in the related art is moved downwardly to a position between the driving function layer 1000 and the base substrate 1, away from the fan-out line 20 (specifically, the second source-drain conductive layer in the driving function layer), so that the film layer between the fan-out line 20 and the second planarization layer 18 is increased. The film layer located between the fan-out line 20 and the second planarization layer 18 can be used to perform a certain degree of planarization on the area where the fan-out line 20 is located, thereby alleviating the adverse effect of the fan-out line 20 on the flatness of the second planarization layer 18 and improving the overall flatness of the second planarization layer 18. Correspondingly, the flatness of the anode pattern layer 8 located on the second planarization layer 18 can also be effectively improved. Therefore, the problem of obvious metal reflection in the anode pattern layer 8 and uneven display of the light-emitting element layer as a whole due to the poor flatness of the anode pattern layer 8 can be effectively improved or even completely solved.

[0079] In some embodiments, the driving function layer 1000 includes: a buffer layer 11, an active layer 3 located on the side of the buffer layer 11 away from the base substrate 1, and a first source-drain conductive layer 6 located on the side of the active layer 3 away from the base substrate 1. The sub-pixel driving circuit 100 includes a plurality of transistors T1 to T5, the active patterns 31 to 35 of the transistors T1 to T5 are located in the active layer 3, the signal supply line is located in the first source-drain conductive layer 6, and the conductive wiring layer 2 is located between the buffer layer 11 and the base substrate 1.

[0080] In some embodiments, the fan-out line 20 is in contact with the buffer layer 11 .

[0081] As shown in FIG11 , in some embodiments, the orthographic projection of the fan-out line 20 on the base substrate 1 does not overlap with the orthographic projection of the active pattern of the transistor ( FIG11 shows an example of the active patterns 31 to 35 of the first transistor T1 to the third transistor T3, the light-emitting control transistor T4, and the driving transistor T5) on the base substrate 1 .

[0082] In the embodiment of the present disclosure, the fan-out line 20 is arranged between the buffer layer 11 and the base substrate 1. At this time, there is a height difference between the surface of the portion of the buffer layer 11 covering the fan-out line 20 and the surface of the portion of the buffer layer 11 not covering the fan-out line 20 and the surface of the portion of the buffer layer 11 not covering the fan-out line 20 and the surface of the portion of the buffer layer 11 not covering the fan-out line 20; that is, the surface flatness of the buffer layer 11 is poor. At this time, if the active pattern of the transistor covers the height difference position, it will cause a height difference on the active pattern of the transistor, and the active pattern of the transistor will be uneven, which will affect the electrical characteristics of the transistor; if the fan-out line 20 is located directly above the active pattern of the transistor, the signal loaded in the fan-out line 20 will have a certain impact on the carrier distribution in the active pattern, affecting the electrical characteristics of the transistor.

[0083] In order to effectively solve the above technical problems, the technical solution disclosed in the present invention ensures that the orthographic projection of the fan-out line 20 on the substrate 1 and the orthographic projection of the active pattern of the transistor on the substrate 1 do not overlap, which can effectively avoid the unevenness of the active pattern of the transistor and avoid the influence of the signal loaded in the fan-out line 20 on the carriers in the active pattern.

[0084] In addition, in actual applications, if the conductive wiring layer 2 is too thick, it will cause obvious protrusions on the buffer layer 11, which is not conducive to the subsequent process. If the conductive wiring layer 2 is too thin, the overall resistance of the fan-out line 20 will be too large, which is not conducive to signal transmission. Based on the dual considerations of the preparation process and the overall resistance of the fan-out line 20, in some embodiments, the thickness of the conductive wiring layer 2 is set at: For example,

[0085] In some embodiments, the sheet resistance of the fan-out line 20 is less than or equal to 0.05Ω / □.

[0086] In the embodiment disclosed herein, after completing the preparation process of the active layer 3, the semiconductor material (such as low-temperature polycrystalline silicon material) in the active layer 3 will be lattice repaired to repair the lattice damage of the active layer 3 caused by ion doping, repair the silicon dangling bonds on the surface of the active layer 3, and activate the doped ions.

[0087] During the lattice repair process, a high temperature environment (generally 580° C.) is formed. To prevent the fan-out line 20 from melting, in some embodiments, the fan-out line is made of a metal material with a melting point greater than 580° C.

[0088] Furthermore, to ensure the electrical stability of the fan-out line 20, the metal material selected should be resistant to oxidation under the high temperatures generated by the lattice repair process, meaning it should have good resistance to high-temperature oxidation. As an example, the fan-out line material uses a three-layer metal stack structure of molybdenum-aluminum-molybdenum (traditional titanium, while having a higher melting point, is easily oxidized at high temperatures).

[0089] In some embodiments, the conductive wiring layer 2 further includes a plurality of first connection terminals 205 corresponding to the plurality of fan-out lines 20 , and one end of the fan-out line 20 is connected to the corresponding signal supply line through the corresponding first connection terminal 205 .

[0090] In some embodiments, the base substrate 1 includes: a display area 1a and a first peripheral area 1c and a second peripheral area 1b located around the display area 1a. The first peripheral area 1c and the second peripheral area 1b are respectively located on opposite sides of the display area 1a in the first direction Y. The second peripheral area 1b includes a binding area, and a binding terminal is provided in the binding area to bind the electronic device (such as a driver chip, a flexible circuit board, etc.) to the display substrate; the first connecting terminal 205 is located in the first peripheral area 1c, that is, the first connecting terminal 205 is located on the side of the display area 1a opposite to the binding area.

[0091] In the embodiment of the present disclosure, one end of the fan-out line 20 is connected to the first connection terminal 205, and the other end of the fan-out line 20 is connected to the second connection terminal (not shown) located in the second peripheral area 1b; in some embodiments, the second connection terminal can specifically be a pin of the driver chip or a binding terminal.

[0092] In some implementations, the signal supply lines extend along a first direction Y. In some embodiments, the plurality of signal supply lines include a plurality of data lines 62; the plurality of fan-out lines 20 include a plurality of data fan-out lines 201-203, with the data fan-out lines 20 coupled to corresponding data lines 62. In some embodiments, the plurality of signal supply lines include a plurality of reference signal lines 63; the plurality of fan-out lines 20 include a plurality of reference fan-out lines 204, with the reference fan-out lines 20 coupled to corresponding reference signal lines 63. This will be described in detail below with reference to specific examples.

[0093] 2 , 3 and 5 , in some embodiments, the sub-pixel driving circuit includes: a driving sub-circuit 101 and a light-emitting control sub-circuit 102 coupled to each other; a plurality of sub-pixel driving circuits 100 are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group includes two sub-pixel driving circuits 100 arranged along a first direction Y, and the two sub-pixel driving circuits 100 in the same sub-pixel driving circuit group reuse the same light-emitting control sub-circuit 102, and the light-emitting control sub-circuit 102 is used to control the two coupled driving sub-circuits 101 to output corresponding driving signals respectively; the plurality of signal supply lines include a plurality of data lines 62, and the data lines 62 extend along the first direction Y.

[0094] In the embodiment of the present disclosure, two sub-pixel driving circuits within the same sub-pixel driving circuit group reuse the same light-emitting control sub-circuit, thereby reducing the number of light-emitting control sub-circuits provided on the display substrate and effectively reducing the layout space of each sub-pixel driving circuit group, which is conducive to achieving high resolution of the display device.

[0095] In some embodiments, the two driving sub-circuits 101 within the same sub-pixel driving circuit group are arranged axially symmetrically, with the axis of symmetry extending along a second direction X, where the second direction X intersects the first direction Y. As an example, the second direction X is perpendicular to the first direction Y. In the disclosed embodiments, the two driving sub-circuits 101 within the same sub-pixel driving circuit group are arranged axially symmetrically, which can effectively reduce the layout space occupied by the sub-pixel driving circuit group, thereby facilitating high resolution of the display device.

[0096] In some embodiments, two adjacent sub-pixel driving circuits 100 in the second direction X are symmetrically arranged, and the axis of symmetry is along the first direction Y.

[0097] In some embodiments, two sub-pixel driving circuits 100 located in the same sub-pixel driving circuit group are adjacent in the first direction Y; the fan-out line 20 includes: at least one first portion 20a located in the display area 1a and extending along the first direction Y, and the orthographic projection of the first portion 20a on the driving function layer 1000 is located between the two sub-pixel driving circuit groups adjacent in the second direction X.

[0098] In some embodiments, at least part of the fan-out line 20 further includes: at least one second portion 20b located within the display area 1a and extending along the second direction X, and the positive projection of the second portion 20b on the driving function layer 1000 is located between two adjacent sub-pixel driving circuit groups in the first direction Y.

[0099] That is, the fan-out line 20 in the embodiment of the present disclosure includes at least a portion extending along the first direction Y, and may also include a portion extending along the second direction X, and the fan-out line 20 is always located between the sub-pixel driving circuit groups. Such a design can effectively prevent the signal loaded in the fan-out line 20 from interfering with the sub-pixel driving circuit 100, thereby improving the operating stability of the sub-pixel driving circuit.

[0100] In some embodiments, the driving sub-circuit 101 includes: a first transistor T1 , a second transistor T2 , a third transistor T3 , a storage capacitor Cst and a driving transistor T5 , and the light emitting control sub-circuit 102 includes: a light emitting control transistor T4 .

[0101] The control electrode of the first transistor T1 is coupled to the first scan line 41 , the first electrode of the first transistor T1 is coupled to the data line 62 , and the second electrode of the first transistor T1 is coupled to the control electrode of the driving transistor T5 .

[0102] The control electrode of the second transistor T2 is coupled to the second scan line 42 , the first electrode of the second transistor T2 is coupled to the reference signal line 63 , and the second electrode of the second transistor T2 is coupled to the control electrode of the driving transistor T5 .

[0103] A control electrode of the third transistor T3 is coupled to the third scan line 43 , a first electrode of the third transistor T3 is coupled to the initialization signal line 51 , and a second electrode of the third transistor T3 is coupled to the second electrode of the driving transistor T5 .

[0104] A control electrode of the light emitting control transistor T4 is coupled to the light emitting control signal line 44 , a first electrode of the light emitting control transistor T4 is coupled to the power line VDD, and a second electrode of the light emitting control transistor T4 is coupled to a first electrode of the driving transistor T5 .

[0105] The second electrode of the driving transistor T5 is coupled to the anode pattern of the corresponding light emitting element OLED.

[0106] A first plate Cst1 of the storage capacitor Cst is coupled to the control electrode of the driving transistor T5 , and a second electrode of the storage capacitor Cst is coupled to the second electrode of the driving transistor T5 .

[0107] 2 , 12 , and 13 , in some embodiments, the display substrate further comprises: a second planarization layer 18 , a light-emitting element OLED layer, and a pixel defining layer 9 . The second planarization layer 18 is located on the side of the driving function layer 1000 away from the base substrate 1 ; the light-emitting element OLED layer and the pixel defining layer 9 are located on the side of the second planarization layer 18 away from the base substrate 1 ; the light-emitting element OLED layer comprises: a plurality of light-emitting elements OLED, the light-emitting element OLED comprising an anode pattern 80 , a light-emitting layer 19 , and a cathode layer 10 , wherein the cathode layer 10 is laid over the entire surface. The pixel defining layer 9 comprises a plurality of sub-pixel accommodating holes 90 corresponding one to one to the light-emitting elements OLED, the light-emitting elements OLED (light-emitting layer 19) being located within the corresponding sub-pixel accommodating holes 90 , and the anode pattern 80 of the light-emitting element OLED being coupled to the corresponding sub-pixel driving circuit 100 .

[0108] In some embodiments, the anode pattern 80 can be made of a metal material (eg, silver) or a laminated structure of a metal material and a transparent conductive material (eg, indium tin oxide-silver-indium tin oxide). The cathode layer 10 can be made of a transparent conductive material (eg, indium tin oxide).

[0109] The functional layers of the display substrate in the embodiment of the present disclosure will be described in detail below with reference to FIG. 1B and FIG. 4 to FIG. 11 .

[0110] As an example, the display substrate includes a plurality of pixels arranged in an array along a first direction Y and a second direction X, and each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along the second direction X. The data line 62 connected to the first sub-pixel is a first data line 621, the data line 62 connected to the second sub-pixel is a second data line 622, and the data line 62 connected to the third sub-pixel is a third data line 623.

[0111] 1B , the driving function layer 1000 includes a buffer layer 11, an active layer 3, a first gate insulating layer 12, a first gate conductive layer 4, a second gate insulating layer 13, a second gate conductive layer 5, an interlayer dielectric layer 14, a first source-drain conductive layer 6, a first planarizing layer 15, a first passivation layer 16, a second source-drain conductive layer 7, a second passivation layer 17, and a second planarizing layer 18, which are arranged in sequence away from the base substrate 1.

[0112] The buffer layer 11, the first gate insulating layer 12, the second gate insulating layer 13, the interlayer dielectric layer 14, the first passivation layer 16, and the second passivation layer 17 can each be made of at least one of silicon oxide and silicon nitride. The first planarization layer 15 and the second planarization layer 18 can both be made of resin.

[0113] As shown in FIG5 , as an example, the conductive wiring layer 2 may be made of a three-layer metal stack structure of molybdenum, aluminum, and molybdenum. The conductive wiring layer 2 includes a first data fan-out line 201 for providing a signal to the first data line 621, a second data fan-out line 202 for providing a signal to the second data line 622, a third data fan-out line 203 for providing a signal to the third data line 623, and a reference fan-out line 204 for providing a signal to the reference signal line 63.

[0114] Based on the above situation, it can be seen that the film layers located between the conductive wiring layer 2 and the anode electrode layer 8 and capable of effectively covering the fan-out line 20 include: a buffer layer 11, a first gate insulation layer 12, a second gate insulation layer 13, an interlayer dielectric layer 14, a first planarization layer 15 and a second planarization layer 18. Such a plurality of covering film layers can better planarize the area where the fan-out line 20 is located.

[0115] 6 and 11 , the active layer 3 includes a first active pattern 31 of the first transistor T1, a second active pattern 32 of the second transistor T2, a third active pattern 33 of the third transistor T3, a fourth active pattern 34 of the light emitting control transistor T4, and a fifth active pattern 35 of the driving transistor T5.

[0116] In some embodiments, the active layer 3 further includes a reference connection portion 36 , which extends along the second direction X. The first electrode of the second transistor T2 is coupled to the reference signal line 63 through the reference connection portion 36 .

[0117] Within the same sub-pixel driving circuit group, the two first active patterns 31 are symmetrically arranged about an axis of symmetry parallel to the second direction X, the two second active patterns 32 are symmetrically arranged about an axis of symmetry parallel to the second direction X, the two third active patterns 33 are symmetrically arranged about an axis of symmetry parallel to the second direction X, the two fourth active patterns 34 are symmetrically arranged about an axis of symmetry parallel to the second direction X, and the two fifth active patterns 35 are symmetrically arranged about an axis of symmetry parallel to the second direction X. The two reference connection portions 3636 corresponding to the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X.

[0118] In two adjacent sub-pixel driving circuits along the second direction X, the two first active patterns 31 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two second active patterns 32 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two third active patterns 33 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two fourth active patterns 34 are symmetrically arranged about a symmetry axis parallel to the first direction Y, and the two fifth active patterns 35 are symmetrically arranged about a symmetry axis parallel to the first direction Y.

[0119] 11 , the orthographic projections of the data fan-out lines 201 - 203 and the reference fan-out line 204 in the conductive wiring layer 2 on the base substrate 1 do not overlap with the orthographic projections of the active patterns 31 - 35 of the transistors in the active layer 3 on the base substrate 1 .

[0120] In some embodiments, the multiple data fan-out lines configured for two adjacent pixels along the second direction X are symmetrically arranged about an axis of symmetry parallel to the first direction Y. Referring to Figures 4, 5, and 11, each pixel unit is configured with three data fan-out lines 201-203. The three data fan-out lines 201-203 configured for the pixel on the left side of the figures are symmetrical with the three data fan-out lines 201-203 configured for the pixel on the right side of the same figures about an axis of symmetry parallel to the first direction Y. More specifically, the first data fan-out line 201 configured for the pixel on the left side of Figures 4, 5, and 11 is symmetrical with the third data fan-out line 203 configured for the pixel on the right side, the second data fan-out line 202 configured for the pixel on the left side is symmetrical with the second data fan-out line 202 configured for the pixel on the right side, and the third data fan-out line 203 configured for the pixel on the left side is symmetrical with the first data fan-out line 201 configured for the pixel on the right side.

[0121] As shown in FIG7 , the material of the first gate conductive layer 4 includes a metal material, such as molybdenum. The first gate conductive layer 4 includes a first scan line 41, a second scan line 42, a third scan line 43, a light control signal line 44, a power connection portion, and a first plate Cst1 of a storage capacitor. The first scan line 41, the second scan line 42, the third scan line 43, the light control signal line 44, and the power connection portion 45 all extend along the second direction X.

[0122] The portion of the first scan line 41 that overlaps with the first active pattern 31 serves as the control electrode of the first transistor T1. The portion of the second scan line 42 that overlaps with the second active pattern 32 serves as the control electrode of the second transistor T2. The portion of the third scan line 43 that overlaps with the third active pattern 33 serves as the control electrode of the third transistor T3. The portion of the light-emission control signal line 44 that overlaps with the fourth active pattern 34 serves as the control electrode of the light-emission control transistor T4. The portion of the first plate Cst1 of the storage capacitor that overlaps with the fifth active pattern 35 serves as the control electrode of the drive transistor T5. The power connection portion 45 is used to electrically connect to a power line VDD to be formed later.

[0123] The first plates Cst1 of the two storage capacitors in the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X. The two first scan lines 41 corresponding to the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X, the two second scan lines 42 are symmetrically arranged about an axis of symmetry parallel to the second direction X, and the two third scan lines 43 are symmetrically arranged about an axis of symmetry parallel to the second direction X.

[0124] In two adjacent sub-pixel driving circuits 100 along the second direction X, the first plates Cst1 of the two storage capacitors are symmetrically arranged about a symmetry axis parallel to the first direction Y.

[0125] 8 , the second gate conductive layer 5 is made of a metal material, such as molybdenum. The second gate conductive layer 5 includes an initialization signal line 51 and a second plate Cst2 of the storage capacitor. The initialization signal line 51 extends along the second direction X.

[0126] The second plates Cst2 of the two storage capacitors in the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X. The two reference connection portions 3636 corresponding to the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X; and the two initialization signal lines 51 corresponding to the same sub-pixel driving circuit group are symmetrically arranged about an axis of symmetry parallel to the second direction X.

[0127] In two adjacent sub-pixel driving circuits 100 along the second direction X, the second plates Cst2 of the two storage capacitors are symmetrically arranged about a symmetry axis parallel to the first direction Y.

[0128] As shown in FIG9 , the material of the first source-drain conductive layer 6 includes a metal material, such as titanium-aluminum-titanium. The first source-drain conductive layer 6 includes a first data line 62, a second data line 62, a third data line 62, a reference signal line 63, a power line VDD, a first conductive connection 60, a first conductive pattern 64, a second conductive pattern 65, a third conductive pattern 66, a fourth conductive pattern 67, a fifth conductive pattern 68, and a sixth conductive pattern 69.

[0129] Among them, the first electrode of the driving transistor T5 is connected to the second electrode of the light-emitting control transistor T4 through the first conductive pattern 64; the power connection part 45 is connected to the first electrode of the light-emitting control transistor T4 through the second conductive pattern 65; the second electrode of the driving transistor T5 is connected to the second electrode plate Cst2 through the third conductive pattern 66, the reference connection part 36 is connected to the first electrode of the second transistor T2 through the fourth conductive pattern 67, and the first electrode of the third transistor T3 is connected to the initialization signal line 51 through the fifth conductive pattern 68; the second electrode of the first transistor T1 is respectively connected to the control electrode of the driving transistor T5 and the second electrode of the second transistor T2 through the sixth conductive pattern 69; the second electrode of the third transistor T3 is connected to the second electrode plate Cst2 of the storage capacitor through the first conductive connection part 60.

[0130] In the same sub-pixel driving circuit group 100, the two first conductive patterns 64 are symmetrically arranged about a symmetry axis parallel to the second direction X, the two third conductive patterns 66 are symmetrically arranged about a symmetry axis parallel to the second direction X, the two fourth conductive patterns 67 are symmetrically arranged about a symmetry axis parallel to the second direction X, the two fifth conductive patterns 68 are symmetrically arranged about a symmetry axis parallel to the second direction X, the two sixth conductive patterns 69 are symmetrically arranged about a symmetry axis parallel to the second direction X, and the two first conductive connecting portions 60 are symmetrically arranged about a symmetry axis parallel to the second direction X.

[0131] In two adjacent sub-pixel driving circuits along the second direction X, the two first conductive patterns 64 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two second conductive patterns 65 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two third conductive patterns 66 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two fourth conductive patterns 67 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two fifth conductive patterns 68 are symmetrically arranged about a symmetry axis parallel to the first direction Y, the two sixth conductive patterns 69 are symmetrically arranged about a symmetry axis parallel to the first direction Y, and the two first conductive connecting portions 60 are symmetrically arranged about a symmetry axis parallel to the first direction Y.

[0132] As shown in FIG10 , the material of the second source-drain conductive layer 7 includes a metal material, such as titanium-aluminum-titanium. The second source-drain conductive layer 7 includes a second conductive connection portion 70. The second electrode of the third transistor T3 is connected to the anode electrode of the corresponding light-emitting element OLED via the second conductive connection portion 70.

[0133] In the same sub-pixel driving circuit group, the two second conductive connection portions 70 are symmetrically arranged about a symmetry axis parallel to the second direction X.

[0134] In two adjacent sub-pixel driving circuits 100 along the second direction X, the two second conductive connection portions 70 are symmetrically arranged about a symmetry axis parallel to the first direction.

[0135] Based on the same inventive concept, the present disclosure also provides a method for preparing a display substrate, which can be used to prepare the display substrate provided in the above embodiments. FIG14 is a schematic flow chart of a method for preparing a display substrate provided in the present disclosure. As shown in FIG14 , the preparation method includes:

[0136] Step S1: providing a substrate.

[0137] Step S2: forming a conductive wiring layer on one side of the substrate, wherein the conductive wiring layer includes a plurality of fan-out lines.

[0138] Step S3: forming a driving function layer on a side of the conductive wiring layer away from the substrate, the driving function layer including: a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits, at least some of the signal supply lines being coupled to corresponding fan-out lines.

[0139] Among them, step S3 may specifically include the steps of forming a buffer layer, forming an active layer, forming a first gate insulating layer, forming a first gate conductive layer, forming a second gate insulating layer, forming a second gate conductive layer, forming an interlayer dielectric layer, forming a first source-drain conductive layer, forming a first planarization layer, forming a first passivation layer, forming a second source-drain conductive layer, forming a second passivation layer and forming a second planarization layer.

[0140] For the detailed description of the above steps S1 to S3, please refer to the corresponding contents in the previous embodiments, which will not be repeated here.

[0141] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display substrate. The display substrate can adopt the display substrate in the previous embodiment. For the specific description of the display substrate, please refer to the content in the previous embodiment and will not be repeated here.

[0142] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.; wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0143] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, wherein: include: substrate; a conductive wiring layer, located on one side of the substrate, comprising a plurality of fan-out lines; The driving function layer is located on the side of the conductive wiring layer away from the substrate, and includes: a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits, at least some of the signal supply lines are coupled to the corresponding fan-out lines.

2. The display substrate according to claim 1, wherein The driving function layer includes: a buffer layer, an active layer located on a side of the buffer layer away from the base substrate, and a first source-drain conductive layer located on a side of the active layer away from the base substrate; the sub-pixel driving circuit includes a plurality of transistors, active patterns of the transistors are located on the active layer, and the signal supply line is located on the first source-drain conductive layer; The conductive wiring layer is located between the buffer layer and the base substrate.

3. The display substrate according to claim 2, wherein: The fan-out line contacts the buffer layer.

4. The display substrate according to claim 2 or 3, wherein: The orthographic projection of the fan-out line on the substrate does not overlap with the orthographic projection of the active pattern of the transistor on the substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: The conductive wiring layer further includes a plurality of first connection terminals corresponding to the plurality of fan-out lines, and one end of the fan-out line is connected to the corresponding signal supply line through the corresponding first connection terminal.

6. The display substrate according to claim 5, wherein: The base substrate includes: a display area and a first peripheral area and a second peripheral area located around the display area, the first peripheral area and the second peripheral area are located on opposite sides of the display area in a first direction, and the second peripheral area includes a binding area; The first connecting terminal is located in the first peripheral area.

7. The display substrate according to claim 6, wherein: The signal supply line extends along the first direction.

8. The display substrate according to any one of claims 1 to 7, wherein: The fan-out line is made of a metal material, and the melting point of the metal material is greater than 580°C.

9. The display substrate according to any one of claims 1 to 8, wherein: The sheet resistance of the fan-out line is less than or equal to 0.05Ω / □.

10. The display substrate according to any one of claims 1 to 9, wherein: The thickness of the fan-out line includes:

11. The display substrate according to any one of claims 1 to 10, wherein: The plurality of signal supply lines include a plurality of data lines; The plurality of fan-out lines include: a plurality of data fan-out lines, and the data fan-out lines are coupled to corresponding data lines.

12. The display substrate according to any one of claims 1 to 11, wherein: The plurality of signal supply lines include a plurality of reference signal lines; The plurality of fan-out lines include: a plurality of reference fan-out lines, the reference fan-out lines and the corresponding The reference signal lines are coupled.

13. The display substrate according to any one of claims 1 to 12, wherein: The sub-pixel driving circuit includes: a driving sub-circuit and a light emitting control sub-circuit coupled to each other; The plurality of sub-pixel driving circuits are divided into a plurality of sub-pixel driving circuit groups, each sub-pixel driving circuit group including two sub-pixel driving circuits arranged along a first direction, the two sub-pixel driving circuits in the same sub-pixel driving circuit group reuse the same light emitting control sub-circuit, and the light emitting control sub-circuit is used to control the two coupled driving sub-circuits to respectively output corresponding driving signals; The plurality of signal supply lines include a plurality of data lines, and the data lines extend along the first direction.

14. The display substrate according to claim 13, wherein: The two driving sub-circuits in the same sub-pixel driving circuit group are arranged axially symmetrically, and the symmetry axis extends along a second direction, and the second direction intersects the first direction.

15. The display substrate according to claim 13 or 14, wherein: The base substrate comprises: a display area, wherein the sub-pixel driving circuit is located in the display area; The two sub-pixel driving circuits in the same sub-pixel driving circuit group are adjacent to each other in the first direction; The fan-out line includes: at least one first portion located in the display area and extending along a first direction, wherein an orthographic projection of the first portion on the driving function layer is located between two adjacent sub-pixel driving circuit groups in a second direction.

16. The display substrate according to claim 15, wherein: At least part of the fan-out line further includes: at least one second portion located in the display area and extending along the second direction, the orthographic projection of the second portion on the driving function layer being located between two adjacent sub-pixel driving circuit groups in the first direction.

17. The display substrate according to any one of claims 13 to 16, wherein: The driving sub-circuit includes: a first transistor, a second transistor, a third transistor, a storage capacitor and a driving transistor, and the light emitting control sub-circuit includes: a light emitting control transistor; The control electrode of the first transistor is coupled to the first scan line, the first electrode of the first transistor is coupled to the data line, and the second electrode of the first transistor is coupled to the control electrode of the driving transistor; The control electrode of the second transistor is coupled to the second scan line, the first electrode of the second transistor is coupled to the reference signal line, and the second electrode of the second transistor is coupled to the control electrode of the driving transistor; A control electrode of the third transistor is coupled to the third scan line, a first electrode of the third transistor is coupled to the initialization signal line, and a second electrode of the third transistor is coupled to the second electrode of the driving transistor; The control electrode of the light emitting control transistor is coupled to the light emitting control signal line, the first electrode of the light emitting control transistor is coupled to the power line, and the second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor; The second electrode of the driving transistor is coupled to the anode pattern of the corresponding light emitting element; The first electrode of the storage capacitor is coupled to the control electrode of the driving transistor, and the second electrode of the storage capacitor is coupled to the second electrode of the driving transistor.

18. The display substrate according to any one of claims 1 to 17, wherein: Also includes: a second planarization layer, located on a side of the driving function layer away from the base substrate; The light emitting element layer and the pixel defining layer are located on the side of the second planarization layer away from the base substrate. The light emitting element layer includes: a plurality of light emitting elements; A plurality of sub-pixel accommodating holes corresponding to the light-emitting elements are provided, the light-emitting elements are located in the corresponding sub-pixel accommodating holes, and the anode patterns of the light-emitting elements are coupled to the corresponding sub-pixel driving circuits.

19. A display device, wherein: include: A display substrate as claimed in any one of claims 1 to 18.

20. A method for preparing a display substrate according to any one of claims 1 to 18, wherein: include: providing a substrate; forming a conductive wiring layer on one side of the base substrate, wherein the conductive wiring layer includes a plurality of fan-out lines; A driving function layer is formed on a side of the conductive wiring layer away from the base substrate, and the driving function layer includes: a plurality of sub-pixel driving circuits and a plurality of signal supply lines for providing signals to the sub-pixel driving circuits, at least some of the signal supply lines are coupled to the corresponding fan-out lines.

Images