Single thread detection of efficient synchronization heads

Abstract

An integrated circuit having an interface circuit is described. During operation, the interface circuit may receive a signal corresponding to a header of a frame compatible with a serial communication protocol, where the received signal includes a temporal pattern of bins having instances of dominant and recessive signal levels. The interface circuit may then calculate, based at least in part on the received signal, a set of conditions, where, when valid, the set of conditions identifies a first dominant bit of the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the interface circuit may: determine a position of a synchronization field in the header relative to the identified first dominant bit; and calculating a Baud rate of the received signal based at least in part on a subset of bins in the synchronization field.

Description

Technical Field

[0001] The present disclosure relates to techniques for communicating using a serial communication protocol. Background Art

[0002] In serial communications, a receiving electronic device (sometimes referred to as a "slave device") that supports autobaud may need to extract the baud rate from the synchronization header in the frame. The synchronization header is usually subject to the communication protocol to ensure the detection or identification of an incorrectly interpreted synchronization header without losing a valid synchronization header. For example, the local interconnect network (LIN) is a single-wire serial communication protocol for communication between components in a vehicle. The LIN specification expects the slave device to always detect the "break and synchronization" (or "break+sync") sequence or field in the synchronization header, which is transmitted by another electronic device (sometimes referred to as a "master device"). Moreover, valid detection of the "break+sync" field can cause or enable detection of what baud rate the master device wants to communicate at. In addition, a frame in LIN communication can be initiated by a master device, and the frame can start with a break field, followed by a synchronization byte field (e.g., which can include eight synchronization bits). This sequence is unique in the LIN communication protocol and can ensure that the slave device detects the start of a new frame. Figure 1 presents an example of an existing break field and a synchronization (break+synch) field in a frame compatible with the LIN communication protocol.

[0003] However, if for any reason the slave device becomes confused (e.g., does not know whether it is currently detecting a "break+sync" field), then the slave device may miss a valid "break+sync" field with a separate start point or time. This undesirable situation may also be caused by a momentary short to ground. It is worth noting that a short to ground may cause a dominant (or low) bit to appear on the LIN bus for tens of milliseconds. This may confuse the slave device, for example, because an incorrect "break" field may be detected, and a subsequent real break may be mistaken for the start bit of the synchronization field.

[0004] To recover from such scenarios and be able to detect a valid "break+sync" field, a controller or control logic in the receiver circuit in the slave device can start a thread that treats each dominant or extended low (e.g., "0") bit as a possible break field. The controller can then continue to verify the sync field unless the sync verification fails (in which case the thread is released or ended). From a hardware perspective, even if the maximum number of threads is a bounded problem, the cost of implementing a multi-threading approach can be significantly higher than a single-threaded approach. Summary of the invention

[0005] Embodiments of an integrated circuit are described. Such an integrated circuit includes: an interface circuit for use with an electronic device. During operation, the interface circuit receives a signal corresponding to a header of a frame compatible with a serial communication protocol, wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels. The interface circuit then calculates a set of conditions based at least in part on the received signal, wherein, when valid, the set of conditions identifies a first dominant bit of the binary bits having a dominant signal level. Furthermore, when the set of conditions is valid, the interface circuit: determines a position of a synchronization field in the header relative to the identified first dominant bit; and calculates a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0006] Note that the serial communication protocol may include a Local Interconnect Network (LIN) communication protocol.

[0007] Furthermore, the dominant signal level may be smaller than the recessive signal level.

[0008] In addition, the set of conditions may include a first instance of the first condition, wherein, when valid, the first instance of the first condition may include that a second dominant bit time of a second dominant bit having a dominant signal level in a binary bit is less than or equal to a first predefined multiple of a first dominant bit time of a first dominant bit, and the first dominant bit may precede the second dominant bit. For example, the first predefined multiple may include 1.25. Alternatively, the set of conditions may include a second condition, and, when valid, the second condition may include that a sum of the second dominant bit time and a first recessive bit time of a first recessive bit having a recessive signal level in a binary bit is greater than or equal to a second predefined multiple of the first dominant bit time. Note that the first recessive bit may be located between the first dominant bit and the second dominant bit.

[0009] In some embodiments, the second predefined multiple includes a ratio of 2 and 11. Alternatively or additionally, the set of conditions may include a second instance of the first condition, wherein, when valid, the second instance of the first condition may include that a third dominant bit time of a third dominant bit having a dominant signal level in the binary bit is less than or equal to a first predefined multiple of a second dominant bit time of the second dominant bit, and the second dominant bit may precede the third dominant bit. Note that the set of conditions may include a third condition, wherein, when valid, the third condition may include that the third dominant bit time is greater than or equal to a third predefined multiple of the second dominant bit time.

[0010] Also, the third predefined multiple may include 0.75.

[0011] Alternatively or additionally, the set of conditions may include a fourth condition. When valid, the fourth condition may include that the sum of the second recessive bit time of the second recessive bit in the binary bit and the third dominant bit time is greater than or equal to a third predefined multiple of the average bit time of a pair of bits in the binary bit, and the sum is less than or equal to the first predefined multiple of the average bit time. Note that the third dominant bit may precede the second recessive bit, and the pair of bits may include the first recessive bit and a dominant bit selected from the group including the first dominant bit, the second dominant bit, and the third dominant bit. In some embodiments, the first predefined multiple includes 1.25 and the third predefined multiple includes 0.75.

[0012] Another embodiment provides a vehicle including the integrated circuit.

[0013] Another embodiment provides a system including the integrated circuit.

[0014] Another embodiment provides a computer-readable storage medium having program instructions for use with an electronic device. When the program instructions are executed by the electronic device, the program instructions cause the electronic device to perform at least some of the operations mentioned above in one or more of the aforementioned embodiments.

[0015] Another embodiment provides a method for selectively calculating a baud rate of a received signal. The method includes at least some of the operations performed by an integrated circuit.

[0016] The present invention is provided for the purpose of illustrating some exemplary embodiments, so as to provide a basic understanding of some aspects of the subject matter described herein. Thus, it will be appreciated that the above-mentioned features are examples and should not be interpreted as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects and advantages of the subject matter described herein will become clear from the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] 1 is a timing diagram illustrating an example of an existing break field and a synchronization (break+synch) field in a frame compatible with a Local Interconnect Network (LIN) communication protocol.

[0018] Figure 2 is a timing diagram illustrating an example in which a valid “break+sync” sequence or field cannot be detected when an unexpected event is present, according to some embodiments of the present disclosure.

[0019] Figure 3 is a diagram illustrating an example of a state machine using predefined conditions for state transitions according to some embodiments of the present disclosure.

[0020] Figure 4is a diagram illustrating some embodiments of the present disclosure Figure 3 FIG. 5 is a diagram of an example of a synchronized (SYN) state in a state machine of FIG.

[0021] Figure 5 is a timing diagram illustrating an example of signals received during LIN communications according to some embodiments of the present disclosure.

[0022] Figure 6 is a timing diagram illustrating an example of signals received during LIN communications according to some embodiments of the present disclosure.

[0023] Figure 7 is a timing diagram illustrating an example of signals received during LIN communications according to some embodiments of the present disclosure.

[0024] Figure 8 is a timing diagram illustrating an example of signals received during LIN communications according to some embodiments of the present disclosure.

[0025] Fig. 9 is a timing diagram illustrating an example of signals received during LIN communications according to some embodiments of the present disclosure.

[0026] Fig.10 is a block diagram illustrating an example of an integrated circuit according to some embodiments of the present disclosure.

[0027] Fig.11 is a flow chart illustrating an example of a method for selectively calculating a baud rate of a received signal according to some embodiments of the present disclosure.

[0028] Note that like reference numerals refer to corresponding parts throughout all figures. Also, multiple instances of the same part are designated by a common prefix separated from the instance number by a dash. DETAILED DESCRIPTION

[0029] An integrated circuit for use with an electronic device is described. Such an integrated circuit may include an interface circuit. During operation, the interface circuit may receive a signal corresponding to a header of a frame compatible with a serial communication protocol, wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal, wherein, when valid, the set of conditions identifies a first dominant bit in the binary bits having a dominant signal level. Furthermore, when the set of conditions is valid, the interface circuit may: determine a position of a synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0030] By correctly identifying the location of the synchronization field and determining the baud rate, these circuit techniques can improve serial communications, for example, using the LIN communication protocol. It is worth noting that the circuit techniques can allow a receiving electronic device using a serial communication protocol to recover from an unexpected state on the bus and detect a valid synchronization header (such as an "interrupt + synchronization" sequence or field) in a frame. Therefore, the circuit techniques can improve the reliability and performance of serial communications. Therefore, the circuit techniques can make communications performed by electronic devices more robust and reliable, thereby promoting the use of integrated circuits in various systems, electronic devices, and applications, such as in vehicles. For example, the integrated circuit can be used in assisted or automatic (or self) driving of a vehicle.

[0031] We now describe an embodiment of a circuit technique. The circuit technique may allow an integrated circuit to selectively calculate a baud rate of a received signal. During operation, the integrated circuit may receive a signal corresponding to a header of a frame compatible with a serial communication protocol (such as a LIN communication protocol), wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels. The integrated circuit may then calculate a set of conditions based at least in part on the received signal, wherein, when valid, the set of conditions identifies a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the integrated circuit may: determine a position of a synchronization field in the header relative to the identified first dominant bit; and calculate the baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0032] The disclosed circuit technique can ensure detection of a valid sync header despite unexpected state transitions on the LIN bus.

[0033] As discussed previously, a slave device may need to detect a "break+sync" sequence or field in order to identify the start of a frame and subsequently determine or derive the baud rate of the current transmission. The LIN specification includes several conditions that can help the slave device successfully detect a "break+sync" sequence or field. It is worth noting that the synchronization field (sometimes referred to as the "sync field") will follow the break field. Moreover, the break field can have a width or duration of at least 11 times the LIN bit time (therefore, there can be an upper limit on the length or duration of the break field. Such as in the LIN specification). (However, 11 is used as an illustrative example, and more generally, the width or duration can be M times the LIN bit time, where M is a non-zero integer.) In addition, although it is not included in the LIN specification, the sync field bits can be compared to each other based at least in part on the tolerance specified by the LIN.

[0034] As expected in the LIN specification, the slave device can detect the "break+sync" sequence or field in various situations. In fact, it is expected that the integrated circuit that complies with the LIN specification guarantees the detection of the "break+sync" sequence or field in various scenarios. For example, if a screwdriver shorts to the ground of the LIN bus when used to replace a component, an unusual scenario may occur. This short circuit to the ground appears as a dominant bit on the LIN bus and may have a random width or duration. If the dominant bit is long (e.g., 10ms) and followed by an actual or real break field (for a 20k baud rate, its duration should be longer than 550μs), the slave device may become confused and may treat the short circuit to the ground pulse as a break field and the actual break field as the start bit of the sync field. In this scenario, the slave device may assume that the sync byte (0x55) will be followed by the least significant bit (LSB) first. Depending on the implementation, the start bit of the sync field can be ignored and two sync bits (a recessive bit and a dominant bit) can be used for comparison to check the validity of the "break+sync" sequence or field. It is worth noting that two consecutive or adjacent bits of the sync field can be used together for comparison to avoid differences in the rise and fall times of the receiving circuitry in the slave device. For this comparison, the slave device can use two bits of time relative to the break field to ensure that the break field is greater than or equal to 11 times the average sync bit time or duration. It is worth noting that some integrated circuits can use the start bit (or dominant bit) of the sync field and the first recessive bit (the least significant bit of the sync byte) for comparison. In either of these scenarios, it is realized during the reception of the sync field or byte that the short to ground is not a break field. This is usually too late for the slave device to return to the actual break and start treating it as the start of a "break+sync" sequence or field. Therefore, in these scenarios, the slave device may lose the entire frame. Figure 2 Timing diagrams illustrating examples where a valid "break+sync" sequence or field cannot be detected when unexpected events are present are presented.

[0035] To address these issues, the slave device can use multithreading. Notably, each dominant bit can be processed as if it were a break field, and subsequent bits can be evaluated as if they were part of a sync field. Furthermore, the slave device can continue to verify the sync field against the assumed break field until a valid "break+sync" field is received. When this happens (and therefore, when verification fails), the thread can be freed up for a new detection. Because there are six dominant bits in the "break+sync" field, the slave device may need at least six threads to ensure that no dominant bits are missed in the break field.

[0036] Note that the multithreading approach may be implemented using multiple instances of the receiving circuit in the slave device. While an incremental improvement may occur, the multithreading approach may still require starting a new thread by assuming that each dominant bit is a potential interrupt field.

[0037] Alternatively, in order to solve the above-mentioned problem, improved single thread can be used from the device. In these methods, one or more aspects or characteristics of the LIN communication protocol and predefined comparisons can be used from the device to realize the desired result in a single thread. Compared with the multithreading method, these methods can provide reduced cost and complexity.

[0038] In an improved single-threaded approach, it may be important to optimize the receiving circuit without compromising the ability to detect the occurrence of a "break+sync" sequence or field. Furthermore, in a single-threaded approach, one or more of the following aspects or features of the LIN communication protocol may be used:

[0039] The interrupt field can always precede the sync field;

[0040] Dominant bits alone cannot be used in comparisons to represent LIN bit times. (It is important to note that because the rise and fall times of the receiving circuit can vary significantly, a dominant or recessive bit can be shorter or longer than expected. However, individual dominant bits can be used to make comparisons between them because the rise and fall time differences in the receiving circuit affect each dominant bit in the same way.)

[0041] The width or duration of the break field may be at least 11 times the average LIN bit time received during the sync field;

[0042] The duration or width of the new bit pair (dominant bit and recessive bit) of the sync field can be kept within a predefined amount or range of twice the average bit time. (More generally, twice can be replaced by N times, where N is an even non-zero integer. For example, depending on system requirements, the predefined range can be ±25% or ±12.5%. More generally, the predefined range can be between 1+P and 1-P, where P is a decimal between 0 and 0.4.);

[0043] The dominant bit comparison can be subdivided to evaluate potential break fields when a "break+sync" detection fails within the same compare cycle; and / or

[0044] Memory cells may be used to hold previous or historical information for detecting a valid "break+sync" field, so that automatic baud detection may be optimized to use, for example, two memory cells or registers. (Note that, for example, the information in two memory cells may be tracked by the same state machine that tracks the progress of "break+sync" field detection.)

[0045] Note that, although the LIN communication protocol is used as an illustrative example in this discussion, the disclosed circuit techniques can be used with other serial communication protocols other than the LIN communication protocol. It is noteworthy that the circuit techniques can be used with other serial communication protocols where it is desirable to detect synchronization patterns to avoid frame loss.

[0046] As discussed previously, LIN-compatible slave devices may support automatic baud detection or determination. This capability allows the slave device to derive or determine the baud rate (or bit rate) of the transmission from the "break+sync" field detected in the synchronization header of the frame. Moreover, the LIN specification defines the synchronization bit to have a relationship with the break field to help the slave device detect a valid "break+sync" field. The current LIN specification does not define the maximum duration of the break field. This degree of freedom constrains the controller or control logic in the receiving circuit or associated with the receiving circuit in the slave device to assume that the dominant bit is a break field, and then continue to verify them when receiving subsequent sync bits. However, when there is a short circuit, the resulting signal glitch may be assumed to be an interrupt field, and the controller may continue and verify the sync field. Therefore, the glitch associated with the short circuit may be large enough to confuse the controller, thinking that the real or actual interrupt is a sync bit. Therefore, in this process, the controller may lose the real or actual interrupt, and thus may lose the frame.

[0047] In some embodiments, the "break+sync" field detection is performed using a state machine that tracks the incoming LIN bits and continuously searches for a valid "break+sync" field using predefined conditions, including:

[0048] COND1: TLy+THy≥2 / 11TLx,

[0049] COND2: 3 / 4mean(T)≤Ty≤5 / 4mean(T),

[0050] COND3: TLy ≥ 3 / 4TLx, and

[0051] COND4: TLy≤5 / 4TLx,

[0052] where x is the previous dominant or recessive bit, y is the current dominant or recessive bit, TLx is the previous dominant bit time, TLy is the current dominant bit time, THy is the current recessive bit, Ty is the sum of TLy and Thy or the sum of the most recent dominant bit time and recessive bit time, and mean(T) is the average two-bit time for the first few pairs of bits (one dominant bit and one recessive bit) in the sync field.

[0053] Note that COND1 can ensure that the width or duration of the interrupt field is at least 11 times the sum of the start bit representing the LIN bit time plus half of the first least significant byte of the sync byte. Moreover, COND2 can ensure that the sync field bits are within a bounded or predefined range from each other. In addition, COND3 can compare the current dominant bit with the previous dominant bit, which ideally should have the same width, and when both dominant bits are from the sync field, the inequality can be true. However, when this comparison is false (or not true), then there may be a situation where the previous dominant bit x is the interrupt field and the current dominant bit y may be the start bit of the sync field. In addition, COND4 can compare the current dominant bit with the previous dominant bit, which ideally should have the same width, and when both dominant bits are from the sync field, the inequality can be true. However, when this comparison is false (or not true), then there may be a situation where the current dominant bit y is the interrupt field.

[0054] Figure 3 A diagram illustrating an example of a state machine that uses the predefined conditions mentioned above to make state transitions is presented. Note that RE is a rising edge, IDLE is the default state, BREAK is a possible break received, SYN is getting a sync field, and RECEIVED indicates that a valid break+sync was received. Also, note that the SYN state is a state machine that indicates how many sync fields have been verified. Figure 4 The diagram is presented Figure 3 FIG. 5 is a diagram of an example of the SYN state in a state machine.

[0055] like Figure 3 As shown in , if any of the predefined conditions evaluates to sync_fail, then the state machine can move to the BRK state, in which the previously saved break field value will be replaced by the most recently received dominant bit.

[0056] In some embodiments, the receiving circuit may include a counter that counts the dominant and recessive bit widths in system clocks. Furthermore, there may be two registers, REG1 and REG2, that may be used to save or store various values ​​during processing of received signals to facilitate evaluation of predefined conditions (such as inequality checks) and to help determine the baud rate from the sync field when a valid "break+sync" field is received. It is noteworthy that REG1 may save or store a potential break field count in IDL and SYN0, while at other times it may save or store an average of two bit times (one dominant bit and one recessive bit). Additionally, REG2 may save or store the last dominant bit received.

[0057] Although examples of numerical values ​​are provided in the foregoing discussion, different numerical values ​​are used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0058] We now present, by way of example, timing diagrams illustrating various scenarios of zero or more failures in the predefined conditions. In scenario 1, none of the predefined conditions fail (an ideal scenario). Figure 5 It is shown in Figure 5 A timing diagram illustrating an example of signals received during LIN communications is presented. Figure 5-Figure 9 , an instance of operation 510 involves checking COND1, an instance of operation 512 involves checking COND2, an instance of operation 514 involves checking COND3, and an instance of operation 516 involves checking COND4. Note that in Figure 5 , operation 510-1 detects a break, which establishes that the break field is at least 11 bit times, in operation 512-1 the bit size is compared to the bit period and aggregated, operation 516-1 is a rough check that this dominant bit is less than the previous dominant bit and the sequence value is considered a break+sync bit for the sync field, and operations 514-1 and 516-2 are dominant bit comparisons to ensure that they are the same size.

[0059] Moreover, in scenario 2, COND1 fails. This Figure 6 It is shown in Figure 6 A timing diagram illustrating an example of signals received during LIN communications is presented. Note that the failure of COND1 in operation 510-1 is essentially a sync_fail condition that causes the state machine to enter the BRK state where the previous break is replaced by the most recently received dominant bit.

[0060] Furthermore, in scenario 3, COND2 fails. This Figure 7 It is shown in Figure 7A timing diagram illustrating an example of signals received during LIN communication is presented. Note that in operation 512-1, the failure of COND2 is essentially a snyc_fail condition, which causes the state machine to enter the BRK state, in which the previous interrupt is replaced by the most recently received dominant bit. Also note that in operation 516-3, the sync_fail condition causes the state machine to enter the BRK state, in which the previous interrupt is replaced by the most recently received dominant bit.

[0061] Furthermore, in scenario 4, COND3 fails. This Figure 8 It is shown in Figure 8 A timing diagram illustrating an example of signals received during LIN communication is presented.In operation 514-1, failure of COND3 causes the state machine to enter state SYN0 where the previous dominant bit becomes an interrupt and the current dominant bit serves as the start bit of the sync field.

[0062] In scenario 5, COND4 fails. This Fig. 9 It is shown in Fig. 9 A timing diagram illustrating an example of signals received during LIN communications is presented. In operation 516-3, the failure of COND4 is a synch_fail condition that causes the state machine to enter the BRK state where the previous interrupt is replaced by the most recently received dominant bit.

[0063] As discussed above, an integrated circuit may at least partially implement circuit technology. Fig.10 A block diagram illustrating an example of an integrated circuit 1000 is presented. This integrated circuit may include an interface circuit 1010 that includes a receiving circuit 1012. In some embodiments, the receiving circuit 1012 may include: an analog front end (such as a preamplifier); an analog-to-digital converter (ADC); one or more detection channels that implement one or more detection techniques; a clock; and control logic to configure and manage the detection circuit. Note that there may be dedicated detection channels in the one or more detection channels for measurements performed by a given integrated circuit. Alternatively or additionally, one or more detection channels may be shared when analyzing measurements performed by different integrated circuits.

[0064] Note that, Fig.10 Not all connections between components are shown. Furthermore, integrated circuit 1000 may include fewer or additional components; two or more components may be combined; a single component may be split into two or more components; and / or the position of one or more components may be changed.

[0065] We now describe an embodiment of the method. Fig.11A flow chart illustrating an example of a method 1100 for selectively calculating a baud rate of a received signal is presented. Such a method may be performed by an integrated circuit such as an interface circuit.

[0066] During operation, the interface circuit may receive a signal corresponding to a header of a frame compatible with a serial communication protocol (operation 1110), wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal (operation 1112), wherein, when valid, the set of conditions identifies a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid (operation 1114), the interface circuit may: determine a position of a synchronization field in the header relative to the identified first dominant bit (operation 1116); and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field (operation 1118). Otherwise (operation 1114), the interface circuit may perform a recovery to operation 1110.

[0067] In some embodiments of method 1100, there may be additional or fewer operations. Furthermore, the order of the operations may be changed, and / or two or more operations may be combined into one operation.

[0068] The disclosed integrated circuits and circuit techniques may be (or may be included in) any electronic device or system. For example, the electronic device may include: a cellular phone or smart phone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook, a media player device, an electronic book device, device, smart watch, wearable computing device, portable computing device, consumer electronic device, camera or image sensor, access point, router, switch, communications equipment, test equipment, vehicle, drone, boat, airplane, car, truck, bus, motorcycle, manufacturing equipment, farm equipment, construction equipment, or another type of electronic device.

[0069] Although specific components are used to describe embodiments of an integrated circuit, in alternative embodiments, different components and / or subsystems may be present in the integrated circuit. Thus, embodiments of the integrated circuit may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more positions of one or more components may be changed, and / or different types of components may be present.

[0070] Moreover, the circuits and components in the embodiments of the integrated circuit can be implemented using any combination of analog and / or digital circuit systems, including: bipolar, PMOS and / or NMOS gates or transistors. In addition, the signals in these embodiments can include digital signals with approximately discrete values ​​and / or analog signals with continuous values. In addition, the components and circuits may be single-ended or differential, and the power supply may be unipolar or bipolar. It is noted that the electrical coupling or connection in the previous embodiments may be direct or indirect. In the previous embodiments, the single line corresponding to the route may indicate one or more single lines or routes.

[0071] As mentioned above, an integrated circuit can implement some or all of the functions of the circuit technology. This integrated circuit can include hardware and / or software mechanisms for implementing the functions associated with the circuit technology.

[0072] In some embodiments, the output of the process for designing an integrated circuit or a part of an integrated circuit including one or more of the circuits described herein can be a computer-readable medium, such as, for example, a tape or an optical disk or a disk. The computer-readable medium can be encoded with a data structure or other information describing the circuit system, which can be physically instantiated as an integrated circuit or a part of an integrated circuit. Although various formats can be used for such encoding, these data structures are usually written in the following formats: Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA) or Open Artwork System Interchange Standard (OASIS). Technicians in the field of integrated circuit design can develop such data structures from the schematic diagrams of the types detailed above and the corresponding descriptions, and encode the data structures on a computer-readable medium. Technicians in the field of integrated circuit manufacturing can use such encoded data to manufacture integrated circuits including one or more of the circuits described herein.

[0073] Although some of the operations in the previous embodiments are implemented in hardware or software, the operations in the previous embodiments can generally be implemented with various configurations and architectures. Therefore, some or all of the operations in the previous embodiments can be performed in hardware, software, or both. For example, at least some of the operations in circuit technology can be implemented using program instructions executed by firmware in a processor or integrated circuit.

[0074] Furthermore, although examples of numerical values ​​are provided in the foregoing discussion, different numerical values ​​are used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0075] In the foregoing description, we referred to “some embodiments.” Note that “some embodiments” describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0076] The foregoing description is intended to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a specific application and its requirements. Moreover, the foregoing description of the embodiments of the present disclosure is presented for the purpose of illustration and description only. They are not intended to be exhaustive or to limit the present disclosure to the disclosed form. Thus, many modifications and variations will be clear to those skilled in the art without departing from the spirit and scope of the present disclosure, and the general principles defined herein may be applied to other embodiments and applications. In addition, the discussion of the foregoing embodiments is not intended to limit the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments shown, but should conform to the broadest scope consistent with the principles and features disclosed herein.

Claims

1. An integrated circuit, comprising: An interface circuit, wherein the interface circuit is configured to: receiving a signal corresponding to a header of a frame compatible with a serial communication protocol, wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels; calculating a set of conditions based at least in part on the received signal, wherein the set of conditions, when valid, identifies a first dominant bit of the binary bits having a dominant signal level; as well as When this set of conditions is valid: determining the position of the synchronization field in the header relative to the identified first dominant bit; and A baud rate of the received signal is calculated based at least in part on a subset of the bits in the synchronization field.

2. The integrated circuit according to claim 1, wherein: The serial communication protocol includes a Local Interconnect Network (LIN) communication protocol.

3. The integrated circuit according to claim 1, wherein: The dominant signal level is less than the recessive signal level.

4. The integrated circuit according to claim 1, wherein: The set of conditions includes a first instance of a first condition; wherein, when valid, the first instance of the first condition includes a second dominant bit time of a second dominant bit having a dominant signal level in the binary bit being less than or equal to a first predefined multiple of a first dominant bit time of the first dominant bit; Among them, the first dominant bit precedes the second dominant bit.

5. The integrated circuit according to claim 4, wherein: The first predefined multiple includes 1.

25.

6. The integrated circuit according to claim 4, wherein: The set of conditions includes a second condition; and wherein, when valid, the second condition includes that a sum of the second dominant bit time and the first recessive bit time of the first recessive bit having a recessive signal level in the binary bit is greater than or equal to a second predefined multiple of the first dominant bit time; and The first recessive bit is located between the first dominant bit and the second dominant bit.

7. The integrated circuit according to claim 6, wherein: The second predefined multiple includes a ratio of 2 and 11.

8. The integrated circuit according to claim 6, wherein: The set of conditions includes a second instance of the first condition; wherein, when valid, the second instance of the first condition includes a third dominant bit time of a third dominant bit having a dominant signal level in the binary bits being less than or equal to a first predefined multiple of a second dominant bit time of the second dominant bit; and Among them, the second dominant bit precedes the third dominant bit.

9. The integrated circuit of claim 8, wherein: The set of conditions includes the third condition; Wherein, when valid, the third condition includes that the third dominant bit time is greater than or equal to a third predefined multiple of the second dominant bit time.

10. The integrated circuit of claim 9, wherein: A third predefined multiple includes 0.

75.

11. The integrated circuit of claim 10, wherein: The first predefined multiple includes 1.25 and the third predefined multiple includes 0.

75.

12. The integrated circuit of claim 9, wherein: The set of conditions includes the fourth condition; wherein, when valid, the fourth condition includes that a sum of a second recessive bit time and a third dominant bit time of a second recessive bit in the binary bit is greater than or equal to a third predefined multiple of an average bit time of a pair of bits in the binary bit, and the sum is less than or equal to a first predefined multiple of the average bit time; wherein the third dominant bit precedes the second recessive bit; and The pair of bits includes a first recessive bit and a dominant bit selected from the group consisting of a first dominant bit, a second dominant bit, and a third dominant bit.

13. A non-transitory computer-readable storage medium for use in conjunction with an electronic device, the computer-readable storage medium storing program instructions, wherein: When executed by an electronic device, the program instructions cause the electronic device to perform one or more operations, including: receiving a signal corresponding to a header of a frame compatible with a serial communication protocol, wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels; calculating a set of conditions based at least in part on the received signal, wherein the set of conditions, when valid, identifies a first dominant bit of the binary bits having a dominant signal level; and When this set of conditions is valid: determining the position of the synchronization field in the header relative to the identified first dominant bit; and A baud rate of the received signal is calculated based at least in part on a subset of the bits in the synchronization field.

14. The non-transitory computer readable storage medium of claim 13, wherein: The serial communication protocol includes a Local Interconnect Network (LIN) communication protocol.

15. The non-transitory computer readable storage medium of claim 13, wherein: The dominant signal level is less than the recessive signal level.

16. The non-transitory computer readable storage medium of claim 13, wherein: The set of conditions includes a first instance of a first condition; wherein, when valid, the first instance of the first condition includes a second dominant bit time of a second dominant bit having a dominant signal level in the binary bit being less than or equal to a first predefined multiple of a first dominant bit time of the first dominant bit; Among them, the first dominant bit precedes the second dominant bit.

17. A method for selectively calculating the baud rate of a received signal, comprising: By electronic equipment: receiving a signal corresponding to a header of a frame compatible with a serial communication protocol, wherein the received signal includes a temporal pattern of binary bits having instances of dominant signal levels and recessive signal levels; calculating a set of conditions based at least in part on the received signal, wherein the set of conditions, when valid, identifies a first dominant bit of the binary bits having a dominant signal level; as well as When this set of conditions is valid: determining the position of the synchronization field in the header relative to the identified first dominant bit; and A baud rate of the received signal is calculated based at least in part on a subset of the bits in the synchronization field.

18. The method according to claim 17, wherein: The serial communication protocol includes a Local Interconnect Network (LIN) communication protocol.

19. The method according to claim 17, wherein: The dominant signal level is less than the recessive signal level.

20. The method according to claim 17, wherein: The set of conditions includes a first instance of a first condition; wherein, when valid, the first instance of the first condition includes a second dominant bit time of a second dominant bit having a dominant signal level in the binary bit being less than or equal to a first predefined multiple of a first dominant bit time of the first dominant bit; Among them, the first dominant bit precedes the second dominant bit.

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