Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate, a plurality of sub-pixels and a plurality of power signal lines, wherein the sub-pixels and the power signal lines are located on the substrate. The plurality of sub-pixels are arranged in multiple rows and multiple columns, the size of the sub-pixels in the row direction is a first size, the size of the sub-pixels in the column direction is a second size, and the first size is larger than the second size; each sub-pixel comprises a first electrode, a second electrode and liquid crystal molecules, wherein the first electrode and the second electrode are oppositely arranged, and the liquid crystal molecules are located between the first electrode and the second electrode. The plurality of power supply signal lines extend along the column direction; every two adjacent first electrodes in the row direction are connected through the corresponding power signal line, and every two adjacent first electrodes in the column direction are connected through the corresponding power signal line. The display device comprises the display substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices such as mobile phones, notebooks, and televisions have become necessities in people's work and life. Liquid crystal display devices have become mainstream display devices due to their advantages such as high brightness, bright colors, and wide viewing angle. At present, liquid crystal display devices have the problem of low pixel aperture ratio. Summary of the invention

[0003] The present application provides a display substrate and a display device.

[0004] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate comprises:

[0005] substrate;

[0006] A plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in a plurality of rows and columns, the size of the sub-pixels in the row direction is a first size, the size of the sub-pixels in the column direction is a second size, and the first size is larger than the second size; the sub-pixels include a first electrode and a second electrode disposed opposite to each other, and a liquid crystal molecule located between the first electrode and the second electrode;

[0007] A plurality of power signal lines extend along the column direction; two adjacent first electrodes in the row direction are connected via the power signal line, and two adjacent first electrodes in the column direction are connected via the power signal line.

[0008] In one embodiment, among the two second electrodes connected to the same power signal line and adjacent to each other in the row direction, in the row direction, the distance from one of the second electrodes to the portion of the power signal line extending along the column direction is a first distance, and the distance from the other second electrode to the portion extending along the column direction is a second distance, and the first distance is different from the second distance.

[0009] In one embodiment, the power signal line includes first sub-signal lines and second sub-signal lines that are alternately arranged, and a size of the first sub-signal line in the column direction is larger than a size of the second sub-signal line in the column direction.

[0010] In one embodiment, the second sub-signal line extends along the column direction; two second electrodes adjacent to each other in the column direction and located on both sides of the center of the second sub-signal line are at equal distances from the center of the second sub-signal line.

[0011] In one embodiment, the display substrate also includes a first signal line extending along the row direction, and the second sub-signal line extends along the column direction; the orthographic projection of the second sub-signal line on the substrate overlaps with the orthographic projection of one of the first signal lines on the substrate; the opposite ends of the second sub-signal line are respectively connected to the first sub-signal line, and the orthographic projections of the opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projection of the first signal line on the substrate.

[0012] In one embodiment, the first sub-signal line includes a first segment, a second segment, and a third segment connected in sequence, the first segment extends along the row direction, the second segment extends along the column direction, the third segment and the first segment are located on opposite sides of the second segment; the end of the first segment facing away from the second segment and the end of the third segment facing away from the second segment are respectively connected to the second sub-signal line.

[0013] In one embodiment, among two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the second segment is different from a distance from the other second electrode to the second segment in the row direction.

[0014] In one embodiment, among two second electrodes connected to the same power signal line and adjacent to each other in the column direction, in the row direction, a distance from one of the second electrodes to the second segment is different from a distance from the other second electrode to the second segment.

[0015] In one embodiment, the first sub-signal line includes a fourth segment and a fifth segment connected, the fourth segment extends along the row direction, the fifth segment extends along the column direction, and the end of the fourth segment away from the fifth segment and the end of the fifth segment away from the fourth segment are connected to the second sub-signal line.

[0016] In one embodiment, among two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the fifth segment is different from a distance from the other second electrode to the fifth segment in the row direction.

[0017] In one embodiment, in two sub-pixels connected to the same power signal line and adjacent in the column direction, in the row direction, the distance from one of the second electrodes to the fifth segment is different from the distance from the other second electrode to the fifth segment.

[0018] In one embodiment, the first sub-signal line includes a connected sixth segment and a seventh segment, the sixth segment extends along the row direction and is located on one side of the seventh segment, and the seventh segment extends along the column direction; opposite ends of the seventh segment are respectively connected to the second sub-signal line.

[0019] In one embodiment, among two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the seventh segment is different from a distance from the other second electrode to the seventh segment in the row direction.

[0020] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer located on a side of the first metal conductive layer away from the substrate, the first sub-signal line is located in the first metal conductive layer, and the second sub-signal line is located in the second metal conductive layer.

[0021] In one embodiment, the display substrate further comprises an insulating layer located between the first metal conductive layer and the second metal conductive layer, the insulating layer is provided with a through hole, and the first sub-signal line is connected to the second sub-signal line through the through hole;

[0022] The display substrate also includes a light-shielding layer located on the side of the sub-pixel away from the substrate, the light-shielding layer is provided with a plurality of openings, an orthographic projection of one of the openings on the substrate falls within an orthographic projection of the second electrode on the substrate; the orthographic projection of the through hole on the substrate falls within an edge region of the orthographic projection of the second electrode on the substrate, and is located within the orthographic projection of the light-shielding layer on the substrate.

[0023] In one embodiment, the first electrode is overlapped with the first sub-signal line, or the first electrode is overlapped with the second sub-signal line.

[0024] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer located on a side of the first metal conductive layer away from the substrate, the power signal line includes a first part extending along the column direction and a second part extending along the row direction, the first part is located in the second metal conductive layer; the second part is located in the first metal conductive layer or is arranged in the same layer as the first electrode, and the second part connects two first electrodes located in the same row and adjacent to each other; the second part is located between the second metal conductive layer and the substrate; the display substrate also includes an insulating layer located between the second part and the second metal conductive layer, the insulating layer is provided with a via, and the first part is connected to the second part through the via.

[0025] In one embodiment, the display substrate further includes a plurality of first signal lines extending along the row direction and a plurality of second signal lines extending along the column direction; the orthographic projections of the second signal lines and the power signal lines on the substrate are located between the orthographic projections of two adjacent columns of sub-pixels on the substrate.

[0026] In one embodiment, the display substrate further comprises a plurality of spacers;

[0027] At least two sides of the orthographic projection of the spacer on the substrate are surrounded by the orthographic projection of the power signal line on the substrate; a plurality of spacers located between two adjacent columns of sub-pixels are distributed on both sides of the power signal line; or,

[0028] The power signal line includes a portion extending along the column direction, and the orthographic projections of the plurality of spacers located between two adjacent columns of sub-pixels on the substrate are located on the same side of the orthographic projections of the adjacent portions extending along the column direction on the substrate; or,

[0029] The spacer is located at a side of the power signal line away from the substrate, and an orthographic projection of the spacer on the substrate overlaps with an orthographic projection of the power signal line on the substrate.

[0030] In one embodiment, the display substrate further comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor;

[0031] The orthographic projections of two adjacent driving transistors in the column direction on the substrate are located on opposite sides of the orthographic projections of adjacent power signal lines on the substrate; or, the orthographic projections of two adjacent driving transistors in the column direction on the substrate are located on the same side of the orthographic projections of adjacent power signal lines on the substrate.

[0032] In one embodiment, the display substrate includes a display area and a frame area, the sub-pixel is located in the display area, the display substrate also includes a wire located in the frame area, the wire is electrically connected to the power signal line and the driving chip respectively; the display substrate also includes a metal conductive layer, and the wire is located in the metal conductive layer.

[0033] In one embodiment, the display substrate further comprises a light shielding layer located on a side of the sub-pixel away from the substrate, the light shielding layer is provided with a plurality of openings, and an orthographic projection of one of the openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate; the display substrate further comprises a plurality of first signal lines extending along the row direction;

[0034] The power signal line comprises a section located between two adjacent openings in the row direction and extending along the column direction, wherein the minimum distance between an edge of an orthographic projection of the section extending along the column direction on the substrate and an edge of an orthographic projection of an adjacent opening on the substrate is in a range of 4 μm to 8 μm; and / or,

[0035] The first electrode is located on a side of the first signal line away from the substrate, and the display substrate further comprises an insulating layer between the first signal line and the first electrode; in the column direction, a distance between an edge of an orthographic projection of the first signal line on the substrate and an edge of an orthographic projection of the second electrode on the substrate is in a range of 3 μm to 5 μm; and / or,

[0036] The orthographic projection of the first signal line on the substrate falls within the orthographic projection of the shading layer on the substrate; the distance between the orthographic projection of the first signal line on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate extending along the row direction ranges from 6 μm to 11 μm.

[0037] According to a second aspect of an embodiment of the present application, a display device is provided, comprising the above-mentioned display substrate.

[0038] The display substrate and display device provided by the embodiments of the present application can avoid the problem of light leakage caused by poor anchoring of liquid crystal molecules in the area where the power signal line has a step difference, by setting the power signal line to extend along the column direction when the power signal line extends along the row direction and part of the power signal line overlaps with the first electrode in the stacking direction of the film layer; that is, the problem can be improved by extending the power signal line along the column direction, so the opening that defines the light-emitting area of ​​the sub-pixel and is opened in the light-shielding layer on the side of the sub-pixel away from the substrate can be set larger, thereby improving the pixel aperture ratio of the display substrate and thus improving the light efficiency of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic diagram of a partial structure of a display substrate provided by an exemplary embodiment of the present application;

[0040] Figure 2 is a partial schematic diagram of multiple film layers of a display substrate provided by an exemplary embodiment of the present application;

[0041] Figure 3 is a partial schematic diagram of multiple film layers of a display substrate provided by another exemplary embodiment of the present application;

[0042] Figure 4 is a partial schematic diagram of multiple film layers of a display substrate provided by yet another exemplary embodiment of the present application;

[0043] Figure 5 is a partial schematic diagram of a first metal conductive layer of a display substrate provided by an exemplary embodiment of the present application;

[0044] Figure 6 is a partial schematic diagram of a first metal conductive layer and a first electrode superimposed on a display substrate provided by an exemplary embodiment of the present application;

[0045] Figure 7 It is a partial schematic diagram of a first metal conductive layer, a first electrode, and a second metal conductive layer of a display substrate provided by an exemplary embodiment of the present application;

[0046] Figure 8 yes Figure 2 A cross-sectional view of the display substrate taken along AA is shown;

[0047] Fig. 9 yes Figure 2 A cross-sectional view of the display substrate shown taken along BB;

[0048] Fig.10 yes Figure 2 Another cross-sectional view of the display substrate taken along line BB is shown;

[0049] Fig.11 is a partial schematic diagram of a first electrode of a display substrate provided by an exemplary embodiment of the present application;

[0050] Fig.12 is a partial schematic diagram of a first metal conductive layer and a first electrode superimposed on a display substrate provided by an exemplary embodiment of the present application;

[0051] Fig.13 It is a partial schematic diagram of a first metal conductive layer, a first electrode, and a second metal conductive layer of a display substrate provided by an exemplary embodiment of the present application;

[0052] Fig.14 yes Figure 3 A cross-sectional view of the display substrate taken along CC is shown;

[0053] Fig.15 is a partial schematic diagram of multiple film layers of a display substrate provided by another exemplary embodiment of the present application;

[0054] Fig.16 is a partial schematic diagram of multiple film layers of a display substrate provided by another exemplary embodiment of the present application;

[0055] Fig.17 It is a partial schematic diagram of multiple film layers of a display substrate provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0056] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0057] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0058] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0059] The embodiments of the present application provide a display substrate and a display device. The display substrate and the display device in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or combine with each other.

[0060] The present application embodiment provides a display substrate. Figure 1 As shown, the display substrate includes a substrate 10 and a plurality of sub-pixels 20 located on the substrate 10, wherein the plurality of sub-pixels 20 are arranged in a plurality of rows and columns, and a size of the sub-pixel 20 in a row direction X is a first size d1, and a size of the sub-pixel 20 in a column direction Y is a second size d2, and the first size d1 is greater than the second size d2.

[0061] like Figures 2 to 4As shown, the sub-pixel includes a first electrode 21 and a second electrode 22 arranged opposite to each other. The sub-pixel 20 also includes liquid crystal molecules located between the first electrode 21 and the second electrode 22. The display substrate also includes a plurality of power signal lines 30, and the power signal lines 30 extend along the column direction Y; two adjacent first electrodes 21 in the row direction X are connected by the power signal lines 30, and two adjacent first electrodes 21 in the column direction Y are connected by the power signal lines 30. The extension of the power signal line 30 in the column direction Y means that the power signal line 30 as a whole extends in the column direction Y, and the power signal line 30 may include a portion extending in the row direction X.

[0062] The display substrate provided in the embodiment of the present application can avoid the problem of light leakage caused by poor anchoring of liquid crystal molecules in the area where the power signal line has a step difference, by setting the power signal line to extend along the column direction when the power signal line extends along the row direction and part of the power signal line overlaps with the first electrode in the stacking direction of the film layer; that is, the problem can be improved by extending the power signal line along the column direction, so the opening that defines the light-emitting area of ​​the sub-pixel and is opened in the light-shielding layer on the side of the sub-pixel away from the substrate can be set larger, thereby improving the pixel aperture ratio of the display substrate and thus improving the light efficiency of the display substrate.

[0063] In one embodiment, the display substrate further includes a plurality of pixel driving circuits. The pixel driving circuits of the display substrate may correspond to the sub-pixels one by one, and each pixel driving circuit is used to drive a corresponding sub-pixel.

[0064] In one embodiment, Figure 1 As shown, the display substrate further includes a plurality of scan signal lines Gate extending along the row direction X and a plurality of data signal lines Data extending along the column direction. Sub-pixels in the same row are connected to the same scan signal line Gate, and the scan signal line Gate may be located between two adjacent rows of sub-pixels. The number of data signal lines Data may be the same as the number of rows of sub-pixels, and the data signal line Data may be located between two adjacent columns of sub-pixels. Since the size of the sub-pixel 20 in the row direction X is greater than its size in the column direction Y, when the size of the display substrate in the row direction X is constant, the number of columns of sub-pixels in the display substrate may be reduced, thereby reducing the number of data signal lines Data, and further reducing the number of driver chips used to provide signals to the data signal lines Data, thereby reducing the cost of the display substrate.

[0065] In one embodiment, Figures 1 to 3As shown, data signal lines Data are respectively arranged on opposite sides of the sub-pixels in the same column; one pixel driving circuit corresponding to two adjacent sub-pixels 20 in the column direction Y is connected to one data signal line Data adjacent to it, and the other pixel driving circuit is connected to another data signal line Data adjacent to it, that is, the pixel driving circuits corresponding to two adjacent sub-pixels 20 in the column direction Y are respectively connected to different data signal lines Data. To avoid polarization of liquid crystal molecules, when the display substrate is displaying, the signal of one of the two adjacent data signal lines Data is greater than the signal of the power signal line 30, and the signal of the other data signal line Data is smaller than the signal of the power signal line 30. The above arrangement can make the data signal received by one of the two adjacent pixel driving circuits in the column direction greater than the signal of the power signal line 30, and the data signal received by the other pixel driving circuit is smaller than the signal of the power signal line 30; at the same time, the data signal received by one of the two adjacent pixel driving circuits in the row direction is greater than the signal of the power signal line 30, and the data signal received by the other pixel driving circuit is smaller than the signal of the power signal line 30, which helps to improve the display uniformity of the display substrate and improve the display effect of the display substrate.

[0066] In one embodiment, the plurality of sub-pixels in the display substrate are divided into a plurality of pixel units, and each pixel unit may include a plurality of sub-pixels with different luminous colors. The plurality of sub-pixels of the same pixel unit may be arranged along the column direction Y, and the sub-pixels of the same pixel unit are respectively connected to different scanning signal lines Gate. The luminous colors of the plurality of sub-pixels in the same row may be the same.

[0067] In one embodiment, the display substrate may include sub-pixels of three different luminous colors, for example, a sub-pixel of red, a sub-pixel of green, and a sub-pixel of blue. A pixel unit may include three sub-pixels of different luminous colors.

[0068] In one embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The material of the flexible substrate may include one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials, and the organic resin materials may include epoxy resin, triazine, silicone resin, or polyimide. The rigid substrate includes any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, etc.; or a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, or an SOI (Silicon On Insulator) substrate.

[0069] In one embodiment, the first electrode 21 is a cathode, the second electrode 22 is an anode, and the power signal line is a low-level power signal line. In some embodiments, the second electrode 22 may be provided with a plurality of strip-shaped gaps.

[0070] In one embodiment, the material of the first electrode 21 and the material of the second electrode 22 may both be transparent conductive materials, such as indium zinc oxide, indium tin oxide, and the like.

[0071] In one embodiment, Figures 2 to 4 As shown, the pixel driving circuit includes a driving transistor 70, and the driving transistor 70 includes a gate electrode 71, a first electrode 72, and a second electrode 73. The first electrode 72 and the second electrode 73 may be located on the side of the gate electrode 71 away from the substrate. One of the first electrode 72 and the second electrode 73 may be a source electrode, and the other may be a drain electrode, for example, the first electrode 72 is the source electrode, and the second electrode 73 is the drain electrode. The pixel driving circuit may also include an active layer, and the active layer may be located between the gate electrode 71 and the substrate. The second electrode 22 of the sub-pixel is connected to the first electrode 72 of the corresponding driving transistor 70.

[0072] In one embodiment, Figures 5 to 7 As shown, the display substrate includes a first metal conductive layer 91 located on a substrate, and a second metal conductive layer 92 located on a side of the first metal conductive layer 91 away from the substrate. The display substrate also includes an insulating layer located between the first metal conductive layer 91 and the second metal conductive layer 92.

[0073] In one embodiment, the second electrode 22 is located on a side of the second metal conductive layer 92 facing away from the substrate, and the display substrate further includes an insulating material layer located between the second metal conductive layer 92 and the second electrode 22 .

[0074] In one embodiment, Figure 5 As shown, the gate electrode 71 and the scan signal line Gate are located in the first metal conductive layer 91, and the gate electrode 71 is connected to the scan signal line Gate.

[0075] In one embodiment, Figure 6 As shown, the first electrode 72 , the second electrode 73 and the data signal line Data are located in the second metal conductive layer 92 .

[0076] In one embodiment, Figure 7 As shown, the insulating material layer is provided with a plurality of through holes 82 , and the second electrode 22 can be electrically connected to the first electrode 72 through the through holes 82 .

[0077] In one embodiment, the display substrate further comprises a light shielding layer and a color filter layer located on the side of the sub-pixel away from the substrate. The light shielding layer is provided with a plurality of openings. Figures 2 to 4As shown, the orthographic projection of one of the openings 50 on the substrate falls within the orthographic projection of one of the second electrodes 22 on the substrate. The openings may correspond to the first electrodes one by one, and the orthographic projection of each of the openings on the substrate falls within the orthographic projection of the corresponding second electrode on the substrate. The color filter layer includes a plurality of color filter portions, and at least a portion of one of the color filter portions is located within one of the openings.

[0078] In one embodiment, the display substrate can be obtained by aligning an array substrate and a color filter substrate. The array substrate includes a substrate, a first metal conductive layer, a second metal conductive layer and a first electrode. The color filter substrate may include a second electrode, a light shielding layer and a color filter layer. In the aligning process, a sealing glue is applied to one of the color filter substrate and the array substrate, and a liquid crystal material is dripped on the other; then, the color filter substrate and the array substrate are aligning to obtain a display substrate.

[0079] In one embodiment, Figures 2 to 4 As shown, of the two second electrodes 22 connected to the same power signal line 30 and adjacent to each other in the row direction, in the row direction X, the distance between one of the second electrodes 22 and the portion of the power signal line 30 extending along the column direction Y is a first distance, and the distance between the other second electrode 22 and the portion extending along the column direction Y is a second distance, and the first distance is different from the second distance. In this way, at least a portion of the data signal line Data located between two columns can be located between the power signal line 30 and a column of sub-pixels farther away from it.

[0080] In one embodiment, Figures 2 to 4 As shown, the power signal line 30 includes first sub-signal lines 31 and second sub-signal lines 32 arranged alternately, the first sub-signal line 31 has a size d3 in the column direction Y, the second sub-signal line 32 has a size d4 in the column direction Y, and d3 is greater than d4. In the same power signal line 30, opposite ends of the first sub-signal line 31 are respectively connected to the adjacent second sub-signal line 32, and opposite ends of the second sub-signal line 32 are respectively connected to the adjacent first sub-signal line 31.

[0081] In one embodiment, Figures 2 to 4 As shown, the second sub-signal line 32 extends along the column direction Y; the distances from the center of the second sub-signal line 32 to the center of the second sub-signal line 32 are equal between two second electrodes 22 adjacent to each other in the column direction Y and located on both sides of the center of the second sub-signal line 32. Figure 2In the example shown, among the two second electrodes 22 located on both sides of the center of the second sub-signal line 32, the distance between one second electrode 22 and the center of the second sub-signal line 32 is d5, and the distance between the other second electrode 22 and the center of the second sub-signal line 32 is d6, and d5 is equal to d6.

[0082] In one embodiment, Figures 2 to 4 As shown, the display substrate further includes a first signal line 41 extending along the row direction X, and the second sub-signal line 32 extends along the column direction Y; the orthographic projection of the second sub-signal line 32 on the substrate overlaps with the orthographic projection of one of the first signal lines 41 on the substrate; the opposite ends of the second sub-signal line 32 are respectively connected to the first sub-signal line 31, and the orthographic projections of the opposite ends of the second sub-signal line 32 on the substrate are located on opposite sides of the orthographic projection of the first signal line 41 on the substrate. The orthographic projection of the first sub-signal line 31 on the substrate is located between the orthographic projections of two adjacent first signal lines 41 on the substrate. In some embodiments, the first signal line 41 is a scanning signal line Gate.

[0083] In one embodiment, Figures 2 to 4 As shown, the display substrate further includes a plurality of second signal lines 42 extending along the column direction; the orthographic projections of the second signal lines 42 and the power signal line 30 on the substrate are both located between the orthographic projections of the sub-pixels in two adjacent columns on the substrate. In some embodiments, the second signal lines 42 are data signal lines Data.

[0084] In one embodiment, Figure 2 As shown, the first sub-signal line 31 includes a first section 311, a second section 312 and a third section 313 connected in sequence, the first section 311 extends along the row direction X, the second section 312 extends along the column direction Y, the third section 313 and the first section 311 are located at opposite sides of the second section 312; the end of the first section 311 away from the second section 312 and the end of the third section 313 away from the second section 312 are connected to the second sub-signal line 32. Such an arrangement facilitates the connection between the first sub-signal line 31 and the second sub-signal line 32, and facilitates the connection between the first sub-signal line 31 and the two first electrodes 21 adjacent to each other in the row direction X. Figure 2 In the illustrated embodiment, the angle between the extension direction of the third section 313 and the extension direction of the second section 312 is an acute angle.

[0085] In one embodiment, Figure 2As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent to each other in the row direction X, in the row direction X, the distance from one of the second electrodes 22 to the second segment 312 is different from the distance from the other second electrode 22 to the second segment 312 .

[0086] In one embodiment, Figure 2 As shown, in two second electrodes connected to the same power signal line 30 and adjacent in the column direction Y, in the row direction X, the distance from one of the second electrodes 22 to the second section 312 is different from the distance from the other second electrode 22 to the second section 312. In this way, the power signal line 30 is in a zigzag shape, and two adjacent driving transistors 70 in the column direction can be arranged on opposite sides of the power signal line 30, so that the two adjacent driving transistors 70 are arranged on opposite sides of the data signal line Data, thereby improving the display uniformity of the display substrate.

[0087] In one embodiment, Figure 3 As shown, the first sub-signal line 31 includes a fourth section 314 and a fifth section 315 connected to each other, the fourth section 314 extends along the row direction X, the fifth section 315 extends along the column direction Y, and the end of the fourth section 314 away from the fifth section 315 and the end of the fifth section 315 away from the fourth section 314 are connected to the second sub-signal line 32. Such a configuration facilitates the connection of the first sub-signal line 31 with the second sub-signal line 32, and facilitates the connection of the first sub-signal line 31 with two adjacent first electrodes 21 in the row direction X; at the same time, the power signal line 30 can be in a zigzag shape, which facilitates the arrangement of two adjacent driving transistors 70 in the column direction on opposite sides of the power signal line 30, and the arrangement of two adjacent driving transistors 70 on opposite sides of the data signal line Data, so as to improve the display uniformity of the display substrate.

[0088] In one embodiment, Figure 3 As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent to each other in the row direction X, in the row direction X, the distance from one of the second electrodes 22 to the fifth segment 315 is different from the distance from the other second electrode 22 to the fifth segment 315 .

[0089] In one embodiment, Figure 3 As shown, in two sub-pixels connected to the same power signal line 30 and adjacent in the column direction Y, in the row direction X, the distance from one of the second electrodes 22 to the fifth section 315 is different from the distance from the other second electrode 22 to the fifth section 315. Such an arrangement is more conducive to the power signal line 30 being in a zigzag shape.

[0090] In one embodiment, Figure 4 As shown, the first sub-signal line 31 includes a sixth segment 316 and a seventh segment 317 connected to each other, the sixth segment 316 extends along the row direction X and is located on one side of the seventh segment 317, and the seventh segment 317 extends along the column direction Y; opposite ends of the seventh segment 317 are respectively connected to the second sub-signal line 32. In this way, the sixth segment 316 and the seventh segment 317 are respectively connected to different first electrodes 21 of two first electrodes 21 adjacent to each other in the row direction, so that the first sub-signal line 31 is respectively connected to the two first electrodes 21 adjacent to each other in the row direction X, and the first sub-signal line 31 is connected to the second sub-signal line 32.

[0091] In one embodiment, Figure 4 As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent to each other in the row direction X, in the row direction X, the distance from one of the second electrodes 22 to the seventh segment 317 is different from the distance from the other second electrode 22 to the seventh segment 317 .

[0092] In one embodiment, Figures 5 to 7 As shown, the first sub-signal line 31 is located in the first metal conductive layer 91, and the second sub-signal line 32 is located in the second metal conductive layer 92. That is, the first sub-signal line 31 and the gate electrode 71 are located in the same layer, and the second sub-signal line 32 and the first electrode 72 and the second electrode 73 are located in the same layer. In this way, in the same power signal line 30, the second sub-signal line 32 can connect two adjacent first sub-signal lines 31 together while avoiding the short circuit between the second sub-signal line 32 and the scanning signal line Gate; and the materials of the first sub-signal line 31 and the second sub-signal line 32 are both metal, which can make the resistance of the power signal line 30 smaller, which is conducive to improving the consistency of the level of each first electrode 21.

[0093] In one embodiment, Figure 6 and Figure 7 As shown, the insulating layer between the first metal conductive layer 91 and the second metal conductive layer 92 is provided with a plurality of through holes 81, and the first sub-signal line 31 and the second sub-signal line 32 are connected through the through holes 81. Specifically, one end of the second sub-signal line 32 is connected to the first sub-signal line 31 through one of the through holes 81, and the other end is connected to the first sub-signal line 31 through another through hole 81.

[0094] In one embodiment, Figure 7As shown, the orthographic projection of the through hole 81 on the substrate falls on the edge region of the orthographic projection of the second electrode 22 on the substrate, and is located within the orthographic projection of the light shielding layer on the substrate. By arranging the through hole 81 at the edge region of the second electrode 22 and being covered by the light shielding layer, the influence on the aperture ratio of the sub-pixel can be reduced.

[0095] In one embodiment, Figure 7 As shown, the orthographic projection of the through hole 82 opened in the insulating material layer on the substrate falls on the edge area of ​​the orthographic projection of the second electrode 22 on the substrate, and is located within the orthographic projection of the light shielding layer on the substrate. By arranging the through hole 82 in the edge area of ​​the second electrode 22 and being covered by the light shielding layer, the through hole 82 can be prevented from affecting the display effect of the display substrate.

[0096] In one embodiment, Figures 5 to 7 As shown, when forming the array substrate of the display substrate, the first metal conductive layer 91 is first formed; then an insulating layer is formed on the side of the first metal conductive layer 91 away from the substrate; then a second metal conductive layer 92 is formed on the insulating layer, and the second sub-signal line 32 located in the second metal conductive layer 92 is connected to the first sub-signal line 31 located in the first metal conductive layer 91 through a through hole 81 opened in the insulating layer; then a first electrode 21 is formed, and the first electrode 21 overlaps the second sub-signal line 32. After the array substrate and the color filter substrate are assembled, Figure 2 The display substrate is shown.

[0097] If the first electrode is formed before the first metal conductive layer is formed when forming the display substrate, in order to avoid short circuit between the first electrode and the scanning signal line Gate located in the first metal conductive layer, the distance from the first electrode to the scanning signal line Gate in the column direction needs to be set to be greater than or equal to 7μm. In this embodiment, since an insulating layer is provided between the first electrode 21 and the scanning signal line Gate located in the first metal conductive layer 91, there is no risk of short circuit between the first electrode 21 and the scanning signal line Gate, and the distance between the first electrode 21 and the scanning signal line Gate in the column direction can be set to be smaller, thereby increasing the area of ​​the opening of the light shielding layer and effectively improving the aperture ratio of the sub-pixel.

[0098] In one example, the power signal line includes a section (ie, the second section 312 ) located between two adjacent openings 50 in the row direction X and extending along the column direction Y. Figure 8As shown, the minimum distance between the edge of the orthographic projection of the second section 312 on the substrate 10 and the edge of the orthographic projection of the adjacent opening 50 on the substrate 10 is x1, and the range of x1 is 4μm to 8μm. This arrangement can avoid the problem of x1 being too small, resulting in the second section 312 being exposed and reflecting light due to the alignment deviation when the array substrate and the color filter substrate are boxed, and can also avoid x1 being too large, affecting the aperture ratio of the sub-pixel. In some embodiments, x1 can be 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, etc.

[0099] In one embodiment, Figure 8 As shown, the orthographic projection of the first electrode 21 on the substrate 10 overlaps with the orthographic projection of the second segment 312 on the substrate 10, and the edge of the orthographic projection of the second segment on the substrate 10 is located inside the edge of the orthographic projection of the first electrode 21 on the substrate 10, and the minimum distance between the edge of the orthographic projection of the first electrode 21 on the substrate 10 and the edge of the orthographic projection of the second segment 312 on the substrate 10 is x2, and the range of x2 is 1.5μm to 3μm. With this arrangement, even if there is a misalignment between the first electrode 21 and the first sub-signal line 31, it can be ensured that there is an overlapping area between the first electrode and the second segment in the stacking direction of the film layer, thereby facilitating the connection between the first electrode and the first sub-signal line. In some embodiments, x2 can be 1.5μm, 2.0μm, 2.5μm, 3.0μm, etc.

[0100] In one embodiment, Fig. 9 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the adjacent opening 50 on the substrate 10 is x3, and the range of x3 is 6μm to 11μm. Such a setting can avoid the problem of side view light leakage of the display substrate due to the range of x3 being too small, and can also avoid the range of x3 being too large to affect the aperture ratio of the sub-pixel. In some embodiments, x3 can be 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, etc.

[0101] In one example, if Fig. 9 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x4, and the range of x4 is 3μm to 5μm. In this way, the influence on the aperture ratio of the sub-pixel can be reduced while ensuring that the signal of the first signal line 41 does not interfere with the signal of the first electrode 21. In some embodiments, x4 can be 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc.

[0102] It should be noted that the above numerical range is determined when the liquid crystal molecules in the display substrate are positive liquid crystal molecules.

[0103] In another embodiment, when the liquid crystal molecules are negative liquid crystal molecules, Fig.10 As shown, in the column direction, the distance between the edge of the positive projection of the first signal line 41 on the substrate 10 and the edge of the positive projection of the adjacent opening 50 on the substrate 10 is x5, and the range of x5 is 3μm to 5μm. When the liquid crystal molecules are negative liquid crystal molecules, there is no light leakage problem in the row direction of the liquid crystal molecules, so x5 can be set to be smaller.

[0104] Furthermore, if Fig.10 As shown, the edge of the orthogonal projection of the opening 50 of the light shielding layer 51 on the substrate 10 extending along the column direction Y is located outside the orthogonal projection of the corresponding first electrode 21 on the substrate 10. That is, when the liquid crystal molecules are negative liquid crystal molecules, most of the area where the opening 50 is enlarged is a non-luminous area, but due to the alignment deviation when the color filter substrate and the array substrate are aligned, it can be avoided that the light shielding layer 51 covers the effective luminous area of ​​the sub-pixel after the alignment, which helps to improve the aperture ratio of the sub-pixel.

[0105] In one embodiment, Figures 11 to 13 As shown, when forming the array substrate of the display substrate, the first electrode 21 is formed first; then the first metal conductive layer 91 is formed, and the first sub-signal line 31 located in the first metal conductive layer is overlapped with the first electrode 21; then the insulating layer located on the side of the first metal conductive layer 91 away from the substrate is formed; then the second metal conductive layer 92 is formed on the insulating layer, and the second sub-signal line 32 located in the second metal conductive layer 92 is connected to the first sub-signal line 31 located in the first metal conductive layer 91 through the through hole 81 opened in the insulating layer. Figure 3 The display substrate is shown.

[0106] Furthermore, if Fig.14 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x6, and the range of x6 is 5μm to 7μm. In this way, it is possible to avoid the situation where the conductive material falls into the gap between the first signal line 41 and the first electrode 21 during the process of forming the first signal line 41 and the first electrode 21, resulting in a short circuit between the two. In some embodiments, x6 can be 5μm, 5.5μm, 6μm, 6.5μm, 7μm, etc.

[0107] In another embodiment, if Fig.15 and Fig.16As shown, the power signal line 30 includes a first portion 33 extending along the column direction Y and a second portion 34 extending along the row direction X, the first portion 33 is located in the second metal conductive layer 92; the second portion 34 is located in the first metal conductive layer 91 or is arranged in the same layer as the first electrode 21, and the second portion 34 connects two first electrodes 21 located in the same row and adjacent to each other. The second portion 34 is located between the second metal conductive layer 92 and the substrate. The display substrate also includes an insulating layer located between the second portion 34 and the second metal conductive layer 92, the insulating layer is provided with a via 83, and the first portion 33 is connected to the second portion 34 through the via 83. Fig.15 In the illustrated embodiment, the second portion 34 is located on the first metal conductive layer 91 , and the first electrode 21 may overlap the second portion 34 . Fig.16 In the embodiment shown, the second portion 34 is disposed in the same layer as the first electrode 21 and is formed simultaneously in the same process step. In this way, the portion of the power signal line 30 extending along the column direction Y is disposed in the same layer and formed integrally, which is helpful to reduce the resistance of the power signal line 30 and improve the consistency of the level signal of the first electrode 21, compared with the solution in which different regions of the portion of the power signal line extending along the column direction Y are located in different layers and connected through vias.

[0108] In one embodiment, Figures 2 to 4 , Fig.15 and Fig.16 As shown, the display substrate further includes a plurality of spacers 62. The spacers 62 can keep a fixed distance between the color filter substrate and the array substrate.

[0109] In one embodiment, Figure 2 , Figure 4 , Fig.15 and Fig.16 As shown, the display substrate further includes a plurality of support portions 61, and the orthographic projection of a spacer 62 on the substrate is located within the orthographic projection of a support portion 61 on the substrate. The support portions 61 and the spacers 62 may correspond one to one. The support portion 61 may be located in the second metal conductive layer 92, and the support portion 61 may be located in the second metal conductive layer and connected to the data signal line Data.

[0110] In one embodiment, Figure 2 As shown, at least two sides of the orthographic projection of the spacer 62 on the substrate are surrounded by the orthographic projection of the power signal line 30 on the substrate; a plurality of the spacers 62 located between two adjacent columns of sub-pixels are distributed on both sides of the power signal line 30 . Figure 2 In the illustrated embodiment, two sides of the spacer 62 are surrounded by the second signal sub-line 32 and the first section 311 .

[0111] In another embodiment, if Figure 3 As shown, the spacer 62 is located on the side of the power signal line 30 away from the substrate, and the orthographic projection of the spacer 62 on the substrate overlaps with the orthographic projection of the power signal line 30 on the substrate. Figure 3 In the embodiment shown, the orthographic projection of the spacer 62 on the substrate 10 partially overlaps with the orthographic projection of the power signal line 30 on the substrate, and partially overlaps with the orthographic projection of the data signal line Data on the substrate. In this way, a supporting portion for supporting the spacer 62 is not required, which helps to reduce the distance between two adjacent columns of sub-pixels.

[0112] In yet another embodiment, Figure 4 , Fig.15 and Fig.16 As shown, the power signal line 30 includes a portion extending along the column direction, and the orthographic projections of the plurality of spacers 62 located between two adjacent columns of sub-pixels on the substrate are located on the same side of the orthographic projections of the adjacent portions extending along the column direction on the substrate. The power signal line adjacent to the spacer refers to the power signal line with the smallest distance from the spacer, and the power signal line and the spacer are both located between the two adjacent columns of sub-pixels mentioned above.

[0113] In one embodiment, Figure 2 and Figure 3 As shown, the orthographic projections of two adjacent driving transistors 70 on the substrate in the column direction Y are located on opposite sides of the orthographic projections of the adjacent power signal lines 30 on the substrate. Figure 4 , Fig.14 and Fig.15 As shown, the orthographic projections of two adjacent driving transistors 70 on the substrate in the column direction Y are located on the same side of the orthographic projections of the adjacent power signal lines 30 on the substrate. The power signal line 30 adjacent to the driving transistor 70 refers to the power signal line 30 with the smallest distance from the driving transistor 70 in the row direction X.

[0114] In one embodiment, Figure 2 , Figure 3 and Fig.16 As shown, the orthographic projections of two adjacent driving transistors 70 in the column direction Y on the substrate are located on opposite sides of the orthographic projections of the adjacent data signal lines Data on the substrate. Figure 4 and Fig.14As shown, the orthographic projections of two adjacent driving transistors 70 on the substrate in the column direction Y are located on the same side of the orthographic projections of the adjacent data signal lines Data on the substrate. The data signal line Data adjacent to the driving transistor 70 refers to the data signal line Data with the shortest distance from the driving transistor 70 in the row direction X.

[0115] In one embodiment, Fig.17 As shown, the display substrate includes a display area 101 and a frame area 102, and the sub-pixel is located in the display area 101. The display substrate also includes a wire 63 located in the frame area 102, and the wire 63 is electrically connected to the power signal line 30 and the driving chip respectively; the display substrate also includes a metal conductive layer, and the wire 63 is located in the metal conductive layer. The wire 63 can transmit the power signal provided by the driving chip to the power signal line 30.

[0116] Furthermore, the wire 63 is located in the first metal conductive layer 91, the first sub-signal line 31 of the power signal line 30 is located in the first metal conductive layer 91, and the wire 63 is connected to the first sub-signal line 31. In this way, the power signal line 30 does not need to be connected to the wire 63 through the through hole on the insulating layer, which helps to improve the signal uniformity of the first electrode. In addition, the wire 63 and the data signal line Data are located in different metal layers, and the part of the data signal line Data extending to the border area 102 will not intersect with the wire 63, and the setting of the wire 63 is more flexible.

[0117] An embodiment of the present application further provides a display device, which includes the display substrate described in any of the above embodiments.

[0118] In some embodiments, the display device further includes a housing, and the display substrate is embedded in the housing.

[0119] The display device provided in the embodiments of the present application may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0120] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0121] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0122] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate; A plurality of sub-pixels located on the substrate, the plurality of sub-pixels are arranged in a plurality of rows and columns, the size of the sub-pixels in the row direction is a first size, the size of the sub-pixels in the column direction is a second size, and the first size is larger than the second size; the sub-pixels include a first electrode and a second electrode disposed opposite to each other, and a liquid crystal molecule located between the first electrode and the second electrode; A plurality of power signal lines extend along the column direction; two adjacent first electrodes in the row direction are connected via the power signal line, and two adjacent first electrodes in the column direction are connected via the power signal line.

2. The display substrate according to claim 1, characterized in that: Among the two second electrodes connected to the same power signal line and adjacent to each other in the row direction, in the row direction, the distance from one of the second electrodes to the portion of the power signal line extending along the column direction is a first distance, and the distance from the other second electrode to the portion extending along the column direction is a second distance, and the first distance is different from the second distance.

3. The display substrate according to claim 1, characterized in that: The power signal line includes a first sub-signal line and a second sub-signal line which are alternately arranged, and a size of the first sub-signal line in the column direction is larger than a size of the second sub-signal line in the column direction.

4. The display substrate according to claim 3, characterized in that: The second sub-signal line extends along the column direction; two second electrodes adjacent to each other in the column direction and located on both sides of the center of the second sub-signal line are at equal distances from the center of the second sub-signal line.

5. The display substrate according to claim 3, characterized in that: The display substrate also includes a first signal line extending along the row direction, and the second sub-signal line extends along the column direction; the orthographic projection of the second sub-signal line on the substrate overlaps with the orthographic projection of one of the first signal lines on the substrate; the opposite ends of the second sub-signal line are respectively connected to the first sub-signal line, and the orthographic projections of the opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projection of the first signal line on the substrate.

6. The display substrate according to any one of claims 3 to 5, characterized in that: The first sub-signal line includes a first segment, a second segment and a third segment connected in sequence, the first segment extends along the row direction, the second segment extends along the column direction, the third segment and the first segment are located on opposite sides of the second segment; the end of the first segment away from the second segment and the end of the third segment away from the second segment are respectively connected to the second sub-signal line.

7. The display substrate according to claim 6, characterized in that: Of the two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the second segment is different from a distance from the other second electrode to the second segment in the row direction.

8. The display substrate according to claim 6, characterized in that: Among two second electrodes connected to the same power signal line and adjacent to each other in the column direction, in the row direction, a distance from one of the second electrodes to the second segment is different from a distance from the other second electrode to the second segment.

9. The display substrate according to any one of claims 3 to 5, characterized in that: The first sub-signal line includes a fourth segment and a fifth segment connected, the fourth segment extends along the row direction, the fifth segment extends along the column direction, and the end of the fourth segment away from the fifth segment and the end of the fifth segment away from the fourth segment are connected to the second sub-signal line.

10. The display substrate according to claim 9, characterized in that: Of the two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the fifth segment is different from a distance from the other second electrode to the fifth segment in the row direction.

11. The display substrate according to claim 9, characterized in that: In two sub-pixels connected to the same power signal line and adjacent to each other in the column direction, in the row direction, a distance from one of the second electrodes to the fifth segment is different from a distance from the other second electrode to the fifth segment.

12. The display substrate according to any one of claims 3 to 5, characterized in that: The first sub-signal line includes a sixth segment and a seventh segment connected to each other. The sixth segment extends along the row direction and is located at one side of the seventh segment. The seventh segment extends along the column direction. Two opposite ends of the seventh segment are respectively connected to the second sub-signal line.

13. The display substrate according to claim 12, characterized in that: Of the two second electrodes connected to the same power signal line and adjacent to each other in the row direction, a distance from one of the second electrodes to the seventh segment is different from a distance from the other second electrode to the seventh segment in the row direction.

14. The display substrate according to claim 3, characterized in that: The display substrate includes a first metal conductive layer and a second metal conductive layer located on a side of the first metal conductive layer away from the substrate. The first sub-signal line is located in the first metal conductive layer, and the second sub-signal line is located in the second metal conductive layer.

15. The display substrate according to claim 14, characterized in that: The display substrate further includes an insulating layer located between the first metal conductive layer and the second metal conductive layer, the insulating layer is provided with a through hole, and the first sub-signal line and the second sub-signal line are connected through the through hole; The display substrate further comprises a light shielding layer located on a side of the sub-pixel away from the substrate, the light shielding layer is provided with a plurality of openings, and an orthographic projection of one of the openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate; The orthographic projection of the through hole on the substrate falls on an edge region of the orthographic projection of the second electrode on the substrate, and is located within the orthographic projection of the light shielding layer on the substrate.

16. The display substrate according to claim 15, characterized in that: The first electrode is overlapped with the first sub-signal line, or the first electrode is overlapped with the second sub-signal line.

17. The display substrate according to claim 1, characterized in that: The display substrate includes a first metal conductive layer and a second metal conductive layer located on the side of the first metal conductive layer away from the substrate. The power signal line includes a first part extending along the column direction and a second part extending along the row direction. The first part is located in the second metal conductive layer; the second part is located in the first metal conductive layer or is arranged in the same layer as the first electrode, and the second part connects two first electrodes located in the same row and adjacent to each other; the second part is located between the second metal conductive layer and the substrate; the display substrate also includes an insulating layer located between the second part and the second metal conductive layer, the insulating layer is provided with a via, and the first part is connected to the second part through the via.

18. The display substrate according to claim 1, characterized in that: The display substrate further comprises a plurality of first signal lines extending along the row direction and a plurality of second signal lines extending along the column direction; the orthographic projections of the second signal lines and the power signal lines on the substrate are located between the orthographic projections of two adjacent columns of sub-pixels on the substrate.

19. The display substrate according to claim 1, characterized in that: The display substrate further includes a plurality of spacers; At least two sides of the orthographic projection of the spacer on the substrate are surrounded by the orthographic projection of the power signal line on the substrate; a plurality of spacers located between two adjacent columns of sub-pixels are distributed on both sides of the power signal line; or The power signal line includes a portion extending along the column direction, and the orthographic projections of the plurality of spacers located between two adjacent columns of sub-pixels on the substrate are located on the same side of the orthographic projections of the adjacent portions extending along the column direction on the substrate; or, The spacer is located at a side of the power signal line away from the substrate, and an orthographic projection of the spacer on the substrate overlaps with an orthographic projection of the power signal line on the substrate.

20. The display substrate according to claim 1, characterized in that: The display substrate further comprises a pixel driving circuit, wherein the pixel driving circuit comprises a driving transistor; The orthographic projections of two adjacent driving transistors in the column direction on the substrate are located on opposite sides of the orthographic projections of adjacent power signal lines on the substrate; or, the orthographic projections of two adjacent driving transistors in the column direction on the substrate are located on the same side of the orthographic projections of adjacent power signal lines on the substrate.

21. The display substrate according to claim 1, characterized in that: The display substrate includes a display area and a frame area, the sub-pixel is located in the display area, the display substrate also includes a wire located in the frame area, the wire is electrically connected to the power signal line and the driving chip respectively; the display substrate also includes a metal conductive layer, the wire is located in the metal conductive layer.

22. The display substrate according to claim 1, characterized in that: The display substrate further comprises a light shielding layer located on a side of the sub-pixel away from the substrate, the light shielding layer is provided with a plurality of openings, and an orthographic projection of one of the openings on the substrate falls within an orthographic projection of one of the second electrodes on the substrate; the display substrate further comprises a plurality of first signal lines extending along the row direction; The power signal line includes a section located between two adjacent openings in the row direction and extending along the column direction, and the minimum distance between the edge of the orthographic projection of the section extending along the column direction on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate is in the range of 4 μm to 8 μm; and / or, The first electrode is located on a side of the first signal line away from the substrate, and the display substrate further comprises an insulating layer between the first signal line and the first electrode; in the column direction, a distance between an edge of an orthographic projection of the first signal line on the substrate and an edge of an orthographic projection of the second electrode on the substrate is in a range of 3 μm to 5 μm; and / or, The orthographic projection of the first signal line on the substrate falls within the orthographic projection of the shading layer on the substrate; the distance between the orthographic projection of the first signal line on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate extending along the row direction ranges from 6 μm to 11 μm.

23. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 22.

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