Chip time sequence path visualization method based on VSCode platform

Abstract

The invention relates to chip design, in particular to a chip time sequence path visualization method based on a VSCode platform, and the method comprises the steps: generating time sequence paths in the chip design, and collecting all generated time sequence paths into a time sequence path report; converting the time sequence path report into a text format which can be read by a VSCode platform by utilizing a text processing tool; screening out a specified target time sequence path and adjacent time sequence paths at the upper and lower levels of the target time sequence path from the time sequence paths after format conversion by setting related parameters; displaying the screened target time sequence path and the adjacent time sequence path in a graphical mode; according to the technical scheme provided by the invention, the defect that the chip time sequence path is difficult to visualize in the prior art can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to chip design, and in particular to a chip timing path visualization method based on a VSCode platform. Background Art

[0002] In the field of integrated circuit design, timing path analysis is a key step to ensure chip performance and reliability. It is used to ensure that data signal transmission and processing of different parts of the chip can occur at the correct time to avoid any possible performance problems or functional failures. Traditional timing path analysis usually relies on professional EDA tools to generate timing reports. However, these reports are often in text format, and it takes a lot of time for design engineers to understand and analyze this data. For chips with relatively complex design structures, design engineers can usually only see the path of a certain type of register when analyzing the timing path, and it is difficult to understand the timing paths of its upper and lower levels.

[0003] Chip timing path visualization is a method to show the specific path of data signal transmission and processing in the chip, which is crucial for optimizing chip design. This visualization method can clearly show the timing paths between the various logic nodes inside the chip and these logic nodes. These timing paths represent the transmission lines of data signals, which can help design engineers identify possible performance limiting factors and perform targeted optimization. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a chip timing path visualization method based on the VSCode platform, which can effectively overcome the defect of the prior art that it is difficult to visualize the chip timing path.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A chip timing path visualization method based on the VSCode platform includes the following steps: S1. Generate the timing paths in the chip design and summarize all the generated timing paths into a timing path report; S2. Use text processing tools to convert the timing path report into a text format that can be read by the VSCode platform; S3, filtering out a designated target timing path and adjacent timing paths of the target timing path from the timing paths after format conversion by setting relevant parameters; S4. Display the selected target timing paths and adjacent timing paths in a graphical manner.

[0006] Preferably, S1 generates timing paths in the chip design, and summarizes all generated timing paths into a timing path report, including: Use Design Compiler software to generate timing paths in chip design and summarize all generated timing paths into a timing path report; Among them, the timing path in the chip design includes the timing path from the data input port to the register, the timing path from the register to the register, the timing path from the register to the data output port, and the timing path from the data input port to the data output port.

[0007] Preferably, the use of Design Compiler software to generate timing paths in chip design and aggregating all generated timing paths into a timing path report includes: S11. Setting the design environment: including setting the process library path, configuring the process library, and setting the file reading path; S12, define the clock: including defining the clock period, duty cycle and port; S13, read the RTL design file; S14, generating a timing path report: including a timing path from a data input port to a register, a timing path from a register to a register, a timing path from a register to a data output port, and a timing path from a data input port to a data output port; Among them, the RTL design file is a Verilog file or a VHDL file.

[0008] Preferably, S2 uses a text processing tool to convert the timing path report into a text format readable by the VSCode platform, including: The text processing tool AWK is used to scan and process the timing path report, and the timing path report is converted into a text format readable by the VSCode platform to support further data screening.

[0009] Preferably, in S3, the specified target timing path and the adjacent timing paths of the target timing path and the adjacent timing paths of the target timing path are screened out from the timing paths after format conversion by setting relevant parameters, including: Based on the C++ language development environment of the VSCode platform, use libraries including iostream, fstream, sstream, cstdlib, vector, map, string, and commands including namespace, and set relevant parameters to filter out the specified target timing path and the adjacent timing paths of the target timing path from the timing path after format conversion; The relevant parameters include the register name of the target timing path and the number of upper and lower levels of the register.

[0010] Preferably, in S4, the screened target timing path and adjacent timing paths are displayed in a graphical manner, including: Based on the C++ language development environment of the VSCode platform, the digraph and graph tools in the Graphviz library are used to display the selected target timing paths and adjacent timing paths in a more intuitive graphical way to obtain the visualization results of the chip timing paths; Among them, the chip timing path visualization results include the specified target timing path and the adjacent timing paths above and below the target timing path, so as to intuitively analyze the timing relationship.

[0011] Compared with the prior art, the chip timing path visualization method based on the VSCode platform provided by the present invention has the following beneficial effects: 1) The timing report in the chip backend design is visually displayed in the form of topology. The path connection information between various registers, memories, and input / output ports in the design can be represented by connection relationships, which effectively helps design engineers to quickly analyze and adjust the timing path, improve the efficiency of timing path analysis and optimization, and help design engineers check and confirm the timing path, as well as analyze and set constraints for invalid paths; 2) This method has good scalability and is suitable for complex chip designs with multiple clock domains and multiple data paths. Through this method, design engineers can quickly locate the path connections of multiple levels above and below the target timing path, helping design engineers greatly improve work efficiency during timing optimization and code optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a schematic diagram of the process of the present invention; Figure 2 This is a schematic diagram of the visualization results of the chip timing path obtained by using the technical solution of the present invention. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] A chip timing path visualization method based on the VSCode (Visual Studio Code) platform, such as Figure 1 As shown, S1, generates the timing paths in the chip design, and summarizes all the generated timing paths into a timing path report, specifically including: Use Design Compiler software to generate timing paths in chip design and summarize all generated timing paths into a timing path report; Among them, the timing path in the chip design includes the timing path from the data input port to the register, the timing path from the register to the register, the timing path from the register to the data output port, and the timing path from the data input port to the data output port.

[0016] Specifically, Design Compiler software is used to generate the timing paths in the chip design, and all the generated timing paths are summarized into a timing path report, including: S11. Setting the design environment: including setting the process library path, configuring the process library, and setting the file reading path; S12, define the clock: including defining the clock period, duty cycle and port; S13, read the RTL design file; S14, generating a timing path report: including a timing path from a data input port to a register, a timing path from a register to a register, a timing path from a register to a data output port, and a timing path from a data input port to a data output port; Among them, the RTL design file is a Verilog file or a VHDL file.

[0017] S2. Use text processing tools to convert the timing path report into a text format that can be read by the VSCode platform, including: The text processing tool AWK is used to scan and process the timing path report, and the timing path report is converted into a text format readable by the VSCode platform to support further data screening.

[0018] S3. Filter out a specified target timing path and adjacent timing paths of the target timing path from the timing paths after format conversion by setting relevant parameters, including: Based on the C++ language development environment of the VSCode platform, use libraries including iostream, fstream, sstream, cstdlib, vector, map, string, and commands including namespace, and set relevant parameters to filter out the specified target timing path and the adjacent timing paths of the target timing path from the timing path after format conversion; The relevant parameters include the register name of the target timing path and the number of upper and lower levels of the register.

[0019] S4. Display the selected target timing paths and adjacent timing paths in a graphical manner, including: Based on the C++ language development environment of the VSCode platform, the digraph and graph tools in the Graphviz library (an open source toolkit for drawing graphs) are used to display the selected target timing paths and adjacent timing paths in a more intuitive graphical way to obtain the visualization results of the chip timing paths; Among them, the chip timing path visualization results include the specified target timing path and the adjacent timing paths above and below the target timing path, so as to intuitively analyze the timing relationship.

[0020] In the technical solution of this application, the register name of the target timing path is set to "adr*_block_tag_shdo_d1_reg_*_", the number of register levels is set to 1, and the final visualization result of the chip timing path is as follows: Figure 2 As shown. Through the visualization results of the chip timing path, design engineers can more intuitively analyze the connection relationship of the registers and determine whether there are logic and connection errors. Compared with the timing report format in this article, the visualization results of the chip timing path can help design engineers analyze and handle problems more efficiently.

[0021] In the technical solution of this application, the VSCode (Visual Studio Code) platform is a cross-platform source code editor that provides developers with built-in support for multiple programming languages, supporting development operations such as debugging, task execution, and version management.

[0022] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip timing path visualization method based on the VSCode platform, characterized by: The following steps are involved: S1. Generate the timing paths in the chip design and summarize all the generated timing paths into a timing path report; S2. Use text processing tools to convert the timing path report into a text format that can be read by the VSCode platform; S3, filtering out a designated target timing path and adjacent timing paths of the target timing path and its upper and lower levels from the timing paths after format conversion by setting relevant parameters; S4. Display the selected target timing paths and adjacent timing paths in a graphical manner.

2. The chip timing path visualization method based on the VSCode platform according to claim 1 is characterized in that: S1 generates the timing paths in the chip design and summarizes all the generated timing paths into a timing path report, including: Use Design Compiler software to generate timing paths in chip design and summarize all generated timing paths into a timing path report; Among them, the timing path in the chip design includes the timing path from the data input port to the register, the timing path from the register to the register, the timing path from the register to the data output port, and the timing path from the data input port to the data output port.

3. The chip timing path visualization method based on the VSCode platform according to claim 2 is characterized in that: The use of Design Compiler software to generate timing paths in chip design and summarizing all generated timing paths into a timing path report includes: S11. Setting the design environment: including setting the process library path, configuring the process library, and setting the file reading path; S12, define the clock: including defining the clock period, duty cycle and port; S13, read the RTL design file; S14, generating a timing path report: including a timing path from a data input port to a register, a timing path from a register to a register, a timing path from a register to a data output port, and a timing path from a data input port to a data output port; Among them, the RTL design file is a Verilog file or a VHDL file.

4. The chip timing path visualization method based on the VSCode platform according to claim 1 is characterized in that: In S2, text processing tools are used to convert the timing path report into a text format that can be read by the VSCode platform, including: The text processing tool AWK is used to scan and process the timing path report, and the timing path report is converted into a text format readable by the VSCode platform to support further data screening.

5. The chip timing path visualization method based on the VSCode platform according to claim 1 is characterized in that: In S3, by setting relevant parameters, the specified target timing path and the adjacent timing paths of the target timing path are screened out from the timing paths after format conversion, including: Based on the C++ language development environment of the VSCode platform, use libraries including iostream, fstream, sstream, cstdlib, vector, map, string, and commands including namespace, and set relevant parameters to filter out the specified target timing path and the adjacent timing paths of the target timing path from the timing path after format conversion; The relevant parameters include the register name of the target timing path and the number of upper and lower levels of the register.

6. The chip timing path visualization method based on the VSCode platform according to claim 1 is characterized in that: S4 graphically displays the selected target timing paths and adjacent timing paths, including: Based on the C++ language development environment of the VSCode platform, the digraph and graph tools in the Graphviz library are used to display the selected target timing paths and adjacent timing paths in a more intuitive graphical way to obtain the visualization results of the chip timing paths; Among them, the chip timing path visualization results include the specified target timing path and the adjacent timing paths above and below the target timing path, so as to intuitively analyze the timing relationship.

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