Pixel circuit and display device

Abstract

The invention provides a pixel circuit and a display device. The pixel circuit comprises a driving circuit, a light-emitting element and a first light-emitting control circuit. The driving circuit is electrically connected with the first electrode of the light-emitting element, and the driving circuit is used for generating a driving current for driving the light-emitting element under the control of the potential of the control end of the driving circuit; the first light-emitting control circuit is electrically connected with a first light-emitting control end, a second electrode of the light-emitting element and a first voltage end respectively, and is used for controlling the second electrode of the light-emitting element to be communicated with the first voltage end under the control of a first light-emitting control signal provided by the first light-emitting control end; the source electrode of a transistor included in the first light-emitting control circuit is electrically connected with the first voltage end. According to the invention, the signal crosstalk risk can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] In the relevant pixel circuit, the first light-emitting control circuit is arranged between the light-emitting element and the driving circuit. The source voltage of the transistor included in the first light-emitting control circuit is variable. Therefore, the gate signal of the transistor included in the first light-emitting control circuit requires a larger cross-voltage, and the risk of signal crosstalk is high. Summary of the invention

[0003] The main purpose of the present invention is to provide a pixel circuit and a display device to solve the problem that the gate signal of the transistor included in the first light emitting control circuit in the existing pixel circuit requires a large cross-voltage and the risk of signal crosstalk is high.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, including a driving circuit, a light-emitting element, and a first light-emitting control circuit;

[0005] The driving circuit is electrically connected to the first electrode of the light emitting element, and the driving circuit is used to generate a driving current to drive the light emitting element under the control of the potential of the control terminal thereof;

[0006] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element and the first voltage terminal respectively, and is used to control the second electrode of the light-emitting element to be connected to the first voltage terminal under the control of the first light-emitting control signal provided by the first light-emitting control terminal;

[0007] The source of the transistor included in the first light emitting control circuit is electrically connected to the first voltage terminal.

[0008] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a second light emitting control circuit;

[0009] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the second voltage terminal and the first terminal of the driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0010] The source of the transistor included in the second light emitting control circuit is electrically connected to the second voltage terminal;

[0011] The second end of the driving circuit is electrically connected to the first electrode of the light emitting element.

[0012] Optionally, the first light emitting control circuit includes a first transistor;

[0013] The gate of the first transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0014] The first transistor is an n-type transistor.

[0015] Optionally, the second light emitting control circuit includes a second transistor;

[0016] The gate of the second transistor is electrically connected to the second light emitting control terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit;

[0017] The second transistor is a p-type transistor.

[0018] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a third light emitting control circuit;

[0019] The third light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the first light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

[0020] Optionally, the third light emitting control circuit includes a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit;

[0021] The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal;

[0022] The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node;

[0023] The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node;

[0024] The second control circuit is electrically connected to the second light-emitting control node, the first light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the first light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

[0025] Optionally, the first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor;

[0026] The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node;

[0027] The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node;

[0028] The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node;

[0029] The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first light emitting control terminal;

[0030] The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first light emitting control terminal;

[0031] A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0032] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a fourth light emitting control circuit;

[0033] The fourth light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the second light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

[0034] Optionally, the fourth light emitting control circuit includes a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit;

[0035] The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal;

[0036] The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node;

[0037] The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node;

[0038] The second control circuit is electrically connected to the second light-emitting control node, the second light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the second light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

[0039] Optionally, the first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor;

[0040] The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node;

[0041] The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node;

[0042] The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node;

[0043] The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second light emitting control terminal;

[0044] The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second light emitting control terminal;

[0045] A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0046] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a first reset circuit;

[0047] The first reset circuit is electrically connected to the first reset end, the first pole of the light-emitting element and the second pole of the light-emitting element respectively, and is used to control the connection between the first pole of the light-emitting element and the second pole of the light-emitting element under the control of a first reset signal provided by the first reset end.

[0048] Optionally, the first reset circuit includes an eighth transistor;

[0049] The gate of the eighth transistor is electrically connected to the first reset terminal, the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element, and the second electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element.

[0050] Optionally, the pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit, a second write control circuit, a compensation control circuit and a second reset circuit;

[0051] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy;

[0052] The second write control circuit is electrically connected to the second write control terminal, the second data line and the first terminal of the drive circuit respectively, and is used to write the second data voltage provided by the second data line into the first terminal of the drive circuit under the control of the second write control signal provided by the second write control terminal;

[0053] The compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to control the communication between the control terminal of the drive circuit and the second terminal of the drive circuit under the control of the compensation control signal provided by the compensation control terminal;

[0054] The second reset circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the control terminal of the driving circuit respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the driving circuit under the control of the second reset signal provided by the second reset terminal.

[0055] Optionally, the second energy storage circuit includes a second capacitor; the second write control circuit includes a ninth transistor, the compensation control circuit includes a tenth transistor, the second reset circuit includes an eleventh transistor; and the drive circuit includes a drive transistor;

[0056] A first end of the second capacitor is electrically connected to the gate of the driving transistor, and a second end of the second capacitor is electrically connected to the second voltage end;

[0057] The gate of the ninth transistor is electrically connected to the second write control terminal, the first electrode of the ninth transistor is electrically connected to the second data line, and the second electrode of the ninth transistor is electrically connected to the first terminal of the driving circuit;

[0058] The gate of the tenth transistor is electrically connected to the compensation control terminal, the first electrode of the tenth transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the tenth transistor is electrically connected to the second terminal of the drive circuit;

[0059] The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the control terminal of the driving circuit;

[0060] The gate of the driving transistor is electrically connected to the control end of the driving circuit, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit.

[0061] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned pixel circuit.

[0062] In an embodiment of the present invention, a first light-emitting control circuit is arranged between a light-emitting element and a first voltage terminal, and by setting the type of transistor included in the first light-emitting control circuit, the source of the transistor is electrically connected to a DC voltage terminal (the first voltage terminal can be a DC voltage terminal), so that the gate voltage range of the transistor can be narrowed, and the gate voltage is centered around the voltage value of a first voltage signal provided by the first voltage terminal, and the on and off states are set to reduce the risk of signal crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 is a structural diagram of a pixel circuit according to an embodiment of the present invention;

[0064] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0065] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0066] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0067] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0068] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0069] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0070] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0071] Fig. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0072] Fig.10 yes Fig. 9 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0073] Fig.11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0074] Fig.12 yes Fig.11 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0075] Fig.13is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0076] Fig.14 yes Fig.13 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0077] Fig.15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0078] Fig.16 yes Fig.15 An operating timing diagram of at least one embodiment of the pixel circuit shown. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0080] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0081] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0082] like Figure 1 As shown, the pixel circuit described in the embodiment of the present invention includes a driving circuit 10, a light-emitting element E0 and a first light-emitting control circuit 11;

[0083] The driving circuit 10 is electrically connected to the first electrode of the light emitting element E0, and the driving circuit 10 is used to generate a driving current to drive the light emitting element E0 under the control of the potential of its control terminal;

[0084] The first light emitting control circuit 11 is electrically connected to the first light emitting control terminal E1, the second electrode of the light emitting element E0 and the first voltage terminal V1 respectively, and is used to control the second electrode of the light emitting element E0 to be connected to the first voltage terminal V1 under the control of the first light emitting control signal provided by the first light emitting control terminal E1;

[0085] The source of the transistor included in the first light emitting control circuit 11 is electrically connected to the first voltage terminal V1 .

[0086] In at least one embodiment of the present invention, the first voltage terminal V1 may be a low voltage terminal, but is not limited thereto.

[0087] In the related art, the first light-emitting control circuit 11 is arranged between the light-emitting element E0 and the driving circuit 10, and the source voltage of the transistor included in the first light-emitting control circuit 11 is variable, so the gate signal of the transistor included in the first light-emitting control circuit 11 requires a larger cross-voltage. Based on this, at least one embodiment of the present invention arranges the first light-emitting control circuit 11 between the light-emitting element E0 and the first voltage terminal V1, and by setting the type of transistor included in the first light-emitting control circuit 11, the source of the transistor is electrically connected to the DC voltage terminal (the first voltage terminal V1 can be a DC voltage terminal), so that the gate voltage range of the transistor can be narrowed, and the gate voltage is centered around the voltage value of the first voltage signal provided by the first voltage terminal V1, and the on-off state is set to reduce the risk of signal crosstalk.

[0088] In at least one embodiment of the present invention, the light emitting element E0 may be a Mini LED (mini light emitting diode) or a Micro LED (micro light emitting diode), but is not limited thereto. In a specific implementation, the light emitting element E0 may also be other types of light emitting elements, for example, the light emitting element E0 may also be an organic light emitting diode.

[0089] Mini LED and Micro LED have self-luminous characteristics and have the following advantages: high brightness, low power consumption, small size, ultra-high resolution and color saturation, etc. Micro LED is made of inorganic materials and has an absolute advantage in optical performance over OLED (organic light-emitting diode), which is also a self-luminous display. It has high luminous efficiency and long life. The material is not easily affected by the environment and is relatively stable, which can also avoid the phenomenon of afterimage. The current driving circuit in the display device using Mini LED or Micro LED adopts PWM (pulse width modulation) technology to solve the problem of low luminous efficiency of Mini LED and Micro LED at low current density and large brightness difference between light-emitting elements. The introduction of high-frequency PWM can improve the problem of screen flickering.

[0090] In the related art, for the PWM circuit that introduces the global high-frequency signal Shf, since the global high-frequency signal Shf is distributed throughout the entire display area and the voltage amplitude of Shf is relatively large, it has a serious coupling effect on the driving backplane, interferes with the voltage of important pixel potential nodes, affects the display quality, and also consumes a lot of logic power. However, at least one embodiment of the present invention can effectively reduce the voltage amplitude of the global high-frequency signal Shf, reduce the coupling effect of the global high-frequency signal Shf on the driving backplane, reduce the interference of Shf on the voltage of important pixel potential nodes, improve the display quality, and reduce the consumption of logic power.

[0091] like Figure 2 As shown, the pixel circuit according to at least one embodiment of the present invention may further include a second light emitting control circuit 20;

[0092] The second light emitting control circuit 20 is electrically connected to the second light emitting control terminal E2, the second voltage terminal V2 and the first terminal of the driving circuit 10 respectively, and is used to control the second voltage terminal V2 and the first terminal of the driving circuit 10 to be connected under the control of the second light emitting control signal provided by the second light emitting control terminal E2;

[0093] The source of the transistor included in the second light emitting control circuit 20 is electrically connected to the second voltage terminal V2;

[0094] The second end of the driving circuit is electrically connected to the first electrode of the light emitting element.

[0095] In a specific implementation, the pixel circuit may further include a second light-emitting control circuit 20. Under the control of a second light-emitting control signal, the second light-emitting control circuit 20 controls the connection between the second voltage terminal V2 and the first terminal of the driving circuit 10. The second voltage terminal V2 may be a DC voltage terminal. The type of transistor included in the second light-emitting control circuit may be set so that the source of the transistor included in the second light-emitting control circuit 20 is electrically connected to the second voltage terminal V2, so as to reduce the gate voltage range of the transistor included in the second light-emitting control circuit 20. The transistor included in the second light-emitting control circuit 20 is centered on the voltage value of the second voltage signal provided by the second voltage terminal V2, and is set to an on-state and an off-state, so as to reduce the risk of signal crosstalk.

[0096] Optionally, the first light emitting control circuit includes a first transistor;

[0097] The gate of the first transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first transistor is electrically connected to the first voltage terminal;

[0098] The first transistor is an n-type transistor.

[0099] Optionally, the second light emitting control circuit includes a second transistor;

[0100] The gate of the second transistor is electrically connected to the second light emitting control terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit;

[0101] The second transistor is a p-type transistor.

[0102] In at least one embodiment of the present invention, the pixel circuit further includes a third light emitting control circuit;

[0103] The third light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the first light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

[0104] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the pixel circuit may further include a third light-emitting control circuit; under the control of the first write control signal, the third light-emitting control circuit writes the first data voltage into the first light-emitting control node, and under the control of the first data voltage, controls the first light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal.

[0105] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the pixel circuit further includes a third light emitting control circuit 30;

[0106] The third light-emitting control circuit 30 is electrically connected to the first light-emitting control terminal E1, the first data line DT1, the first write control terminal W1, the third voltage terminal V3, the fourth voltage terminal V4, the first light-emitting control voltage terminal EM1 and the second light-emitting control voltage terminal HF, respectively, and is used to write the first data voltage Vdta1 provided by the first data line DT1 into the first light-emitting control node NC1 under the control of the first write control signal provided by the first write control terminal W1, and maintain the potential of the first light-emitting control node NC1, and control the first light-emitting control terminal E1 to be connected with the first light-emitting control voltage terminal EM1 or the second light-emitting control voltage terminal HF under the control of the first data voltage Vdata1.

[0107] In at least one embodiment of the present invention, the third voltage terminal V3 may be a low level terminal, and the fourth voltage terminal V4 may be a high level terminal.

[0108] In at least one embodiment of the present invention, the second light emitting control voltage terminal HF can be used to provide a global high-frequency signal Shf.

[0109] In at least one embodiment of the present invention, the third light emitting control circuit includes a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit;

[0110] The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal;

[0111] The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node;

[0112] The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node;

[0113] The second control circuit is electrically connected to the second light-emitting control node, the first light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the first light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

[0114] In a specific implementation, the third light-emitting control circuit may include a first write control circuit, a first control circuit, a second control circuit and a first energy storage circuit; the first write control circuit writes the first data voltage to the first light-emitting control node under the control of the first write control signal; the first energy storage circuit maintains the potential of the first light-emitting control node; the first control circuit controls the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node; the second control circuit controls the first light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the potential of the second light-emitting control node.

[0115] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the third light emitting control circuit may include a first writing control circuit 41, a first control circuit 42, a second control circuit 43 and a first energy storage circuit 44;

[0116] The first write control circuit 41 is electrically connected to the first write control terminal W1, the first data line DT1 and the first light-emitting control node NC1 respectively, and is used to write the first data voltage Vdata1 into the first light-emitting control node NC1 under the control of the first write control signal;

[0117] The first energy storage circuit 44 is electrically connected to the first light emitting control node NC1, and is used to maintain the potential of the first light emitting control node NC1;

[0118] The first control circuit 42 is electrically connected to the first light-emitting control node NC1, the third voltage terminal V3, the fourth voltage terminal V4 and the second light-emitting control node NC2 respectively, and is used to control the second light-emitting control node NC2 to be connected to the third voltage terminal V3 or the fourth voltage terminal V4 under the control of the potential of the first light-emitting control node NC1;

[0119] The second control circuit 43 is electrically connected to the second light-emitting control node NC2, the first light-emitting control terminal E1, the first light-emitting control voltage terminal EM1 and the second light-emitting control voltage terminal HF, respectively, and is used to control the connection between the first light-emitting control terminal E1 and the first light-emitting control voltage terminal EM1 or the second light-emitting control voltage terminal HF under the control of the potential of the second light-emitting control node NC2.

[0120] Optionally, the first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor;

[0121] The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node;

[0122] The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node;

[0123] The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node;

[0124] The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first light emitting control terminal;

[0125] The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first light emitting control terminal;

[0126] A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0127] The pixel circuit described in at least one embodiment of the present invention further includes a fourth light emitting control circuit;

[0128] The fourth light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the second light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

[0129] In a specific implementation, the pixel circuit may further include a fourth light-emitting control circuit, which, under the control of a first write control signal, writes a first data voltage into a first light-emitting control node and maintains the potential of the first light-emitting control node, and, under the control of the first data voltage, controls the second light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal.

[0130] like Figure 5 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a fourth light emitting control circuit 50;

[0131] The fourth light-emitting control circuit 50 is electrically connected to the second light-emitting control terminal E2, the first data line DT1, the first write control terminal W1, the third voltage terminal V3, the fourth voltage terminal V4, the first light-emitting control voltage terminal EM1 and the second light-emitting control voltage terminal HF, respectively, and is used to write the first data voltage Vdata1 provided by the first data line DT1 into the first light-emitting control node NC1 under the control of the first write control signal provided by the first write control terminal W1, and maintain the potential of the first light-emitting control node NC1, and under the control of the first data voltage, control the second light-emitting control terminal E2 to be connected with the first light-emitting control voltage terminal EM1 or the second light-emitting control voltage terminal HF2.

[0132] In at least one embodiment of the present invention, the fourth light emitting control circuit includes a second energy storage circuit, a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit;

[0133] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy;

[0134] The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal;

[0135] The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node;

[0136] The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node;

[0137] The second control circuit is electrically connected to the second light-emitting control node, the second light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the second light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

[0138] In a specific implementation, the fourth light-emitting control circuit may include a first write control circuit, a first control circuit, a second control circuit and a first energy storage circuit; the first write control circuit writes the first data voltage to the first light-emitting control node under the control of the first write control signal; the first energy storage circuit maintains the potential of the first light-emitting control node; the first control circuit controls the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node; the second control circuit controls the second light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the potential of the second light-emitting control node.

[0139] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the fourth light emitting control circuit includes a first writing control circuit 41, a first control circuit 42, a second control circuit 43 and a first energy storage circuit 44;

[0140] The first write control circuit 41 is electrically connected to the first write control terminal W1, the first data line DT1 and the first light-emitting control node NC1 respectively, and is used to write the first data voltage Vdata1 into the first light-emitting control node NC1 under the control of the first write control signal;

[0141] The first energy storage circuit 44 is electrically connected to the first light emitting control node NC1, and is used to maintain the potential of the first light emitting control node NC1;

[0142] The first control circuit 42 is electrically connected to the first light-emitting control node NC1, the third voltage terminal V3, the fourth voltage terminal V4 and the second light-emitting control node NC2 respectively, and is used to control the second light-emitting control node NC2 to be connected to the third voltage terminal V3 or the fourth voltage terminal V4 under the control of the potential of the first light-emitting control node NC1;

[0143] The second control circuit 43 is electrically connected to the second light-emitting control node NC2, the second light-emitting control terminal E2, the first light-emitting control voltage terminal EM1 and the second light-emitting control voltage terminal HF, respectively, and is used to control the connection between the second light-emitting control terminal E2 and the first light-emitting control voltage terminal EM1 or the second light-emitting control voltage terminal HF under the control of the potential of the second light-emitting control node NC2.

[0144] Optionally, the first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor;

[0145] The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node;

[0146] The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node;

[0147] The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node;

[0148] The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second light emitting control terminal;

[0149] The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second light emitting control terminal;

[0150] A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0151] The pixel circuit described in at least one embodiment of the present invention further includes a first reset circuit;

[0152] The first reset circuit is electrically connected to the first reset end, the first pole of the light-emitting element and the second pole of the light-emitting element respectively, and is used to control the connection between the first pole of the light-emitting element and the second pole of the light-emitting element under the control of a first reset signal provided by the first reset end.

[0153] In a specific implementation, the pixel circuit may further include a first reset circuit, which controls the first electrode of the light-emitting element and the second electrode of the light-emitting element to be connected under the control of a first reset signal to reset the light-emitting element.

[0154] In at least one embodiment of the present invention, through the design of a new first reset circuit, the resetting of the light-emitting element does not require the introduction of an external initial voltage; and the transistor included in the first reset circuit can be used as a detection switch during the yield detection of the driving backplane. During the manufacturing process of the driving backplane, the light-emitting element is not connected to the circuit through eutectic welding, die bonding or mass transfer technologies. By turning on the transistor included in the first reset circuit, the pixel circuit can be operated, thereby improving the detection rate of driving backplane defects.

[0155] Optionally, the first reset circuit includes an eighth transistor;

[0156] The gate of the eighth transistor is electrically connected to the first reset terminal, the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element, and the second electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element.

[0157] In at least one embodiment of the present invention, the pixel circuit may further include a second energy storage circuit, a second write control circuit, a compensation control circuit, and a second reset circuit;

[0158] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy;

[0159] The second write control circuit is electrically connected to the second write control terminal, the second data line and the first terminal of the drive circuit respectively, and is used to write the second data voltage provided by the second data line into the first terminal of the drive circuit under the control of the second write control signal provided by the second write control terminal;

[0160] The compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to control the communication between the control terminal of the drive circuit and the second terminal of the drive circuit under the control of the compensation control signal provided by the compensation control terminal;

[0161] The second reset circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the control terminal of the driving circuit respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the driving circuit under the control of the second reset signal provided by the second reset terminal.

[0162] In a specific implementation, the pixel circuit may further include a second energy storage circuit, a second write control circuit, a compensation control circuit and a second reset circuit; the second write control circuit writes the second data voltage provided by the second data line into the first end of the driving circuit under the control of a second write control signal; the compensation control circuit controls the connection between the control end of the driving circuit and the second end of the driving circuit under the control of the compensation control signal; the second reset circuit writes the second initial voltage into the control end of the driving circuit under the control of the second reset signal.

[0163] like Figure 7 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 70, a first reset circuit 71, a second write control circuit 72, a compensation control circuit 73 and a second reset circuit 74;

[0164] The second energy storage circuit 70 is electrically connected to the control end of the driving circuit 10 and is used to store electrical energy;

[0165] The first reset circuit 71 is electrically connected to the first reset terminal R1, the first pole of the light-emitting element E0, and the second pole of the light-emitting element E0, respectively, and is used to control the connection between the first pole of the light-emitting element E0 and the second pole of the light-emitting element E0 under the control of the first reset signal provided by the first reset terminal R1.

[0166] The second write control circuit 72 is electrically connected to the second write control terminal W2, the second data line DT2 and the first terminal of the drive circuit 10 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DT2 into the first terminal of the drive circuit 10 under the control of the second write control signal provided by the second write control terminal W2;

[0167] The compensation control circuit 73 is electrically connected to the compensation control terminal S0, the control terminal of the drive circuit 10 and the second terminal of the drive circuit 10 respectively, and is used to control the communication between the control terminal of the drive circuit 10 and the second terminal of the drive circuit 10 under the control of the compensation control signal provided by the compensation control terminal S0;

[0168] The second reset circuit 74 is electrically connected to the second reset terminal R2, the second initial voltage terminal I2 and the control terminal of the driving circuit 10 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 10 under the control of the second reset signal provided by the second reset terminal R2.

[0169] like Figure 8 As shown, in Figure 6Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 70, a first reset circuit 71, a second write control circuit 72, a compensation control circuit 73 and a second reset circuit 74;

[0170] The second energy storage circuit 70 is electrically connected to the control terminal of the driving circuit 10 and is used to store electrical energy;

[0171] The first reset circuit 71 is electrically connected to the first reset terminal R1, the first pole of the light-emitting element E0, and the second pole of the light-emitting element E0, respectively, and is used to control the connection between the first pole of the light-emitting element E0 and the second pole of the light-emitting element E0 under the control of the first reset signal provided by the first reset terminal R1.

[0172] The second write control circuit 72 is electrically connected to the second write control terminal W2, the second data line DT2 and the first terminal of the drive circuit 10 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DT2 into the first terminal of the drive circuit 10 under the control of the second write control signal provided by the second write control terminal W2;

[0173] The compensation control circuit 73 is electrically connected to the compensation control terminal S0, the control terminal of the drive circuit 10 and the second terminal of the drive circuit 10 respectively, and is used to control the communication between the control terminal of the drive circuit 10 and the second terminal of the drive circuit 10 under the control of the compensation control signal provided by the compensation control terminal S0;

[0174] The second reset circuit 74 is electrically connected to the second reset terminal R2, the second initial voltage terminal I2 and the control terminal of the driving circuit 10 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 10 under the control of the second reset signal provided by the second reset terminal R2.

[0175] Optionally, the second energy storage circuit includes a second capacitor, the second write control circuit includes a ninth transistor, the compensation control circuit includes a tenth transistor, the second reset circuit includes an eleventh transistor; and the drive circuit includes a drive transistor;

[0176] A first end of the second capacitor is electrically connected to the gate of the driving transistor, and a second end of the second capacitor is electrically connected to the second voltage end;

[0177] The gate of the ninth transistor is electrically connected to the second write control terminal, the first electrode of the ninth transistor is electrically connected to the second data line, and the second electrode of the ninth transistor is electrically connected to the first terminal of the driving circuit;

[0178] The gate of the tenth transistor is electrically connected to the compensation control terminal, the first electrode of the tenth transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the tenth transistor is electrically connected to the second terminal of the drive circuit;

[0179] The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the control terminal of the driving circuit;

[0180] The gate of the driving transistor is electrically connected to the control end of the driving circuit, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit.

[0181] like Fig. 9 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0; the light emitting element is a micro light emitting diode M1;

[0182] The first light emitting control circuit comprises a first transistor T1;

[0183] The gate of the first transistor T1 is electrically connected to the first light emitting control terminal E1, the drain of the first transistor T1 is electrically connected to the cathode of the micro light emitting diode M1, and the source of the first transistor T1 is electrically connected to the low voltage terminal VSS;

[0184] The first transistor T1 is an n-type transistor;

[0185] The second light emitting control circuit comprises a second transistor T2;

[0186] The gate of the second transistor T2 is electrically connected to the second light emitting control terminal E2, the source of the second transistor T2 is electrically connected to the high voltage terminal VDD, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor T0;

[0187] The second transistor T2 is a p-type transistor;

[0188] The first write control circuit includes a third transistor T3, the first control circuit includes a fourth transistor T4 and a fifth transistor T5, the second control circuit includes a sixth transistor T6 and a seventh transistor T7, and the first energy storage circuit includes a first capacitor C1;

[0189] The gate of the third transistor T3 is electrically connected to the first write control terminal W1, the source of the third transistor T3 is electrically connected to the first data line DT1, and the drain of the third transistor T3 is electrically connected to the first light emission control node NC1;

[0190] The gate of the fourth transistor T4 is electrically connected to the first light emission control node NC1, the source of the fourth transistor T4 is electrically connected to the low level end VGL, and the drain of the fourth transistor T4 is electrically connected to the second light emission control node NC2;

[0191] The gate of the fifth transistor T5 is electrically connected to the first light emission control node NC1, the source of the fifth transistor T5 is electrically connected to the high level terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the second light emission control node NC2;

[0192] The gate of the sixth transistor T6 is electrically connected to the second light emitting control node NC2, the source of the sixth transistor T6 is electrically connected to the first light emitting control voltage terminal EM1, and the drain of the sixth transistor T6 is electrically connected to the first light emitting control terminal E1;

[0193] The gate of the seventh transistor T7 is electrically connected to the second light emitting control node NC2, the source of the seventh transistor T7 is electrically connected to the second light emitting control voltage terminal HF, and the drain of the seventh transistor T7 is electrically connected to the first light emitting control terminal E1;

[0194] The first end of the first capacitor C1 is electrically connected to the first light emitting control node NC1, and the second end of the first capacitor C1 is electrically connected to the first initial voltage terminal I1; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit;

[0195] The first reset circuit comprises an eighth transistor T8;

[0196] The gate of the eighth transistor T8 is electrically connected to the first reset terminal R1, the source of the eighth transistor T8 is electrically connected to the anode of the micro light emitting diode M1, and the drain of the eighth transistor T8 is electrically connected to the cathode of the micro light emitting diode M1;

[0197] The second energy storage circuit includes a second capacitor C2; the second write control circuit includes a ninth transistor T9, the compensation control circuit includes a tenth transistor T10, and the second reset circuit includes an eleventh transistor T11;

[0198] A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor T0, and a second end of the second capacitor C2 is electrically connected to the high voltage terminal VDD;

[0199] The gate of the ninth transistor T9 is electrically connected to the second write control terminal W2, the source of the ninth transistor T9 is electrically connected to the second data line DT2, and the drain of the ninth transistor T9 is electrically connected to the source of the driving transistor T0;

[0200] The gate of the tenth transistor T10 is electrically connected to the compensation control terminal S0, the drain of the tenth transistor T10 is electrically connected to the gate of the driving transistor T0, and the source of the tenth transistor T10 is electrically connected to the drain of the driving transistor T0;

[0201] A gate of the eleventh transistor T11 is electrically connected to the second reset terminal R2 , a drain of the eleventh transistor T11 is electrically connected to the second initial voltage terminal I2 , and a second electrode of the eleventh transistor T11 is electrically connected to the gate of the driving transistor T0 .

[0202] exist Fig. 9 In at least one embodiment of the pixel circuit shown, the first node N1 is electrically connected to the gate of T0, the second node N2 is electrically connected to the source of T0, the third node N3 is electrically connected to the drain of T0, and the fourth node N4 is electrically connected to the cathode of M1.

[0203] exist Fig. 9 In at least one embodiment of the pixel circuit shown, T1 , T10 , T11 , T8 , T4 , T5 , and T7 are all n-type transistors, and the other transistors are all p-type transistors.

[0204] At least one embodiment of the present invention is a pixel circuit combining an n-type transistor and a p-type transistor to reduce the gate voltage amplitude range of T1 and the gate voltage amplitude range of T2. When a PWM circuit is introduced, the voltage amplitude of the global high-frequency signal Shf can be effectively reduced.

[0205] exist Fig. 9 In at least one embodiment of the pixel circuit shown, T10 and T11 are oxide transistors with a relatively low leakage current Ioff, which improves the leakage of the first node N1 and the third node N3;

[0206] T9 is a p-type transistor, T10 is an n-type transistor, and the second write control signal provided by W2 is in opposite phase to the compensation control terminal provided by S0.

[0207] In a specific implementation, T9 and T10 may both be n-type transistors, or T9 and T10 may both be p-type transistors. In this case, the gate of T9 and the gate of T10 may be electrically connected to the same control terminal, thereby reducing the number of driving circuits used.

[0208] In at least one embodiment of the present invention, in the pixel circuit, a transistor type suitable for the process capability can be selected according to the process capability and the offset characteristics under stress.

[0209] In the related art, due to the vertical manufacturing process of OLED, the pixel circuit can only use a common cathode or a common anode, and all transistors and capacitors are located on one side of the anode. In at least one embodiment of the present invention, the light emitting diode adopts a flip-chip structure, so that a transistor can be placed between the cathode of the light emitting diode and the low voltage terminal VSS.

[0210] exist Fig. 9 In at least one embodiment of the pixel circuit shown, the brightness of the pixel driving circuit can be measured by T8. When manufacturing the display panel, the light emitting diode is connected last, and the transistor and the capacitor are manufactured before the light emitting diode is connected. At this time, the third node N3 and the fourth node N4 can be controlled to be connected by T8 to test the performance of the pixel driving circuit.

[0211] like Fig.10 As shown, the present invention Fig. 9 When at least one embodiment of the pixel circuit shown is in operation, the nth frame display time may include a reset phase S1, a display data writing phase S2, a light emission control data writing phase S3 and a light emission phase S4 which are arranged successively;

[0212] In the reset phase S1, E2 provides a high voltage signal, EM1 provides a low voltage signal, R2 provides a high voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a high voltage signal, W1 provides a low voltage signal, T8 is turned on, the anode of M1 and the cathode of M1 are connected to reset M1; T2 is turned off, T3 is turned on, DT1 provides a reset signal to NC1 to reset the potential of NC1, and C1 maintains the potential of NC1; T11 is turned on to write the second initial voltage Vinit2 provided by I2 into the first node N1, so that T0 can be turned on when the display data writing phase S2 starts;

[0213] In the reset stage S1, the potential of the reset signal can be a low voltage, so that T4 is turned on, the potential of NC2 is a low voltage, T6 is turned on, E1 and EM1 are connected, and since EM1 provides a low voltage signal at this time, T1 is turned off;

[0214] In the display data writing phase S2, E2 provides a high voltage signal, EM1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a high voltage signal, W2 provides a low voltage signal, R1 provides a high voltage signal, W1 provides a high voltage signal, T9 is turned on, DT2 provides a second data voltage Vdata2 to the second node N2, Vdata2 can be a display data voltage, T10 is turned on, the first node N1 and the third node N3 are connected; T8 is turned on, the anode of M1 and the cathode of M1 are connected to reset M1;

[0215] At the beginning of the display data writing phase S2, T0 is turned on, and Vdata charges C2 through turned-on T9, T0, and T10 to increase the potential of the first node N1 until the potential of the first node N1 becomes Vdata2+Vth. When the charging is completed, T0 is turned off, and Vth is the threshold voltage of T0.

[0216] In the light emitting control data writing phase S4, E2 provides a high voltage signal, EM1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a low voltage signal, W1 provides a low voltage signal, T3 is turned on, DT1 provides a first data voltage Vdata1 to NC1, and the first data voltage Vdata1 can be a light emitting control data voltage;

[0217] In the light emission control data writing phase S3,

[0218] When the potential of Vdata1 is high, the potential of NC1 is high, C1 maintains the potential of NC1, T5 is turned on, T4 is turned off, NC2 is connected to the high level terminal VGH, the potential of NC2 is high, T7 is turned on, T6 is turned off, and E1 is connected to HF;

[0219] When the potential of Vdata1 is low, the potential of NC1 is low, and C1 maintains the potential of NC1; T5 is turned off, T4 is turned on, NC2 is connected to the low level terminal VGL, the potential of NC2 is low, T7 is turned off, T6 is turned on, and E1 is connected to EM1;

[0220] In the light-emitting stage S4, E2 provides a low voltage signal, EM1 provides a high voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a low voltage signal, W1 provides a high voltage signal, and T2 is turned on;

[0221] When the potential of Vdata1 is high voltage in the light-emitting control data writing stage S3, in the light-emitting stage S5, E1 is connected with HF, and HF provides a high-frequency signal. When HF provides a high-voltage signal, T1 is turned on, and the pixel circuit performs low-brightness display at this time. By setting the duty cycle of the high-frequency signal provided by HF, the light-emitting time of M1 can be controlled;

[0222] When the potential of Vdata1 is low voltage in the light emitting control data writing stage S3, in the light emitting stage S5, E1 and EM1 are connected, T1 is turned on, and the pixel circuit performs high brightness display.

[0223] exist Fig.10 , Fig.12 and Fig.14 Among them, the one labeled Fn is the display time of the nth frame, the one labeled Fn+1 is the display time of the n+1th frame, and n is a positive integer.

[0224] The present invention Fig.11 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Fig. 9 The differences of at least one embodiment of the pixel circuit shown are as follows: T3, T4, T5, T6, T7 and C1 are not included;

[0225] The gate of T1 is electrically connected to the first light emitting control terminal E1.

[0226] like Fig.12 As shown, the present invention Fig.11 When at least one embodiment of the pixel circuit shown is in operation, the nth frame display time may include a reset phase S1, a display data writing phase S2, and a light emitting phase S4 which are arranged successively;

[0227] In the reset phase S1, E2 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a high voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a high voltage signal, T8 is turned on, the anode of M1 and the cathode of M1 are connected to reset M1; T11 is turned on to write the second initial voltage Vinit2 provided by I2 into the first node N1, so that T0 can be turned on when the display data writing phase S2 starts;

[0228] In the display data writing phase S2, E2 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a high voltage signal, W2 provides a low voltage signal, R1 provides a high voltage signal, T9 is turned on, DT2 provides a second data voltage Vdata2 to the second node N2, Vdata2 can be a display data voltage, T10 is turned on, and the first node N1 is connected to the third node N3;

[0229] At the beginning of the display data writing phase S2, T0 is turned on, and Vdata charges C2 through turned-on T9, T0, and T10 to increase the potential of the first node N1 until the potential of the first node N1 becomes Vdata2+Vth. When the charging is completed, T0 is turned off, and Vth is the threshold voltage of T0.

[0230] In the light-emitting stage S4, E2 provides a low voltage signal, E1 provides a high voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a low voltage signal, T1 and T2 are turned on, T8 is turned off, and T0 drives M1 to emit light.

[0231] like Fig.13 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0; the light emitting element is a micro light emitting diode M1;

[0232] The first light emitting control circuit comprises a first transistor T1;

[0233] The gate of the first transistor T1 is electrically connected to the first light emitting control terminal E1, the drain of the first transistor T1 is electrically connected to the cathode of the micro light emitting diode M1, and the source of the first transistor T1 is electrically connected to the low voltage terminal VSS;

[0234] The first transistor T1 is an n-type transistor;

[0235] The second light emitting control circuit comprises a second transistor T2;

[0236] The gate of the second transistor T2 is electrically connected to the second light emitting control terminal E2, the source of the second transistor T2 is electrically connected to the high voltage terminal VDD, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor T0;

[0237] The second transistor T2 is a p-type transistor;

[0238] The first write control circuit includes a third transistor T3, the first control circuit includes a fourth transistor T4 and a fifth transistor T5, the second control circuit includes a sixth transistor T6 and a seventh transistor T7, and the first energy storage circuit includes a first capacitor C1;

[0239] The gate of the third transistor T3 is electrically connected to the first write control terminal W1, the source of the third transistor T3 is electrically connected to the first data line DT1, and the drain of the third transistor T3 is electrically connected to the first light emission control node NC1;

[0240] The gate of the fourth transistor T4 is electrically connected to the first light emission control node NC1, the source of the fourth transistor T4 is electrically connected to the low level end VGL, and the drain of the fourth transistor T4 is electrically connected to the second light emission control node NC2;

[0241] The gate of the fifth transistor T5 is electrically connected to the first light emission control node NC1, the source of the fifth transistor T5 is electrically connected to the high level terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the second light emission control node NC2;

[0242] The gate of the sixth transistor T6 is electrically connected to the second light emitting control node NC2, the source of the sixth transistor T6 is electrically connected to the first light emitting control voltage terminal EM1, and the drain of the sixth transistor T6 is electrically connected to the second light emitting control terminal E2;

[0243] The gate of the seventh transistor T7 is electrically connected to the second light emitting control node NC2, the source of the seventh transistor T7 is electrically connected to the second light emitting control voltage terminal HF, and the drain of the seventh transistor T7 is electrically connected to the second light emitting control terminal E2;

[0244] The first end of the first capacitor C1 is electrically connected to the first light emitting control node NC1, and the second end of the first capacitor C1 is electrically connected to the first initial voltage terminal I1; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit;

[0245] The second energy storage circuit includes a second capacitor C2; the second write control circuit includes a ninth transistor T9, the compensation control circuit includes a tenth transistor T10, and the second reset circuit includes an eleventh transistor T11;

[0246] A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor T0, and a second end of the second capacitor C2 is electrically connected to the high voltage terminal VDD;

[0247] The gate of the ninth transistor T9 is electrically connected to the second write control terminal W2, the source of the ninth transistor T9 is electrically connected to the second data line DT2, and the drain of the ninth transistor T9 is electrically connected to the source of the driving transistor T0;

[0248] The gate of the tenth transistor T10 is electrically connected to the compensation control terminal S0, the drain of the tenth transistor T10 is electrically connected to the gate of the driving transistor T0, and the source of the tenth transistor T10 is electrically connected to the drain of the driving transistor T0;

[0249] A gate of the eleventh transistor T11 is electrically connected to the second reset terminal R2 , a drain of the eleventh transistor T11 is electrically connected to the second initial voltage terminal I2 , and a second electrode of the eleventh transistor T11 is electrically connected to the gate of the driving transistor T0 .

[0250] exist Fig.13 In at least one embodiment of the pixel circuit shown, the first node N1 is electrically connected to the gate of T0, the second node N2 is electrically connected to the source of T0, the third node N3 is electrically connected to the drain of T0, and the fourth node N4 is electrically connected to the cathode of M1.

[0251] exist Fig.13 In at least one embodiment of the pixel circuit shown, T1 , T10 , T11 , T4 , T5 , and T7 are all n-type transistors, and the other transistors are all p-type transistors.

[0252] At least one embodiment of the present invention is a pixel circuit combining an n-type transistor and a p-type transistor to reduce the gate voltage amplitude range of T1 and the gate voltage amplitude range of T2. When a PWM circuit is introduced, the voltage amplitude of the global high-frequency signal Shf can be effectively reduced.

[0253] exist Fig.13 In at least one embodiment of the pixel circuit shown, T10 and T11 are oxide transistors with a relatively low leakage current Ioff, which improves the leakage of the first node N1 and the third node;

[0254] T9 is a p-type transistor, T10 is an n-type transistor, and the second write control signal provided by W2 is in opposite phase to the compensation control terminal provided by S0.

[0255] In a specific implementation, T9 and T10 may both be n-type transistors, or T9 and T10 may both be p-type transistors. In this case, the gate of T9 and the gate of T10 may be electrically connected to the same control terminal, thereby reducing the number of driving circuits used.

[0256] like Fig.14 As shown, the present invention Fig.13 When at least one embodiment of the driving circuit shown is in operation, the nth frame display time Fn may include a reset phase S1, a display data writing phase S2, a light emitting control data writing phase S3 and a light emitting phase S4 which are arranged successively;

[0257] In the reset phase S1, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a high voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, and W1 provides a low voltage signal; T3 is turned on, DT1 provides a reset signal to NC1 to reset the potential of NC1, and C1 maintains the potential of NC1; T11 is turned on to write the second initial voltage Vinit2 provided by I2 into the first node N1, so that T0 can be turned on when the display data writing phase S2 begins;

[0258] In the reset phase S1, the potential of the reset signal may be a low voltage, so that T4 is turned on, the potential of NC2 is a low voltage, T6 is turned on, E2 is connected to EM1, and since EM1 provides a high voltage signal at this time, T2 is turned off;

[0259] In the display data writing phase S2, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a high voltage signal, W2 provides a low voltage signal, W1 provides a high voltage signal, T9 is turned on, DT2 provides a second data voltage Vdata2 to the second node N2, Vdata2 can be a display data voltage, T10 is turned on, and the first node N1 is connected to the third node N3;

[0260] At the beginning of the display data writing phase S2, T0 is turned on, and Vdata charges C2 through turned-on T9, T0, and T10 to increase the potential of the first node N1 until the potential of the first node N1 becomes Vdata2+Vth. When the charging is completed, T0 is turned off, and Vth is the threshold voltage of T0.

[0261] In the light emitting control data writing phase S3, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, W1 provides a low voltage signal, T3 is turned on, DT1 provides a first data voltage Vdata1 to NC1, and the first data voltage Vdata1 can be a light emitting control data voltage;

[0262] In the light emission control data writing phase S3,

[0263] When the potential of Vdata1 is high, the potential of NC1 is high, C1 maintains the potential of NC1, T5 is turned on, T4 is turned off, NC2 is connected to the high level terminal VGH, the potential of NC2 is high, T7 is turned on, T6 is turned off, and E2 is connected to HF;

[0264] When the potential of Vdata1 is low, the potential of NC1 is low, and C1 maintains the potential of NC1; T5 is turned off, T4 is turned on, NC2 is connected to the low level terminal VGL, the potential of NC2 is low, T7 is turned off, T6 is turned on, and E2 is connected to EM1;

[0265] In the light-emitting stage S4, EM1 provides a low voltage signal, E1 provides a high voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, W1 provides a high voltage signal, and T1 is turned on;

[0266] When the potential of Vdata1 is high voltage in the light-emitting control data writing stage S3, in the light-emitting stage S5, E2 is connected with HF, and HF provides a high-frequency signal. When HF provides a high-voltage signal, T2 is turned on, and the pixel circuit performs low-brightness display. By setting the duty cycle of the high-frequency signal provided by HF, the light-emitting time of M1 can be controlled;

[0267] When the potential of Vdata1 is low voltage in the light emitting control data writing stage S3, in the light emitting stage S5, E2 is connected to EM1, T2 is turned on, and the pixel circuit performs high brightness display.

[0268] The present invention Fig.15 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Fig.13 The difference of at least one embodiment of the pixel circuit shown is as follows: Fig.15 At least one embodiment of the pixel circuit shown further includes an eighth transistor T8;

[0269] The gate of the eighth transistor T8 is electrically connected to the first reset terminal R1, the source of the eighth transistor T8 is electrically connected to the anode of the micro light emitting diode M1, and the drain of the eighth transistor T8 is electrically connected to the cathode of the micro light emitting diode M1;

[0270] T8 is an n-type transistor.

[0271] like Fig.16 As shown, the present invention Fig.15 When at least one embodiment of the pixel circuit shown is in operation, the nth frame display time Fn may include a reset phase S1, a display data writing phase S2, a light emission control data writing phase S3 and a light emission phase S4 which are arranged successively;

[0272] In the reset phase S1, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a high voltage signal, S0 provides a low voltage signal, W2 provides a high voltage signal, R1 provides a high voltage signal, and W1 provides a low voltage signal; T3 is turned on, DT1 provides a reset signal to NC1 to reset the potential of NC1, and C1 maintains the potential of NC1; T11 is turned on to write the second initial voltage Vinit2 provided by I2 to the first node N1, so that T0 can be turned on when the display data writing phase S2 begins; T8 is turned on, and the anode of M1 is connected to the cathode of M1;

[0273] In the reset phase S1, the potential of the reset signal may be a low voltage, so that T4 is turned on, the potential of NC2 is a low voltage, T6 is turned on, E2 is connected to EM1, and since EM1 provides a high voltage signal at this time, T2 is turned off;

[0274] In the display data writing phase S2, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a high voltage signal, R1 provides a high voltage signal, W2 provides a low voltage signal, W1 provides a high voltage signal, T9 is turned on, DT2 provides a second data voltage Vdata2 to the second node N2, Vdata2 can be a display data voltage, T10 is turned on, the first node N1 and the third node N3 are connected; T8 is turned on, the anode of M1 is connected to the cathode of M1;

[0275] At the beginning of the display data writing phase S2, T0 is turned on, and Vdata charges C2 through turned-on T9, T0, and T10 to increase the potential of the first node N1 until the potential of the first node N1 becomes Vdata2+Vth. When the charging is completed, T0 is turned off, and Vth is the threshold voltage of T0.

[0276] In the light emitting control data writing phase S3, EM1 provides a high voltage signal, E1 provides a low voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, R1 provides a low voltage signal, W2 provides a high voltage signal, W1 provides a low voltage signal, T3 is turned on, DT1 provides a first data voltage Vdata1 to NC1, and the first data voltage Vdata1 can be a light emitting control data voltage;

[0277] In the light emission control data writing phase S3,

[0278] When the potential of Vdata1 is high, the potential of NC1 is high, C1 maintains the potential of NC1, T5 is turned on, T4 is turned off, NC2 is connected to the high level terminal VGH, the potential of NC2 is high, T7 is turned on, T6 is turned off, and E2 is connected to HF;

[0279] When the potential of Vdata1 is low, the potential of NC1 is low, and C1 maintains the potential of NC1; T5 is turned off, T4 is turned on, NC2 is connected to the low level terminal VGL, the potential of NC2 is low, T7 is turned off, T6 is turned on, and E2 is connected to EM1;

[0280] In the light-emitting stage S4, EM1 provides a low voltage signal, E1 provides a high voltage signal, R2 provides a low voltage signal, S0 provides a low voltage signal, R1 provides a low voltage signal, W2 provides a high voltage signal, W1 provides a high voltage signal, and T1 is turned on;

[0281] When the potential of Vdata1 is high voltage in the light-emitting control data writing stage S3, in the light-emitting stage S5, E2 is connected with HF, and HF provides a high-frequency signal. When HF provides a high-voltage signal, T2 is turned on, and the pixel circuit performs low-brightness display. By setting the duty cycle of the high-frequency signal provided by HF, the light-emitting time of M1 can be controlled;

[0282] When the potential of Vdata1 is low voltage in the light emitting control data writing stage S3, in the light emitting stage S5, E2 is connected to EM1, T2 is turned on, and the pixel circuit performs high brightness display.

[0283] The display device described in the embodiment of the present invention includes the above-mentioned pixel circuit.

[0284] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a driving circuit, a light-emitting element and a first light-emitting control circuit; The driving circuit is electrically connected to the first electrode of the light emitting element, and the driving circuit is used to generate a driving current to drive the light emitting element under the control of the potential of the control terminal thereof; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element and the first voltage terminal respectively, and is used to control the second electrode of the light-emitting element to be connected to the first voltage terminal under the control of the first light-emitting control signal provided by the first light-emitting control terminal; The source of the transistor included in the first light emitting control circuit is electrically connected to the first voltage terminal.

2. The pixel circuit according to claim 1, wherein: Also includes a second light emitting control circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the second voltage terminal and the first terminal of the driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The source of the transistor included in the second light emitting control circuit is electrically connected to the second voltage terminal; The second end of the driving circuit is electrically connected to the first electrode of the light emitting element.

3. The pixel circuit according to claim 1, wherein: The first light emitting control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first light-emitting control terminal, the first electrode of the first transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the first transistor is electrically connected to the first voltage terminal; The first transistor is an n-type transistor.

4. The pixel circuit according to claim 2, characterized in that: The second light emitting control circuit includes a second transistor; The gate of the second transistor is electrically connected to the second light emitting control terminal, the first electrode of the second transistor is electrically connected to the second voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit; The second transistor is a p-type transistor.

5. The pixel circuit according to claim 1, wherein: Also includes a third light emitting control circuit; The third light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the first light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

6. The pixel circuit according to claim 5, characterized in that: The third light emitting control circuit includes a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit; The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal; The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node; The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node; The second control circuit is electrically connected to the second light-emitting control node, the first light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the first light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

7. The pixel circuit according to claim 6, characterized in that: The first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor; The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node; The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node; The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node; The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first light emitting control terminal; The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first light emitting control terminal; A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

8. The pixel circuit according to claim 2, characterized in that: Also includes a fourth light emitting control circuit; The fourth light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first data line, the first write control terminal, the third voltage terminal, the fourth voltage terminal, the first light-emitting control voltage terminal and the second light-emitting control voltage terminal, respectively, and is used to write the first data voltage provided by the first data line into the first light-emitting control node under the control of the first write control signal provided by the first write control terminal, and maintain the potential of the first light-emitting control node, and control the second light-emitting control terminal to be connected to the first light-emitting control voltage terminal or the second light-emitting control voltage terminal under the control of the first data voltage.

9. The pixel circuit according to claim 8, characterized in that: The fourth light emitting control circuit includes a first writing control circuit, a first control circuit, a second control circuit and a first energy storage circuit; The first write control circuit is electrically connected to the first write control terminal, the first data line and the first light-emitting control node respectively, and is used to write the first data voltage into the first light-emitting control node under the control of the first write control signal; The first energy storage circuit is electrically connected to the first light emitting control node, and is used to maintain the potential of the first light emitting control node; The first control circuit is electrically connected to the first light-emitting control node, the third voltage terminal, the fourth voltage terminal and the second light-emitting control node respectively, and is used to control the second light-emitting control node to be connected to the third voltage terminal or the fourth voltage terminal under the control of the potential of the first light-emitting control node; The second control circuit is electrically connected to the second light-emitting control node, the second light-emitting control end, the first light-emitting control voltage end and the second light-emitting control voltage end, respectively, and is used to control the connection between the second light-emitting control end and the first light-emitting control voltage end or the second light-emitting control voltage end under the control of the potential of the second light-emitting control node.

10. The pixel circuit according to claim 9, characterized in that: The first write control circuit includes a third transistor, the first control circuit includes a fourth transistor and a fifth transistor, the second control circuit includes a sixth transistor and a seventh transistor, and the first energy storage circuit includes a first capacitor; The gate of the third transistor is electrically connected to the first write control terminal, the first electrode of the third transistor is electrically connected to the first data line, and the second electrode of the third transistor is electrically connected to the first light emitting control node; The gate of the fourth transistor is electrically connected to the first light emission control node, the first electrode of the fourth transistor is electrically connected to the third voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second light emission control node; The gate of the fifth transistor is electrically connected to the first light emission control node, the first electrode of the fifth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second light emission control node; The gate of the sixth transistor is electrically connected to the second light emitting control node, the first electrode of the sixth transistor is electrically connected to the first light emitting control voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second light emitting control terminal; The gate of the seventh transistor is electrically connected to the second light emitting control node, the first electrode of the seventh transistor is electrically connected to the second light emitting control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second light emitting control terminal; A first end of the first capacitor is electrically connected to the first light emitting control node, and a second end of the first capacitor is electrically connected to a first initial voltage end.

11. The pixel circuit according to any one of claims 1 to 10, characterized in that: Also comprising a first reset circuit; The first reset circuit is electrically connected to the first reset end, the first pole of the light-emitting element and the second pole of the light-emitting element respectively, and is used to control the connection between the first pole of the light-emitting element and the second pole of the light-emitting element under the control of a first reset signal provided by the first reset end.

12. The pixel circuit according to claim 11, characterized in that: The first reset circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the first reset terminal, the first electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element, and the second electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element.

13. The pixel circuit according to any one of claims 1 to 10, characterized in that: It also includes a second energy storage circuit, a second write control circuit, a compensation control circuit and a second reset circuit; The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy; The second write control circuit is electrically connected to the second write control terminal, the second data line and the first terminal of the drive circuit respectively, and is used to write the second data voltage provided by the second data line into the first terminal of the drive circuit under the control of the second write control signal provided by the second write control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to control the communication between the control terminal of the drive circuit and the second terminal of the drive circuit under the control of the compensation control signal provided by the compensation control terminal; The second reset circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the control terminal of the driving circuit respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the driving circuit under the control of the second reset signal provided by the second reset terminal.

14. The pixel circuit according to claim 13, characterized in that: The second energy storage circuit includes a second capacitor; the second write control circuit includes a ninth transistor, the compensation control circuit includes a tenth transistor, the second reset circuit includes an eleventh transistor; the drive circuit includes a drive transistor; A first end of the second capacitor is electrically connected to the gate of the driving transistor, and a second end of the second capacitor is electrically connected to the second voltage end; The gate of the ninth transistor is electrically connected to the second write control terminal, the first electrode of the ninth transistor is electrically connected to the second data line, and the second electrode of the ninth transistor is electrically connected to the first terminal of the driving circuit; The gate of the tenth transistor is electrically connected to the compensation control terminal, the first electrode of the tenth transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the tenth transistor is electrically connected to the second terminal of the drive circuit; The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the control terminal of the driving circuit; The gate of the driving transistor is electrically connected to the control end of the driving circuit, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit.

15. A display device, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 14.

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