Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, a data line, a grid line, a semiconductor layer and a transistor. The semiconductor layer and the grid line are stacked and located between a film layer where the grid line is located and a film layer where the data line is located. The transistor comprises a grid electrode, an active layer, a first electrode and a second electrode, the grid electrode is electrically connected with the grid line, the first electrode is electrically connected with the data line, and the semiconductor layer comprises the active layer. The grid line is located on the side, away from the substrate, of the data line, the grid electrode and the data line are arranged on the same layer, the semiconductor layer comprises a semiconductor part stacked with the grid line, the semiconductor part and the active layer are arranged at an interval, and the display substrate further comprises a shading part which is arranged on the same layer with the data line and is perpendicular to the substrate. At least part of the semiconductor part is overlapped with the shading part, and at least part of the semiconductor part overlapped with the grid line is shaded through the shading part arranged on the same layer as the data line, so that bad transverse grains can be eliminated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] The display modes of the liquid crystal display panel include the Advanced Super Dimension Switching (ADS) display mode, the High Advanced-Super Dimensional Switching (HADS) display mode, etc. The ADS display mode is limited by the pixel structure, and the width of the dark field area at the data line position is relatively wide, which affects the transmittance of the display panel. It is often used in large-size display products, such as television (TV) products. In the HADS display mode, the width of the dark field area at the data line position is relatively narrow, and the transmittance of the display panel is relatively high. It is often used in small and medium-sized display products. However, in the display panel using the HADS display mode, since the common electrode covers the data line, when it is used in large-size display products, it is a big challenge to the charging rate. In order to reduce the load, the organic film (ORG) process can be used, but the process is relatively complicated. Summary of the invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device.

[0004] The embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a plurality of data lines, a plurality of gate lines, a semiconductor layer and a plurality of transistors located on the base substrate. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, the second direction intersecting with the first direction; the semiconductor layer is stacked with the film layer where the gate lines are located, and is located between the film layer where the gate lines are located and the film layer where the data lines are located; each transistor comprises a gate, an active layer, a first electrode and a second electrode, the gate is electrically connected to the gate line, the first electrode is electrically connected to the data line, the semiconductor layer comprises the active layer, and along a direction perpendicular to the base substrate, the gate, the first electrode and the second electrode all overlap with the active layer. The plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, the gate electrode is arranged in the same layer as the data line, the semiconductor layer includes a semiconductor portion stacked with the gate line, the semiconductor portion is spaced apart from the active layer, the display substrate also includes a light shielding portion, which is arranged in the same layer as the data line, and in a direction perpendicular to the base substrate, at least a portion of the semiconductor portion overlaps with the light shielding portion.

[0005] For example, according to an embodiment of the present disclosure, at least one gate line includes a protrusion and a gate line main body connected to each other, a straight line extending along the first direction passes through the gate and the orthographic projections of the protrusion on the substrate, the semiconductor portion includes a first semiconductor portion stacked with the protrusion and a second semiconductor portion stacked with the gate line main body, and more than 80% of the area of ​​the orthographic projection of the first semiconductor portion on the substrate falls within the orthographic projection of the shading portion on the substrate.

[0006] For example, according to an embodiment of the present disclosure, at least part of the edge of the light-shielding portion is farther away from the second semiconductor portion than the edge of the first semiconductor portion, and the orthographic projection of the first semiconductor portion on the substrate is completely within the orthographic projection of the light-shielding portion and the gate on the substrate.

[0007] For example, according to an embodiment of the present disclosure, along a direction perpendicular to the base substrate, a portion of the second semiconductor portion overlaps with the light shielding portion.

[0008] For example, according to an embodiment of the present disclosure, more than 70% of the area of ​​the orthographic projection of the second semiconductor portion stacked with the portion of the at least one gate line located between two adjacent data lines on the base substrate falls within the orthographic projection of the shading portion on the base substrate.

[0009] For example, according to an embodiment of the present disclosure, there are multiple light shielding portions, and at least one light shielding portion and a gate of at least one transistor are integrated into a structure.

[0010] For example, according to an embodiment of the present disclosure, a size of an overlapping portion between the integrated structure and the gate line main body in the first direction is greater than a size of an overlapping portion between the integrated structure and the protrusion in the first direction.

[0011] For example, according to an embodiment of the present disclosure, there are multiple light shielding portions, at least one light shielding portion is spaced apart from a gate of any transistor, and the light shielding portion is insulated from the gate line.

[0012] For example, according to an embodiment of the present disclosure, a gap is provided between the light shielding portion and the gate closest thereto, and at least a portion of the gap overlaps with the protrusion along a direction perpendicular to the base substrate.

[0013] For example, according to an embodiment of the present disclosure, a gap is provided between the at least one light shielding portion and the gate closest thereto, a portion of the gate away from the main body of the gate line electrically connected thereto protrudes toward the light shielding portion, and the shapes of the gate and the corresponding light shielding portion are complementary.

[0014] For example, according to an embodiment of the present disclosure, the light shielding portion includes a first light shielding portion overlapping the first semiconductor portion and a second light shielding portion overlapping the second semiconductor portion, and an edge of the second light shielding portion is closer to the data line than an edge of the first light shielding portion.

[0015] For example, according to an embodiment of the present disclosure, along a direction perpendicular to the base substrate, the main portion of the gate line does not overlap with the gate, and the gate is electrically connected to the protrusion.

[0016] For example, according to an embodiment of the present disclosure, the distance between the light shielding portion and the data line closest thereto is 2 to 15 micrometers.

[0017] For example, according to an embodiment of the present disclosure, the distance between the light shielding portion and the gate closest thereto is 2 to 15 micrometers.

[0018] For example, according to an embodiment of the present disclosure, a size of a portion of the light shielding portion that exceeds an edge of the semiconductor portion overlapping with the light shielding portion is greater than 1.65 micrometers and less than 5 micrometers.

[0019] For example, according to an embodiment of the present disclosure, the film layer where the gate line is located is in direct contact with the semiconductor layer.

[0020] For example, according to an embodiment of the present disclosure, the display substrate further includes: a first electrode layer, located between the data line and the base substrate, and a second electrode layer, located on a side of the gate line away from the data line. The first electrode layer includes a pixel electrode, the pixel electrode is electrically connected to the second electrode of the transistor, the second electrode layer includes a common electrode, the first electrode layer also includes a conductive portion, at least part of the conductive portion is stacked and directly in contact with the data line, and the second electrode layer also includes a plurality of connecting portions, and the gate is electrically connected to the protruding portion through at least one connecting portion.

[0021] An embodiment of the present disclosure provides a display device, comprising any of the above-mentioned display substrates.

[0022] For example, according to an embodiment of the present disclosure, the display device further includes: a backlight source located at the light incident side of the display substrate. The backlight source includes a pulse width modulation backlight source. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 It is a schematic diagram of a local planar structure of a display substrate.

[0025] Figure 2 For along Figure 1 The schematic diagram of the local cross-section structure taken along line AA' is shown.

[0026] FIG. 3A to FIG. 3C To form Figure 1 The process flow diagram of the display substrate is shown.

[0027] Figure 4 It is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure.

[0028] Figure 5 for Figure 4 The shown diagram is an enlarged view of part of the structure of the display substrate.

[0029] Figure 6 for Figure 5 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate.

[0030] Figure 7 for Figure 5 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate.

[0031] Figure 8 for Figure 5 The figure shows an enlarged view of the local structure of the display substrate.

[0032] Fig. 9 For along Figure 8 The diagram shows a partial cross-sectional structure schematically taken along line BB' in the display substrate.

[0033] Fig.10 For along Figure 8 The diagram shows a partial cross-sectional structure diagram of a substrate cut along line CC'.

[0034] Fig.11 for Figure 8 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate.

[0035] Fig.12 for Figure 8 The diagram shows a stacking diagram of the semiconductor layer in the substrate and the film layer where the gate line is located.

[0036] Fig.13 for Figure 8 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate.

[0037] Fig.14 A schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure.

[0038] Fig.15 for Fig.14 The diagram shows a partial structural diagram of a display substrate.

[0039] Fig.16 For along Fig.15 The diagram shows a partial cross-sectional structure of the substrate taken along line DD'.

[0040] Fig.17 for Fig.15 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate.

[0041] Fig.18 for Fig.15 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate.

[0042] Fig.19 It is a schematic diagram of a partial structure of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The features such as "parallel", "vertical" and "same" used in the embodiments of the present disclosure include the features such as "parallel", "vertical", "same" in the strict sense, and "approximately parallel", "approximately vertical", "approximately the same" and other situations containing certain errors, taking into account the measurement and the errors related to the measurement of a specific amount (for example, the limitations of the measurement system), indicating the acceptable deviation range for a specific value determined by ordinary technicians in the field. For example, "approximately" can be expressed within one or more standard deviations, or within 10% or 5% of the value. When the number of a component is not particularly indicated in the following of the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The “same-layer arrangement” referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different.

[0045] Figure 1 It is a schematic diagram of a local planar structure of a display substrate. Figure 2 For along Figure 1 The schematic diagram of the local cross-section structure cut by line AA' is shown in FIG. Figure 1 and Figure 2 As shown, the display substrate can adopt the HADS display mode, and the display substrate includes a base substrate 10, a plurality of data lines 11 and a plurality of gate lines 12 located on the base substrate 10, and the plurality of data lines 11 and the plurality of gate lines 12 are insulated and cross-arranged to define a plurality of sub-pixels. Each sub-pixel includes a pixel electrode 13, a common electrode 14 and a transistor 20, and the transistor 20 includes a first electrode 21, a second electrode 22 and a gate 23, and the gate line 12 is electrically connected to the gate 23 of the transistor 20 to control the opening or closing of the transistor 20, the pixel electrode 13 is electrically connected to the second electrode 22 of the transistor 20, and the data line 11 is electrically connected to the first electrode 21 of the transistor 20, and the data line 11 inputs the voltage signal required for displaying the picture to the pixel electrode 13 of the sub-pixel through the transistor 20 to realize the display of the display device including the display substrate.

[0046] like Figure 1As shown, the display substrate further includes a semiconductor layer 15 , which is stacked with the film layer where the gate line 12 is located, and the semiconductor layer 15 is located between the film layer where the gate line 12 is located and the base substrate 10 .

[0047] FIG. 3A to FIG. 3C To form Figure 1 The process flow diagram of the substrate is shown in FIG. Figure 2 and Figure 3A As shown, a half-tone mask patterning process is used to form the data line 11, the pixel electrode 13 and the gate 23 of the transistor 20. A conductive layer 31 is formed between the data line 11 and the base substrate 10 and is disposed on the same layer as the pixel electrode 13. Figure 2 and Figure 3B As shown, a half-tone mask patterning process is used to form the gate line 12, the common electrode line 16, the first electrode 21 and the second electrode 22 of the transistor 20, and a semiconductor layer 15 is formed between the gate line 12, the common electrode line 16, the first electrode 21 and the second electrode 22 of the transistor 20 and the base substrate 10. The semiconductor layer 15 includes an active layer 24 stacked with the first electrode 21 and the second electrode 22 of the transistor 20 and a semiconductor stacking portion 17 stacked with the gate line 12 and the common electrode line 16. Figure 1 , Figure 2 as well as Figure 3C As shown, a via 18 is formed in the insulating layer where the gate line 12 is away from the base substrate 10 and the data line 11 is away from the base substrate 10, and then a film layer where the common electrode 14 is located is formed on the side of the insulating layer away from the base substrate. The display substrate also includes multiple connecting parts 19 arranged on the same layer as the common electrode 14.

[0048] like Figure 1 As shown, the first electrode 21 of the transistor 20 is electrically connected to the data line 11 through the corresponding connecting portion 19, the second electrode 22 of the transistor 20 is electrically connected to the pixel electrode 13 through the corresponding connecting portion 19, the gate 23 of the transistor 20 is electrically connected to the gate line 12 through the corresponding connecting portion 19, and the common electrode line 16 is electrically connected to the common electrode 14 through the corresponding connecting portion 19. The connecting portion 19 connected to the common electrode line 16 can be an integrated structure with the common electrode 14.

[0049] like Figure 2 As shown, the display substrate further includes an insulating layer 32 and an insulating layer 33 . The insulating layer 32 is located between the semiconductor layer 15 and the film layer where the data line 11 is located, and the insulating layer 33 is located between the film layer where the common electrode 14 is located and the film layer where the gate line 12 is located.

[0050] exist Figure 3BIn the process steps shown, while the gate line and the semiconductor stack part are formed, the edge of the semiconductor stack part protrudes outward relative to the edge of the gate line. For example, the area of ​​the semiconductor stack part is larger than the area of ​​the gate line, and the distance between the edge of the semiconductor stack part and the common electrode, and / or the distance between the semiconductor stack part and the pixel electrode is closer, so that the coupling capacitance between the gate line directly in contact with the semiconductor stack part and the common electrode, and / or the gate line and the pixel electrode is larger.

[0051] The display substrate is applied to a liquid crystal display device, and the backlight source included in the liquid crystal display device is located on the side of the semiconductor stacking part away from the gate line. Since there is no light shielding layer between the semiconductor stacking part and the backlight source, the light emitted by the backlight source to the display substrate directly irradiates the semiconductor stacking part. For example, the backlight source can be a pulse width modulation (PWM) backlight source, and the on state and the off state of the backlight source are different, so that the conductive state of the semiconductor stacking part before and after being illuminated is different. This difference is directly reflected in the delay of the signal transmitted by the gate line, that is, the falling edge time Tf of the gate signal is different; when designing the display substrate, the gate output enable (Gate Output Enable, GOE) is certain, and when the backlight source is in different states of on and off, the gate line signal opening time is different, and the charging time of the sub-pixel is different, which will cause the sub-pixel to have a difference in brightness, thereby easily causing the risk of bad horizontal stripes.

[0052] The present disclosure provides a display substrate and a display device. The display substrate includes a display substrate, including: a substrate substrate and a plurality of data lines, a plurality of gate lines, a semiconductor layer and a plurality of transistors located on the substrate substrate. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and the second direction intersects with the first direction; the semiconductor layer is stacked with the film layer where the gate lines are located, and is located between the film layer where the gate lines are located and the film layer where the data lines are located; each transistor includes a gate, an active layer, a first electrode and a second electrode, the gate is electrically connected to the gate line, the first electrode is electrically connected to the data line, the semiconductor layer includes an active layer, and the gate, the first electrode and the second electrode are overlapped with the active layer in a direction perpendicular to the substrate substrate. The plurality of gate lines are located on a side of the plurality of data lines away from the substrate substrate, the gate and the data lines are arranged in the same layer, the semiconductor layer includes a semiconductor portion stacked with the gate lines, and the semiconductor portion is spaced apart from the active layer, the display substrate also includes a light shielding portion, which is arranged in the same layer as the data lines, and in a direction perpendicular to the substrate substrate, at least part of the semiconductor portion overlaps with the light shielding portion. The display substrate provided by the present disclosure sets the gate line on the side of the data line away from the base substrate, and at least partially shields the semiconductor part stacked with the gate line through a shading part set in the same layer as the data line, thereby reducing the influence of the switching of the backlight source on the capacitance of the gate line, thereby reducing the influence on the falling edge time of the gate signal transmitted on the gate line, and further eliminating the horizontal stripe defect.

[0053] The display substrate and the display device provided by the present disclosure are described below with reference to the accompanying drawings.

[0054] Figure 4 It is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure. Figure 5 for Figure 4 The shown diagram is an enlarged view of part of the structure of the display substrate. Figure 6 for Figure 5 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate. Figure 7 for Figure 5 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate. Figure 8 for Figure 5 The figure shows an enlarged view of the local structure of the display substrate. Fig. 9 For along Figure 8 The diagram shows a partial cross-sectional structure schematically taken along line BB' in the display substrate. Fig.10 For along Figure 8 The diagram shows a partial cross-sectional structure diagram of a substrate cut along line CC'. Fig.11 for Figure 8 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate. Fig.12 for Figure 8 The diagram shows a stacking diagram of the semiconductor layer in the substrate and the film layer where the gate line is located. Fig.13 for Figure 8 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate.

[0055] like Figure 4 , Figure 8 , Fig. 9 and Fig.10 As shown, the display substrate includes a base substrate 01, and a plurality of data lines 100, a plurality of gate lines 200, a semiconductor layer 300 and a plurality of transistors 400 located on the base substrate 01. The plurality of data lines 100 are arranged along a first direction, and the plurality of gate lines 200 are arranged along a second direction, and the first direction intersects the second direction. Figure 4 The first direction is schematically shown as the X direction and the second direction is the Y direction. For example, the first direction and the second direction can be interchanged. For example, the first direction is perpendicular to the second direction. For example, the angle between the first direction and the second direction can be 80 to 100 degrees.

[0056] For example, Figure 4 As shown, a plurality of data lines 100 and a plurality of gate lines 200 are insulated and cross-arranged to define a plurality of pixel regions, each of which is provided with a sub-pixel. Figures 5 to 7 A pixel area is schematically shown.

[0057] For example, Figure 4 and Figure 5 As shown, a sub-pixel may include at least one transistor 400. The embodiment of the present disclosure schematically shows that a sub-pixel includes one transistor 400, but is not limited thereto and may also include two or more sub-pixels. For example, the display substrate includes a plurality of sub-pixels. For example, the plurality of sub-pixels are arranged in an array along a first direction and a second direction.

[0058] like Figure 4 , Figures 8 to 13 As shown, the semiconductor layer 300 is stacked with the film layer where the gate line 200 is located, and is located between the film layer where the gate line 200 is located and the film layer where the data line 100 is located; each transistor 400 includes a gate 403, an active layer 404, a first electrode 401 and a second electrode 402, the gate 403 is electrically connected to the gate line 200, the first electrode 401 is electrically connected to the data line 100, the semiconductor layer 300 includes an active layer 404, and along a direction perpendicular to the substrate 01, the gate 403, the first electrode 401 and the second electrode 402 are all overlapped with the active layer 404. For example, when the display substrate is applied to a liquid crystal display device, the liquid crystal display device includes a backlight source, such as a pulse width modulation (PWM) backlight source, and the gate 403 is located between the active layer 404 and the backlight source, and the gate 403 can shield the active layer 404 to prevent the light emitted by the backlight source from irradiating the active layer 404. For example, the gate line 200 controls the opening or closing of the transistor 400 , and the data line 100 inputs a voltage signal required for displaying a picture to the pixel electrode 611 (described later) of the sub-pixel through the transistor 400 to realize display of the display device including the display substrate.

[0059] For example, one of the first pole 401 and the second pole 402 of the transistor 400 is a source, and the other is a drain. For example, the transistor 400 may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain thereof may be indistinguishable in structure. In one embodiment of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is the second pole, so the first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure are interchangeable as needed. For example, the first pole of the transistor described in the embodiment of the present disclosure may be a source, and the second pole may be a drain; or, the first pole of the transistor may be a drain, and the second pole may be a source. In addition, transistors may be divided into N-type transistors and P-type transistors according to the characteristics of the transistor. The transistor provided in the embodiment of the present disclosure may adopt an N-type transistor or a P-type transistor according to actual needs.

[0060] like Figure 4 , Figures 8 to 13 As shown, a plurality of gate lines 200 are located on a side of a plurality of data lines 100 away from a substrate 01, a gate 403 is disposed in the same layer as the data line 100, and a semiconductor layer 300 includes a semiconductor portion 310 stacked with the gate line 200, and the semiconductor portion 310 is spaced apart from an active layer 404. For example, in a direction perpendicular to the substrate 01, the active layer 404 does not overlap with the gate line 200, and the semiconductor portion 310 does not overlap with the first electrode 401 and the second electrode 402 of the transistor 400. For example, the active layer 404 is insulated from the semiconductor portion 310.

[0061] Generally, a display substrate adopting the HADS display mode has an organic insulating layer arranged between the data line and the electrode (ITO) on the side away from the base substrate to increase the distance between the data line and the electrode. However, compared with a display substrate adopting the ADS display mode, a display substrate adopting the HADS display mode has an additional process for manufacturing the organic insulating layer, thereby increasing the process complexity.

[0062] Compared with display devices generally adopting the HADS display mode, in the display substrate provided by the present invention, the film layers of the data lines and the gate lines are interchanged, which not only allows a large distance to remain between the data lines and electrodes, such as the common electrode (described later), to reduce the coupling capacitance between the two and reduce the load on the data lines, but also allows the same preparation process as the display substrate adopting the ADS display mode to achieve unchanged process complexity and improve the transmittance of the display substrate.

[0063] like Figure 4 , Figure 8 as well as Figures 11 to 13 As shown, the display substrate further includes a light shielding portion 500, which is disposed in the same layer as the data line 100, and in a direction perpendicular to the base substrate 01, at least a portion of the semiconductor portion 310 overlaps with the light shielding portion 500. For example, the light shielding portion 500 is disposed in the same layer as the gate 403.

[0064] In the display substrate provided by the present disclosure, while the gate line is arranged to be located on the side of the data line away from the base substrate, at least a portion of the semiconductor portion stacked with the gate line is shielded by a shading portion arranged in the same layer as the data line, thereby reducing the influence of the switching of the backlight source on the capacitance of the gate line, thereby reducing the influence on the falling edge time of the gate signal transmitted on the gate line, and further eliminating horizontal stripe defects.

[0065] and Figure 1 Compared with the display substrate shown in the figure, the display substrate provided by the present disclosure provides a light shielding portion between the semiconductor portion stacked with the gate lines and the backlight source to effectively shield the backlight source from directly irradiating the semiconductor portion, thereby eliminating the risk of horizontal stripe defects.

[0066] In some examples, such as Figure 4As shown, there are multiple light shielding portions 500, and at least one light shielding portion 500 is an integrated structure with the gate 403 of at least one transistor 400. For example, the gate 403 of at least one transistor 400 is multiplexed as the light shielding portion 500. For example, the gates 403 of each transistor 400 are multiplexed as the light shielding portion 500.

[0067] In some examples, such as Figure 4 , Figure 8 and Fig.12 As shown, at least one gate line 200 includes a protrusion 210 and a gate line main body 220 connected to each other. For example, the protrusion 210 in the gate line 200 is a part of the gate line 200, and the gate line 200 includes a linear structure extending along the X direction, that is, the gate line main body 220, and a protrusion 210 connected to the linear structure, and the protrusion 210 is a part protruding toward the second pole 402 of the transistor 400 relative to the gate line main body 220. For example, the protrusion 210 and the gate line main body 220 are structures that are integrally arranged. For example, the dividing line between the protrusion 210 and the gate line main body 220 can be the dividing line L1 shown in the figure.

[0068] For example, Figure 4 , Figure 8 and Fig.12 As shown, at least one gate line 200 includes a plurality of protrusions 210 and a gate line main body 220, each transistor 400 corresponds to a protrusion 210, and the plurality of protrusions 210 are located on the same side of the gate line main body 220. For example, each gate line 200 includes a protrusion 210, such as each gate line 200 includes a plurality of protrusions 210 and a gate line main body 220.

[0069] In some examples, such as Figure 4 , Figure 8 , Figures 11 to 13 As shown, a straight line extending along the first direction passes through the orthographic projection of the gate 403 and the protrusion 210 on the substrate. For example, along a direction perpendicular to the substrate 01, at least a portion of the protrusion 210 overlaps with the gate 403. For example, the gate 403 is electrically connected to the protrusion 210 to achieve electrical connection with the gate line 200.

[0070] In some examples, such as Fig.12 As shown, the semiconductor portion 310 includes a first semiconductor portion 311 stacked with the protrusion 210 and a second semiconductor portion 312 stacked with the gate line main body 220. For example, the first semiconductor portion 311 and the second semiconductor portion 312 are integrated. Fig.12 A boundary line L2 between the first semiconductor portion 311 and the second semiconductor portion 312 is schematically shown. The boundary line L2 is closer to the active layer 404 of the transistor 400 than the boundary line L1 .

[0071] For example, Fig.12 As shown, the planar shape of the first semiconductor portion 311 may be substantially the same as the planar shape of the protrusion 210, and the area of ​​the first semiconductor portion 311 is slightly larger than the area of ​​the protrusion 210. For example, the planar shape of the second semiconductor portion 312 may be a long strip, the length of the second semiconductor portion 312 is slightly larger than the length of the gate line main body 220, and the width of the second semiconductor portion 312 is slightly larger than the width of the gate line main body 220.

[0072] In some examples, such as Fig.10 As shown, the film layer where the gate line 200 is located is in direct contact with the semiconductor layer 300 .

[0073] For example, Fig.12 As shown, the pattern of the layer where the gate line 200 is located and the pattern of the layer where the semiconductor part 310 is located are formed using the same mask plate, such as a half-tone mask process, the two layers of patterns are stacked and directly contacted, and the edge of the semiconductor part 310 protrudes relative to the edge of the gate line 200, as shown in FIG. Fig.12 It is shown that the edge of the semiconductor portion 310 is located outside the edge of the gate line 200, and the portion of the edge of the semiconductor portion 310 protruding relative to the edge of the gate line 200 can be called an active layer tail (ActTail). Therefore, the area of ​​the first semiconductor portion is slightly larger than the area of ​​the protruding portion, and the width of the second semiconductor portion is slightly larger than the width of the gate line body.

[0074] For example, Fig.11 As shown, the pattern of the layer where the data line 100 is located and the pattern of the layer where the pixel electrode 611 is located are formed by using the same mask plate, such as a half-tone mask process, and the two layers of patterns are stacked and directly contacted.

[0075] For example, Fig.12 As shown, the orthographic projection of the gate line 200 on the substrate is completely located within the orthographic projection of the semiconductor portion 310 on the substrate.

[0076] For example, Fig.12As shown, the semiconductor layer 300 also includes an active stacked portion 320, and the active stacked portion 320 and the active layer 404 are an integrated structure, the active stacked portion 320 overlaps with a portion of the first pole 401 and the second pole 402 of the transistor 300, and the active layer 404 overlaps with another portion of the first pole 401 and the second pole 402 of the transistor 400. For example, the orthographic projection of the active layer 404 on the substrate is completely located within the orthographic projection of the gate 403 on the substrate, and the active stacked portion 320 overlaps with the data line 100 and the pixel electrode 611 (described later). For example, the orthographic projection of the first pole 401 and the second pole 402 of the transistor 400 on the substrate is completely located within the orthographic projection of the structure of the active stacked portion 320 and the active layer 404 integrated on the substrate. For example, the semiconductor layer 300 overlapping with the first pole 401 of the transistor 400 and the semiconductor layer 300 overlapping with the second pole 402 of the transistor 400 are an integrated structure.

[0077] In some examples, such as Figure 12 to Figure 14 As shown, more than 80% of the area of ​​the orthographic projection of the first semiconductor portion 311 on the base substrate falls within the orthographic projection of the light shielding portion 500 on the base substrate.

[0078] and Figure 1 Compared with the display substrate shown in the figure, the display substrate provided by the present invention sets a shading portion between the first semiconductor portion and the backlight source, and makes more than 80% of the first semiconductor portion covered by the shading portion, so as to effectively block the backlight source from directly irradiating the first semiconductor portion, which is beneficial to reduce the risk of horizontal stripe defects.

[0079] For example, Figure 12 to Figure 13 As shown, more than 85% of the area of ​​the orthographic projection of the first semiconductor portion 311 on the substrate falls within the orthographic projection of the light shielding portion 500 (or the gate 403) on the substrate. For example, more than 90% of the area of ​​the orthographic projection of the first semiconductor portion 311 on the substrate falls within the orthographic projection of the light shielding portion 500 (or the gate 403) on the substrate. For example, more than 95% of the area of ​​the orthographic projection of the first semiconductor portion 311 on the substrate falls within the orthographic projection of the light shielding portion 500 (or the gate 403) on the substrate. For example, the orthographic projection of the first semiconductor portion 311 on the substrate completely falls within the orthographic projection of the light shielding portion 500 (or the gate 403) on the substrate.

[0080] In the display substrate provided by the present disclosure, by setting the shading portion and the gate of the transistor as an integrated structure, the first semiconductor portion can be shielded as much as possible, such as completely covering the first semiconductor portion to more effectively reduce the direct irradiation of the backlight source to the first semiconductor portion, further reducing the risk of horizontal stripe defects.

[0081] In some examples, such as Figure 8 , Figures 11 to 13 As shown, along the direction perpendicular to the substrate (such as the direction perpendicular to the XY plane), part of the second semiconductor portion 312 overlaps with the light shielding portion 500. For example, the number of the light shielding portions 500 is multiple, and along the direction perpendicular to the substrate, the second semiconductor portion 312 includes a first portion overlapping with the light shielding portion 500 and a second portion overlapping with the data line 100, and the first portion and the second portion are alternately arranged along the X direction. For example, the two distances between the portion of the light shielding portion 500 located between two adjacent data lines 100 that overlaps with the second semiconductor portion 312 and the two adjacent data lines 100 may be the same or different.

[0082] By arranging the light shielding portion to shield the second semiconductor portion in the semiconductor layer that overlaps with the main portion of the gate line, it is beneficial to further reduce the influence of the illuminated semiconductor layer on the signal in the gate line.

[0083] In some examples, such as Figure 8 and Fig.13 As shown, more than 70% of the area of ​​the orthographic projection of the second semiconductor portion 312 stacked with the portion of at least one gate line 200 located between two adjacent data lines 100 on the substrate substrate falls within the orthographic projection of the light shielding portion 500 on the substrate substrate. For example, taking the second semiconductor portion 312 overlapping with one gate line 200 as one second semiconductor portion 312 as an example, more than 70% of the area of ​​the orthographic projection of the portion of at least one second semiconductor portion 312 located between two adjacent data lines 100 on the substrate substrate falls within the orthographic projection of the light shielding portion 500 on the substrate substrate. For example, more than 70% of the orthographic projection of at least one second semiconductor portion 312, except for the portion overlapping with the data line 100, on the substrate substrate 01 falls within the orthographic projection of the light shielding portion 500 on the substrate substrate.

[0084] By setting more than 70% of the second semiconductor portion between adjacent data lines to overlap with the shading portion, the area of ​​the second semiconductor portion directly illuminated by the backlight source can be greatly reduced, thereby reducing the impact of the second semiconductor portion irradiated by light on the signal on the gate line.

[0085] In some examples, such as Figure 8 , Figures 11 to 13 As shown, the integrated structure, such as the gate 403 reused as the shading portion 500 or the shading portion 500 reused as the gate 403, has a size in the first direction of the overlapping portion with the gate line main body 220 that is larger than the size in the first direction of the overlapping portion of the integrated structure and the protrusion 210.

[0086] In some examples, such as Figures 11 to 13As shown, the size of the portion of the gate 403 overlapping with the protrusion 210 of the gate line 200 in the Y direction is larger than the size of the portion of the gate 403 overlapping with the active layer 404 in the Y direction so that the edge of the gate 403 protrudes more than the edge of the protrusion 210, which is beneficial for the gate reused as a light-shielding portion to shield the semiconductor portion at the edge of the protrusion.

[0087] In some examples, such as Figures 11 to 13 As shown, at least part of the edge of the light shielding portion 500 is further away from the second semiconductor portion 312 than the edge of the first semiconductor portion 311, and the orthographic projection of the first semiconductor portion 311 on the substrate is completely located within the orthographic projection of the light shielding portion 500 and the gate 403 on the substrate. For example, the orthographic projection of the first semiconductor portion 311 on the substrate is completely located within the orthographic projection of the gate 403 multiplexed as the light shielding portion 500 on the substrate.

[0088] In some examples, such as Fig.13 As shown, the dimension D2 of the portion of the light shielding portion 500 that exceeds the edge of the semiconductor portion 310 that overlaps with it is greater than 1.65 microns and less than 5 microns, so that after considering the process fluctuations and the fluctuations of the critical dimension value, the light shielding portion can still block the influence of the backlight on the semiconductor portion. For example, the dimension D2 of the edge of the light shielding portion 300 that exceeds the edge of the semiconductor portion 310 can be 2 to 4 microns, or 2.5 to 4.5 microns, or 3 to 3.5 microns, etc. For example, the dimension of the portion of the light shielding portion 500 that exceeds the edge of the first semiconductor portion 311 that overlaps with it can be the above-mentioned dimension D2. For example, the dimension of the portion of the light shielding portion 500 that exceeds the edge of the second semiconductor portion 312 that overlaps with it can be the above-mentioned dimension D2.

[0089] In some examples, such as Fig.13 As shown, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto is 2 to 15 microns, so that the light shielding portion protrudes as much as possible toward the data line direction to block the backlight from irradiating the semiconductor portion, while avoiding a short circuit between the light shielding portion and the data line. For example, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto may be 4.5 to 12 microns. For example, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto may be 4.8 to 10 microns. For example, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto may be 5 to 8 microns. For example, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto may be 6 to 9 microns. For example, the distance D1 between the light shielding portion 500 and the data line 100 closest thereto may be 5.5 to 7 microns.

[0090] In some examples, such as Figures 11 to 13As shown, the light shielding portion 500 includes a first light shielding portion 510 overlapping the first semiconductor portion 311 and a second light shielding portion 520 overlapping the second semiconductor portion 312 , and the edge of the second light shielding portion 520 protrudes toward both sides relative to the edge of the first light shielding portion 510 . Fig.11 The schematic diagram shows the positional relationship between the first light shielding portion 510 and the second light shielding portion 520 when the gate 403 is multiplexed as the light shielding portion 500 .

[0091] For example, Figure 8 and Fig.11 As shown, the distance between the first light shielding portion 510 and the data line 100 located on the left side thereof is smaller than the distance between the first light shielding portion 510 and the data line 100 located on the right side thereof, such as a portion of the common electrode 621 extending along the Y direction is provided between the first light shielding portion 510 and the data line 100 located on the right side thereof, so that the first light shielding portion shields the active layer and the first semiconductor portion while minimizing the overlapping area of ​​the common electrode and the gate line, and preventing the connection portion electrically connected to the data line from being short-circuited with the common electrode provided on the same layer. The direction indicated by the arrow in the X direction in the figure is rightward. For example, in a direction perpendicular to the substrate, the protrusion 210 does not overlap with the common electrode 621.

[0092] In some examples, such as Figures 4 to 13 As shown, the display substrate further includes a first electrode layer 610 and a second electrode layer 620 which are stacked, the first electrode layer 610 is located between the data line 400 and the base substrate 01, and the second electrode layer 620 is located on the side of the gate line 200 away from the data line 100. The first electrode layer 610 includes a pixel electrode 611, the pixel electrode 611 is electrically connected to the second electrode 402 of the transistor 400, the second electrode layer 620 includes a common electrode 621, the first electrode layer 610 further includes a conductive portion 612, at least part of the conductive portion 612 is stacked and directly in contact with the data line 100, the second electrode layer 620 further includes a plurality of connecting portions 622, and the gate 403 is electrically connected to the protrusion 210 through at least one connecting portion 622. For example, the first electrode layer 610 and the second electrode layer 620 are both made of a light-transmitting conductive material. For example, the material of the first electrode layer 610 and the material of the second electrode layer 620 can be the same, such as both are indium tin oxide (ITO), but not limited thereto, the material of the first electrode layer and the material of the second electrode layer can also be different.

[0093] For example, Figures 5 to 7 As shown, the pixel electrode 611 may be a block electrode, and the common electrode 621 may be a plurality of strip electrodes. For example, the sub-pixel including the pixel electrode 611 and the common electrode 621 may be a dual-domain structure.

[0094] For example, Figure 6 and Fig.11As shown, the conductive portion 612 includes a portion stacked and directly contacted with the data line 100 and a portion stacked and directly contacted with the gate 403. For example, the two portions of the conductive portion 612 stacked with the data line 100 and the gate 403 may be spaced apart, but are not limited thereto, and the two portions may be an integrated structure. For example, the plane shape of the conductive portion 612 stacked and directly contacted with the gate 403 may be substantially the same as the plane shape of the gate 403, and the area of ​​the conductive portion 612 is slightly larger than the area of ​​the gate 403.

[0095] For example, Figures 8 to 10 As shown, the number of the connecting parts 622 can be multiple, a part of the multiple connecting parts 622 is used to connect the gate 403 and the gate line 200, a part of the multiple connecting parts 622 is used to connect the data line 100 and the first electrode 401 of the transistor 400, and a part of the multiple connecting parts 622 is used to connect the pixel electrode 611 and the second electrode 402 of the transistor 400.

[0096] For example, Fig. 9 and Fig.10 As shown, an insulating layer 02 is arranged between the data line 100 and the semiconductor layer 300, an insulating layer 03 is arranged between the first electrode 401 of the transistor 400 and the second electrode layer 620, via holes 023 are arranged in the insulating layer 02 and the insulating layer 03, and the connecting portion 622 is electrically connected to the data line 100 and the first electrode 401 of the transistor through the via hole 023; a via hole 024 is arranged in the insulating layer 02 and the insulating layer 03, and the connecting portion 622 is electrically connected to the gate 403 and the gate line 200 through the via hole 024.

[0097] For example, Fig. 9 As shown, the material of the film layer where the data line 100 and the film layer where the gate line 200 are located may include copper. For example, the material of the insulating layer 02 and the insulating layer 03 may include silicon nitride. For example, the material of the semiconductor layer 300 may include A-Si.

[0098] For example, Figure 7 , Figure 8 as well as Fig.12 As shown, the display substrate further includes a common electrode line 230 disposed in the same layer as the gate line 200, and the common electrode line 230 is electrically connected to the common electrode 621. For example, the semiconductor layer 300 further includes a portion that is stacked with the common electrode line 230 and in direct contact with it.

[0099] In some examples, such as Figure 8 As shown, along the direction perpendicular to the substrate, the gate line main body 220 does not overlap with the gate 403 , and the gate 403 is electrically connected to the protrusion 210 . For example, the gate 403 is electrically connected to the protrusion 210 through the connection portion 622 .

[0100] The display substrate provided by the present disclosure is schematically formed by patterning pixel electrodes and data lines using the same mask plate. In this case, the display substrate includes a conductive portion that is stacked and directly in contact with the data line and the gate, but is not limited to this. The pattern of the film layer where the data line is located and the pixel electrode pattern can be formed separately using different mask plates. In this case, there is no conductive portion stacked with the data line and the gate.

[0101] Fig.14 A schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure. Fig.15 for Fig.14 The diagram shows a partial structural diagram of a display substrate. Fig.16 For along Fig.15 The diagram shows a partial cross-sectional structure of the substrate taken along line DD'. Fig.17 for Fig.15 The diagram shows a stacking diagram of a film layer where data lines are located and a film layer where pixel electrodes are located in a display substrate. Fig.18 for Fig.15 The diagram shows a stacking diagram of a film layer where a data line is located, a film layer where a pixel electrode is located, a semiconductor layer, and a film layer where a gate line is located in a display substrate.

[0102] Figures 14 to 18 The display substrate shown is Figures 4 to 13 The display substrate shown is different in that the shape of the light shielding portion 500 is different. Fig.14 The data lines, pixel electrodes, first electrodes, second electrodes and active layers of transistors, gate lines, semiconductor parts, common electrodes and common electrode lines in the display substrate shown in the figure can be connected with Figure 4 The corresponding structures shown have the same features and will not be described in detail here.

[0103] In some examples, such as Figures 14 to 18 As shown, there are multiple light shielding portions 500, at least one light shielding portion 500 is spaced apart from the gate 403 of any transistor 400, and the light shielding portion 500 is insulated from the gate line 200. By spacing the light shielding portion and the gate to insulate the light shielding portion from the gate line, it is helpful to reduce the influence of the light shielding portion on the signal transmitted on the gate line.

[0104] In some examples, such as Fig.15 , Fig.17 and Fig.18 As shown, a space S is provided between the light shielding portion 500 and the gate electrode 403 closest thereto, and at least a portion of the space S overlaps with the protrusion 210 along a direction perpendicular to the substrate, such as a direction perpendicular to the XY plane.

[0105] In some examples, such as Fig.17As shown, the distance D3 between the light shielding portion 500 and the gate 403 closest to it is 2 to 15 microns. For example, the distance D3 can be the size of the interval S. For example, the distance D3 between the light shielding portion 500 and the gate 403 closest to it is 5 microns. For example, the distance D3 between the light shielding portion 500 and the gate 403 closest to it is 3 to 10 microns. For example, the distance D3 between the light shielding portion 500 and the gate 403 closest to it is 4.5 to 6 microns. By setting the distance between the light shielding portion and the gate closest to it, it is possible to achieve that the light shielding portion shields the semiconductor portion while avoiding a short circuit between the light shielding portion and the gate.

[0106] In some examples, such as Fig.17 and Fig.18 As shown, a gap S is provided between at least one light shielding portion 500 and the gate 403 closest thereto, a portion of the gate 403 away from the gate line main body 220 electrically connected thereto protrudes toward the light shielding portion 500, and the gate 403 and the corresponding light shielding portion 500 have complementary shapes. For example, the gate 403 includes a first portion overlapping with the active layer 404 and a second portion electrically connected to the gate line 200, the second portion is located between the first portion and the light shielding portion 500, and the size of the first portion in the Y direction is greater than the size of the second portion in the Y direction.

[0107] For example, Fig.17 and Fig.18 As shown, in the direction indicated by the arrow in the Y direction, the size of the gate 403 in the X direction gradually increases, and the size of the light shielding portion 500 in the X direction gradually decreases, so that the edge of the gate close to the light shielding portion and the edge of the light shielding portion close to the gate are roughly parallel, while the light shielding portion shields the semiconductor portion as much as possible and the space utilization is improved.

[0108] For example, Fig.17 As shown, the edge of the gate 403 away from the gate line and extending along the X direction is substantially in a straight line with the edge of the light shielding portion 500 away from the gate line and extending along the X direction to prevent the light shielding portion from being too close to the pixel electrode.

[0109] For example, Fig.17 As shown, the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 are insulated to prevent the light shielding portion from being electrically connected to the gate. For example, the distance between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 is smaller than the distance between the light shielding portion 500 and the gate 403. For example, the edges of the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 that are close to each other are arranged in parallel.

[0110] For example, Fig.17As shown, the distance D4 between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 is greater than 0 and not greater than 15 microns. For example, the distance D4 between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 may be 1 micron. For example, the distance D4 between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 may be 1.2 to 5 microns. For example, the distance D4 between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 may be 1.5 to 3 microns. For example, the distance D4 between the conductive portion stacked with the light shielding portion 500 and the conductive portion stacked with the gate 403 may be 2 to 7 microns.

[0111] Fig.19 It is a schematic diagram of a partial structure of a display device provided according to an embodiment of the present disclosure.

[0112] like Fig.19 As shown, another embodiment of the present disclosure provides a display device 1, including a display substrate 001 provided in any of the above examples.

[0113] In some examples, such as Fig.19 As shown, the display device further includes a backlight source 002 . The backlight source 002 is located on the light incident side of the display substrate 001 . The backlight source 002 includes a pulse width modulation backlight source.

[0114] For example, the display device may be a liquid crystal display device. For example, the display substrate may be an array substrate, and the display device may further include an opposing substrate disposed opposite to the display substrate. For example, the opposing substrate may include a black matrix and a color filter layer. For example, the display device may further include a liquid crystal layer located between the array substrate and the opposing substrate.

[0115] For example, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a laptop computer, a navigator, etc., but the present embodiment is not limited thereto.

[0116] There are a few points to note:

[0117] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0118] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0119] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: substrate substrate; A plurality of data lines are located on the base substrate, and the plurality of data lines are arranged along a first direction; A plurality of gate lines are located on the substrate, the plurality of gate lines are arranged along a second direction, and the second direction intersects with the first direction; A semiconductor layer is stacked with the film layer where the gate line is located, and is located between the film layer where the gate line is located and the film layer where the data line is located; A plurality of transistors are disposed on the substrate, each transistor comprising a gate, an active layer, a first electrode and a second electrode, the gate being electrically connected to the gate line, the first electrode being electrically connected to the data line, the semiconductor layer comprising the active layer, and along a direction perpendicular to the substrate, the gate, the first electrode and the second electrode all overlap with the active layer, The plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, the gate and the data lines are arranged in the same layer, the semiconductor layer includes a semiconductor portion stacked with the gate lines, and the semiconductor portion is spaced apart from the active layer. The display substrate further includes a light shielding portion, which is disposed in the same layer as the data line, and in a direction perpendicular to the base substrate, at least a portion of the semiconductor portion overlaps with the light shielding portion.

2. The display substrate according to claim 1, wherein: At least one gate line includes a protrusion and a gate line main body connected to each other, a straight line extending along the first direction passes through the gate and the orthographic projections of the protrusion on the base substrate, the semiconductor portion includes a first semiconductor portion stacked with the protrusion and a second semiconductor portion stacked with the gate line main body, and more than 80% of the area of ​​the orthographic projection of the first semiconductor portion on the base substrate falls within the orthographic projection of the shading portion on the base substrate.

3. The display substrate according to claim 2, wherein: At least part of the edge of the light shielding portion is farther away from the second semiconductor portion than the edge of the first semiconductor portion, and the orthographic projection of the first semiconductor portion on the base substrate is completely located within the orthographic projection of the light shielding portion and the gate on the base substrate.

4. The display substrate according to claim 2, wherein: A portion of the second semiconductor portion overlaps the light shielding portion along a direction perpendicular to the base substrate.

5. The display substrate according to claim 4, wherein: More than 70% of the area of ​​the orthographic projection of the second semiconductor portion stacked with the portion of the at least one gate line located between two adjacent data lines on the base substrate falls within the orthographic projection of the light shielding portion on the base substrate.

6. The display substrate according to claim 2, wherein: There are a plurality of light shielding portions, and at least one light shielding portion and a gate of at least one transistor are integrated into one structure.

7. The display substrate according to claim 6, wherein: A size of an overlapping portion of the integrated structure and the gate line main body in the first direction is greater than a size of an overlapping portion of the integrated structure and the protrusion in the first direction.

8. The display substrate according to claim 2, wherein: There are multiple light shielding parts, at least one light shielding part is spaced apart from the gate of any transistor, and the light shielding part is insulated from the gate line.

9. The display substrate according to claim 8, wherein: A space is provided between the light shielding portion and the gate electrode closest thereto, and at least a portion of the space overlaps with the protruding portion along a direction perpendicular to the base substrate.

10. The display substrate according to claim 8, wherein: A gap is provided between the at least one light shielding portion and the gate closest thereto, a portion of the gate away from the gate line main body electrically connected thereto protrudes toward the light shielding portion, and the shapes of the gate and the corresponding light shielding portion are complementary.

11. The display substrate according to claim 2, wherein: The light shielding portion includes a first light shielding portion overlapping the first semiconductor portion and a second light shielding portion overlapping the second semiconductor portion, and an edge of the second light shielding portion is closer to the data line than an edge of the first light shielding portion.

12. The display substrate according to claim 2, wherein: Along a direction perpendicular to the base substrate, the gate line main body does not overlap with the gate, and the gate is electrically connected to the protrusion.

13. The display substrate according to any one of claims 1 to 12, wherein: The distance between the light shielding portion and the data line closest thereto is 2 to 15 micrometers.

14. The display substrate according to claim 8, wherein: The distance between the light shielding portion and the gate closest thereto is 2 to 15 micrometers.

15. The display substrate according to claim 1, wherein: A size of a portion of the light shielding portion that exceeds an edge of the semiconductor portion overlapping the light shielding portion is greater than 1.65 micrometers and less than 5 micrometers.

16. The display substrate according to any one of claims 1 to 12, wherein: The film layer where the gate line is located is in direct contact with the semiconductor layer.

17. The display substrate according to claim 2, further comprising: The first electrode layer is located between the data line and the base substrate. The second electrode layer is located on a side of the gate line away from the data line, Among them, the first electrode layer includes a pixel electrode, which is electrically connected to the second electrode of the transistor, the second electrode layer includes a common electrode, the first electrode layer also includes a conductive part, at least a part of the conductive part is stacked and directly contacted with the data line, the second electrode layer also includes a plurality of connecting parts, and the gate is electrically connected to the protrusion through at least one connecting part.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. The display device according to claim 18, further comprising: A backlight source is located on the light incident side of the display substrate. Wherein, the backlight source comprises a pulse width modulation backlight source.

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