Display substrate and driving method thereof, display device, driving device and medium

Abstract

The invention discloses a display substrate and a driving method thereof, a display device, a driving device and a medium. The display substrate comprises a plurality of sub-pixels, each sub-pixel comprises a pixel driving circuit and a light-emitting device, each light-emitting device at least comprises a first electrode and a pixel definition layer, the first electrodes are connected with the pixel driving circuits, and pixel openings exposing the first electrodes are formed in the pixel definition layers; the pixel opening at least comprises a first opening edge located on one side of the first direction of the pixel opening and a second opening edge located on one side of the reverse direction of the first direction of the pixel opening, and the pixel driving circuit is connected with at least one signal line; in at least one sub-pixel, the orthographic projection of at least one of the first opening edge and the second opening edge on the plane of the display substrate is at least partially overlapped with the orthographic projection of the signal line on the plane of the display substrate. According to the method and the device, the side view angle brightness difference caused by alignment difference is effectively reduced, and the spliced watermark is effectively eliminated.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a driving method thereof, a display device, a driving device and a medium. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] At present, large-size, especially super-large-size display devices usually adopt a multiple exposure process of an exposure machine, and display devices spliced ​​by multiple exposures have problems such as splicing watermarks. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a driving method thereof, a display device, a driving device and a medium, so as to solve the problems of splicing watermarks in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including multiple sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device, the light-emitting device includes at least a first electrode and a pixel definition layer, the first electrode is connected to the pixel driving circuit, and a pixel opening exposing the first electrode is provided on the pixel definition layer; the pixel opening includes at least a first opening edge located on one side of a first direction of the pixel opening and a second opening edge located on the opposite side of the first direction of the pixel opening, the pixel driving circuit is connected to at least one signal line extending along a second direction, and the first direction intersects with the second direction; in at least one sub-pixel, the orthographic projection of at least one of the first opening edge and the second opening edge on the plane of the display substrate at least partially overlaps with the orthographic projection of the signal line on the plane of the display substrate.

[0007] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a first power line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane.

[0008] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a data signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane.

[0009] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a compensation signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line on the display substrate plane.

[0010] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along the first direction, and the signal lines include at least a first power line, a data signal line, and a compensation signal line; in the first sub-pixel, an orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane, and an orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane; in the second sub-pixel, an orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line on the display substrate plane, The orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane; in the third sub-pixel, the orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane; in the fourth sub-pixel, the orthographic projection of the first opening edge on the substrate at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the second opening edge on the substrate at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane.

[0011] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0012] On the other hand, the present disclosure also provides a driving method for a display substrate that drives the aforementioned display substrate. The display device at least includes a first sub-substrate and a second sub-substrate that are spliced ​​together, and the first sub-substrate and the second sub-substrate form a splicing line at the splicing position; the first sub-substrate at least includes a first transition zone close to the splicing line and a first normal zone located on the side of the first transition zone away from the splicing line, and the second sub-substrate at least includes a second transition zone close to the splicing line and a second normal zone located on the side of the second transition zone away from the splicing line; the first transition zone and the second transition zone each include at least one pixel column, each pixel column includes M sub-pixels, and the sub-pixels at least include a pixel driving circuit, and the pixel driving circuit is connected to a driving signal line, and M is a positive integer greater than 1; the driving method includes:

[0013] Processing at least one original driving signal of at least one pixel column in the first transition region and the second transition region into at least one processed driving signal;

[0014] At least one processed driving signal and the remaining original driving signals are provided to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column.

[0015] In an exemplary embodiment, in at least one of the first transition zone and the second transition zone, along a direction approaching the stitching line, the number of the original driving signals in the pixel column gradually decreases, and the number of the processed driving signals in the pixel column gradually increases.

[0016] In an exemplary embodiment, in at least one of the first transition region and the second transition region, the number of the original driving signals in the pixel column farthest from the stitching line is M.

[0017] In an exemplary embodiment, in at least one of the first transition region and the second transition region, the number of the processed driving signals in the pixel column closest to the stitching line is M.

[0018] In an exemplary embodiment, in at least one of the first transition zone and the second transition zone, the number of processed driving signals in the pixel column closest to the stitching line is k*M, and the number of original driving signals is (1-k)*M, k=0.2 to 0.8.

[0019] In an exemplary embodiment, k=0.5.

[0020] In an exemplary embodiment, the drive signal includes a data signal line, the drive signal includes a data signal, and the processed drive signal includes a first data signal;

[0021] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0022] Processing the data signal of each pixel column in the first transition area so that the data signal of the i-th pixel column includes M1 original data signals and M2 first data signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)]; n is the number of pixel columns in the first transition area, i=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the first data signal is V-ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal;

[0023] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0024] In each pixel column of the first normal zone, the second transition zone and the second normal zone, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column of the first transition zone, M1 original data signals and M2 first data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

[0025] In an exemplary embodiment, the drive signal includes a data signal line, the drive signal includes a data signal, and the processed drive signal includes a second data signal;

[0026] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0027] Processing the data signal of each pixel column in the second transition area so that the data signal of the j-th pixel column includes M3 original data signals and M4 second data signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)]; n is the number of pixel columns in the second transition area, j=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the second data signal is V+ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal;

[0028] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0029] In each pixel column of the first transition zone, the first normal zone and the second normal zone, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column of the second transition zone, M3 original data signals and M4 second data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

[0030] In an exemplary embodiment, the driving signal includes a data signal line, the driving signal includes a data signal, and the processed driving signal includes a first data signal and a second data signal;

[0031] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0032] Processing the data signals of each pixel column in the first transition area and the second transition area so that the data signal of the i-th pixel column in the first transition area includes M1 original data signals and M2 first data signals, and the data signal of the j-th pixel column in the second transition area includes M3 original data signals and M4 second data signals, M1=0.5*M[(i-1) / (n-1)], M2=0.5*M[1-(i-1) / (n-1)], M3=0.5*M[(j-1) / (n-1)], M4=0.5*M[1-(j-1) / (n-1)]; n is the number of pixel columns in the first transition area and the second transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the first data signal is V-ΔV, the second data signal is V+ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal;

[0033] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0034] In each pixel column in the first normal area and the second normal area, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column in the first transition area, M1 original data signals and M2 first data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column in the second transition area, M3 original data signals and M4 second data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

[0035] In an exemplary embodiment, the drive signal includes a compensation signal line, the drive signal includes a compensation signal, and the processed drive signal includes a first compensation signal;

[0036] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0037] Extracting the compensation signal of each pixel column in the second transition area, processing the compensation signal of each pixel column in the first transition area, so that the compensation signal of the i-th pixel column in the first transition area includes M1 original compensation signals and M2 first compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)]; n is the number of pixel columns in the first transition area; the original compensation signal is the compensation signal of the i-th pixel column in the first transition area, the first compensation signal is the compensation signal of the j-th pixel column in the second transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of the pixel columns gradually increases along the direction away from the splicing line;

[0038] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0039] In each pixel column of the first normal zone, the second transition zone and the second normal zone, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column of the first transition zone, M1 original compensation signals and M2 first compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0040] In an exemplary embodiment, the drive signal includes a compensation signal line, the drive signal includes a compensation signal, and the processed drive signal includes a second compensation signal;

[0041] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0042] Extract the compensation signal of each pixel column in the first transition area, and process the compensation signal of each pixel column in the second transition area, so that the compensation signal of the j-th pixel column in the second transition area includes M3 original compensation signals and M4 second compensation signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)]; n is the number of pixel columns in the second transition area; the original compensation signal is the compensation signal of the j-th pixel column in the second transition area, and the second compensation signal is the compensation signal of the i-th pixel column in the first transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of the pixel columns gradually increases along the direction away from the splicing line;

[0043] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0044] In each pixel column of the first transition zone, the first normal zone and the second normal zone, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column of the second transition zone, M3 original compensation signals and M4 second compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0045] In an exemplary embodiment, the drive signal includes a compensation signal line, the drive signal includes a compensation signal, and the processed drive signal includes a first compensation signal and a second compensation signal;

[0046] Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal, comprising:

[0047] The compensation signal of each pixel column in the first transition area and the second transition area is extracted, and the compensation signal of each pixel column in the first transition area and the second transition area is processed so that the compensation signal of the i-th pixel column in the first transition area includes M1 original compensation signals and M2 first compensation signals, and the compensation signal of the j-th pixel column in the second transition area includes M3 original compensation signals and M4 second compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)], M3=M[(j-1) / (n-1)], M4=M[1-( j-1) / (n-1)]; n is the number of pixel columns in the first transition zone and the second transition zone, i=1, 2, ..., n, j=1, 2, ..., n, and the number of pixel columns gradually increases along the direction away from the stitching line; the original compensation signal of the first transition zone is the compensation signal of the i-th pixel column in the first transition zone, and the first compensation signal is the compensation signal of the j-th pixel column in the second transition zone; the original compensation signal of the second transition zone is the compensation signal of the j-th pixel column in the second transition zone, and the second compensation signal is the compensation signal of the i-th pixel column in the first transition zone;

[0048] Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising:

[0049] In each pixel column in the first normal area and the second normal area, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column in the first transition area, M1 original compensation signals and M2 first compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column in the second transition area, M3 original compensation signals and M4 second compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0050] On the other hand, the present disclosure further provides a driving device, including a processor and a memory storing a computer program that can be run on the processor, wherein the processor implements the steps of the aforementioned display substrate driving method when executing the program.

[0051] On the other hand, the present disclosure further provides a non-transitory computer-readable storage medium storing program instructions, which can implement the aforementioned display substrate driving method when the program instructions are executed.

[0052] The embodiments of the present disclosure provide a display substrate and a driving method thereof, a display device, a driving device and a medium. By setting the orthographic projection of the first opening edge and / or the second opening edge of the pixel opening on the substrate to at least partially overlap with the orthographic projection of the signal line on the substrate, not only the degree of reflection of different pixel openings is basically the same, but also the outgoing light of the pixel opening at a side viewing angle is largely the light reflected by the metal wire, which effectively reduces the brightness difference at a side viewing angle caused by the difference in alignment and effectively eliminates the splicing watermark.

[0053] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0055] Figure 1 is a structural schematic diagram of a display device;

[0056] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0057] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0058] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0059] Figure 5 It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0060] Figure 6 It is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0061] Figure 7 This is a schematic diagram of an embodiment of the present disclosure after a transparent conductive layer pattern is formed;

[0062] Fig. 8A and Figure 8B This is a schematic diagram of an embodiment of the present disclosure after a first conductive layer pattern is formed;

[0063] Fig. 9A and Fig. 9B This is a schematic diagram of an embodiment of the present disclosure after a semiconductor layer pattern is formed;

[0064] Fig. 10A and Fig. 10BThis is a schematic diagram of an embodiment of the present disclosure after a second conductive layer pattern is formed;

[0065] Fig.11 This is a schematic diagram of an embodiment of the present disclosure after a third insulating layer pattern is formed;

[0066] Fig. 12A and Fig. 12B This is a schematic diagram of an embodiment of the present disclosure after a third conductive layer pattern is formed;

[0067] Fig.13 This is a schematic diagram of an embodiment of the present disclosure after a flat layer pattern is formed;

[0068] Fig.14 This is a schematic diagram of an embodiment of the present disclosure after forming an electrode conductive layer pattern;

[0069] Fig.15 This is a schematic diagram of an embodiment of the present disclosure after a pixel definition layer pattern is formed;

[0070] Fig.16 A schematic diagram of the positional relationship between a pixel opening and a signal line according to an embodiment of the present disclosure;

[0071] Fig.17 It is a schematic structural diagram of another display substrate of an exemplary embodiment of the present disclosure;

[0072] Fig.18 A schematic diagram of a method for driving a display substrate according to an exemplary embodiment of the present disclosure;

[0073] Fig.19 A schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure;

[0074] Fig. 20 A schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure;

[0075] Fig.21 A schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure;

[0076] Fig. 22 A schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure;

[0077] Fig.23 The diagram is a schematic diagram of yet another method for driving a display substrate according to an exemplary embodiment of the present disclosure.

[0078] Description of reference numerals:

[0079] 11—first electrode plate; 12—connecting plate; 13—connecting wire;

[0080] 21—power connection line; 22—compensation connection line; 23—shielding layer;

[0081] 24—interlayer connection electrode; 31—first active layer; 32—second active layer;

[0082] 33—third active layer; 34—second electrode plate; 41—first scanning signal line;

[0083] 42—second scanning signal line; 43—second gate electrode; 44—auxiliary power line;

[0084] 45—auxiliary data line; 46—auxiliary compensation line; 51—first connection electrode;

[0085] 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode;

[0086] 55—fifth connecting electrode; 56—sixth connecting electrode; 60—first power line;

[0087] 70—data signal line; 80—compensation signal line; 81—first compensation signal line;

[0088] 82—second compensation signal line; 83—compensation connection electrode; 91—first signal connection electrode;

[0089] 92—second signal connection electrode; 100—first sub-substrate; 101—base;

[0090] 102—driving circuit layer; 103—light emitting structure layer; 104—packaging structure layer;

[0091] 110—first transition area; 120—first normal area; 200—second sub-substrate;

[0092] 210—second transition zone; 220—second normal zone; 300—splicing line;

[0093] 301—first electrode; 302—organic light-emitting layer; 303—second electrode;

[0094] 401—first encapsulation layer; 402—second encapsulation layer; 403—third encapsulation layer;

[0095] 500—pixel opening; 501—first opening edge; 502—second opening edge. DETAILED DESCRIPTION

[0096] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0097] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0098] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0099] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0100] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0101] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0102] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0103] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0104] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0105] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0106] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0107] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0108] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver and a pixel array, the timing controller is respectively connected to the data driver and the scan driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the display unit may include at least a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel PXij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver may generate a data voltage to be provided to the data signal lines 531, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines 531 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal having a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction level pulse to a next level circuit under the control of a clock signal, where m may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0109] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light, and the four sub-pixels may each include a circuit unit and a light-emitting device, and the circuit unit may include a pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each pixel unit is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0110] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a white subpixel (W) emitting white light, the third subpixel P3 may be a blue subpixel (B) emitting blue light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light.

[0111] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. In an exemplary embodiment, four sub-pixels may be arranged in parallel horizontally to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a square, a diamond, or in parallel vertically, which is not limited in the present disclosure.

[0112] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels of the display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, each sub-pixel in the display substrate may include a driving circuit layer 102 arranged on a substrate 101, a light-emitting structure layer 103 arranged on a side of the driving circuit layer 102 away from the substrate, and an encapsulation structure layer 104 arranged on a side of the light-emitting structure layer 103 away from the substrate.

[0113] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of circuit units, and the circuit unit may include at least a pixel driving circuit composed of a storage capacitor and a plurality of transistors. The light-emitting structure layer 103 of each sub-pixel may include a plurality of light-emitting units, and the light-emitting unit may include at least a light-emitting device, and the light-emitting device may include at least a first electrode 301, an organic light-emitting layer 302, and a second electrode 303, the first electrode 301 is connected to the pixel driving circuit, the organic light-emitting layer 302 is connected to the first electrode 301, and the second electrode 303 is connected to the organic light-emitting layer 302, and the organic light-emitting layer 302 emits light of corresponding colors under the drive of the first electrode 301 and the second electrode 303. In an exemplary embodiment, the first electrode and the second electrode may be an anode and a cathode, respectively, or the first electrode and the second electrode may be a cathode and an anode, respectively. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0114] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer and the electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of all sub-pixels may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap. In some possible implementations, the display substrate may include other film layers, which are not limited in the present disclosure.

[0115] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit has a 3T1C structure and may include three transistors (a first transistor T1, a second transistor T2 and a third transistor T3) and a storage capacitor C. The pixel driving circuit is respectively connected to five signal lines (a first scanning signal line S1, a second scanning signal line S2, a data signal line D, a compensation signal line S and a first power line VDD).

[0116] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, and the second node N2 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C.

[0117] In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor. A first end of the storage capacitor C is connected to the first node N1, a second end of the storage capacitor C is connected to the second node N2, and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0118] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line D, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the first scan signal line S1, the first transistor T1 inputs a data signal of the data signal line D to the gate electrode of the second transistor T2.

[0119] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received by its gate electrode.

[0120] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the second scan signal line S2, a first electrode of the third transistor T3 is connected to the compensation signal line S, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the second scan signal line S2, the third transistor T3 extracts a threshold voltage Vth and a mobility of the second transistor T2 in response to a compensation timing to compensate for the threshold voltage Vth.

[0121] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked first electrode (first electrode), an organic light emitting layer, and a second electrode (second electrode), or may be a QLED, including a stacked first electrode (first electrode), a quantum dot light emitting layer, and a second electrode (second electrode). The first electrode of the light emitting device EL is connected to the second node N2, the second electrode of the light emitting device EL is connected to the second power line VSS, and the light emitting device EL is used to respond to the current of the second electrode of the second transistor T2 and emit light of corresponding brightness.

[0122] In an exemplary embodiment, the signal of the first power line VDD is a high level signal that is continuously provided, and the signal of the second power line VSS is a low level signal that is continuously provided.

[0123] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 may include a P-type transistor and an N-type transistor.

[0124] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate, that is, the LTPS+Oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0125] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a light-emitting device, the light-emitting device comprising at least a first electrode and a pixel definition layer, the first electrode being connected to the pixel driving circuit, and a pixel opening exposing the first electrode being provided on the pixel definition layer; the pixel opening comprising at least a first opening edge located on one side of a first direction of the pixel opening and a second opening edge located on the opposite side of the first direction of the pixel opening, the pixel driving circuit being connected to at least one signal line extending along a second direction, the first direction intersecting with the second direction; in at least one sub-pixel, an orthographic projection of at least one of the first opening edge and the second opening edge on a plane of the display substrate at least partially overlaps with an orthographic projection of the signal line on the plane of the display substrate.

[0126] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a first power line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane.

[0127] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a data signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane.

[0128] In an exemplary embodiment, in at least one subpixel, the signal line includes at least a compensation signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line on the display substrate plane.

[0129] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along the first direction, and the signal lines include at least a first power line, a data signal line, and a compensation signal line; in the first sub-pixel, an orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane, and an orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane; in the second sub-pixel, an orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line on the display substrate plane, The orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane; in the third sub-pixel, the orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane; in the fourth sub-pixel, the orthographic projection of the first opening edge on the substrate at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the second opening edge on the substrate at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane.

[0130] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0131] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In an exemplary embodiment, the driving circuit layer may include a plurality of circuit units, the light-emitting structure layer may include a plurality of light-emitting units, the circuit unit may include at least a pixel driving circuit, the light-emitting unit may include at least a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit.

[0132] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0133] In an exemplary embodiment of the present disclosure, the position of the circuit unit's orthographic projection on the substrate corresponds one-to-one to the position of the light-emitting unit's orthographic projection on the substrate, and the circuit unit and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixels are uniformly used to refer to circuit units and light-emitting units.

[0134] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged along a first direction X may be referred to as pixel rows, a plurality of sub-pixels sequentially arranged along a second direction Y may be referred to as pixel columns, a plurality of pixel rows and a plurality of pixel columns constitute an array-arranged pixel array, and the first direction X and the second direction Y intersect.

[0135] In an exemplary embodiment, the first direction X may be a horizontal direction, the second direction Y may be a vertical direction, and the first direction X and the second direction Y may be perpendicular to each other.

[0136] Figure 5 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a pixel unit (four sub-pixels) in a bottom emission display substrate. Figure 5 As shown, in a direction parallel to the display substrate, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 arranged in sequence along a first direction X, and each sub-pixel may include a pixel driving circuit.

[0137] In an exemplary embodiment, at least one pixel unit may include a first scan signal line 41, a second scan signal line 42, two first power lines 60, four data signal lines 70 and a compensation signal line 80, all of which are connected to pixel driving circuits in four sub-pixels.

[0138] In an exemplary embodiment, the first scan signal line 41 and the second scan signal line 42 may be in the shape of a straight line or a folded line extending along the first direction X, and the first scan signal line 41 and the second scan signal line 42 are sequentially arranged along the second direction Y. The first power line 60, the data signal line 70, and the compensation signal line 80 may be in the shape of a straight line or a folded line extending along the second direction Y, the two first power lines 60 may be respectively arranged on both sides of the pixel unit in the first direction X, the four data signal lines 70 and the one compensation signal line 80 may be arranged between the two first power lines 60, two of the four data signal lines 70 may be located between the compensation signal line 80 and one of the first power lines 60, and the other two of the four data signal lines 70 may be located between the compensation signal line 80 and another first power line 60.

[0139] In an exemplary embodiment, a first sub-pixel P1 is formed between one first power line 60 and one data signal line 70 adjacent to the first direction X, a second sub-pixel P2 is formed between the compensation signal line 80 and one data signal line 70 adjacent to the opposite direction of the first direction X, a third sub-pixel P3 is formed between the compensation signal line 80 and one data signal line 70 adjacent to the first direction X, and a fourth sub-pixel P4 is formed between another first power line 60 and one data signal line 70 adjacent to the opposite direction of the first direction X.

[0140] In an exemplary embodiment, among the four sub-pixels of the pixel unit, the pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor. The first transistor T1, the second transistor T2 and the third transistor T3 may each include an active layer, a gate electrode, a first electrode and a second electrode, and the storage capacitor may include a transparent first electrode plate and a transparent second electrode plate to form a transparent storage capacitor.

[0141] In an exemplary embodiment, the first scan signal line 41 is connected to the gate electrode of the first transistor T1 in each sub-pixel, the second scan signal line 42 is connected to the gate electrode of the third transistor T3 in each sub-pixel, the data signal line 70 is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line 80 is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power line 60 is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2, the second electrode of the second transistor T2 in each sub-pixel is connected to the first electrode of the third transistor T3, the first electrode plate in each sub-pixel is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, and the second electrode plate in each sub-pixel is respectively connected to the second electrode of the first transistor T1 and the gate electrode of the second transistor T2.

[0142] In an exemplary embodiment, at least one pixel unit may further include a plurality of connection lines, and the plurality of connection lines may include at least two power connection lines 21 extending along the first direction X and two compensation connection lines 22 extending along the first direction X, forming a one-to-two structure of the first power lines and a one-to-four structure of the compensation signal lines.

[0143] In an exemplary embodiment, one power connection line 21 is provided in the first sub-pixel P1 and the second sub-pixel P2, a first end of the power connection line 21 is connected to the first power line 60 in the first sub-pixel P1, and a second end is connected to the second transistor T2 in the second sub-pixel P2. Another power connection line 21 is provided in the third sub-pixel P3 and the fourth sub-pixel P4, a first end of the power connection line 21 is connected to the first power line 60 in the fourth sub-pixel P4, and a second end is connected to the second transistor T2 in the third sub-pixel P3. In this way, one first power line 60 can provide power signals to the pixel driving circuits of the two sub-pixels through one power connection line 21.

[0144] In an exemplary embodiment, one compensation connection line 22 is provided at the first sub-pixel P1 and the second sub-pixel P2, and the compensation connection line 22 is connected to the compensation signal line 80 on one hand, and is respectively connected to the third transistor T3 of the first sub-pixel P1 and the third transistor T3 of the second sub-pixel P2 on the other hand. Another compensation connection line 22 is provided at the third sub-pixel P3 and the fourth sub-pixel P4, and the compensation connection line 22 is connected to the compensation signal line 80 on one hand, and is respectively connected to the third transistor T3 of the third sub-pixel P3 and the third transistor T3 of the fourth sub-pixel P4 on the other hand. In this way, one compensation signal line 80 can provide compensation signals to the pixel driving circuits of the four sub-pixels.

[0145] The embodiment of the disclosed embodiment saves the number of signal lines and reduces the occupied space through the one-to-two structure of the first power line and the one-to-four structure of the compensation signal line. It has a simple structure, a reasonable layout, fully utilizes the layout space, improves space utilization, and is conducive to improving resolution.

[0146] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer may include a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer stacked on the substrate, the light emitting structure layer may include an electrode conductive layer disposed on a side of the driving circuit layer away from the substrate and a pixel definition layer disposed on a side of the electrode conductive layer away from the substrate, the electrode conductive layer may include a plurality of first electrodes, the first electrodes being connected to corresponding pixel driving circuits, the pixel definition layer may include a plurality of pixel openings, the pixel openings exposing corresponding first electrodes. In an exemplary embodiment, the first electrode may be an anode, or the first electrode may be a cathode.

[0147] Figure 6 FIG. 2 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of an electrode conductive layer and a pixel definition layer in a bottom emission display substrate. Figure 6 As shown, the electrode conductive layer may include at least a plurality of first electrodes 301, which are respectively arranged in a plurality of sub-pixels and respectively connected to the pixel driving circuits of the corresponding sub-pixels. The pixel definition layer may include at least a plurality of pixel openings 500, which are respectively arranged in a plurality of sub-pixels and respectively expose the first electrodes 301 of the sub-pixels.

[0148] In an exemplary embodiment, the pixel opening 500 of each sub-pixel may include at least a first opening edge 501 located on one side of the first direction X of the pixel opening and a second opening edge 502 located on the opposite side of the first direction X of the pixel opening. The shapes of the first opening edge 501 and the second opening edge 502 may be straight lines or broken lines extending along the second direction Y.

[0149] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the first power line 60 on the substrate.

[0150] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the data signal line 70 on the substrate.

[0151] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the compensation signal line 80 on the substrate.

[0152] In an exemplary embodiment, in the first subpixel P1, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the first power line 60 on the substrate.

[0153] In an exemplary embodiment, in the second subpixel P2, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 80 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate.

[0154] In an exemplary embodiment, in the third subpixel P3, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 80 on the substrate.

[0155] In an exemplary embodiment, in the fourth subpixel P4, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the first power line 60 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate.

[0156] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0157] In an exemplary embodiment, taking a pixel unit including four sub-pixels (a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4) as an example, the preparation process of the display substrate in the exemplary embodiment of the present disclosure may include the following operations.

[0158] (11) Forming a transparent conductive layer pattern. In an exemplary embodiment, forming a transparent conductive layer pattern may include: depositing a transparent conductive film on a substrate, patterning the transparent conductive film through a patterning process, and forming a transparent conductive layer pattern on the substrate, such as Figure 7 In an exemplary embodiment, the transparent conductive layer may be referred to as an ITO layer.

[0159] In an exemplary embodiment, the transparent conductive layer pattern of each sub-pixel may include at least a first electrode plate 11 of a storage capacitor, a connection plate 12 , and a connection line 13 .

[0160] In an exemplary embodiment, the shape of the first electrode plate 11 can be rectangular, the corners of the rectangle can be chamfered, the edges of the rectangle can be fold lines, the first electrode plate 11 can be set in the middle area of ​​the sub-pixel in the second direction Y, and the first electrode plate 11 is configured to form a transparent electrode plate of a transparent storage capacitor.

[0161] In an exemplary embodiment, the connecting plate 12 may be polygonal in shape, may be disposed on one side of the first electrode plate 11 in the second direction Y and connected to the first electrode plate 11 , and may be configured to be connected to a shielding layer formed subsequently.

[0162] In an exemplary embodiment, the connection line 13 may be in the shape of a strip extending along the second direction Y, and the connection line 13 may be disposed on a side of the first electrode plate 11 away from the connection plate 12, and connected to the first electrode plate 11. A connection block 13-1 may be disposed at an end of the connection line 13 away from the first electrode plate 11, and the connection block 13-1 may be in the shape of a strip extending along the first direction X and connected to the connection line 13, and the connection block 13-1 is configured to be connected to an interlayer connection electrode formed subsequently.

[0163] In an exemplary embodiment, the first electrode plate 11 , the connection plate 12 , and the connection line 13 of each sub-pixel may be an integrated structure connected to each other.

[0164] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the transparent conductive layer, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0165] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel may include at least a power connection line 21 , a compensation connection line 22 , a shielding layer 23 , and an interlayer connection electrode 24 .

[0166] In an exemplary embodiment, the power connection line 21 may be in the shape of a strip extending along the first direction X. The power connection line 21 may be reused as a lateral power connection line of the pixel unit, and provide a power signal to the second transistor T2 of the sub-pixel by connecting to a first power line formed subsequently.

[0167] In an exemplary embodiment, the power connection lines 21 of some of the sub-pixels adjacent in the first direction X may be interconnected in an integrated structure. For example, the power connection lines 21 in the first sub-pixel P1 and the second sub-pixel P2 are interconnected in an integrated structure, the power connection lines 21 in the third sub-pixel P3 and the fourth sub-pixel P3 are interconnected in an integrated structure, but the power connection lines 21 in the second sub-pixel P2 and the third sub-pixel P3 are not connected.

[0168] In an exemplary embodiment, the shape of the compensation connection line 22 can be a strip shape extending along the first direction X. The compensation connection line 22 can be reused as a compensation lateral connection line of the pixel unit, and through connection with a subsequently formed compensation signal line, a compensation voltage is provided to the third transistor T3 of the sub-pixel.

[0169] In an exemplary embodiment, the compensation connection lines 22 of some of the sub-pixels adjacent in the first direction X may be interconnected as an integrated structure. For example, the compensation connection lines 22 in the first sub-pixel P1 and the second sub-pixel P2 are interconnected as an integrated structure, the compensation connection lines 22 in the third sub-pixel P3 and the fourth sub-pixel P3 are interconnected as an integrated structure, but the compensation connection lines 22 in the second sub-pixel P2 and the third sub-pixel P3 are not connected.

[0170] In an exemplary embodiment, the shielding layer 23 may be rectangular in shape and may be disposed between the power connection line 21 and the compensation connection line 22. The shielding layer 23 is configured to provide shielding for the second transistor T2 to prevent light from affecting the channel and reduce leakage current, thereby preventing the influence of light on transistor characteristics and ensuring the electrical performance of the second transistor T2.

[0171] In an exemplary embodiment, the orthographic projection of the shielding layer 23 on the substrate may be located within the range of the orthographic projection of the connecting plate 12 on the substrate, and the shielding layer 23 is directly overlapped with the connecting plate 12 .

[0172] In an exemplary embodiment, the interlayer connection electrode 24 may be rectangular in shape and may be disposed between the shielding layer 23 and the compensation connection line 22 . The interlayer connection electrode 24 is configured to be connected to the second electrode of the third transistor T3 formed subsequently.

[0173] In an exemplary embodiment, the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps the orthographic projection of the connection block 13 - 1 of the connection line 13 on the substrate, and the interlayer connection electrode 24 directly overlaps the connection block 13 - 1 .

[0174] In an exemplary embodiment, the first conductive layer pattern of each pixel unit may further include a compensation connection electrode 83. The compensation connection electrode 83 may be in the shape of a strip extending along the second direction Y, and the compensation connection electrode 83 may be disposed between adjacent compensation connection lines 22 in the first direction X, that is, the compensation connection electrode 83 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, and the compensation connection electrode 83 is configured as a connection electrode for a compensation signal line, and connects the first compensation signal line and the second compensation signal line disposed at intervals by connecting to the compensation signal line formed subsequently.

[0175] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 9A and Fig. 9B As shown, Fig. 9B for Fig. 9A Schematic diagram of the semiconductor layer in the figure.

[0176] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 , and a second electrode plate 34 .

[0177] In an exemplary embodiment, the shape of the second electrode plate 34 can be rectangular, and the orthographic projection of the second electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 34 is configured to form another transparent electrode plate of a transparent storage capacitor, and the first electrode plate 11 and the second electrode plate 34 constitute a transparent storage capacitor.

[0178] In an exemplary embodiment, the first active layer 31 can serve as an active layer of the first transistor T1, the second active layer 32 can serve as an active layer of the second transistor T2, the third active layer 33 can serve as an active layer of the third transistor T3, the first active layer 31 and the second active layer 32 can be disposed between the power connection line 21 and the second electrode plate 34, and the third active layer 33 can be disposed between the compensation connection line 22 and the second electrode plate 34.

[0179] In example embodiments, the first active layer 31 , the second active layer 32 , and the third active layer 33 may each include a channel region and first and second regions located at both sides of the channel region.

[0180] In an exemplary embodiment, the shape of the first active layer 31 can be "L"-shaped, the first region 31-1 of the first active layer 31 can be located on the side of the channel region away from the second electrode plate 34, the second region 31-2 of the first active layer 31 can be located on the side of the channel region close to the second electrode plate 34, and the orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the shielding layer 23 on the substrate.

[0181] In an exemplary embodiment, the second region 31 - 2 of the first active layer 31 may be connected to the second electrode plate 34 , and the first active layer 31 and the second electrode plate 34 may be an integral structure connected to each other.

[0182] In an exemplary embodiment, the shape of the second active layer 32 may be an "I" shape, and the orthographic projection of the second active layer 32 on the substrate may at least partially overlap with the orthographic projection of the shielding layer 23 on the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 32 on the substrate may be located within the range of the orthographic projection of the shielding layer 23 on the substrate, and the shielding layer 23 may shield the channel region of the second active layer 32 to prevent light from affecting the channel, reduce leakage current, and thus prevent the influence of light on transistor characteristics. The first region 32-1 of the second active layer 32 may be located on a side of the channel region away from the second electrode plate 34, and the orthographic projection of the first region 32-1 of the second active layer 32 on the substrate may be located within the range of the orthographic projection of the shielding layer 23 on the substrate. The second region 32-2 of the second active layer 32 may be located on a side of the channel region close to the second electrode plate 34.

[0183] In an exemplary embodiment, the shape of the third active layer 33 may be an "I" shape, and the orthographic projection of the third active layer 33 on the substrate is spaced from the orthographic projection of the second electrode plate 34 on the substrate, that is, there is no overlapping area between the third active layer 33 and the second electrode plate 42, which is conducive to designing the channel width-to-length ratio of the third transistor according to relevant requirements. The first area 33-1 of the third active layer 33 may be located on the side of the channel region away from the second electrode plate 34, and the orthographic projection of the first area 33-1 of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 22 on the substrate. The second area 33-2 of the third active layer 33 may be located on the side of the channel region close to the second electrode plate 34, and the orthographic projection of the second area 33-2 of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 24 on the substrate.

[0184] In an exemplary embodiment, the semiconductor layer may use a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0185] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, such as Fig. 10A and Fig. 10B As shown, Fig. 10B for Fig. 10A In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GATE) layer.

[0186] In an exemplary embodiment, the second conductive layer pattern in each pixel unit may include at least a first scan signal line 41 , a second scan signal line 42 , a second gate electrode 43 , an auxiliary power line 44 , an auxiliary data line 45 , and an auxiliary compensation line 46 .

[0187] In an exemplary embodiment, the first scan signal line 41 may be in the shape of a strip extending along the first direction X, and the first scan signal line 41 may be located on one side of the second electrode plate 34 in the second direction Y. A first gate electrode 41-1 is disposed on the first scan signal line 41 of each sub-pixel, and the first gate electrode 41-1 serves as a gate electrode of the first transistor T1, and an orthographic projection of the first gate electrode 41-1 on the substrate at least partially overlaps with an orthographic projection of the first active layer 31 on the substrate.

[0188] In an exemplary embodiment, the first scan signal lines 41 may be arranged with equal widths, and the width is the dimension of the first scan signal lines 41 in the second direction Y. A plurality of through holes may be arranged on the first scan signal lines 41, and the shape of the plurality of through holes may be a strip shape extending in the first direction X, and the orthographic projections of the plurality of through holes on the substrate at least partially overlap with the orthographic projections of the first power lines, data signal lines, and compensation signal lines formed subsequently on the substrate, and the plurality of through holes are configured to reduce the parasitic capacitance between the first scan signal lines 41 and the first power lines, data signal lines, and compensation signal lines.

[0189] In an exemplary embodiment, the second scan signal line 42 may be in the shape of a strip extending along the first direction X, the second scan signal line 42 may be located on a side of the second electrode plate 34 away from the first scan signal line 41, the orthographic projection of the second scan signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third active layer 33 in each sub-pixel on the substrate, and the second scan signal line 42 in the overlapping area may serve as the gate electrode of the third transistor T3.

[0190] In an exemplary embodiment, the second scan signal line 42 may be provided with unequal widths, and the width is the size of the second scan signal line 42 in the second direction Y. The second scan signal line 42 includes an area overlapping with the third active layer 33 and an area not overlapping with the third active layer 33, and the width of the second scan signal line 42 in the area overlapping with the third active layer 33 may be smaller than the width of the second scan signal line 42 in the area not overlapping with the third active layer 33. In the area not overlapping with the third active layer 33, a plurality of through holes may be provided on the second scan signal line 42, and the shape of the plurality of through holes may be a strip shape extending in the first direction X, and the orthographic projections of the plurality of through holes on the substrate at least partially overlap with the orthographic projections of the first power line, the data signal line, and the compensation signal line formed subsequently on the substrate, and the plurality of through holes are configured to reduce the parasitic capacitance between the second scan signal line 42 and the first power line, the data signal line, and the compensation signal line.

[0191] In an exemplary embodiment, the first scan signal line 41 and the second scan signal line 42 may be disposed in parallel.

[0192] In an exemplary embodiment, the first scanning signal line 41 and the second scanning signal line 42 are both disposed discontinuously. In at least one sub-pixel, the first scanning signal line 41 is provided with at least one first break K1 , and the second scanning signal line 42 is provided with at least one second break K2 .

[0193] In an exemplary embodiment, the first break K1 may be disposed at any one or more of the following positions: within the first subpixel P1, within the second subpixel P2, within the third subpixel P3, within the fourth subpixel P4, or between adjacent subpixels. The second break K2 may be disposed at any one or more of the following positions: within the first subpixel P1, within the second subpixel P2, within the third subpixel P3, within the fourth subpixel P4, or between adjacent subpixels.

[0194] In an exemplary embodiment, at least one first break K1 may be provided in the first sub-pixel P1, and the first break K1 disconnects the first scanning signal line 41 to form a discontinuous structure of the first scanning signal line 41. In an exemplary embodiment, the first scanning signal lines 41 on both sides of the first break K1 may be connected to each other through the first signal connection electrodes formed subsequently to achieve transmission of the first scanning signal.

[0195] In an exemplary embodiment, at least one second break K2 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, and the second break K2 disconnects the second scanning signal line 42 to form a discontinuous structure of the second scanning signal line 42. In an exemplary embodiment, the second scanning signal lines 42 on both sides of the second break K2 may be connected to each other through a second signal connection electrode formed subsequently to achieve transmission of the second scanning signal.

[0196] In an exemplary embodiment, the compensation connection electrode 83 may be disposed in the second break K2 , and an orthographic projection of the compensation connection electrode 83 on the substrate at least partially overlaps with an orthographic projection of the second break K2 on the substrate.

[0197] In an exemplary embodiment, the second gate electrode 43 may be in a strip shape extending along the first direction X, and the second gate electrode 43 may serve as a gate electrode of the second transistor T2. In each sub-pixel, on the one hand, the orthographic projection of the second gate electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer 32 on the substrate, and on the other hand, the orthographic projection of the second gate electrode 43 on the substrate at least partially overlaps with the second region 31-2 of the first active layer 31.

[0198] In an exemplary embodiment, the auxiliary power line 44 may be in the shape of a strip extending along the second direction Y, and may be disposed in the first sub-pixel P1 and the fourth sub-pixel P4, respectively. In the first sub-pixel P1, the auxiliary power line 44 is located on one side of the second electrode plate 34 in the opposite direction of the first direction X. In the fourth sub-pixel P4, the auxiliary power line 44 is located on one side of the second electrode plate 34 in the first direction X. The auxiliary power line 44 is configured to be connected to the first power line formed subsequently, forming a double-layer routing, ensuring the reliability of power signal transmission, and reducing the resistance of the first power line.

[0199] In an exemplary embodiment, the auxiliary data line 45 may be in the shape of a strip extending along the second direction Y, and may be disposed in each sub-pixel. In the first sub-pixel P1 and the third sub-pixel P3, the auxiliary data line 45 is located on one side of the second electrode plate 34 in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, the auxiliary data line 45 is located on one side of the second electrode plate 34 in the opposite direction of the first direction X. The auxiliary data line 45 is configured to be connected to a subsequently formed data signal line to form a double-layer routing line, thereby ensuring the reliability of data signal transmission and reducing the resistance of the data signal line.

[0200] In an exemplary embodiment, the auxiliary compensation line 46 may be in the shape of a strip extending along the second direction Y, and may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The auxiliary compensation line 46 is configured to be connected to a compensation signal line formed subsequently to form a double-layer routing line, thereby ensuring the reliability of compensation signal transmission and reducing the resistance of the compensation signal line.

[0201] In an exemplary embodiment, main portions of the auxiliary power lines 44 , the auxiliary data lines 45 , and the auxiliary compensation lines 46 may be disposed in parallel.

[0202] In an exemplary embodiment, the second gate electrodes 43 in the first and fourth subpixels P1 and P4 may be disposed mirror-symmetrically with respect to the auxiliary compensation line 46 , and the second gate electrodes 43 in the second and third subpixels P2 and P3 may be disposed mirror-symmetrically with respect to the auxiliary compensation line 46 .

[0203] In an exemplary embodiment, the auxiliary power lines 44 in the first subpixel P1 and the fourth subpixel P4 may be disposed in mirror symmetry with respect to the auxiliary compensation line 46 , and the second scan signal lines 42 may be disposed in mirror symmetry with respect to the auxiliary compensation line 46 .

[0204] In an exemplary embodiment, this process also includes a conductorization treatment. The conductorization treatment is to perform plasma treatment using the second conductive layer as a shield after forming the second conductive layer pattern, and the semiconductor layer shielded by the second conductive layer is used as the channel region of the transistor, and the semiconductor layer not shielded by the second conductive layer is processed into a conductorization layer to form a conductorized second electrode plate and a conductorized source and drain region.

[0205] (15) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of via holes are provided on the third insulating layer, such as Fig.11 shown.

[0206] In an exemplary embodiment, the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0207] In an exemplary embodiment, a first via hole V1 may be provided in each sub-pixel, an orthographic projection of the first via hole V1 on the substrate is located within the range of an orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose a surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed data signal line to the first region of the first active layer through the via hole.

[0208] In an exemplary embodiment, the second via hole V2 may be provided in each sub-pixel, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, and the orthographic projection of the second via hole V2 on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 43 on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away, and the surface of the second region of the first active layer and the surface of the second gate electrode 43 are exposed at the same time. The second via hole V2 is a transfer via hole, and the transfer via hole is composed of two half holes, one half hole is formed on the second region of the first active layer, and the other half hole is formed on the second gate electrode 43, so that the transfer via hole composed of the two half holes simultaneously exposes the surface of the second region of the first active layer and the surface of the second gate electrode 43. In an exemplary embodiment, the second via hole V2 is configured to allow the first connection electrode formed subsequently to be connected to the second gate electrode 43 and the second region of the first active layer through the via hole at the same time.

[0209] In an exemplary embodiment, a third via hole V3 may be provided in each sub-pixel, an orthographic projection of the third via hole V3 on the substrate being located within the range of an orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer within the third via hole V3 being etched away to expose a surface of the first region of the second active layer, and the third via hole V3 being configured to connect a subsequently formed first power line or a sixth connecting electrode to the first region of the second active layer through the via hole.

[0210] In an exemplary embodiment, the fourth via hole V4 can be arranged in each sub-pixel. On the one hand, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the second area of ​​the second active layer on the substrate. On the other hand, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the blocking layer 23 on the substrate. The fourth via hole V4 is a transfer via hole. The third insulating layer, the second insulating layer and the first insulating layer in the fourth via hole V4 are etched away, and the surface of the second area of ​​the second active layer and the surface of the blocking layer 23 are exposed at the same time. The fourth via hole V4 is configured to enable a subsequently formed second connecting electrode to be connected to the second area of ​​the second active layer and the blocking layer 23 through the via hole at the same time.

[0211] In an exemplary embodiment, the fifth via hole V5 can be arranged in each sub-pixel. On the one hand, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the first area of ​​the third active layer on the substrate. On the other hand, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 22 on the substrate. The fifth via hole V5 is a transfer via hole. The third insulating layer, the second insulating layer and the first insulating layer in the fifth via hole V5 are etched away, and the surface of the first area of ​​the third active layer and the surface of the compensation connection line 22 are exposed at the same time. The fifth via hole V5 is configured to enable the subsequently formed fourth connection electrode to be connected to the compensation connection line 22 and the first area of ​​the third active layer through the via hole at the same time.

[0212] In an exemplary embodiment, the sixth via hole V6 can be arranged in each sub-pixel. On the one hand, the orthographic projection of the sixth via hole V6 on the substrate at least partially overlaps with the orthographic projection of the second area of ​​the third active layer on the substrate. On the other hand, the orthographic projection of the sixth via hole V6 on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 24 on the substrate. The sixth via hole V6 is a transfer via hole. The third insulating layer, the second insulating layer and the first insulating layer in the sixth via hole V6 are etched away, and the surface of the second area of ​​the third active layer and the surface of the interlayer connection electrode 24 are exposed at the same time. The sixth via hole V6 is configured to enable a subsequently formed third connection electrode to be connected to the interlayer connection electrode 24 and the second area of ​​the third active layer through the via hole at the same time.

[0213] In an exemplary embodiment, the seventh via hole V7 can be arranged in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first end of the power connection line 21 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the seventh via hole V7 are etched away to expose the surface of the first end of the power connection line 21, and the seventh via hole V7 is configured to connect the subsequently formed first power line to the first end of the power connection line 21 through the via hole.

[0214] In an exemplary embodiment, the eighth via hole V8 can be arranged in the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the second end of the power connection line 21 on the substrate, and the third insulating layer, the second insulating layer and the first insulating layer in the eighth via hole V8 are etched away to expose the surface of the second end of the power connection line 21, and the eighth via hole V8 is configured to connect the subsequently formed sixth connection electrode to the second end of the power connection line 21 through the via hole.

[0215] In an exemplary embodiment, the ninth via hole V9 may be disposed in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the auxiliary power line 44 on the substrate, the third insulating layer in the ninth via hole V9 is etched away to expose the surface of the auxiliary power line 44, and the ninth via hole V9 is configured to connect the first power line formed subsequently to the auxiliary power line 44 through the via hole. In an exemplary embodiment, the ninth via hole V9 may include a plurality of via holes, and the plurality of ninth via holes V9 may be arranged in sequence along the second direction Y to increase the connection reliability between the first power line and the auxiliary power line 44.

[0216] In an exemplary embodiment, the tenth via hole V10 may be disposed in each sub-pixel, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the auxiliary data line 45 on the substrate, the third insulating layer in the tenth via hole V10 is etched away to expose the surface of the auxiliary data line 45, and the tenth via hole V10 is configured to allow a subsequently formed data signal line to be connected to the auxiliary data line 45 through the via hole. In an exemplary embodiment, the tenth via hole V10 may include a plurality of via holes, and the plurality of tenth via holes V10 may be sequentially arranged along the second direction Y to increase the connection reliability between the data signal line and the auxiliary data line 45.

[0217] In an exemplary embodiment, the eleventh via hole V11 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the auxiliary compensation line 46 on the substrate, the third insulating layer in the eleventh via hole V11 is etched away to expose the surface of the auxiliary compensation line 46, and the eleventh via hole V11 is configured to allow a compensation signal line formed subsequently to be connected to the auxiliary compensation line 46 through the via hole. In an exemplary embodiment, the eleventh via hole V11 may include a plurality of via holes, and the plurality of eleventh via holes V11 may be sequentially arranged along the second direction Y to increase the connection reliability between the compensation signal line and the auxiliary compensation line 46.

[0218] In an exemplary embodiment, the twelfth via hole V12 and the thirteenth via hole V13 can be arranged in the first sub-pixel P1, the orthographic projection of the twelfth via hole V12 on the substrate can be located within the range of the orthographic projection of the first scanning signal line 41 on one side of the first break K1 on the substrate, and the orthographic projection of the thirteenth via hole V13 on the substrate can be located within the range of the orthographic projection of the first scanning signal line 41 on the other side of the first break K1 on the substrate, the third insulating layer in the twelfth via hole V12 and the thirteenth via hole V13 is etched away to expose the surfaces of the first scanning signal line 41 on both sides of the first break K1 respectively, and the twelfth via hole V12 and the thirteenth via hole V13 are configured to connect the subsequently formed first signal connection electrodes to the first scanning signal lines 41 on both sides of the first break K1 respectively through the above-mentioned via holes.

[0219] In an exemplary embodiment, the fourteenth via hole V14 can be arranged in the second sub-pixel P2, the fifteenth via hole V15 can be arranged in the third sub-pixel P3, the orthographic projection of the fourteenth via hole V14 on the substrate can be located within the range of the orthographic projection of the second scanning signal line 42 on one side of the second break K2 on the substrate, the orthographic projection of the fifteenth via hole V15 on the substrate can be located within the range of the orthographic projection of the second scanning signal line 42 on the other side of the second break K2 on the substrate, the third insulating layer in the fourteenth via hole V14 and the fifteenth via hole V15 is etched away to expose the surfaces of the second scanning signal line 42 on both sides of the second break K2, respectively, and the fourteenth via hole V14 and the fifteenth via hole V15 are configured to connect the subsequently formed second signal connection electrodes to the second scanning signal lines 42 on both sides of the second break K2 through the above-mentioned via holes.

[0220] In an exemplary embodiment, the sixteenth via hole V16 can be arranged between the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the sixteenth via hole V16 on the substrate can be located within the range of the orthographic projection of the first end of the compensation connection electrode 83 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the first end of the compensation connection electrode 83, and the sixteenth via hole V16 is configured to connect a subsequently formed compensation signal line to the first end of the compensation connection electrode 83 through the via hole.

[0221] In an exemplary embodiment, the seventeenth via hole V17 can be arranged between the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the seventeenth via hole V17 on the substrate can be located within the range of the orthographic projection of the second end of the compensation connection electrode 83 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the second end of the compensation connection electrode 83, and the seventeenth via hole V17 is configured to connect a subsequently formed compensation signal line to the second end of the compensation connection electrode 83 through the via hole.

[0222] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, such as Fig. 12A and Fig. 12B As shown, Fig. 12B for Fig. 12A In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal (SD) layer.

[0223] In an exemplary embodiment, the third conductive layer pattern in each pixel unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a first power line 60, a data signal line 70, a compensation signal line 80, a first signal connection electrode 91 and a second signal connection electrode 92.

[0224] In an exemplary embodiment, the first power line 60 may be respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and the shape of the first power line 60 may be a line shape in which the main part extends along the second direction Y. On one hand, the first power line 60 is connected to the first region of the second active layer through the third via hole V3, so as to write the power signal into the second transistor T2. On the other hand, the first power line 60 is connected to the first end of the power connection line 21 through the seventh via hole V7, and the first power line 60 transmits the power signal to the power connection line 21, so that the first power line 60 located in the first sub-pixel P1 can transmit the power signal to the second sub-pixel P2 through the power connection line 21, and the first power line 60 located in the fourth sub-pixel P4 can transmit the power signal to the third sub-pixel P3 through the power connection line 21. On the other hand, the first power line 60 is connected to the auxiliary power line 44 through a plurality of ninth via holes V9, so that the first power line 60 and the auxiliary power line 44 form a double-layer routing.

[0225] In an exemplary embodiment, the first power line 60 may be a straight line or a folded line of equal width, or a straight line or a folded line of unequal width. Using a straight line or a folded line of variable width can not only facilitate the layout of the pixel structure but also reduce parasitic capacitance.

[0226] In an exemplary embodiment, the data signal line 70 is respectively disposed in each sub-pixel, and the shape of the data signal line 70 may be a line shape in which the main portion extends along the second direction Y. On the one hand, the data signal line 70 is connected to the first region of the first active layer through the first via hole V1 to achieve writing of the data signal into the first transistor T1, and on the other hand, the data signal line 70 is connected to the auxiliary data line 45 through a plurality of tenth via holes V10, so that the data signal line 70 and the auxiliary data line 45 form a double-layer routing.

[0227] In an exemplary embodiment, the data signal line 70 may be a straight line or a folded line of equal width, or a straight line or a folded line of unequal width. Using a straight line or a folded line with variable width can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0228] In an exemplary embodiment, the compensation signal line 80 can be arranged between the second sub-pixel P2 and the third sub-pixel P3, and the compensation signal line 80 can include a first compensation signal line 81 and a second compensation signal line 82. The first compensation signal line 81 and the second compensation signal line 82 can be respectively arranged on both sides of the second signal connection electrode 92 in the second direction Y. The shape of the first compensation signal line 81 and the second compensation signal line 82 can be a strip shape with a main part extending along the second direction Y, forming compensation signal lines arranged at intervals.

[0229] In an exemplary embodiment, the first compensation signal line 81 is connected to the first end of the compensation connection electrode 83 through the sixteenth via hole V16, and the second compensation signal line 82 is connected to the second end of the compensation connection electrode 83 through the seventeenth via hole V17, so that the first compensation signal line 81 and the second compensation signal line 82 on both sides of the second signal connection electrode 92 are interconnected through the compensation connection electrode 83.

[0230] In an exemplary embodiment, the second compensation signal line 82 may also be connected to the auxiliary compensation line 46 through a plurality of eleventh vias V11 , so that the second compensation signal line 82 and the auxiliary compensation line 46 form a double-layer routing.

[0231] In an exemplary embodiment, the first compensation signal line 81 and the second compensation signal line 82 can be straight lines or broken lines of equal width, or straight lines or broken lines of unequal width. The use of straight lines or broken lines with variable widths can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0232] In an exemplary embodiment, the first connection electrode 51 may be rectangular in shape and may be disposed in each sub-pixel, and the first connection electrode 51 in each sub-pixel is simultaneously connected to the second region of the first active layer and the second gate electrode through the second via hole V2. In an exemplary embodiment, the first connection electrode 51 may serve as the second electrode of the first transistor T1. Since the second region of the first active layer is connected to the second electrode plate 34, the first connection electrode 51 enables the second electrode of the first transistor T1, the second gate electrode 43, and the second electrode plate 34 to have the same potential, that is, the potential of the first node N1 in the pixel driving circuit.

[0233] In an exemplary embodiment, the second connection electrode 52 may be rectangular in shape and may be disposed in each sub-pixel, and the second connection electrode 52 in each sub-pixel is simultaneously connected to the second region of the second active layer and the shielding layer 23 through the fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 may serve as the second electrode of the second transistor T2. Since the shielding layer 23 is connected to the connection plate 12, and the connection plate 12 is connected to the first electrode plate 11, the second connection electrode 52 enables the second electrode of the second transistor T2 and the first electrode plate 11 of the storage capacitor to have the same potential.

[0234] In an exemplary embodiment, the third connection electrode 53 may be rectangular in shape and may be disposed in each sub-pixel, and the third connection electrode 53 in each sub-pixel is simultaneously connected to the second region of the third active layer and the interlayer connection electrode through the sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as the second electrode of the third transistor T3. Since the interlayer connection electrode 24 is connected to the connection line 13, and the connection line 13 is connected to the first electrode plate 11, the third connection electrode 53 enables the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential.

[0235] In an exemplary embodiment, since the second connecting electrode 52 makes the first electrode plate 11 and the second electrode of the second transistor T2 have the same potential, and the third connecting electrode 53 makes the first electrode plate 11 and the second electrode of the third transistor T3 have the same potential, the second connecting electrode 52 and the third connecting electrode 53 make the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11 have the same potential, that is, the potential of the second node N2 in the pixel driving circuit.

[0236] In an exemplary embodiment, the fourth connection electrode 54 may be rectangular in shape and may be disposed in each sub-pixel, and the fourth connection electrode 54 in each sub-pixel is simultaneously connected to the first region of the third active layer and the compensation connection line 22 through the fifth via hole V5 of the sub-pixel. In an exemplary embodiment, the fourth connection electrode 54 may serve as the first electrode of the third transistor T3, and since the compensation connection line 22 is connected to the first compensation signal line 81, the fourth connection electrode 54 may write the compensation signal into the first electrode of the third transistor T3 of each sub-pixel.

[0237] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the first direction X, and may be respectively disposed in the second sub-pixel P2 and the third sub-pixel P3, a first end of the fifth connection electrode 55 is connected to the first compensation signal line 81, a second end of the fifth connection electrode 55 extends to the second sub-pixel P2 along the opposite direction of the first direction X or extends to the third sub-pixel P3 along the first direction X, and is connected to the fourth connection electrode 54 of the sub-pixel. In an exemplary embodiment, the fifth connection electrode 55 may serve as an auxiliary connection line, and since the fifth connection electrode 55 is connected to the first compensation signal line 81, the fourth connection electrode 54 is connected to the fifth connection electrode 55, and the compensation connection line 22 is connected to the fourth connection electrode 54, the connection between the compensation connection line 22 and the first compensation signal line 81 is realized, and the first compensation signal line 81 transmits the compensation signal to the compensation connection line 22.

[0238] In an exemplary embodiment, the first compensation signal line 81 , the fourth connection electrode 54 , and the fifth connection electrode 55 in the second sub-pixel P2 and the third sub-pixel P3 may be an integral structure connected to each other.

[0239] In an exemplary embodiment, the sixth connection electrode 56 may be in the shape of a strip extending along the second direction Y, and may be disposed in the second sub-pixel P2 and the third sub-pixel P3, respectively. The first end of the sixth connection electrode 56 is connected to the power connection line 21 through the eighth via hole V8, and the second end of the sixth connection electrode 56 is connected to the first region of the second active layer through the third via hole V3 of the sub-pixel. In an exemplary embodiment, the sixth connection electrode 56 may serve as the first electrode of the second transistor T2. Since the power connection line 21 is connected to the first power line 60, the sixth connection electrode 56 may write a power signal into the first electrode of the second transistor T2 of the second sub-pixel P2 and the third sub-pixel P3.

[0240] In an exemplary embodiment, the shape of the first signal connection electrode 91 can be a strip shape extending along the first direction X, and can be arranged in the first sub-pixel P1. The first end of the first signal connection electrode 91 is connected to the first scanning signal line 41 located on one side of the first break K1 through the twelfth via hole V12, and the second end of the first signal connection electrode 91 is connected to the first scanning signal line 41 located on the other side of the first break K1 through the thirteenth via hole V13, so that the first scanning signal lines 41 on both sides of the first break K1 are interconnected through the first signal connection electrode 91.

[0241] In an exemplary embodiment, the second signal connection electrode 92 can be shaped like a strip extending along the first direction X, and can be arranged between the second sub-pixel P2 and the third sub-pixel P3. The first end of the second signal connection electrode 92 is connected to the second scanning signal line 42 located on one side of the second break K2 through the fourteenth via hole V14, and the second end of the second signal connection electrode 92 is connected to the second scanning signal line 42 located on the other side of the second break K2 through the fifteenth via hole V15, so that the second scanning signal lines 42 on both sides of the second break K2 are interconnected through the second signal connection electrode 92.

[0242] In an exemplary embodiment, at least one through hole may be provided on the second signal connection electrode 92, and the through hole is configured to reduce the parasitic capacitance between the second signal connection electrode 92 and the compensation connection electrode 83, that is, to reduce the parasitic capacitance between the second scanning signal line and the compensation signal line, by an orthographic projection of the through hole on the substrate and the compensation connection electrode 83.

[0243] In an exemplary embodiment of the present disclosure, a data signal line 70 extending along the second direction Y is provided in each sub-pixel, and the data signal line 70 is connected to the first transistor T1 of the sub-pixel through a via hole, so that the data signal line 70 of each sub-pixel writes the data signal into the first electrode of the first transistor T1 of the sub-pixel.

[0244] The exemplary embodiment of the present disclosure realizes writing power signals into the second transistors T2 of the four sub-pixels respectively by providing two first power lines 60 extending along the second direction Y and two power connection lines 21 extending along the first direction X in the pixel unit. In the first sub-pixel P1 and the fourth sub-pixel P4, the first power line 60 is directly connected to the first electrode of the second transistor T2 through a via hole. In the second sub-pixel P2 and the third sub-pixel P3, the first power line 60 is connected to the first electrode of the second transistor T2 through the sixth connection electrode 56.

[0245] The exemplary embodiment of the present disclosure realizes writing the compensation signal into the third transistor T3 of the four sub-pixels respectively by setting a compensation signal line (a first compensation signal line 81 and a second compensation signal line 82 connected by a compensation connection electrode 83) in the main part extending along the second direction Y and two compensation connection lines 22 extending along the first direction X in the pixel unit. Among them, in the second sub-pixel P2 and the third sub-pixel P3, the compensation signal line is connected to the first electrode of the third transistor T3 through the fifth connection electrode 55 and the fourth connection electrode 54 respectively. In the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line is connected to the first electrode of the third transistor T3 through the compensation connection line 22 and the fourth connection electrode 54 respectively. The present disclosure provides compensation signals to four sub-pixels by setting a compensation signal line, which can ensure that the RC delay of the compensation signal before writing into the transistor is substantially the same, thereby ensuring display uniformity.

[0246] In the exemplary embodiment of the present disclosure, at least one first break is set on the first scanning signal line, and the first scanning signal lines on both sides of the first break are connected to each other through the first signal connection electrode. Compared with the display substrate using continuous scanning signal lines, the exemplary embodiment of the present disclosure divides the first scanning signal line into multiple sections, which can not only effectively reduce the amount of static electricity generated by the scanning signal line during the dry etching process, but also avoid the situation where the transistor channel is broken down due to static electricity accumulation, effectively avoid the edge dark spots of the display device, and improve the yield rate and display quality while ensuring the continuous transmission of the first scanning signal.

[0247] In the exemplary embodiment of the present disclosure, at least one second break is set on the second scanning signal line, and the second scanning signal lines on both sides of the second break are connected to each other through the second signal connection electrode. Compared with the display substrate using continuous scanning signal lines, the exemplary embodiment of the present disclosure divides the second scanning signal lines into multiple sections, which can not only effectively reduce the amount of static electricity generated by the scanning signal lines during the dry etching process, but also avoid the situation where the transistor channel is broken down due to static electricity accumulation, effectively avoid the edge dark spots of the display device, and improve the yield rate and display quality while ensuring the continuous transmission of the second scanning signal.

[0248] The exemplary embodiment of the present disclosure divides the compensation signal line into multiple sections by setting the second break between the second sub-pixel P2 and the third sub-pixel P3. The compensation signal lines are interconnected through the compensation connecting electrodes, which effectively reduces the amount of static electricity generated by the compensation signal lines during the dry etching process and avoids the breakdown of the transistor channel due to static electricity accumulation, effectively avoids the occurrence of dark spots on the edges of the display device, and improves the yield rate and display quality while ensuring the continuous transmission of the compensation signal lines.

[0249] (17) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: coating a planar film on the substrate on which the aforementioned pattern is formed, patterning the planar film using a patterning process to form a planar layer pattern covering the third conductive layer, wherein a plurality of via holes are formed on the planar layer, and the plurality of via holes at least include a twenty-first via hole V21 located in each sub-pixel, such as Fig.13 shown.

[0250] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the flat layer in the twenty-first via hole V21 is removed to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect the subsequently formed first electrode to the second connecting electrode 52 through the via hole.

[0251] In an exemplary embodiment, the display substrate may include a fourth insulating layer and a color filter layer. On the substrate formed with the aforementioned pattern, the fourth insulating layer is first formed, and then the color filter layer is formed on the fourth insulating layer. Subsequently, a flat film is coated, and the flat film and the fourth insulating film are patterned using a patterning process to form a fourth insulating layer covering the third conductive layer, a color filter layer arranged on the fourth insulating layer, and a flat layer pattern covering the color filter layer, and a plurality of vias are opened on the flat layer and the fourth insulating layer.

[0252] (18) Forming an electrode conductive layer pattern. In an exemplary embodiment, forming the electrode conductive layer pattern may include: depositing an electrode conductive film on the substrate on which the aforementioned pattern is formed, patterning the electrode conductive film using a patterning process to form an electrode conductive layer pattern disposed on the flat layer, wherein the electrode conductive layer pattern includes at least a first electrode 301 located in each sub-pixel, such as Fig.14 shown.

[0253] In an exemplary embodiment, the electrode conductive layer pattern may include a red first electrode in the first sub-pixel P1, a white first electrode in the second sub-pixel P2, a blue first electrode in the third sub-pixel P3, and a green first electrode in the fourth sub-pixel P4, and the first electrode in each sub-pixel is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 serves as the second electrode of the second transistor T2, the connection between the first electrode 301 and the second electrode of the second transistor T2 is achieved.

[0254] In an exemplary embodiment, the first electrode 301 may be in a strip shape extending along the second direction Y, and a protrusion is provided on one side of the first electrode in each sub-pixel in the second direction Y, and the protrusion is connected to the second connection electrode 52 through the twenty-first via hole V21.

[0255] In an exemplary embodiment, an orthographic projection of the first electrode in each sub-pixel on the substrate includes an orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0256] (19) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern, wherein the pixel definition layer pattern includes at least a pixel opening 500 located in each sub-pixel, such as Fig.15 shown.

[0257] In an exemplary embodiment, the shape and area of ​​the pixel opening 500 of different sub-pixels may be different. The exemplary embodiment of the present disclosure can adapt to the transmittance of the color filter layer of different sub-pixels by designing the four sub-pixels to have different aperture ratios, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the life of the four sub-pixel light-emitting devices and ensuring the product life.

[0258] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels may be the same or may be different, and the areas of the pixel openings of the four sub-pixels may be the same or may be different.

[0259] In an exemplary embodiment, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a pentagon, a hexagon, a circle, and an ellipse.

[0260] In an exemplary embodiment, an orthographic projection of the pixel opening 500 in each sub-pixel on the substrate at least partially overlaps with an orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0261] In an exemplary embodiment, the orthographic projection of the storage capacitor in each sub-pixel on the substrate may be located within the range of the orthographic projection of the pixel opening 500 in the sub-pixel on the substrate.

[0262] Fig.16 FIG. 1 is a schematic diagram of the positional relationship between a pixel opening and a signal line of an exemplary embodiment of the present disclosure. Fig.16 As shown, in an exemplary embodiment, the pixel opening 500 of each sub-pixel includes at least a first opening edge 501 located on one side of the first direction X of the pixel opening and a second opening edge 502 located on the opposite side of the first direction X of the pixel opening. The shapes of the first opening edge 501 and the second opening edge 502 can be straight lines or broken lines extending along the second direction Y.

[0263] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the first power line 60 on the substrate.

[0264] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the data signal line 70 on the substrate.

[0265] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of at least one of the first opening edge 501 and the second opening edge 502 on the substrate at least partially overlaps with an orthographic projection of the compensation signal line 80 on the substrate.

[0266] In an exemplary embodiment, in the first subpixel P1, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the first power line 60 on the substrate.

[0267] In an exemplary embodiment, in the second subpixel P2, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 80 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate.

[0268] In an exemplary embodiment, in the third subpixel P3, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 80 on the substrate.

[0269] In an exemplary embodiment, in the fourth subpixel P4, the orthographic projection of the first opening edge 501 on the substrate at least partially overlaps with the orthographic projection of the first power line 60 on the substrate, and the orthographic projection of the second opening edge 502 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate.

[0270] The present invention sets the orthographic projection of the first opening edge and / or the second opening edge of the pixel opening on the substrate to at least partially overlap with the orthographic projection of the first power line 60, the data signal line 70 or the compensation signal line 80 on the substrate, that is, the pixel opening is pressed on the metal line, so that at a side viewing angle, the outgoing light of the pixel opening is largely the light reflected by the metal line, which can effectively reduce the brightness difference at a side viewing angle caused by the alignment difference and eliminate the splicing watermark (mura).

[0271] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer by evaporation or inkjet printing, the organic light-emitting layer is connected to the first electrode through a pixel opening, forming a second electrode on the organic light-emitting layer, and the second electrode is connected to the organic light-emitting layer. Forming an encapsulation structure layer, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0272] At this point, a driving circuit layer, a light-emitting structure layer disposed on the driving circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, and a flat layer stacked in sequence on the substrate. The light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, and the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked.

[0273] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0274] In an exemplary embodiment, the transparent conductive layer and the electrode conductive layer may be made of transparent conductive materials, such as indium tin oxide ITO or indium zinc oxide IZO, etc. The first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which may be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer is called a gate insulating (GI) layer, and the third insulating layer is called an interlayer insulating (ILD) layer. The flat layer may be made of an organic material, such as a resin, etc., and the pixel definition layer may be made of polyimide, acrylic or polyethylene terephthalate.

[0275] At present, large-size, especially ultra-large-size display devices are usually spliced ​​by multiple exposure processes of exposure machines. Display devices spliced ​​by multiple exposures have problems such as splicing watermarks. Usually, the splicing watermark appears as an obvious dividing line at a side angle. The inventors of this application have found that the appearance of the splicing watermark is caused by the difference in alignment in the exposure process. Due to the deviation in the alignment of multiple exposures, the positions of the light-emitting areas formed by the pixel openings and the signal lines in the driving circuit layer in the display substrates formed by different exposure processes are inconsistent (for example, the distance between the edge of the light-emitting area and the signal line is inconsistent), resulting in different degrees of reflection in different light-emitting areas, which leads to different brightness of adjacent display substrates at a side angle, and the appearance of splicing watermarks (mura) in the area near the splicing line.

[0276] It can be seen from the structure and preparation process of the display substrate provided by the present disclosure that the display substrate provided by the present disclosure, by setting the orthographic projection of the first opening edge and / or the second opening edge of the pixel opening on the substrate to at least partially overlap with the orthographic projection of the signal line on the substrate, that is, the pixel opening is pressed on the metal wire, which not only makes the degree of reflection of different pixel openings basically the same, but also makes the outgoing light of the pixel opening at a side viewing angle largely the light reflected by the metal wire, effectively reducing the brightness difference at a side viewing angle caused by the difference in alignment, and effectively eliminating the splicing watermark.

[0277] The display substrate provided by the exemplary embodiment of the present disclosure, by setting at least one break on the first scanning signal line and / or the second scanning signal line, the scanning signal lines on both sides of the break are connected to each other through signal connection electrodes, which not only effectively reduces the amount of static electricity generated by the scanning signal lines during the dry etching process, but also avoids the breakdown of the transistor channel due to static electricity accumulation, effectively avoids the occurrence of dark spots on the edges of the display device, and improves the yield rate and display quality while ensuring the continuous transmission of the scanning signal.

[0278] The display substrate provided by the exemplary embodiment of the present disclosure adopts a transparent storage capacitor, and the storage capacitor is composed of a transparent transparent conductive layer and a transparent semiconductor layer. Since light can be emitted through the transparent storage capacitor, the storage capacitor can be set in the pixel opening, which effectively increases the capacitance of the storage capacitor and effectively increases the pixel opening ratio. The preparation process disclosed in the present disclosure can be implemented using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process. The process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0279] The structure and preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0280] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0281] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0282] The exemplary embodiment of the present disclosure further provides a method for driving a display substrate, so as to drive the display substrate of the aforementioned embodiment.

[0283] Fig.17 FIG. 2 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure. Fig.17As shown, the display substrate may include at least a first sub-substrate 100 and a second sub-substrate 200. The first sub-substrate 100 and the second sub-substrate 200 may include the same structural layer, but each structural layer in the first sub-substrate 100 and the second sub-substrate 200 adopts a different exposure process. The first sub-substrate 100 and the second sub-substrate 200 are spliced ​​together, and the first sub-substrate 100 and the second sub-substrate 200 form a splicing line 300 at the splicing position.

[0284] In an exemplary embodiment, the first sub-substrate 100 and the second sub-substrate 200 may each include M pixel rows and N pixel columns, that is, the first sub-substrate 100 and the second sub-substrate 200 each include M*N sub-pixels arranged in a matrix, where M and N are both positive integers greater than 1.

[0285] In an exemplary embodiment, each pixel column may include M sub-pixels arranged in sequence along the second direction Y, each sub-pixel may include a pixel driving circuit, the pixel driving circuits in the M sub-pixels in a pixel column are respectively connected to the driving signal lines, and the driving signal lines are configured to provide driving signals to the M pixel driving circuits respectively.

[0286] In an exemplary embodiment, the driving signal line may be a data signal line, the driving signal may be a data signal, and the data signal line is configured to provide the data signal to the M pixel driving circuits, respectively.

[0287] In an exemplary embodiment, the driving signal line may be a compensation signal line, the driving signal may be a compensation signal, and the compensation signal line is configured to provide the compensation signal to the M pixel driving circuits, respectively.

[0288] In an exemplary embodiment, the first sub-substrate 100 may include at least a first transition zone 110 close to the splicing line 300 and a first normal zone 120 located on a side of the first transition zone 110 away from the splicing line 300, and the second sub-substrate 200 may include at least a second transition zone 210 close to the splicing line 300 and a second normal zone 220 located on a side of the second transition zone 210 away from the splicing line 300, that is, the first transition zone 110 and the second transition zone 210 are respectively located on both sides of the splicing line 300 and are adjacent to the splicing line 300.

[0289] In an exemplary embodiment, the first transition region 110 and the second transition region 210 may each include n pixel columns, that is, the first transition region 110 and the second transition region 210 may each include n*M sub-pixels, where n is a positive integer greater than 1 and less than N.

[0290] In an exemplary embodiment, n may be approximately 20 to 200, that is, the first transition region 110 and the second transition region 210 may each include 20 to 200 pixel columns.

[0291] In an exemplary embodiment, at a front viewing angle, the brightness of the first sub-substrate 100 is substantially the same as that of the second sub-substrate 200, that is, the brightness of the first transition region 110 is substantially the same as that of the second transition region 210. At a side viewing angle, due to the brightness difference caused by the alignment difference, the brightness of the first sub-substrate 100 is higher than that of the second sub-substrate 200, that is, the brightness of the first transition region 110 is higher than that of the second transition region 210, and a splicing watermark appears in the vicinity of the splicing line 300.

[0292] In order to solve the problems of splicing watermarks in existing display devices, the present disclosure provides a method for driving a display substrate. In an exemplary embodiment, the display substrate includes at least a first sub-substrate and a second sub-substrate that are spliced ​​together, and the first sub-substrate and the second sub-substrate form a splicing line at the splicing position; the first sub-substrate includes at least a first transition zone close to the splicing line and a first normal zone located on the side of the first transition zone away from the splicing line, and the second sub-substrate includes at least a second transition zone close to the splicing line and a second normal zone located on the side of the second transition zone away from the splicing line; the first transition zone and the second transition zone each include at least one pixel column, each pixel column includes M sub-pixels, and the sub-pixels include at least a pixel driving circuit, and the pixel driving circuit is connected to a driving signal line, and M is a positive integer greater than 1. The method for driving a display substrate may include:

[0293] Processing at least one original driving signal of at least one pixel column in the first transition region and the second transition region into at least one processed driving signal;

[0294] At least one processed driving signal and the remaining original driving signals are provided to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column.

[0295] In an exemplary embodiment, in at least one of the first transition zone and the second transition zone, along a direction approaching the stitching line, the number of the original driving signals in the pixel column gradually decreases, and the number of the processed driving signals in the pixel column gradually increases.

[0296] In an exemplary embodiment, in at least one of the first transition region and the second transition region, the number of the original driving signals in the pixel column farthest from the stitching line is M.

[0297] In an exemplary embodiment, in at least one of the first transition zone and the second transition zone, the number of processed driving signals in the pixel column closest to the stitching line is k*M, and the number of original driving signals is (1-k)*M, k=0.2 to 0.8.

[0298] In an exemplary embodiment, k=0.5.

[0299] In an exemplary embodiment, the driving signal may include a data signal line, the driving signal may include a data signal, and the processed driving signal may include a first data signal and / or a second data signal.

[0300] In an exemplary embodiment, the first data signal is V-ΔV, and the second data signal is V+ΔV, where V is an original data signal and ΔV is an additional signal for changing the original data signal.

[0301] In an exemplary embodiment, the value of the additional signal ΔV can be determined according to the change in the display grayscale. For example, if the display grayscale corresponding to the original data signal is 100, the value of the additional signal ΔV can be determined by setting the display grayscale corresponding to the first data signal or the second data signal to 99 or 101.

[0302] In an exemplary embodiment, the drive signal may include a compensation signal line, the drive signal may include a compensation signal, and the processed drive signal may include a first compensation signal and / or a second compensation signal;

[0303] In an exemplary embodiment, for the first transition region, the original compensation signal may be a compensation signal for an i-th pixel column in the first transition region, and the first compensation signal may be a compensation signal for a j-th pixel column in the second transition region.

[0304] In an exemplary embodiment, for the second transition region, the original compensation signal may be a compensation signal for a j-th pixel column in the second transition region, and the second compensation signal may be a compensation signal for an i-th pixel column in the first transition region.

[0305] The driving method of the display substrate of the present disclosure is described below by way of some exemplary embodiments. In the following embodiments, the first transition region 110 and the second transition region 210 each include n pixel columns, and the number of the pixel columns gradually increases along the direction away from the stitching line 300, and the nth pixel column is located on the side of the first pixel column away from the stitching line 300. Each pixel column includes M sub-pixels, that is, the number of pixel rows in the first transition region 110 and the second transition region 210 is M.

[0306] Fig.18 Schematic diagram of a method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0307] A1. Process the data signals of n pixel columns in the first transition zone 110 so that the data signals of each pixel column include an original signal group and a processed signal group, the original signal group of the i-th pixel column includes M1 original data signals, and the processed signal group of the i-th pixel column includes M2 first data signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)], i=1, 2, ..., n.

[0308] A2. In each pixel column of the first normal area 120, the second transition area 210, and the second normal area 220, M original data signals are respectively provided to M pixel driving circuits in the pixel column through data signal lines. In each pixel column of the first transition area 110, M1 original data signals in the original signal group and M2 first data signals in the processed signal group are respectively provided to M pixel driving circuits in the pixel column through data signal lines.

[0309] An exemplary embodiment of the present disclosure provides a driving method for gradually reducing the brightness of a first transition region, so as to alleviate the brightness difference between two display substrates at a side viewing angle and effectively avoid a splicing watermark.

[0310] like Fig.18 As shown, in an exemplary embodiment, for the first normal area 120, the second transition area 210 and the second normal area 220, the data signal lines in all pixel columns provide original data signals to realize normal brightness display of each pixel column, and for the first transition area 110, the data signal lines in all pixel columns provide part of the original data signal and part of the first data signal, and the first data signal is a data signal processed from the original data signal to realize the brightness reduction display of each pixel column. At the front viewing angle, although the brightness difference between the first transition area 110 and the second transition area 210 increases, no obvious dividing line is formed. At the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 decreases, and no obvious dividing line is formed. In this way, by dispersing the brightness difference to the front viewing angle and the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 at the side viewing angle is effectively reduced, so that the splicing watermarks at both the front viewing angle and the side viewing angle are invisible.

[0311] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original data signals provided by the data signal lines in each pixel column gradually decreases, the number of first data signals provided by the data signal lines in each pixel column gradually increases, and the brightness of each pixel column in the first transition zone 110 gradually decreases, so that the first transition zone 110 forms a first brightness transition zone with a gradual brightness transition, which has little effect on the display effects in both the front viewing angle and the side viewing angle.

[0312] In an exemplary embodiment, since the data signal line of the pixel column (nth pixel column) farthest from the stitching line 300 in the first transition zone 110 provides all the original data signals, the brightness of the pixel column does not change, and the data signal lines of all the pixel columns in the first normal zone 120 provide all the original data signals, the brightness of the first normal zone 120 does not change, and therefore, no dividing line is formed at the junction of the first transition zone 110 and the first normal zone 120 in both the front viewing angle and the side viewing angle.

[0313] In an exemplary embodiment, since the data signal lines of the pixel column (the first pixel column) closest to the splicing line 300 in the first transition zone 110 all provide the first data signal, that is, the brightness of the pixel column is reduced the most, and the data signal lines of all pixel columns in the second transition zone 210 all provide the original data signal, that is, the brightness of the second transition zone 210 does not change, the brightness at the junction of the first transition zone 110 and the second transition zone 210 gradually transitions in both the front viewing angle and the side viewing angle, the brightness difference at the front viewing angle increases, and the brightness difference at the side viewing angle decreases, and the brightness difference is dispersed in both the front viewing angle and the side viewing angle, reducing the brightness difference between the first transition zone 110 and the second transition zone 210 at the side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at the front viewing angle and the side viewing angle, and the splicing watermark is invisible in both the front viewing angle and the side viewing angle.

[0314] In an exemplary embodiment, the first pixel column provides 100% of the first data signal and the nth pixel column provides 100% of the original data signal in this embodiment is only an example, and the first pixel column and the nth pixel column may include part of the original data signal and part of the first data signal. For example, the first pixel column may include 1% of the original data signal and 99% of the first data signal, and the nth pixel column may include 99% of the original data signal and 1% of the first data signal, which is not limited in the present disclosure.

[0315] Fig.19 FIG. 1 is a schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0316] B1. Process the data signals of n pixel columns in the second transition zone 210 so that the data signals of each pixel column include an original signal group and a processed signal group, the original signal group of the j-th pixel column includes M3 original data signals, and the processed signal group of the j-th pixel column includes M4 second data signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)], j=1, 2, ..., n.

[0317] B2. In each pixel column of the first transition area 110, the first normal area 120, and the second normal area 220, M original data signals are respectively provided to M pixel driving circuits in the pixel column through data signal lines. In each pixel column of the second transition area 210, M3 original data signals in the original signal group and M4 second data signals in the processed signal group are respectively provided to M pixel driving circuits in the pixel column through data signal lines.

[0318] The exemplary embodiments of the present disclosure provide a driving method for gradually increasing the brightness of the second transition zone to alleviate the brightness difference between the two display substrates at a side viewing angle and effectively avoid splicing watermarks.

[0319] like Fig.19 As shown, in an exemplary embodiment, for the first transition area 110, the first normal area 120 and the second normal area 220, the data signal lines in all pixel columns provide original data signals to realize normal brightness display of each pixel column, and for the second transition area 210, the data signal lines in all pixel columns provide part of the original data signal and part of the second data signal, and the second data signal is a data signal processed by the original data signal to realize the brightness increase display of each pixel column. At the front viewing angle, although the brightness difference between the first transition area 110 and the second transition area 210 increases, no obvious dividing line is formed. At the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 decreases, and no obvious dividing line is formed. In this way, by dispersing the brightness difference in the two directions of the front viewing angle and the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 at the side viewing angle is effectively reduced, so that the splicing watermarks in both the front viewing angle and the side viewing angle are invisible.

[0320] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original data signals provided by the data signal lines in each pixel column gradually decreases, the number of second data signals provided by the data signal lines in each pixel column gradually increases, and the brightness of each pixel column in the second transition zone 210 gradually increases, so that the second transition zone 210 forms a second brightness transition zone with a gradual brightness transition, which has little effect on the display effects in both the front viewing angle and the side viewing angle.

[0321] In an exemplary embodiment, since the data signal line of the pixel column (nth pixel column) farthest from the stitching line 300 in the second transition zone 210 provides all the original data signals, the brightness of the pixel column does not change, and the data signal lines of all the pixel columns in the second normal zone 220 provide all the original data signals, the brightness of the second normal zone 220 does not change, and therefore, no dividing line is formed at the junction of the second transition zone 210 and the second normal zone 220 in both the front viewing angle and the side viewing angle.

[0322] In an exemplary embodiment, since the data signal lines of the pixel column (the first pixel column) closest to the stitching line 300 in the second transition zone 210 all provide the second data signal, that is, the brightness of the pixel column increases the most, and the data signal lines of all pixel columns in the first transition zone 110 all provide the original data signal, that is, the brightness of the first transition zone 110 does not change, the brightness at the junction of the first transition zone 110 and the second transition zone 210 gradually transitions in both the front viewing angle and the side viewing angle, the brightness difference at the front viewing angle increases, and the brightness difference at the side viewing angle decreases, and the brightness difference is dispersed in both the front viewing angle and the side viewing angle, reducing the brightness difference between the first transition zone 110 and the second transition zone 210 at the side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at the front viewing angle and the side viewing angle, and the stitching watermark is invisible in both the front viewing angle and the side viewing angle.

[0323] In an exemplary embodiment, the first pixel column provides 100% of the second data signal and the nth pixel column provides 100% of the original data signal in this embodiment is only an example, and the first pixel column and the nth pixel column may include part of the original data signal and part of the second data signal. For example, the first pixel column may include 1% of the original data signal and 99% of the second data signal, and the nth pixel column may include 99% of the original data signal and 1% of the second data signal, which is not limited in the present disclosure.

[0324] Fig. 20 FIG. 1 is a schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0325] C1. Process the data signals of n pixel columns in the first transition area 110 and the second transition area 210 respectively, so that the data signals of each pixel column include an original signal group and a processed signal group. In the first transition area 110, the original signal group of the i-th pixel column includes M1 original data signals, and the processed signal group of the i-th pixel column includes M2 first data signals, M1=0.5*M[(i-1) / (n-1)], M2=0.5*M[1-(i-1) / (n-1)]. In the second transition area 210, the original signal group of the j-th pixel column includes M3 original data signals, and the processed signal group of the j-th pixel column includes M4 second data signals, M3=0.5*M[(j-1) / (n-1)], M4=0.5*M[1-(j-1) / (n-1)]. i=1, 2, ..., n, j=1, 2, ..., n.

[0326] C2. In each pixel column of the first normal area 120 and the second normal area 220, M original data signals are respectively provided to M pixel driving circuits in the pixel column through the data signal lines.

[0327] C3. In each pixel column in the first transition zone 110, M1 original data signals in the original signal group and M2 first data signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through data signal lines. In each pixel column in the second transition zone 210, M3 original data signals in the original signal group and M4 second data signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through data signal lines.

[0328] The present disclosure provides a driving method for gradually reducing the brightness of a first transition zone and gradually increasing the brightness of a second transition zone, so as to alleviate the brightness difference between two display substrates at a side viewing angle and effectively avoid splicing watermarks.

[0329] like Fig. 20 As shown, in an exemplary embodiment, for the first normal area 120 and the second normal area 220, the data signal lines in all pixel columns provide original data signals to realize normal brightness display of each pixel column, and for the first transition area 110, the data signal lines in all pixel columns provide part of the original data signal and part of the first data signal to realize the brightness reduction display of each pixel column, and for the second transition area 210, the data signal lines in all pixel columns provide part of the original data signal and part of the second data signal to realize the brightness increase display of each pixel column. At the front viewing angle, although the brightness difference between the first transition area 110 and the second transition area 210 increases, no obvious dividing line is formed. At the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 decreases, and no obvious dividing line is formed. In this way, by dispersing the brightness difference to the front viewing angle and the side viewing angle, the brightness difference between the first transition area 110 and the second transition area 210 at the side viewing angle is effectively reduced, so that the splicing watermarks in both the front viewing angle and the side viewing angle are invisible.

[0330] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original data signals provided by the data signal lines in each pixel column gradually decreases, and the number of first data signals or second data signals provided by the data signal lines in each pixel column gradually increases, the brightness of each pixel column in the first transition zone 110 gradually decreases, and the brightness of each pixel column in the second transition zone 210 gradually increases, so that the first transition zone 110 and the second transition zone 210 respectively form a first brightness transition zone and a second brightness transition zone with gradual brightness transition, which has little effect on the display effects in the two directions of front viewing angle and side viewing angle.

[0331] In an exemplary embodiment, since the data signal lines of the pixel columns farthest from the stitching line 300 in the first transition zone 110 and the second transition zone 210 all provide original data signals, the brightness of the pixel columns does not change, and the data signal lines of all pixel columns in the first normal zone 120 and the second normal zone 220 all provide original data signals, and the brightness of the first normal zone 120 and the second normal zone 220 does not change, in both the front viewing angle and the side viewing angle, no dividing line is formed at the junction of the first transition zone 110 and the first normal zone 120, and at the junction of the second transition zone 210 and the second normal zone 220.

[0332] In an exemplary embodiment, since the data signal line of the pixel column closest to the splicing line 300 in the first transition zone 110 provides 50% of the original data signal and 50% of the first data signal, and the data signal line of the pixel column closest to the splicing line 300 in the second transition zone 210 provides 50% of the original data signal and 50% of the second data signal, the brightness at the junction of the first transition zone 110 and the second transition zone 210 gradually transitions in both the front viewing angle and the side viewing angle, the brightness difference at the front viewing angle increases, and the brightness difference at the side viewing angle decreases, and the brightness difference is dispersed in both the front viewing angle and the side viewing angle, reducing the brightness difference between the first transition zone 110 and the second transition zone 210 at the side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at the front viewing angle and the side viewing angle, and the splicing watermark is invisible in both the front viewing angle and the side viewing angle.

[0333] In an exemplary embodiment, the first pixel column of the first transition region 110 provides 50% of the original data signal and 50% of the first data signal, and the first pixel column of the second transition region 210 provides 50% of the original data signal and 50% of the second data signal. This is only an example description, and the present disclosure is not limited here. For example, the first pixel column of the first transition region 110 can provide k*M first data signals and (1-k)*M original data signals, and the first pixel column of the second transition region 210 can provide k*M second data signals and (1-k)*M original data signals, where k=0.2 to 0.8.

[0334] Fig.21 FIG. 1 is a schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0335] D1. Extract compensation signals of n pixel columns in the second transition zone 210, and process the compensation signals of n pixel columns in the first transition zone 110 so that the compensation signals of each pixel column in the first transition zone 110 include an original signal group and a processed signal group, the original signal group of the i-th pixel column includes M1 original compensation signals, and the processed signal group of the i-th pixel column includes M2 first compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)], the original compensation signal of the i-th pixel column can be the compensation signal of the i-th pixel column in the first transition zone 110, and the first compensation signal of the i-th pixel column can be the compensation signal of the j-th pixel column in the second transition zone 210, i=1, 2, ..., n, j=1, 2, ..., n.

[0336] D2. In each pixel column of the first normal area 120, the second transition area 210 and the second normal area 220, the M original compensation signals are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line. In each pixel column of the first transition area 110, the M1 original compensation signals in the original signal group and the M2 first compensation signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0337] An exemplary embodiment of the present disclosure provides a driving method for gradually changing the brightness of a first transition region to alleviate the brightness difference between two display substrates at a side viewing angle and effectively avoid splicing watermarks.

[0338] like Fig.21 As shown, in an exemplary embodiment, for the first normal area 120, the second transition area 210 and the second normal area 220, the compensation signal lines in all pixel columns provide original compensation signals to achieve normal brightness display of each pixel column, and for the first transition area 110, the compensation signal lines in all pixel columns provide part of the original compensation signal and part of the first compensation signal, and the first compensation signal is the compensation signal of the corresponding pixel column in the second transition area 210 to achieve brightness change display of each pixel column, which effectively reduces the brightness difference between the first transition area 110 and the second transition area 210 at a side viewing angle, so that the splicing watermark is invisible at a side viewing angle.

[0339] In an exemplary embodiment of the present disclosure, compensation signals of corresponding pixel columns in the second transition zone 210 are partially or fully adopted in each pixel column in the first transition zone 110, and the brightness of each pixel column in the first transition zone 110 is adjusted by changing the compensation signal, so that the brightness of each pixel column in the first transition zone 110 gradually approaches the brightness of the corresponding pixel column in the second transition zone 210 under a side viewing angle.

[0340] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original compensation signals provided by the compensation signal lines in each pixel column gradually decreases, the number of first compensation signals provided by the compensation signal lines in each pixel column gradually increases, and the brightness change of each pixel column in the first transition zone 110 gradually increases, so that the first transition zone 110 forms a first brightness transition zone with a gradual brightness transition, which has little effect on the display effects in the two directions of the front viewing angle and the side viewing angle.

[0341] In an exemplary embodiment, since the compensation signal line of the pixel column (nth pixel column) farthest from the stitching line 300 in the first transition zone 110 provides all the original compensation signals, the brightness of the pixel column does not change, and the compensation signal lines of all the pixel columns in the first normal zone 120 provide all the original compensation signals, the brightness of the first normal zone 120 does not change, and therefore, no dividing line is formed at the junction of the first transition zone 110 and the first normal zone 120 in both the front viewing angle and the side viewing angle.

[0342] In an exemplary embodiment, since the compensation signal lines of the pixel columns (the first pixel column) closest to the stitching line 300 in the first transition zone 110 and the second transition zone 210 are all the first compensation signals (the compensation signal of the first pixel column in the second transition zone 210), the compensation signals of the two are the same, and thus the brightness compensation degrees of the pixel columns at the junction of the first transition zone 110 and the second transition zone 210 are the same, which effectively reduces the brightness difference between the first transition zone 110 and the second transition zone 210 at a side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at a side viewing angle, and the stitching watermark at a side viewing angle is invisible.

[0343] In an exemplary embodiment, the first pixel column provides 100% of the first compensation signal and the n-th pixel column provides 100% of the original compensation signal in this embodiment is only an example, and the first pixel column and the n-th pixel column may include part of the original compensation signal and part of the first compensation signal. For example, the first pixel column may include 1% of the original data signal and 99% of the first compensation signal, and the n-th pixel column may include 99% of the original data signal and 1% of the first compensation signal, which is not limited in the present disclosure.

[0344] Fig. 22 FIG. 1 is a schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0345] E1. Extract compensation signals of n pixel columns in the first transition zone 110, and process the compensation signals of n pixel columns in the second transition zone 210 so that the compensation signals of each pixel column in the second transition zone 210 include an original signal group and a processed signal group, the original signal group of the j-th pixel column includes M3 original compensation signals, and the processed signal group of the j-th pixel column includes M4 second compensation signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)], the original compensation signal of the j-th pixel column can be the compensation signal of the j-th pixel column in the second transition zone 210, and the second compensation signal of the j-th pixel column can be the compensation signal of the i-th pixel column in the first transition zone 110, i=1, 2, ..., n, j=1, 2, ..., n.

[0346] E2. In each pixel column of the first transition area 110, the first normal area 120, and the second normal area 220, the M original compensation signals are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line. In each pixel column of the second transition area 210, the M3 original compensation signals in the original signal group and the M4 second compensation signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0347] An exemplary embodiment of the present disclosure provides a driving method for gradually changing the brightness of the second transition zone to alleviate the brightness difference between the two display substrates at a side viewing angle and effectively avoid splicing watermarks.

[0348] like Fig. 22 As shown, in an exemplary embodiment, for the first transition zone 110, the first normal zone 120 and the second normal zone 220, the compensation signal lines in all pixel columns provide original compensation signals to achieve normal brightness display of each pixel column, and for the second transition zone 210, the compensation signal lines in all pixel columns provide part of the original compensation signal and part of the second compensation signal, and the second compensation signal is the compensation signal of the corresponding pixel column in the first transition zone 110 to achieve brightness change display of each pixel column, which effectively reduces the brightness difference between the first transition zone 110 and the second transition zone 210 at a side viewing angle, so that the splicing watermark is invisible at a side viewing angle.

[0349] An exemplary embodiment of the present disclosure partially or completely adopts the compensation signal of the corresponding pixel column in the first transition zone 110 in each pixel column of the second transition zone 210, and adjusts the brightness of each pixel column in the second transition zone 210 by changing the compensation signal, so that the brightness of each pixel column in the second transition zone 210 gradually approaches the brightness of the corresponding pixel column in the first transition zone 110 under a side viewing angle.

[0350] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original compensation signals provided by the compensation signal lines in each pixel column gradually decreases, the number of second compensation signals provided by the compensation signal lines in each pixel column gradually increases, and the brightness change of each pixel column in the second transition zone 210 gradually increases, so that the second transition zone 210 forms a second brightness transition zone with a gradual brightness transition, which has little effect on the display effects in the two directions of the front viewing angle and the side viewing angle.

[0351] In an exemplary embodiment, since the compensation signal line of the pixel column (nth pixel column) farthest from the stitching line 300 in the second transition zone 210 provides all the original compensation signals, the brightness of the pixel column does not change, and the compensation signal lines of all the pixel columns in the second normal zone 220 provide all the original compensation signals, the brightness of the second normal zone 220 does not change, and therefore, no dividing line is formed at the junction of the second transition zone 210 and the second normal zone 220 in both the front viewing angle and the side viewing angle.

[0352] In an exemplary embodiment, since the compensation signal lines of the pixel columns (the first pixel column) closest to the stitching line 300 in the first transition zone 110 and the second transition zone 210 are all the second compensation signals (the compensation signal of the first pixel column in the first transition zone 110), the compensation signals of the two are the same, and thus the brightness compensation degrees of the pixel columns at the junction of the first transition zone 110 and the second transition zone 210 are the same, which effectively reduces the brightness difference between the first transition zone 110 and the second transition zone 210 at a side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at a side viewing angle, and the stitching watermark at a side viewing angle is invisible.

[0353] In an exemplary embodiment, the first pixel column provides 100% of the second compensation signal and the nth pixel column provides 100% of the original compensation signal in this embodiment is only an example, and the first pixel column and the nth pixel column may include part of the original compensation signal and part of the second compensation signal. For example, the first pixel column may include 1% of the original data signal and 99% of the second compensation signal, and the nth pixel column may include 99% of the original data signal and 1% of the second compensation signal, which is not limited in the present disclosure.

[0354] Fig.23 FIG. 1 is a schematic diagram of another method for driving a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the method for driving a display substrate according to the present embodiment may include:

[0355] F1. Extract compensation signals of n pixel columns in the first transition area 110 and the second transition area 210 respectively, and process the compensation signals of n pixel columns in the first transition area 110 and the second transition area 210 so that the compensation signals of each pixel column in the first transition area 110 and the second transition area 210 include an original signal group and a processed signal group. In the first transition area 110, the original signal group of the i-th pixel column includes M1 original compensation signals, and the processed signal group of the i-th pixel column includes M2 first compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)], the original compensation signal of the i-th pixel column can be the compensation signal of the i-th pixel column in the first transition area 110, and the first compensation signal of the i-th pixel column can be the compensation signal of the j-th pixel column in the second transition area 210. In the second transition region 210, the original signal group of the j-th pixel column includes M3 original compensation signals, the processed signal group of the j-th pixel column includes M4 second compensation signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)], the original compensation signal of the j-th pixel column can be the compensation signal of the j-th pixel column in the second transition region 210, and the second compensation signal of the j-th pixel column can be the compensation signal of the i-th pixel column in the first transition region 110. i=1, 2, ..., n, j=1, 2, ..., n.

[0356] F2. In each pixel column of the first normal area 120 and the second normal area 220, the M original compensation signals are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line. In each pixel column of the first transition area 110, the M1 original compensation signals in the original signal group and the M2 first compensation signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line. In each pixel column of the second transition area 210, the M3 original compensation signals in the original signal group and the M4 second compensation signals in the processed signal group are respectively provided to the M pixel driving circuits in the pixel column through the compensation signal line.

[0357] An exemplary embodiment of the present disclosure provides a driving method for gradually changing the brightness of a first transition region and a second transition region to alleviate the brightness difference between two display substrates at a side viewing angle and effectively avoid splicing watermarks.

[0358] like Fig.23As shown, in an exemplary embodiment, for the first normal area 120 and the second normal area 220, the compensation signal lines in all pixel columns provide original compensation signals to achieve normal brightness display of each pixel column, and for the first transition area 110, the compensation signal lines in all pixel columns provide part of the original compensation signal and part of the first compensation signal, and for the second transition area 210, the compensation signal lines in all pixel columns provide part of the original compensation signal and part of the second compensation signal, the first compensation signal can be the compensation signal of the corresponding pixel column in the second transition area 210, and the second compensation signal can be the compensation signal of the corresponding pixel column in the first transition area 110, to achieve brightness change display of each pixel column, effectively reducing the brightness difference between the first transition area 110 and the second transition area 210 at a side viewing angle, so that the splicing watermark is invisible at a side viewing angle.

[0359] In an exemplary embodiment of the present disclosure, each pixel column in the first transition zone 110 partially or fully adopts the compensation signal of the corresponding pixel column in the second transition zone 210, and each pixel column in the second transition zone 210 partially or fully adopts the compensation signal of the corresponding pixel column in the first transition zone 110, and the brightness of each pixel column in the first transition zone 110 and the second transition zone 210 is adjusted by changing the compensation signal, so that the brightness of each pixel column in the first transition zone 110 gradually approaches the brightness of each pixel column in the second transition zone 210 at a side viewing angle.

[0360] In an exemplary embodiment, along the direction approaching the stitching line 300, the number of original compensation signals provided by the compensation signal lines in each pixel column gradually decreases, and the number of first compensation signals or second compensation signals provided by the compensation signal lines in each pixel column gradually increases, and the brightness change of each pixel column in the first transition zone 110 and the second transition zone 210 gradually increases, so that the first transition zone 110 and the second transition zone 210 respectively form a first brightness transition zone and a second brightness transition zone with gradual brightness transition, which has little effect on the display effects in the two directions of front viewing angle and side viewing angle.

[0361] In an exemplary embodiment, since the compensation signal line of the pixel column farthest from the stitching line 300 in the first transition zone 110 and the second transition zone 210 provides all the original compensation signals, the brightness of the pixel column does not change, and the compensation signal lines of all the pixel columns in the first normal zone 120 and the second normal zone 220 provide all the original compensation signals, the brightness of the first normal zone 120 and the second normal zone 220 does not change, so in both the front viewing angle and the side viewing angle, no dividing line is formed at the junction of the first transition zone 110 and the first normal zone 120, and at the junction of the second transition zone 210 and the second normal zone 220.

[0362] In an exemplary embodiment, since the compensation signal lines of the pixel columns closest to the stitching line 300 in the first transition zone 110 and the second transition zone 210 are all the first compensation signal (the compensation signal of the first pixel column in the second transition zone 210) and the second compensation signal (the compensation signal of the first pixel column in the first transition zone 110), the compensation signals of the two are interchanged, and thus the brightness compensation degrees of the pixel columns at the junction of the first transition zone 110 and the second transition zone 210 are interchanged, which effectively reduces the brightness difference between the first transition zone 110 and the second transition zone 210 at a side viewing angle, so that no obvious dividing line is formed between the first transition zone 110 and the second transition zone 210 at a side viewing angle, and the stitching watermark at a side viewing angle is invisible.

[0363] In an exemplary embodiment, the first compensation signal of the first transition region 110 and the second compensation signal of the second transition region 210 may be interchanged in the same row, or may be interchanged in the same column, or may be randomly allocated, which is not limited in the present disclosure.

[0364] In an exemplary embodiment, the first pixel column of the first transition region 110 of the present embodiment provides 100% of the first compensation signal, and the first pixel column of the second transition region 210 provides 100% of the second compensation signal is only an example, and the present disclosure is not limited thereto. For example, the first pixel column of the first transition region 110 may include 1% of the original data signal and 99% of the first compensation signal, the nth pixel column of the first transition region 110 may include 99% of the original data signal and 1% of the first compensation signal, the first pixel column of the second transition region 210 may include 1% of the original data signal and 99% of the second compensation signal, and the nth pixel column of the second transition region 210 may include 99% of the original data signal and 1% of the second compensation signal.

[0365] In an exemplary embodiment, the calculation expressions of M1, M2, M3 and M4 in the aforementioned embodiments are only examples, and other expressions that can realize the incremental processing of signals may also be used. The calculated values ​​of the calculation expressions may be rounded, which is not limited in the present disclosure.

[0366] The present disclosure provides a driving method for a display substrate, which effectively reduces the brightness difference between the first transition zone and the second transition zone at a side viewing angle due to alignment differences by changing the brightness of the first transition zone and / or the second transition zone, and gradually transitions the brightness of each pixel column along a direction close to a stitching line, thereby effectively alleviating the brightness difference between the two display substrates at a side viewing angle due to alignment differences, and effectively avoiding stitching watermarks.

[0367] The exemplary embodiment of the present disclosure further provides a driving device, including a processor and a memory storing a computer program executable on the processor, wherein the processor implements the steps of the aforementioned display substrate driving method when executing the program.

[0368] The exemplary embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing program instructions, which can implement the aforementioned method for driving a display substrate when the program instructions are executed.

[0369] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present invention. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: The invention comprises a plurality of sub-pixels, at least one of which comprises a pixel driving circuit and a light-emitting device, wherein the light-emitting device comprises at least a first electrode and a pixel definition layer, wherein the first electrode is connected to the pixel driving circuit, and a pixel opening exposing the first electrode is provided on the pixel definition layer; The pixel opening at least comprises a first opening edge located on one side of the pixel opening in a first direction and a second opening edge located on the opposite side of the first direction of the pixel opening, the pixel driving circuit is connected to at least one signal line extending along a second direction, and the first direction intersects the second direction; In at least one sub-pixel, an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the signal line on the display substrate plane.

2. The display substrate according to claim 1, characterized in that: In at least one sub-pixel, the signal line includes at least a first power line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane.

3. The display substrate according to claim 1, characterized in that: In at least one sub-pixel, the signal line includes at least a data signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane.

4. The display substrate according to claim 1, characterized in that: In at least one sub-pixel, the signal line includes at least a compensation signal line, and an orthographic projection of at least one of the first opening edge and the second opening edge on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line on the display substrate plane.

5. The display substrate according to any one of claims 1 to 4, characterized in that: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along the first direction, and the signal lines include at least a first power line, a data signal line and a compensation signal line; in the first sub-pixel, an orthographic projection of an edge of the first opening on a display substrate plane at least partially overlaps with an orthographic projection of the data signal line on the display substrate plane, and an orthographic projection of an edge of the second opening on a display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane; In the second sub-pixel, the orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane, and the orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane; In the third sub-pixel, the orthographic projection of the first opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the second opening edge on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane; In the fourth subpixel, the orthographic projection of the first opening edge on the substrate at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the second opening edge on the substrate at least partially overlaps with the orthographic projection of the data signal line on the display substrate plane.

6. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 1 to 5.

7. A method for driving a display substrate according to any one of claims 1 to 5, characterized in that: The display substrate at least comprises a first sub-substrate and a second sub-substrate which are spliced ​​together, wherein the first sub-substrate and the second sub-substrate form a splicing line at a splicing position; the first sub-substrate at least comprises a first transition area close to the splicing line and a first normal area located on a side of the first transition area away from the splicing line, and the second sub-substrate at least comprises a second transition area close to the splicing line and a second normal area located on a side of the second transition area away from the splicing line; the first transition area and the second transition area each comprise at least one pixel column, each pixel column comprises M sub-pixels, and the sub-pixels at least comprise a pixel driving circuit, wherein the pixel driving circuit is connected to a driving signal line, and M is a positive integer greater than 1; the driving method comprises: Processing at least one original driving signal of at least one pixel column in the first transition region and the second transition region into at least one processed driving signal; At least one processed driving signal and the remaining original driving signals are provided to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column.

8. The driving method according to claim 7, characterized in that: In at least one of the first transition zone and the second transition zone, along a direction approaching the stitching line, the number of the original driving signals in the pixel column gradually decreases, and the number of the processed driving signals in the pixel column gradually increases.

9. The driving method according to claim 7, characterized in that: In at least one of the first transition region and the second transition region, the number of the original driving signals in the pixel column farthest from the stitching line is M.

10. The driving method according to claim 7, characterized in that: In at least one of the first transition region and the second transition region, the number of processed driving signals in the pixel column closest to the stitching line is M.

11. The driving method according to claim 7, characterized in that: In at least one of the first transition zone and the second transition zone, the number of processed driving signals in the pixel column closest to the stitching line is k*M, and the number of original driving signals is (1-k)*M, where k=0.2 to 0.

8.

12. The driving method according to claim 11, characterized in that: k＝0.5。 13. The driving method according to any one of claims 7 to 12, characterized in that: The drive signal includes a data signal line, the drive signal includes a data signal, and the processed drive signal includes a first data signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: Processing the data signal of each pixel column in the first transition area so that the data signal of the i-th pixel column includes M1 original data signals and M2 first data signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)]; n is the number of pixel columns in the first transition area, i=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the first data signal is V-ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column of the first normal zone, the second transition zone and the second normal zone, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column of the first transition zone, M1 original data signals and M2 first data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

14. The driving method according to any one of claims 7 to 12, characterized in that: The drive signal includes a data signal line, the drive signal includes a data signal, and the processed drive signal includes a second data signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: Processing the data signal of each pixel column in the second transition area so that the data signal of the j-th pixel column includes M3 original data signals and M4 second data signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)]; n is the number of pixel columns in the second transition area, j=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the second data signal is V+ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column of the first transition zone, the first normal zone and the second normal zone, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column of the second transition zone, M3 original data signals and M4 second data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

15. The driving method according to any one of claims 7 to 12, characterized in that: The drive signal includes a data signal line, the drive signal includes a data signal, and the processed drive signal includes a first data signal and a second data signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: Processing the data signals of each pixel column in the first transition area and the second transition area so that the data signal of the i-th pixel column in the first transition area includes M1 original data signals and M2 first data signals, and the data signal of the j-th pixel column in the second transition area includes M3 original data signals and M4 second data signals, M1=0.5*M[(i-1) / (n-1)], M2=0.5*M[1-(i-1) / (n-1)], M3=0.5*M[(j-1) / (n-1)], M4=0.5*M[1-(j-1) / (n-1)]; n is the number of pixel columns in the first transition area and the second transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of pixel columns gradually increases in a direction away from the splicing line; the first data signal is V-ΔV, the second data signal is V+ΔV, V is the original data signal, and ΔV is an additional signal used to change the original data signal; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column in the first normal area and the second normal area, M original data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column in the first transition area, M1 original data signals and M2 first data signals are provided to the M pixel driving circuits in the pixel column through data signal lines; in each pixel column in the second transition area, M3 original data signals and M4 second data signals are provided to the M pixel driving circuits in the pixel column through data signal lines.

16. The driving method according to any one of claims 7 to 12, characterized in that: The drive signal includes a compensation signal line, the drive signal includes a compensation signal, and the processed drive signal includes a first compensation signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: Extracting the compensation signal of each pixel column in the second transition area, processing the compensation signal of each pixel column in the first transition area, so that the compensation signal of the i-th pixel column in the first transition area includes M1 original compensation signals and M2 first compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)]; n is the number of pixel columns in the first transition area; the original compensation signal is the compensation signal of the i-th pixel column in the first transition area, the first compensation signal is the compensation signal of the j-th pixel column in the second transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of the pixel columns gradually increases along the direction away from the splicing line; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column of the first normal zone, the second transition zone and the second normal zone, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column of the first transition zone, M1 original compensation signals and M2 first compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

17. The driving method according to any one of claims 7 to 12, characterized in that: The drive signal includes a compensation signal line, the drive signal includes a compensation signal, and the processed drive signal includes a second compensation signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: Extract the compensation signal of each pixel column in the first transition area, and process the compensation signal of each pixel column in the second transition area, so that the compensation signal of the j-th pixel column in the second transition area includes M3 original compensation signals and M4 second compensation signals, M3=M[(j-1) / (n-1)], M4=M[1-(j-1) / (n-1)]; n is the number of pixel columns in the second transition area; the original compensation signal is the compensation signal of the j-th pixel column in the second transition area, and the second compensation signal is the compensation signal of the i-th pixel column in the first transition area, i=1, 2, ..., n, j=1, 2, ..., n, and the number of the pixel columns gradually increases along the direction away from the splicing line; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column of the first transition zone, the first normal zone and the second normal zone, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column of the second transition zone, M3 original compensation signals and M4 second compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

18. The driving method according to any one of claims 7 to 12, characterized in that: The driving signal includes a compensation signal line, the driving signal includes a compensation signal, and the processed driving signal includes a first compensation signal and a second compensation signal; Processing at least one original driving signal of at least one pixel column in the first transition area and the second transition area into at least one processed driving signal includes: The compensation signal of each pixel column in the first transition area and the second transition area is extracted, and the compensation signal of each pixel column in the first transition area and the second transition area is processed so that the compensation signal of the i-th pixel column in the first transition area includes M1 original compensation signals and M2 first compensation signals, and the compensation signal of the j-th pixel column in the second transition area includes M3 original compensation signals and M4 second compensation signals, M1=M[(i-1) / (n-1)], M2=M[1-(i-1) / (n-1)], M3=M[(j-1) / (n-1)], M4=M[1-( j-1) / (n-1)]; n is the number of pixel columns in the first transition zone and the second transition zone, i=1, 2, ..., n, j=1, 2, ..., n, and the number of pixel columns gradually increases along the direction away from the stitching line; the original compensation signal of the first transition zone is the compensation signal of the i-th pixel column in the first transition zone, and the first compensation signal is the compensation signal of the j-th pixel column in the second transition zone; the original compensation signal of the second transition zone is the compensation signal of the j-th pixel column in the second transition zone, and the second compensation signal is the compensation signal of the i-th pixel column in the first transition zone; Providing at least one processed driving signal and the remaining original driving signals to M pixel driving circuits in the pixel column through the driving signal lines of the pixel column, comprising: In each pixel column in the first normal area and the second normal area, M original compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column in the first transition area, M1 original compensation signals and M2 first compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line; in each pixel column in the second transition area, M3 original compensation signals and M4 second compensation signals are provided to the M pixel driving circuits in the pixel column through the compensation signal line.

19. A driving device comprising a processor and a memory storing a computer program executable on the processor, wherein: When the processor executes the program, the steps of the method for driving the display substrate according to any one of claims 7 to 18 are implemented.

20. A non-transitory computer-readable storage medium storing program instructions, which can implement the display substrate driving method according to any one of claims 7 to 18 when the program instructions are executed.

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