Display substrate and display device

Abstract

A display substrate and a display device wherein the display substrate comprises: a base (10) and a plurality of sub-pixels disposed on the base (10), at least one sub-pixel comprising: a pixel circuit comprising: a third transistor (T3) and a plurality of transistors connected to the third transistor (T3); the active patterns of at least two transistors connected to the gate electrode of the third transistor (T3) are first active layers (A1), and the active patterns of at least two transistors connected to any one of the first pole and the second pole of the third transistor (T3) and the active layer of the third transistor (T3) are second active layers (A2); the first active layer (A1) and the second active layer (A2) are arranged along a first direction (D1) and at least partially extend along a second direction (D2), and the length of the first active layer (A1) along the second direction (D2) is greater than that of the second active layer (A2) along the second direction (D2).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel comprising: a pixel circuit, the pixel circuit comprising: a third transistor and a plurality of transistors connected to the third transistor, the transistor comprising an active pattern, the active patterns of at least two transistors connected to a gate electrode of the third transistor forming an integral structure and constituting a first active layer, the active patterns of at least two transistors connected to either a first electrode or a second electrode of the third transistor and the active pattern of the third transistor forming an integral structure and constituting a second active layer;

[0006] The first active layer and the second active layer are arranged along a first direction and at least partially extend along a second direction, and the first direction intersects with the second direction;

[0007] A length of the first active layer along the second direction is greater than a length of the second active layer along the second direction.

[0008] In an exemplary embodiment, the plurality of transistors connected to the third transistor include: a first transistor, a second transistor, a fourth transistor, and a fifth transistor, wherein the first to fifth transistors are N-type transistors;

[0009] The second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the second electrode of the second transistor and the second electrode of the fourth transistor are electrically connected to the gate electrode of the third transistor respectively, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor;

[0010] The active pattern includes a channel region and a conductive region, and the conductive region of any active pattern is located on both sides of the channel region; wherein the active pattern of the second transistor and the active pattern of the fourth transistor are the first active layer, and the active pattern of the first transistor, the active pattern of the third transistor and the active pattern of the fifth transistor are the second active layer.

[0011] In an exemplary embodiment, the active pattern of the first transistor and the active pattern of the fifth transistor are respectively located on both sides of the active pattern of the third transistor, the active pattern of the second transistor includes: a first conductive region and a second conductive region; the active pattern of the fourth transistor includes: a third conductive region and a fourth conductive region; the first conductive region and the third conductive region extend along the second direction, the second conductive region and the fourth conductive region extend along the first direction; the third conductive region is connected to the first conductive region.

[0012] In an exemplary embodiment, the second conductive region is located on a side of the first conductive region close to the second active layer, and is located on a side of a center line of the active layer together with at least a portion of the active pattern of the first transistor, where the center line of the active layer is a center line of the second active layer extending along the first direction;

[0013] The fourth conductive region is located on a side of the third conductive region close to the second active layer, and is located on the other side of a center line of the active layer together with at least a portion of the active pattern of the fifth transistor.

[0014] In an exemplary embodiment, the further comprising: a first signal line disposed on the substrate, at least a portion of the first signal line extending along a first direction, and a gate electrode of at least one transistor being disposed in a different layer from the first signal line;

[0015] The resistivity of the film layer where the first signal line is located is smaller than the resistivity of the film layer where the gate electrode of the at least one transistor is located.

[0016] In an exemplary embodiment, the gate electrode of the first transistor to the gate electrode of the fifth transistor are spaced apart from each other;

[0017] A length of the gate electrode of the third transistor along the second direction is greater than a length of the gate electrode of any one of the first transistor, the second transistor, the fourth transistor, and the fifth transistor along the second direction.

[0018] In an exemplary embodiment, the pixel circuit further includes: a capacitor, the capacitor including: a first plate and a second plate; the first plate of the capacitor is located on a side of the second plate of the capacitor close to the substrate;

[0019] An orthographic projection of the first plate of the capacitor on the substrate at least partially overlaps with an orthographic projection of the first conductive region, the active pattern of the third transistor, and the third conductive region on the substrate.

[0020] In an exemplary embodiment, the first signal line includes: a third scan signal line, an initial signal line, a first power line, and a light emitting signal line; the first transistor is connected to the third scan signal line and the initial signal line, respectively, and the fifth transistor is connected to the first power line and the light emitting signal line, respectively;

[0021] The orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps with the orthographic projections of the third scanning signal line, the initial signal line, the first power line, the light-emitting signal line, the first plate of the capacitor, the first conductive area and the third conductive area on the substrate.

[0022] In an exemplary embodiment, along the second direction, a distance between an orthographic projection of the gate electrode of the second transistor on the substrate and an orthographic projection of the second plate of the capacitor on the substrate is smaller than a distance between an orthographic projection of the gate electrode of the second transistor on the substrate and an orthographic projection of the gate electrode of the first transistor on the substrate;

[0023] The distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate.

[0024] In an exemplary embodiment, the second plate of the capacitor is provided with a groove, and the groove exposes at least a portion of the first plate of the capacitor, the first conductive region, and the third conductive region.

[0025] In an exemplary embodiment, within the same sub-pixel, an opening direction of the groove is located on a side away from the second active layer.

[0026] In an exemplary embodiment, the second electrode plate of the capacitor includes: a capacitor main body, a first capacitor connecting portion, and a second capacitor connecting portion, wherein the first capacitor connecting portion and the second capacitor connecting portion are respectively located on both sides of the capacitor main body, and the groove is provided on one side of the capacitor main body;

[0027] The capacitor main body extends along a first direction, the first capacitor connecting portion at least partially extends along a second direction, and the second capacitor connecting portion extends along the second direction;

[0028] The average length of the capacitor main portion along the first direction is greater than the average length of the first capacitor connecting portion along the first direction, and the average length of the first capacitor connecting portion along the first direction is greater than the average length of the second capacitor connecting portion along the first direction.

[0029] In an exemplary embodiment, an orthographic projection of the capacitor body on the substrate at least partially overlaps with orthographic projections of the first plate of the capacitor, the first conductive region, and the third conductive region on the substrate;

[0030] The orthographic projections of the first capacitor connecting portion and the second capacitor connecting portion on the substrate at least partially overlap with the orthographic projections of the first conductive area and the third conductive area on the substrate, and do not overlap with the orthographic projection of the first plate of the capacitor on the substrate.

[0031] In an exemplary embodiment, the first plate of the capacitor includes: a first region and a second region; the first region is the region exposed by the groove of the second plate of the capacitor, and the second region is all regions except the first region;

[0032] The orthographic projection of the second electrode plate of the capacitor on the substrate covers the orthographic projection of the second region of the first electrode plate of the capacitor on the substrate.

[0033] In an exemplary embodiment, the first signal line further includes: a reference signal line, a first scan signal line, and a second scan signal line, the second transistor is connected to the second scan signal line and the reference signal line, respectively, and the fourth transistor is connected to the first scan signal line;

[0034] The reference signal line, the second scanning signal line, the initial signal line, the third scanning signal line, the light emitting signal line, the first power line and the first scanning signal line are sequentially arranged along a first direction.

[0035] In an exemplary embodiment, the present invention further includes: a second signal line disposed on the substrate, the second signal line extending along the second direction, the second signal line including: a data signal line;

[0036] The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate.

[0037] In an exemplary embodiment, the data signal line includes: a data signal main line and a plurality of data signal connection lines, the data signal main line extending along the second direction, and the data signal connection lines extending along the first direction;

[0038] The orthographic projection of the data signal main line on the substrate at least partially overlaps with the orthographic projection of the first conductive area, the third conductive area and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line on the substrate at least partially overlaps with the orthographic projection of the fourth conductive area on the substrate.

[0039] In an exemplary embodiment, the invention further comprises: a driving structure layer provided on the substrate; the driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate;

[0040] The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located in at least one sub-pixel;

[0041] The first conductive layer at least includes: a gate electrode of a first transistor, a gate electrode of a second transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, and a first plate of a capacitor located in at least one sub-pixel;

[0042] The second conductive layer includes at least: a second plate of a capacitor located in at least one sub-pixel;

[0043] The third conductive layer at least includes: a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, a reference signal line, a first power line, an initial signal line, and the second electrode of a first transistor, the second electrode of a second transistor, the second electrode of a third transistor, and the first electrode and the second electrode of a fourth transistor located in at least one sub-pixel;

[0044] The fourth conductive layer at least includes: a data signal line.

[0045] In an exemplary embodiment, the driving structure layer further includes: a first planar layer and a fifth insulating layer located between the third conductive layer and the fourth conductive layer;

[0046] The fifth insulating layer is located on a side of the first planar layer away from the substrate;

[0047] The thickness of the first planarizing layer is greater than the thickness of the fifth insulating layer.

[0048] In an exemplary embodiment, the thickness of the first planar layer is 1.4 micrometers to 2.3 micrometers, and the thickness of the fifth insulating layer is 50 nanoangstroms to 2500 nanoangstroms.

[0049] In an exemplary embodiment, the thickness of the third conductive layer is greater than the thickness of the first conductive layer or the second conductive layer;

[0050] The resistivity of the fourth conductive layer is lower than that of the first conductive layer.

[0051] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0052] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0053] Summary of the Figures

[0054] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0055] FIG1 is a schematic structural diagram of a display device;

[0056] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0057] FIG3 is a schematic diagram of a planar structure of another display substrate;

[0058] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit;

[0059] FIG4B is an operation timing diagram of the pixel circuit provided in FIG4A ;

[0060] FIG5 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0061] FIG6 is a cross-sectional view of a display substrate provided in an embodiment of the present disclosure;

[0062] FIG7 is a schematic diagram of a portion of the film layer of the display substrate provided in FIG5 ;

[0063] FIG8 is a second schematic diagram of a portion of the film layer of the display substrate provided in FIG5 ;

[0064] FIG9 is a third schematic diagram of a portion of the film layer of the display substrate provided in FIG5 ;

[0065] FIG10 is a fourth schematic diagram of a partial film layer of the display substrate provided in FIG5 ;

[0066] FIG11 is a schematic diagram after forming a semiconductor layer pattern;

[0067] FIG12 is a schematic diagram of a first conductive layer pattern;

[0068] FIG13 is a schematic diagram after forming a first conductive layer pattern;

[0069] FIG14 is a schematic diagram of a second conductive layer pattern;

[0070] FIG15 is a schematic diagram after forming a second conductive layer pattern;

[0071] FIG16 is a schematic diagram after forming a fourth insulating layer pattern;

[0072] FIG17 is a schematic diagram of a pattern of a third conductive layer;

[0073] FIG18 is a schematic diagram after forming a third conductive layer pattern;

[0074] FIG19 is a schematic diagram after forming a fifth insulating layer pattern;

[0075] FIG20 is a schematic diagram of a fourth conductive layer pattern;

[0076] FIG. 21 is a schematic diagram after forming a fourth conductive layer pattern.

[0077] Details

[0078] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0079] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0080] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0081] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0082] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0083] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0084] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0085] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0086] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0088] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0089] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0090] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0091] Display substrates utilize low-temperature polysilicon (LTPS) or a backplane formed by combining low-temperature polysilicon transistors with oxide transistors (LTPO). These technologies offer advantages such as high resolution, high response speed, high brightness, and a high aperture ratio, making them popular in the market. However, display products using LTPS or LTPO technologies face challenges in achieving high PPI displays due to complex pixel circuit connectivity, a large number of gate control lines, and the large number of electrodes occupied by the pixel circuits. These factors also increase the risk of leakage current.

[0092] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit. The pixel circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0093] Figure 2 is a schematic diagram of a planar structure of a display substrate, and Figure 3 is a schematic diagram of a planar structure of another display substrate. As shown in Figures 2 and 3, the display substrate may include a plurality of pixel units P arranged in a matrix. The plurality of pixel units P include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and at least one third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel circuit and a light-emitting device. The pixel circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the subpixel in which they are located.

[0094] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0095] In an exemplary embodiment, as shown in FIG2 , a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure. FIG2 illustrates the arrangement in a horizontal parallel pattern as an example.

[0096] In an exemplary embodiment, as shown in FIG3 , a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure. FIG3 illustrates an example of a square arrangement of four sub-pixels.

[0097] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a stacked electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0098] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0099] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit. In an exemplary embodiment, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG4A , the pixel circuit may include five transistors (first transistor T1 to fifth transistor T5) and one capacitor C. Capacitor C may include a first plate C1 and a second plate C2.

[0100] In an exemplary embodiment, as shown in FIG4A , a gate electrode of the first transistor T1 is electrically connected to the third scan signal line Gate3, a first electrode of the first transistor T1 is electrically connected to the initial signal line INIT, and a second electrode of the first transistor T1 is electrically connected to the second node N2; a gate electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a gate electrode of the third transistor T3 is electrically connected to the first node N1, and a first electrode of the third transistor T3 is electrically connected to the second node N2 , the second electrode of the third transistor T3 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1; the gate electrode of the fifth transistor T5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the second node N2.

[0101] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the second node N2 and the second power line VSS, wherein a first electrode of the light emitting device L is electrically connected to the second node N2 and a second electrode of the light emitting device L is electrically connected to the second power line VSS.

[0102] In an exemplary embodiment, the light-emitting device includes a current-driven device, and a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED), can be used. A typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0103] In an exemplary embodiment, the first transistor T1 can be called an anode reset transistor. When the signal of the third scan signal line Gate3 is an active level signal, the initial signal of the initial signal line INIT is written into the first electrode of the light emitting device L to initialize the first electrode of the light emitting device L.

[0104] In an exemplary embodiment, the second transistor T2 may be referred to as a node reset transistor, and when the signal of the second scan signal line Gate2 is an active level signal, the signal of the reference signal line REF is written into the first node N1 to initialize the signal of the first node N1.

[0105] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between a gate electrode and a second electrode thereof.

[0106] In an exemplary embodiment, the fourth transistor T4 may be referred to as a write transistor, and writes an initial signal of the data signal line Data into the second node N2 when the signal of the first scan signal line Gate1 is an active level signal.

[0107] In an exemplary embodiment, the fifth transistor T5 may be referred to as a light emitting transistor. When the signal of the light emitting signal line EM is an active level signal, the fifth transistor T5 forms a driving current path between the first power line VDD and the second power line VSS to enable the light emitting device to emit light.

[0108] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0109] In an exemplary embodiment, the first transistor T1 to the fifth transistor T5 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0110] In example embodiments, the transistors of the first to fifth transistors T1 to T5 may be N-type transistors.

[0111] In an exemplary embodiment, the first power line VDD continuously provides a high level signal and is a constant voltage signal, the second power line VSS continuously provides a low level signal, and the initial signal line INIT provides a constant voltage signal.

[0112] In an exemplary embodiment, a voltage value of a signal of the initial signal line INIT may be lower than a voltage value of a signal of the second power line VSS, and erroneous light emission of the light emitting device may be avoided.

[0113] FIG4B is an operating timing diagram of the pixel circuit provided in FIG4A . The following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel circuit illustrated in FIG4A during the display phase. FIG4B is illustrated using an example in which the first transistor T1 to the fifth transistor T5 are N-type transistors. The pixel circuit in FIG4B includes the first transistor T1 to the fifth transistor T5, a capacitor C, and eight signal lines (a data signal line Data, a first scan signal line Gate1, a second scan signal line Gate2, a third scan signal line Gate3, an initial signal line INIT, a reference signal line REF, an emission signal line EM, and a first power line VDD).

[0114] 4A and 4B , the operation process of the pixel circuit may include:

[0115] The first phase P1 is called the initialization phase. The signals of the second scanning signal line Gate2 and the third scanning signal line Gate3 are high-level signals, and the signals of the first scanning signal line Gate1 and the light-emitting signal line EM are low-level signals. The signal of the second scanning signal line Gate2 is a high-level signal, the second transistor T2 is turned on, and the signal of the reference signal line REF is written into the first node N1 through the turned-on second transistor T2 to initialize the signal of the first node N1. At this time, the voltage value V1 of the signal at the first node N1 is V ref , V ref The voltage value of the signal of the reference signal line REF. The signal of the third scanning signal line Gate3 is a high-level signal, the first transistor T1 is turned on, and the signal of the initial signal line INIT is written into the second node N2 to initialize (reset) the first electrode of the light-emitting device L, clearing the pre-stored voltage inside it, and completing the initialization. At this time, the voltage value of the signal of the second node N2 is V2=V init , V init is the voltage value of the signal of the initial signal line INIT. In this stage, since the voltage value of the signal of the initial signal line INIT may be lower than the voltage value of the signal of the second power line VSS, the light emitting device L does not emit light.

[0116] The second stage P2 is called the threshold compensation stage. The signals of the second scanning signal line Gate2 and the luminous signal line EM are high-level signals, and the signals of the first scanning signal line Gate1 and the third scanning signal line Gate3 are low-level signals. The signal of the second scanning signal line Gate2 is a high-level signal, the second transistor T2 is turned on, and the signal of the reference signal line REF is continuously written into the first node N1 through the turned-on second transistor T2. At this time, the voltage value V1 of the signal at the first node N1 is V ref The signal of the light emitting signal line EM is a high level signal, the fifth transistor T5 is turned on, and the signal of the first power line VDD is written into the second node N2 through the turned-on fifth transistor T5, the third node N3 and the turned-on third transistor T3 until the voltage V2 of the signal at the second node N2 is equal to V ref -V th , V th is the threshold voltage of the third transistor T3. At this time, the voltage value of the signal at the third node N3 is V3=V vdd , V vdd The voltage value of the signal of the first power line VDD is stored in the capacitor C, and the voltage difference V between the signal of the first node N1 and the second node N2 is stored in the capacitor C. th In this stage, the light emitting device L does not emit light.

[0117] The third phase P3 is called the data writing phase. The signal of the first scanning signal line Gate1 is a high-level signal, the signals of the second scanning signal line Gate2, the third scanning signal line Gate3 and the light-emitting signal line EM are low-level signals, and the data signal line Data outputs a data signal. The signal of the first scanning signal line Gate1 is a high-level signal, the fourth transistor T4 is turned on, and the data signal of the data signal line Data is written into the first node N1 through the turned-on fourth transistor T4. At this time, the voltage value V1 of the signal at the first node N1 is V data , V data The voltage value of the data signal is the voltage value of the first node N1. The voltage value of the signal at the first node N1 jumps compared with the voltage value at the previous stage. Therefore, under the action of the capacitor C, the signal at the second node N2 also jumps. At this time, the voltage value of the signal at the second node N2 is V2=V ref -V th +α(V data -V ref ). In this stage, the light emitting device L does not emit light.

[0118] In the fourth phase P4, also known as the light-emitting phase, the signal on the light-emitting signal line EM is a high-level signal, while the signals on the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are low-level signals. The signal on the light-emitting signal line EM is a high-level signal, the fifth transistor T5 is turned on, and the signal on the first power line VDD provides a driving current to the first electrode of the light-emitting device L via the turned-on fifth transistor T5, the third node N3, and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0119] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode (also the first node N1) and the second electrode (also the second node N2). Since the voltage value of the signal at the first node N1 is V1=V data , the voltage value of the signal at the second node N2 is V2=V ref -V th +α(V data -V ref ), so the driving current of the third transistor T3 is: I=K*(V gs -Vth) 2 =K*[(V data -V ref +V th -α(V data -V ref ))-Vth] 2 =K*[(1-α) (V data -V ref )] 2

[0120] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, V gs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0121] In an exemplary embodiment, the signal of the luminescence signal line EM can be a high-level signal or a low-level signal in the third phase. FIG4B illustrates the case where the signal of the luminescence signal line EM is a low-level signal in the third phase. When the data signal line is used by a single pixel circuit, the signal of the luminescence signal line EM can be a high-level signal or a low-level signal in the third phase. When the data signal line is shared by adjacent pixel circuits, the signal of the luminescence signal line EM can be a low-level signal in the third phase. Otherwise, uneven display may occur between different pixel circuits.

[0122] In an exemplary embodiment, the signal on the light-emitting signal line EM can be a continuously high-level signal or a periodic pulse signal during the fourth phase P4. When the signal on the light-emitting signal line EM is continuously high-level during the fourth phase P4, the light-emitting device continuously emits light. When the signal on the light-emitting signal line EM is a periodic pulse signal during the fourth phase P4, it can be used to pulse-width modulate the light. That is, the light-emitting device does not emit light continuously, but rather turns on and off repeatedly.

[0123] In an exemplary embodiment, the scan signal lines include a first scan signal line, a second scan signal line, and a third scan signal line.

[0124] Figure 5 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure, Figure 6 is a cross-sectional view of a display substrate provided in an embodiment of the present disclosure, Figure 7 is a schematic diagram of a portion of the membrane layers of the display substrate provided in Figure 5, Figure 8 is a schematic diagram of a portion of the membrane layers of the display substrate provided in Figure 5, and Figure 9 is a schematic diagram of a portion of the membrane layers of the display substrate provided in Figure 5. As shown in Figures 5 to 9, the display substrate provided in an embodiment of the present disclosure includes: a substrate 10 and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel including: a pixel circuit, the pixel circuit including: a third transistor T3 and a plurality of transistors connected to the third transistor T3. The transistor includes an active pattern, the active patterns of at least two transistors connected to the gate electrode of the third transistor T3 are an integrated structure and constitute a first active layer A1, the active patterns of at least two transistors connected to either the first electrode or the second electrode of the third transistor T3 and the active pattern T31 of the third transistor are an integrated structure and constitute a second active layer A2.

[0125] As shown in Figure 7 , the first active layer A1 and the second active layer A2 are arranged along a first direction D1 and extend at least partially along a second direction D2, with the first direction D1 and the second direction D2 intersecting. A length L1 of the first active layer A1 along the second direction D2 is greater than a length L2 of the second active layer A2 along the second direction D2. Figure 5 uses two pixel circuits as an example for illustration.

[0126] In an exemplary embodiment, the active layer of each sub-pixel includes a third transistor and an active pattern of a plurality of transistors connected to the third transistor.

[0127] In an exemplary embodiment, the display substrate may be an OLED display substrate or a liquid crystal display (LCD) display substrate.

[0128] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0129] In an exemplary embodiment, the display substrate includes a display area and a non-display area surrounding at least one side of the display area. A plurality of sub-pixels may be located in the display area.

[0130] In an exemplary embodiment, the shape of the display area may be a square or a rounded rectangle, or may be other shapes, which is not limited in the present disclosure.

[0131] The display substrate provided by the embodiment of the present disclosure includes: a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel includes: a pixel circuit, the pixel circuit includes: a third transistor and a plurality of transistors connected to the third transistor; the transistor includes an active pattern, the active patterns of at least two transistors connected to the gate electrode of the third transistor are an integrated structure and form a first active layer, the active patterns of at least two transistors connected to any one of the first and second electrodes of the third transistor and the active pattern of the third transistor are an integrated structure and form a second active layer; the first active layer and the second active layer are arranged along a first direction and at least partially extend along a second direction, and the first direction intersects with the second direction; the first active layer The length along the second direction is greater than the length of the second active layer along the second direction. First, the present disclosure sets the active patterns of multiple transistors as an integrated structure, so that the active layer of each sub-pixel includes only two parts, so that the transistors can be directly connected through the active layer part after conductorization, which simplifies the process, improves the layout space utilization, and is conducive to achieving high PPI. Secondly, the present disclosure sets the length of the first active layer along the second direction to be greater than the length of the second active layer along the second direction, which can lengthen the active patterns of at least two transistors connected to the gate electrode of the third transistor, reduce the leakage current between the at least two transistors connected to the gate electrode of the third transistor, and improve the reliability of the display substrate.

[0132] In an exemplary embodiment, as shown in FIG5 , the plurality of transistors connected to the third transistor T3 include: a first transistor T1, a second transistor T2, a fourth transistor T4, and a fifth transistor T5. The second electrode of the first transistor T1 is electrically connected to the second electrode of the third transistor T3, the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4 are respectively connected to the gate electrode of the third transistor T3, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.

[0133] In an exemplary embodiment, the first to fifth transistors T1 to T5 are N-type transistors.

[0134] In an exemplary embodiment, the active pattern includes a channel region and a conductive region, and the conductive regions of any active pattern are located on both sides of the channel region;

[0135] 7 , the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor are the first active layer A1 , and the active pattern T11 of the first transistor, the active layer T31 of the third transistor, and the active pattern T51 of the fifth transistor are the second active layer A2 .

[0136] In an exemplary embodiment, as shown in FIG. 7 , the active pattern T11 of the first transistor and the active pattern T51 of the fifth transistor are respectively located on both sides of the active pattern T31 of the third transistor.

[0137] In an exemplary embodiment, as shown in FIG. 7 , the active pattern T21 of the second transistor includes a first conductive region T21A and a second conductive region T21B, and the active pattern T41 of the fourth transistor includes a third conductive region T41A and a fourth conductive region T41B.

[0138] In an exemplary embodiment, as shown in FIG. 7 , the first and third conductive regions T21A and T41A extend along the second direction D2 , the second and fourth conductive regions T21B and T41B extend along the first direction D1 , and the third conductive region T41A is connected to the first conductive region T21A.

[0139] In an exemplary embodiment, as shown in FIG7 , the second conductive region T21B is located on a side of the first conductive region T21A close to the second active layer A2 and is located on one side of a center line O of the active layer together with at least a portion of the active pattern of the first transistor. The fourth conductive region T41B is located on a side of the third conductive region T41A close to the second active layer A2 and is located on the other side of a center line O of the active layer together with at least a portion of the active pattern of the fifth transistor. The center line O of the active layer is a center line of the second active layer extending along the first direction D1.

[0140] In an exemplary embodiment, as shown in FIG7 , a distance L3 between the second conductive region T21B and the active layer centerline O is greater than a distance L4 between a boundary of the active pattern T11 of the first transistor away from the active layer centerline O and the active layer centerline O. In an exemplary embodiment, as shown in FIG7 , a distance L5 between the fourth conductive region T41B and the active layer centerline O is greater than a distance L6 between a boundary of the active pattern T51 of the fifth transistor away from the active layer centerline O and the active layer centerline O.

[0141] In an exemplary embodiment, as shown in FIG7 , along the second direction D2, the distance between the second conductive region T21B and the second active layer A2 is less than or equal to the distance between the fourth conductive layer T41B and the second active layer A2. In the second direction D2, the distance between the second conductive region T21B and the second active layer A2 is equal to the difference between the distance L3 between the second conductive region T21B and the active layer centerline O and the distance L4 between the boundary of the active pattern T11 of the first transistor away from the active layer centerline O and the active layer centerline O. Along the second direction D2, the distance between the fourth conductive layer T41B and the second active layer A2 is equal to the difference between the distance L5 between the fourth conductive region T41B and the active layer centerline O and the distance L6 between the active layer centerline O.

[0142] In an exemplary embodiment, the display substrate may further include: a first signal line arranged on the substrate, at least a portion of the first signal line extending along the first direction D1, the gate electrode of at least one transistor and the first signal line are arranged in a different layer, and the resistivity of the film layer where the first signal line is located is less than the resistivity of the film layer where the gate electrode of the at least one transistor is located.

[0143] The present disclosure provides that the gate electrode of at least one transistor and the first signal line are arranged in different layers, and the resistivity of the film layer where the first signal line is located is lower than the resistivity of the film layer where the gate electrode of at least one transistor is located. Firstly, the film layer where the gate electrode of at least one transistor is located can be made of a metal material with good stability, such as molybdenum. Since molybdenum is resistant to high temperatures and will not be oxidized, even if it is over-etched during subsequent film etching, there will be no connection abnormalities. Secondly, the first signal line can be made of a low-resistance metal material that is easily oxidized and cannot withstand high temperatures. For example, it can be formed of metals such as aluminum, copper, or alloys thereof. The resistivity of the film layer where the first signal line is located is relatively low, which can reduce the impedance of the first signal line and meet the wire resistance requirements of high-PPI, large-size display products.

[0144] In an exemplary embodiment, the gate electrodes T12 of the first transistor to T52 of the fifth transistor are disposed at intervals.

[0145] In example embodiments, a length of a gate electrode of the third transistor along the second direction may be greater than a length of a gate electrode of any one of the first transistor, the second transistor, the fourth transistor, and the fifth transistor along the second direction.

[0146] In an exemplary embodiment, as shown in Figures 7 and 8 , the pixel circuit further includes a capacitor, which includes a first plate C1 and a second plate C2. The first plate C1 of the capacitor is located on a side of the second plate C2 closer to the substrate. Figure 7 only shows the first plate C1 of the capacitor.

[0147] In an exemplary embodiment, as shown in FIG7 , the first plate of the capacitor is disposed on the same layer as the active pattern of the transistor, or can be disposed on the same layer as the gate electrode of the transistor. When the first plate of the capacitor is disposed on the same layer as the gate electrode of the transistor, the first plate C1 of the capacitor can be reused as the gate electrode T32 of the third transistor. The present disclosure can increase the area of ​​the first plate of the capacitor by reusing the first plate C1 of the capacitor as the gate electrode T32 of the third transistor, thereby maximizing the area of ​​the first plate of the capacitor and facilitating high PPI. FIG5 to FIG9 illustrate the case where the first plate of the capacitor is disposed on the same layer as the gate electrode of the transistor.

[0148] In an exemplary embodiment, in conjunction with Figures 7 and 8, when the first plate of the capacitor is arranged in the same layer as the gate electrode of the transistor, the orthographic projection of the first plate C1 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first conductive region, the active pattern of the third transistor, and the third conductive region on the substrate.

[0149] In an exemplary embodiment, FIG10 is a fourth schematic diagram of a portion of the film layers of the display substrate provided in FIG5 . As shown in FIG5 and FIG10 , the first signal line may include a third scan signal line Gate3, an initial signal line INIT, a first power line VDD, and an emission signal line EM. The first transistor is connected to the third scan signal line and the initial signal line, respectively, and the fifth transistor is connected to the first power line and the emission signal line, respectively.

[0150] In an exemplary embodiment, as shown in conjunction with Figures 5, 7, 8, and 10, the orthographic projection of the second plate C2 of the capacitor on the substrate at least partially overlaps with the orthographic projections of the third scan signal line Gate3, the initial signal line INIT, the first power line VDD, the light emitting signal line EM, the first plate C1 of the capacitor, the first conductive region, and the third conductive region on the substrate. By arranging for the orthographic projection of the second plate of the capacitor on the substrate to at least partially overlap with the orthographic projections of the third scan signal line, the first power line, and the first plate of the capacitor on the substrate, the present disclosure can maximize the capacitor area and improve the reliability of the display substrate.

[0151] In an exemplary embodiment, as shown in FIG8 , along a second direction, D2, the distance between the orthogonal projection of the gate electrode of the second transistor on the substrate and the orthogonal projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthogonal projection of the gate electrode of the second transistor on the substrate and the orthogonal projection of the gate electrode of the first transistor on the substrate, and the distance between the orthogonal projection of the gate electrode of the fourth transistor on the substrate and the orthogonal projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthogonal projection of the gate electrode of the fourth transistor on the substrate and the orthogonal projection of the gate electrode of the fifth transistor on the substrate. The present disclosure increases the area of ​​the second plate of the capacitor without affecting signal transmission, thereby maximizing the area of ​​the first and second plates of the capacitor and facilitating high PPI.

[0152] In an exemplary embodiment, as shown in FIG. 8 , the second plate C2 of the capacitor is provided with a groove K, which exposes at least a portion of the first plate C1 of the capacitor, the first conductive region T21A, and the third conductive region T41A.

[0153] In an exemplary embodiment, as shown in FIG. 8 , within the same sub-pixel, the opening direction of the groove K is located on a side away from the second active layer.

[0154] In an exemplary embodiment, as shown in FIG8 , the second electrode plate C2 of the capacitor includes: a capacitor main body C21, a first capacitor connecting portion C22, and a second capacitor connecting portion C23, wherein the first capacitor connecting portion C22 and the second capacitor connecting portion C23 are respectively located on both sides of the capacitor main body C21 and are respectively connected to the capacitor main body C21, and the groove K is provided on one side of the capacitor main body C21;

[0155] In an exemplary embodiment, as shown in FIG. 8 , the capacitor main portion C21 extends along the first direction D1 , the first capacitor connecting portion C22 at least partially extends along the second direction D2 , and the second capacitor connecting portion C23 extends along the second direction D2 .

[0156] In an exemplary embodiment, as shown in FIG8 , the average length of the capacitor main portion C21 along the first direction D1 is greater than the average length of the first capacitor connecting portion C22 along the first direction D1, and the average length of the first capacitor connecting portion C22 along the first direction D1 is greater than the average length of the second capacitor connecting portion C23 along the first direction D1.

[0157] In an exemplary embodiment, as shown in FIG. 8 , an orthographic projection of the capacitor body C21 on the substrate at least partially overlaps with an orthographic projection of the capacitor first plate C1 , the first conductive region T21A, and the third conductive region T41A on the substrate.

[0158] In an exemplary embodiment, as shown in FIG8 , the orthographic projections of the first capacitor connecting portion C22 and the second capacitor connecting portion C23 on the substrate at least partially overlap with the orthographic projections of the first conductive region T21A and the third conductive region T41A on the substrate, and do not overlap with the orthographic projection of the first plate C1 of the capacitor on the substrate.

[0159] In an exemplary embodiment, as shown in FIG8 , the first plate C1 of the capacitor includes a first region R1 and a second region R2. The first region R1 is the area exposed by the groove of the second plate of the capacitor, and the second region R2 is all areas other than the first region R1. The orthographic projection of the second plate C2 of the capacitor on the substrate overlaps the orthographic projection of the second region R2 of the first plate of the capacitor on the substrate.

[0160] Since the first plate of the capacitor is in a floating state most of the time and is susceptible to interference, the present disclosure arranges the orthographic projection of the second plate C2 of the capacitor on the substrate to cover the orthographic projection of the second region R2 of the first plate of the capacitor on the substrate, so that the first plate of the capacitor can be arranged below the second plate C2 of the capacitor to the maximum extent, which can effectively shield the first plate of the capacitor from noise interference and improve the reliability of the display substrate.

[0161] 5 , the first signal line further includes a reference signal line REF, a first scan signal line Gate1 and a second scan signal line Gate2 , the second transistor is connected to the second scan signal line and the reference signal line respectively, and the fourth transistor is connected to the first scan signal line.

[0162] 5 , the reference signal line REF, the second scan signal line Gate2 , the initial signal line INIT, the third scan signal line Gate3 , the emission signal line EM, the first power line VDD and the first scan signal line Gate1 are sequentially arranged along the first direction D1 .

[0163] In an exemplary embodiment, as shown in FIG. 5 , the display substrate may further include a second signal line disposed on the base, the second signal line extending along the second direction D2 , and the second signal line including a data signal line Data.

[0164] In an exemplary embodiment, as shown in FIG5 and FIG9 , the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projections of the first conductive region T21A, the third conductive region T41A, the fourth conductive region T41B, and the second plate C2 of the capacitor on the substrate. In an exemplary embodiment, the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate, which can save space on the display substrate and achieve a high PPI.

[0165] In an exemplary embodiment, the data signal lines Data include: a data signal main line DataA and a plurality of data signal connection lines DataB. The data signal main line DataA extends along the second direction D2, and the data signal connection lines DataB extends along the first direction D1.

[0166] In an exemplary embodiment, the orthographic projection of the data signal main line DataA on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line DataB on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

[0167] In an exemplary embodiment, as shown in FIG6 , the display substrate may further include: a driving structure layer 20 disposed on the substrate 10 ; the driving structure layer 20 includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate 10 ;

[0168] The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located in at least one sub-pixel;

[0169] The first conductive layer at least includes: a gate electrode of a first transistor located in at least one sub-pixel, a gate electrode of a second transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, and a first plate of a capacitor;

[0170] The second conductive layer includes at least: a second plate of a capacitor located in at least one sub-pixel;

[0171] The third conductive layer at least includes: a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, a reference signal line, a first power line, an initial signal line, and the second electrode of a first transistor, the second electrode of a second transistor, the second electrode of a third transistor, and the first electrode and the second electrode of a fourth transistor located in at least one sub-pixel;

[0172] The fourth conductive layer at least includes: a data signal line.

[0173] In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and capacitors constituting a pixel circuit. FIG. 6 shows only one transistor 210 and one capacitor 220 as an example.

[0174] In an exemplary embodiment, the display substrate may further include a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer disposed on a side of the light emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0175] In an exemplary embodiment, the light-emitting structure layer 30 may include an anode 32, a pixel definition layer 31, an organic light-emitting layer 33 and a cathode 34. The anode 32 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 33 is connected to the anode 32, and the cathode 34 is connected to the organic light-emitting layer 33. The organic light-emitting layer 33 emits light of corresponding color under the drive of the anode 32 and the cathode 34.

[0176] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer 402 and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0177] In an exemplary embodiment, the touch structure layer of each sub-pixel may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer 44. The first touch metal layer may include multiple bridging electrodes, the second touch metal layer may include multiple first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0178] In an exemplary embodiment, the first and second conductive layers can be made of a relatively stable metal material, such as molybdenum. Because molybdenum is resistant to high temperatures and does not oxidize, even if the first and second conductive layers are over-etched during subsequent film etching, no connection abnormalities will occur.

[0179] In example embodiments, the third conductive layer may have a resistivity lower than that of the first conductive layer.

[0180] In an exemplary embodiment, the resistivity of the fourth conductive layer is less than that of the first conductive layer. For example, it can be formed of a material such as aluminum, copper, or an alloy thereof. The resistivity of the fourth conductive layer is relatively small, which can reduce the impedance of the second signal line and meet the wire resistance requirements of high PPI and large-size display products.

[0181] In example embodiments, the thickness of the third conductive layer may be greater than the thickness of the first conductive layer or the second conductive layer.

[0182] In an exemplary embodiment, the thickness of the third conductive layer may be greater than 500 nanometers. For example, the thickness of the third conductive layer may be 500 nanometers, or may be 650 nanometers.

[0183] In an exemplary embodiment, the thicknesses of the third conductive layer and the fourth conductive layer may be the same or different, which is not limited in the present disclosure.

[0184] In an exemplary embodiment, as shown in FIG6 , the driving structure layer may further include: a first insulating layer 21 disposed between the substrate 10 and the semiconductor layer, a second insulating layer 22 disposed between the semiconductor layer and the first conductive layer, a third insulating layer 23 disposed between the first conductive layer and the second conductive layer, a fourth insulating layer 24 disposed between the second conductive layer and the third conductive layer, a first flat layer 25 and a fifth insulating layer 26 disposed between the third conductive layer and the fourth conductive layer, and a second flat layer 27 disposed on a side of the fourth conductive layer away from the substrate.

[0185] In an exemplary embodiment, the fifth insulating layer 26 is located on the side of the first flat layer 25 away from the substrate 10. The fifth insulating layer is located on the side of the first flat layer away from the substrate, which not only avoids damaging the first flat layer when the fourth conductive layer is subsequently formed, but also does not contaminate the deposition and etching equipment of the fourth conductive layer.

[0186] In an exemplary embodiment, the thickness of the first planar layer 25 is greater than the thickness of the fifth insulating layer 26. The thickness of the first planar layer of the present disclosure is set so that the first planar layer is thicker, which not only reduces the risk of short circuits between the third conductive layer and the fourth conductive layer, but also reduces the capacitance between the signals of the third conductive layer and the fourth conductive layer. In other words, it can reduce the resistance and capacitance load, which is more conducive to high PPI and large-size panel driving.

[0187] In example embodiments, the thickness of the first planarization layer may be 1.4 micrometers to 2.3 micrometers.

[0188] In exemplary embodiments, the fifth insulating layer may have a thickness of 50 nanoangstroms to 2500 nanoangstroms.

[0189] In an exemplary embodiment, the second planarization layer can planarize the step difference of the fourth conductive layer, thereby improving the planarity of the driving structure layer and facilitating the subsequent fabrication of the light-emitting structure layer.

[0190] In an exemplary embodiment, the driving structure layer may further include: a sixth insulating layer between the fourth conductive layer and the second planar layer.

[0191] In an exemplary embodiment, as shown in FIG5 , the second transistor T2 and the fourth transistor T4 are disposed at the edge of the entire pixel circuit, which can minimize the signal line crossover connected to the fourth transistor T4 and minimize the capacitance and resistance loads, thereby improving the driving capability of the pixel circuit.

[0192] In an exemplary embodiment, as shown in Figure 5, the pixel circuits of adjacent sub-pixels have the same pixel structure. Adjacent sub-pixels include adjacent sub-pixels located in the same row and adjacent sub-pixels located in the same column.

[0193] In exemplary embodiments, the light-emitting device may have a top-emitting structure or a bottom-emitting structure, which is not limited in this disclosure. A top-emitting structure refers to a light-emitting device in which the first electrode (anode) is a reflective electrode and the second electrode (cathode) is a transmissive electrode. A bottom-emitting structure refers to a light-emitting device in which the first electrode (anode) is a transmissive electrode and the second electrode (cathode) is a reflective electrode.

[0194] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0195] Figures 11 to 21 are schematic diagrams of a display substrate manufacturing process provided by an exemplary embodiment. Figures 11 to 21 are illustrated using a row of two columns of sub-pixels as an example. As shown in Figures 11 to 21, a display substrate manufacturing process provided by an exemplary embodiment may include:

[0196] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern located on the first insulating layer, as shown in FIG11 , which is a schematic diagram after forming the semiconductor layer pattern.

[0197] In an exemplary embodiment, as shown in FIG. 11 , the semiconductor layer pattern may include at least an active pattern T11 of a first transistor located in at least one sub-pixel, an active pattern T21 of a second transistor, an active pattern T31 of a third transistor, an active pattern T41 of a fourth transistor, and an active pattern T51 of a fifth transistor.

[0198] In an exemplary embodiment, as shown in FIG11 , the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor are connected to each other as an integral structure. The active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor are connected to each other as an integral structure. The active pattern T11 of the first transistor and the active pattern T21 of the second transistor are spaced apart.

[0199] In an exemplary embodiment, as shown in FIG11 , in the first direction D1, the integrated structure of the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor of the present sub-pixel is located on a side of the integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor close to the sub-pixel in the previous column.

[0200] In an exemplary embodiment, as shown in FIG11 , in the second direction D2, the active pattern T11 of the first transistor of the present subpixel may be located on a side of the active pattern T31 of the third transistor closer to the subpixels in the previous row, and the active pattern T51 of the fifth transistor of the present subpixel may be located on a side of the active pattern T31 of the third transistor closer to the subpixels in the next row. The active pattern T21 of the second transistor of the present subpixel may be located on a side of the active pattern T41 of the fourth transistor closer to the subpixels in the previous row.

[0201] In an exemplary embodiment, as shown in FIG. 11 , the shape of the active pattern T21 of the second transistor may be Font.

[0202] In exemplary embodiments, as shown in FIG. 11 , the active pattern T41 of the fourth transistor may have an “L” shape.

[0203] In an exemplary embodiment, as shown in FIG11 , the shape of the integrated structure of the active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor may be in the shape of a “[” with the opening facing the integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor.

[0204] In an exemplary embodiment, as shown in FIG. 11 , the integrated structure of the active patterns T11 , T31 , and T51 of the first, third, and fifth transistors is located within the opening of the integrated structure of the active patterns T21 and T41 of the second, fourth, and fourth transistors.

[0205] In an exemplary embodiment, as shown in FIG11 , the main body portions of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor may be shaped like a strip extending along the second direction D2. The integrated structure of the active pattern T11 of the first transistor, the active pattern T31 of the third transistor, and the active pattern T51 of the fifth transistor extends along the second direction D2.

[0206] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The first region and the second region will be conductive after the first conductive layer is subsequently formed, and therefore may also be referred to as conductive regions. In an exemplary embodiment, the second region T11-2 of the active pattern T11 of the first transistor may also serve as the second region T31-2 of the active pattern T31 of the third transistor, the second region T21-2 of the active pattern T21 of the second transistor may also serve as the second region T41-2 of the active pattern T41 of the fourth transistor, and the first region T31-1 of the active pattern T31 of the third transistor may also serve as the second region T51-2 of the active pattern T51 of the fifth transistor. The first region T11-1 of the active pattern T11 of the first transistor, the first region T21-1 of the active pattern T21 of the second transistor, the first region T41-1 of the active pattern T41 of the fourth transistor, and the first region T51-1 of the active pattern T51 of the fifth transistor may be provided separately.

[0207] In an exemplary embodiment, as shown in FIG. 11 , the second region T21-2 of the active pattern T21 of the second transistor may be referred to as the first conductive region T21A of the active pattern T21 of the second transistor, and the first region T21-1 of the active pattern T21 of the second transistor may be referred to as the second conductive region T21B of the active pattern T21 of the second transistor, wherein the first conductive region T21A extends along the second direction D2, and the second conductive region T21B extends along the first direction D1.

[0208] In an exemplary embodiment, as shown in FIG11 , the second region T41-2 of the active pattern T41 of the fourth transistor may be referred to as the third conductive region T41A of the active pattern T41 of the fourth transistor, and the first region T41-1 of the active pattern T41 of the fourth transistor may be referred to as the fourth conductive region T41B of the active pattern T41 of the fourth transistor, wherein the third conductive region T41A extends along the second direction D2, and the fourth conductive region T41B extends along the first direction D1.

[0209] In an exemplary embodiment, as shown in FIG. 11 , the third conductive region T41A is connected to the first conductive region T21A.

[0210] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG12 and FIG13 , FIG12 is a schematic diagram of the first conductive layer pattern, and FIG13 is a schematic diagram after forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0211] In an exemplary embodiment, as shown in Figures 12 and 13, the first conductive layer pattern may include at least: a gate electrode T12 of a first transistor located in at least one sub-pixel, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a gate electrode T42 of a fourth transistor, a gate electrode T52 of a fifth transistor, and a first plate C1 of a capacitor.

[0212] In an exemplary embodiment, the first electrode C1 may also serve as the gate electrode T32 of the third transistor T3 .

[0213] In an exemplary embodiment, the first electrode plate C1 may be rectangular in shape, and an orthographic projection of the first electrode plate C1 on the substrate at least partially overlaps an orthographic projection of the active pattern of the third transistor on the substrate and an orthographic projection of the first conductive region and the third conductive region on the substrate.

[0214] In an exemplary embodiment, the gate electrode T12 of the first transistor has a bar shape extending along the first direction D1.

[0215] In an exemplary embodiment, the gate electrode T22 of the second transistor has a bar shape extending along the first direction D1.

[0216] In an exemplary embodiment, the gate electrode T42 of the fourth transistor has a bar shape extending along the first direction D1.

[0217] In an exemplary embodiment, the gate electrode T52 of the fifth transistor has a bar shape extending along the first direction D1.

[0218] In an exemplary embodiment, a length of the integrated structure of the gate electrode T32 of the third transistor and the first plate C1 of the capacitor along the second direction D2 is greater than a length of any one of the gate electrode T12 of the first transistor, the gate electrode T22 of the second transistor, the gate electrode T42 of the fourth transistor, and the gate electrode T52 of the fifth transistor along the second direction D2.

[0219] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductively processed using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the active pattern of the first transistor to the channel region of the active pattern of the fifth transistor. The semiconductor layer in the area not shielded by the first conductive layer is conductively processed. That is, the first and second areas of the active pattern of the first transistor to the active pattern of the fifth transistor are both conductively processed. After the conductive processing, the first area T31-1 of the active pattern T31 of the third transistor (also the second area T51-2 of the active pattern T51 of the fifth transistor) can be reused as the first electrode T33 of the third transistor and the second electrode T54 of the fifth transistor.

[0220] In an exemplary embodiment, the gate electrode T12 of the first transistor is arranged across the active pattern of the first transistor, the gate electrode T22 of the second transistor is arranged across the active pattern of the second transistor, the gate electrode T32 of the third transistor is arranged across the active pattern of the third transistor, the gate electrode T42 of the fourth transistor is arranged across the active pattern of the fourth transistor, and the gate electrode T52 of the fifth transistor is arranged across the active pattern of the fifth transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0221] (3) Forming a second conductive layer pattern, including: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern, and patterning the third insulating film and the second conductive film through a patterning process to form a third insulating layer and a second conductive layer pattern located on the third insulating layer, as shown in Figures 14 and 15 , where Figure 14 is a schematic diagram of the second conductive layer pattern, and Figure 15 is a schematic diagram after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0222] In an exemplary embodiment, as shown in FIG. 14 and FIG. 15 , the second conductive layer pattern may include at least a second plate C2 of a capacitor located in at least one sub-pixel.

[0223] In an exemplary embodiment, as shown in Figures 14 and 15 , the second electrode plate C2 may include a capacitor body C21, a first capacitor connecting portion C22, and a second capacitor connecting portion C23. The first capacitor connecting portion C22 and the second capacitor connecting portion C23 are located on either side of the capacitor body C21 and are connected to the capacitor body C21.

[0224] In an exemplary embodiment, as shown in Figures 14 and 15, the first capacitor connection portion C22 of the present sub-pixel can be located on the side of the capacitor main portion C21 close to the sub-pixels in the previous row, and the second capacitor connection portion C23 of the present sub-pixel can be located on the side of the capacitor main portion C21 close to the sub-pixels in the next row.

[0225] In an exemplary embodiment, as shown in Figures 14 and 15, the length of the first capacitor connecting portion C22 along the first direction D1 is greater than the length of the second capacitor connecting portion C23 along the first direction D1, and the length of the capacitor main portion C21 along the first direction D1 is greater than the length of the first capacitor connecting portion C22 along the first direction D1.

[0226] In an exemplary embodiment, as shown in Figures 14 and 15, the first capacitor connection portion C22 of the present sub-pixel is close to the boundary of the previous column of sub-pixels and is flush with the second capacitor connection portion C22 close to the boundary of the previous column of sub-pixels, and is also flush with the boundary of the capacitor main portion C21 close to the boundary of the previous column of sub-pixels.

[0227] In an exemplary embodiment, as shown in FIG15 , the capacitor body C21 may be shaped like a square with a recess K. The recess K is disposed on a side of the capacitor body C21 of the current sub-pixel that is close to the sub-pixel in the previous column. The recess K exposes the first electrode (also the gate electrode of the third transistor) and the second electrode of the second transistor (also the second electrode of the fourth transistor).

[0228] In an exemplary embodiment, as shown in FIG. 15 , within the same sub-pixel, the opening direction of the groove K is located on a side away from the second active layer.

[0229] In an exemplary embodiment, as shown in FIG. 14 and FIG. 15 , the shape of the groove K may be a square, or other shapes, which is not limited in the present disclosure.

[0230] In an exemplary embodiment, as shown in FIG15 , the orthographic projection of the capacitor body C21 on the substrate at least partially overlaps with the orthographic projections of at least part of the first plate of the capacitor (also the gate electrode of the third transistor), the first conductive region, and the third conductive region on the substrate.

[0231] In an exemplary embodiment, as shown in FIG. 14 and FIG. 15 , the first capacitor connection portion C22 may have an “L” shape.

[0232] In an exemplary embodiment, as shown in FIG. 14 and FIG. 15 , the second capacitor connection portion C23 may be shaped like a bar extending along the second direction D2 .

[0233] In an exemplary embodiment, as shown in FIG15 , the orthographic projection of any one of the first capacitor connecting portion C22 and the second capacitor connecting portion C23 on the substrate may at least partially overlap with the orthographic projection of the first conductive region and the third conductive region on the substrate, and may not overlap with the orthographic projection of the first plate of the capacitor (which is also the gate electrode of the third transistor) on the substrate.

[0234] In an exemplary embodiment, a length of any one of the first capacitor connecting portion C22 and the second capacitor connecting portion C23 along the first direction D1 may be greater than or equal to a length of the second electrode of the second transistor (also the second electrode of the fourth transistor) along the first direction D1.

[0235] In an exemplary embodiment, along the second direction, the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the second transistor on the substrate and the orthographic projection of the gate electrode of the first transistor on the substrate; the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate.

[0236] (4) forming a fourth insulating layer pattern, comprising: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned pattern, wherein the fourth insulating layer is provided with a plurality of via patterns, as shown in FIG16 , which is a schematic diagram after the fourth insulating layer pattern is formed.

[0237] In an exemplary embodiment, as shown in FIG16 , the plurality of via holes of the fourth insulating layer include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, and a tenth via hole V10 located in at least one sub-pixel.

[0238] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the second insulating layer and the third insulating layer within the first via hole V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via hole V1 is configured to connect a subsequently formed initial signal line INIT to the first area of ​​the active pattern of the first transistor through the via hole.

[0239] In an exemplary embodiment, as shown in Figure 16, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor (also the second area of ​​the active pattern of the third transistor) and the second plate of the capacitor on the substrate, and a portion of the second insulating layer and a portion of the third insulating layer within the second via V2 are etched away to expose the second area of ​​the active pattern of the first transistor (also the second area of ​​the active pattern of the third transistor) and the surface of the second plate of the capacitor. The second via V2 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the active pattern of the first transistor (also the second area of ​​the active pattern of the third transistor) and the second plate of the capacitor through the via.

[0240] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the second insulating layer and the third insulating layer within the third via hole V3 are etched away, exposing the surface of the first area of ​​the active pattern of the second transistor, and the third via hole V3 is configured to connect a subsequently formed reference signal line to the first area of ​​the active pattern of the second transistor through the via hole.

[0241] In an exemplary embodiment, as shown in Figure 16, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) and the first plate of the capacitor on the substrate, and part of the second insulating layer and part of the third insulating layer in the fourth via V4 are etched away to expose the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) and the surface of the first plate of the capacitor. The fourth via V4 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) and the first plate of the capacitor through the via.

[0242] In an exemplary embodiment, as shown in Figure 16, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the second insulating layer and the third insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0243] In an exemplary embodiment, as shown in Figure 16, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the sixth via V6 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the sixth via V6 is configured to connect a subsequently formed first power line to the first area of ​​the active pattern of the fifth transistor through the via.

[0244] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor on the substrate, the third insulating layer in the seventh via hole V7 is etched away to expose the surface of the gate electrode of the first transistor, and the seventh via hole V7 is configured to connect a subsequently formed third scan signal line to the gate electrode of the first transistor through the via hole.

[0245] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor on the substrate, the third insulating layer in the eighth via V8 is etched away to expose the surface of the gate electrode of the second transistor, and the eighth via V8 is configured to connect a subsequently formed second scan signal line to the gate electrode of the second transistor through the via.

[0246] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor on the substrate, the third insulating layer in the ninth via hole V9 is etched away to expose the surface of the gate electrode of the fourth transistor, and the ninth via hole V9 is configured to connect a subsequently formed first scanning signal line to the gate electrode of the fourth transistor through the via hole.

[0247] In an exemplary embodiment, as shown in FIG16 , the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the third insulating layer in the tenth via hole V10 is etched away to expose the surface of the gate electrode of the fifth transistor, and the tenth via hole V10 is configured to connect a subsequently formed light-emitting signal line to the gate electrode of the fifth transistor through the via hole.

[0248] (5) Forming a third conductive layer pattern, including: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the fourth insulating layer, as shown in FIG17 and FIG18 . FIG17 is a schematic diagram of the third conductive layer pattern, and FIG18 is a schematic diagram after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0249] In an exemplary embodiment, as shown in Figures 17 and 18, the third conductive layer pattern may include at least: a first scan signal line Gate1, a second scan signal line Gate2, a third scan signal line Gate3, a light emitting signal line EM, a reference signal line REF, a first power line VDD, an initial signal line INIT, and a second electrode T14 of a first transistor located in at least one sub-pixel, a second electrode T24 of a second transistor, a second electrode T34 of a third transistor, and a first electrode T43 and a second electrode T44 of a fourth transistor.

[0250] 17 and 18 , the reference signal line REF may be in the shape of a line having a main portion extending along the first direction D1 . The region where the reference signal line REF overlaps the active pattern of the second transistor serves as the first electrode T23 of the second transistor.

[0251] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the reference signal line REF is connected to the first region of the active pattern of the second transistor through the third via hole.

[0252] 17 and 18 , the second scan signal line Gate2 is located between the reference signal line REF and the initial signal line INIT. The second scan signal line Gate2 may have a line shape with a main portion extending along the first direction D1.

[0253] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , an orthographic projection of the second scan signal line Gate2 on the substrate at least partially overlaps an orthographic projection of the gate electrode of the second transistor on the substrate.

[0254] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the second scan signal line Gate2 is connected to the gate electrode of the second transistor through the eighth via hole.

[0255] In an exemplary embodiment, as shown in Figures 17 and 18, the initial signal line INIT is located on a side of the second scan signal line Gate2 away from the reference signal line REF. The initial signal line INIT may be in the shape of a line with a main portion extending along a first direction D1. The region where the initial signal line INIT overlaps with the active pattern of the first transistor serves as the first electrode T13 of the first transistor.

[0256] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the initial signal line INIT is connected to the first region of the active pattern of the first transistor through a first via hole.

[0257] 17 and 18 , the third scan signal line Gate3 is located on a side of the initial signal line INIT away from the second scan signal line Gate2 . The third scan signal line Gate3 may be in a line shape with a main portion extending along the first direction D1 .

[0258] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , an orthographic projection of the third scan signal line Gate3 on the substrate at least partially overlaps an orthographic projection of the gate electrode of the first transistor on the substrate.

[0259] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the third scan signal line Gate3 is connected to the gate electrode of the first transistor through the seventh via hole.

[0260] 17 and 18, the emission signal line EM is located on a side of the third scan signal line Gate3 away from the initial signal line INIT. The emission signal line EM may have a line shape with a main portion extending along the first direction D1.

[0261] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , an orthographic projection of the light emitting signal line EM on the substrate at least partially overlaps with an orthographic projection of the gate electrode of the fifth transistor on the substrate.

[0262] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the light emitting signal line EM is connected to the gate electrode of the fifth transistor through a tenth via hole.

[0263] In an exemplary embodiment, as shown in Figures 17 and 18, the first power line VDD is located on a side of the emission signal line EM away from the third scan signal line Gate3. The first power line VDD may be in the shape of a line with a main portion extending along a first direction D1. The area where the first power line VDD overlaps the active pattern of the fifth transistor serves as the first electrode T13 of the fifth transistor.

[0264] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the first power line VDD is connected to the first region of the active pattern of the fifth transistor through the sixth via hole.

[0265] 17 and 18 , the first scan signal line Gate1 is located on a side of the first power line VDD away from the emission signal line EM. The first scan signal line Gate1 may be in a line shape with a main portion extending along the first direction D1.

[0266] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , an orthographic projection of the first scan signal line Gate1 on the substrate at least partially overlaps an orthographic projection of the gate electrode of the fourth transistor on the substrate.

[0267] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the first scan signal line Gate1 is connected to the gate electrode of the fourth transistor through a ninth via hole.

[0268] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T14 of the first transistor and the second electrode T34 of the third transistor are integrally formed and located between the third scan signal line Gate3 and the emission signal line EM. The integral structure of the second electrode T14 of the first transistor and the second electrode T34 of the third transistor can be in the shape of a strip extending along the first direction D1.

[0269] In an exemplary embodiment, as shown in FIG17 and FIG18 , an orthographic projection of the integrated structure of the second electrode T14 of the first transistor and the second electrode T34 of the third transistor on the substrate at least partially overlaps with an orthographic projection of the second plate of the capacitor on the substrate.

[0270] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T14 of the first transistor (also the second electrode T34 of the third transistor) is connected to the second area of ​​the active pattern of the first transistor (also the second area of ​​the active pattern of the third transistor) and the second plate of the capacitor through a second via.

[0271] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T24 of the second transistor and the second electrode T44 of the fourth transistor are integrally structured and are located between the second electrode T14 of the first transistor (also the second electrode T34 of the third transistor) and the light emitting signal line EM. The second electrode T24 of the second transistor (also the second electrode T44 of the fourth transistor) may be in the shape of a strip extending along the first direction D1.

[0272] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the orthographic projection of the second electrode T24 of the second transistor (also the second electrode T44 of the fourth transistor) on the substrate is located within the orthographic projection of the groove of the second plate of the capacitor on the substrate.

[0273] In an exemplary embodiment, as shown in Figures 17 and 18, the second electrode T24 of the second transistor (also the second electrode T44 of the fourth transistor) is connected to the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the fourth transistor) and the first plate of the capacitor through a fourth via.

[0274] 17 and 18 , the first electrode T43 of the fourth transistor is located on a side of the first scan signal line Gate1 away from the first power line VDD. The first electrode VL3 of the fourth transistor may be in the shape of a bar extending along the first direction D1.

[0275] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , an orthographic projection of the first electrode T43 of the fourth transistor on the substrate is located within an orthographic projection of the active pattern of the fourth transistor on the substrate.

[0276] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the first electrode T43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a fifth via hole.

[0277] In an exemplary embodiment, the first scanning signal line Gate1, the second scanning signal line Gate2, the third scanning signal line Gate3, the light-emitting signal line EM, the reference signal line REF, the first power line VDD and the initial signal line INIT can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0278] (6) forming a fifth insulating layer pattern, comprising: coating a first flat film on a substrate having the aforementioned pattern formed thereon, patterning the first flat film through a patterning process to form a first flat layer, depositing a fifth insulating film on the first flat layer, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern, wherein the fifth insulating layer pattern is provided with a plurality of via patterns, as shown in FIG19 , which is a schematic diagram after the fifth insulating layer pattern is formed.

[0279] In an exemplary embodiment, as shown in FIG. 19 , the plurality of via holes in the fifth insulation layer pattern includes at least an eleventh via hole V11 and a twelfth via hole V12 located in at least one sub-pixel.

[0280] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode T14 of the first transistor (also the second electrode T34 of the third transistor) on the substrate, the first flat layer within the eleventh via hole V11 is etched away to expose the surface of the second electrode T14 of the first transistor (also the second electrode T34 of the third transistor), and the eleventh via hole V11 is configured to connect a subsequently formed anode connection electrode to the second electrode T14 of the first transistor (also the second electrode T34 of the third transistor) through the via hole.

[0281] In an exemplary embodiment, as shown in FIG19 , the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the first flat layer in the twelfth via V12 is etched away to expose the surface of the first electrode of the fourth transistor, and the twelfth via V12 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.

[0282] (7) Forming a fourth conductive layer pattern, including: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, as shown in FIG20 and FIG21 . FIG20 is a schematic diagram of the fourth conductive layer pattern, and FIG21 is a schematic diagram after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0283] In exemplary embodiments, as shown in FIG. 20 and FIG. 21 , the fourth conductive layer pattern may include at least a data signal line Data and an anode connection electrode VL.

[0284] 20 and 21 , the anode connection electrode VL of the subpixel is located on a side of the data signal line connected to the subpixel close to the next column of subpixels. The anode connection electrode VL is in a strip shape extending along the second direction D2.

[0285] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , an orthographic projection of the anode connection electrode VL on the substrate at least partially overlaps with an orthographic projection of the second electrode of the first transistor (also the second electrode of the third transistor) and the third scan signal line on the substrate.

[0286] In an exemplary embodiment, as shown in Figures 20 and 21, the anode connection electrode VL is connected to the second electrode of the first transistor (also the second electrode of the third transistor) through an eleventh via. Since the second electrode of the first transistor (also the second electrode of the third transistor) is connected to the second plate of the capacitor, the anode connection electrode VL is connected to the second region of the active pattern of the first transistor (also the second region of the active pattern of the third transistor) and the second plate of the capacitor through the second electrode of the first transistor (also the second electrode of the third transistor).

[0287] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the data signal line Data at least partially extends along the second direction D2 .

[0288] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , an orthographic projection of the data signal line Data on the substrate at least partially overlaps with an orthographic projection of the first conductive region, the third conductive region, the fourth conductive region, and the second plate of the capacitor on the substrate.

[0289] 20 and 21 , the data signal lines Data include: a data signal main line DataA and a plurality of data signal connection lines DataB. The data signal main line DataA extends along the second direction D2, and the data signal connection lines DataB extends along the first direction D1.

[0290] In an exemplary embodiment, the orthographic projection of the data signal main line DataA on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line DataB on the substrate at least partially overlaps with the orthographic projection of the fourth conductive region on the substrate.

[0291] 20 and 21 , the data signal line Data is connected to the first electrode of the fourth transistor through the twelfth via hole, and the data signal connection line DataB of the data signal line Data is connected to the first electrode of the fourth transistor through the twelfth via hole.

[0292] (8) forming a second flat layer pattern, comprising: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film through a patterning process to form a sixth insulating layer covering the aforementioned pattern, coating a second flat film on the sixth insulating layer, and patterning the second flat film through a patterning process to form a second flat layer pattern covering the aforementioned pattern.

[0293] The second planar layer pattern includes at least a thirteenth via hole. The orthographic projection of the thirteenth via hole on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate. The sixth insulating layer in the thirteenth via hole is etched away to expose the surface of the anode connecting electrode. The thirteenth via hole is configured to connect an anode of a subsequently formed light-emitting device to the anode connecting electrode through the via hole.

[0294] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of pixel circuits, and the pixel circuits are connected to the first scan signal line, the second scan signal line, the third scan signal line, the light emitting signal line, the reference signal line, the initial signal line, the data signal line and the first power line. The drive structure layer can be arranged on the substrate. The drive structure layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer and a second planar layer arranged in sequence on the substrate.

[0295] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0296] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0297] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.

[0298] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as resin.

[0299] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0300] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the second planar layer, wherein the fifth conductive layer includes at least a plurality of first electrode patterns.

[0301] In an exemplary embodiment, the fifth conductive layer pattern may include: a plurality of first electrode patterns. The plurality of first electrode patterns may include a first electrode of a first light-emitting device, a first electrode of a second light-emitting device, a first electrode of a third light-emitting device, and a first electrode of a fourth light-emitting device, wherein the first electrode of the first light-emitting device is located in a red sub-pixel emitting red light, the first electrode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the first electrode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the first electrode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0302] In an exemplary embodiment, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along the second direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the second direction. Alternatively, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along the first direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the first direction.

[0303] In an exemplary embodiment, the first electrode of the first light emitting device, the first electrode of the second light emitting device, the first electrode of the third light emitting device, and the first electrode of the fourth light emitting device may be connected to the connection electrode of the sub-pixel through a via hole exposing the connection electrode of the sub-pixel.

[0304] In an exemplary embodiment, the shapes and areas of the first electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0305] In an exemplary embodiment, at least one of the first electrodes of the first, second, third, and fourth light emitting devices may include an anode body portion and an anode connection portion connected to each other, the anode connection portion being connected to the connection electrode.

[0306] In an exemplary embodiment, the first electrode of a first light-emitting device may include a first anode body portion and a first anode connecting portion connected to each other. The first anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the first anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a second light-emitting device may include a second anode body portion and a second anode connecting portion connected to each other. The second anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the second anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a third light-emitting device may include a third anode body portion and a third anode connecting portion connected to each other. The third anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the third anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a fourth light-emitting device may include a fourth anode body portion and a fourth anode connecting portion connected to each other. The fourth anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the fourth anode connecting portion may be in the shape of a strip.

[0307] In an exemplary embodiment, the fifth conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0308] (10) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, depositing the pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition layer pattern exposing the fifth conductive layer pattern, coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material through a patterning process to form an organic structure layer pattern, depositing a sixth conductive film on the substrate on which the organic material layer pattern is formed, and patterning the sixth conductive film through a patterning process to form the sixth conductive layer.

[0309] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the sixth conductive layer, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0310] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0311] In an exemplary embodiment, the sixth conductive layer may include at least second electrodes (cathodes) of the plurality of light emitting devices.

[0312] In an exemplary embodiment, the sixth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0313] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0314] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0315] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0316] In an exemplary embodiment, the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0317] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0318] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0319] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising: a pixel circuit, the pixel circuit comprising: a third transistor and a plurality of transistors connected to the third transistor; the transistor comprising an active pattern, the active patterns of at least two transistors connected to the gate electrode of the third transistor are an integrated structure and form a first active layer, the active patterns of at least two transistors connected to any one of a first electrode and a second electrode of the third transistor and the active pattern of the third transistor are an integrated structure and form a second active layer; The first active layer and the second active layer are arranged along a first direction and at least partially extend along a second direction, and the first direction intersects with the second direction; A length of the first active layer along the second direction is greater than a length of the second active layer along the second direction.

2. The display substrate according to claim 1, wherein: The plurality of transistors connected to the third transistor include: a first transistor, a second transistor, a fourth transistor and a fifth transistor, wherein the first transistor to the fifth transistor are N-type transistors; The second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the second electrode of the second transistor and the second electrode of the fourth transistor are electrically connected to the gate electrode of the third transistor respectively, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor; The active pattern includes a channel region and a conductive region, and the conductive region of any active pattern is located on both sides of the channel region; wherein the active pattern of the second transistor and the active pattern of the fourth transistor are the first active layer, and the active pattern of the first transistor, the active pattern of the third transistor and the active pattern of the fifth transistor are the second active layer.

3. The display substrate according to claim 2, wherein: The active pattern of the first transistor and the active pattern of the fifth transistor are respectively located on both sides of the active pattern of the third transistor, the active pattern of the second transistor includes: a first conductive region and a second conductive region; the active pattern of the fourth transistor includes: a third conductive region and a fourth conductive region; the first conductive region and the third conductive region extend along the second direction, the second conductive region and the fourth conductive region extend along the first direction; the third conductive region is connected to the first conductive region.

4. The display substrate according to claim 3, wherein: The second conductive region is located on a side of the first conductive region close to the second active layer, and is located on a side of a center line of the active layer together with at least a portion of the active pattern of the first transistor, the center line of the active layer being a center line of the second active layer extending along the first direction; The fourth conductive region is located on a side of the third conductive region close to the second active layer, and is located on the other side of a center line of the active layer together with at least a portion of the active pattern of the fifth transistor.

5. The display substrate according to claim 3 or 4, further comprising: A first signal line is disposed on the substrate, at least a portion of the first signal line extends along a first direction, and a gate electrode of at least one transistor is disposed in a different layer from the first signal line; The resistivity of the film layer where the first signal line is located is smaller than the resistivity of the film layer where the gate electrode of the at least one transistor is located.

6. The display substrate according to claim 5, wherein: The gate electrode of the first transistor to the gate electrode of the fifth transistor are arranged at intervals; A length of a gate electrode of the third transistor along the second direction is greater than a length of a gate electrode of any one of the first transistor, the second transistor, the fourth transistor, and the fifth transistor along the second direction.

7. The display substrate according to claim 5 or 6, wherein: The pixel circuit further includes: a capacitor, the capacitor including: a first plate and a second plate; the first plate of the capacitor is located on a side of the second plate of the capacitor close to the substrate; An orthographic projection of the first plate of the capacitor on the substrate at least partially overlaps with an orthographic projection of the first conductive region, an active pattern of the third transistor, and the third conductive region on the substrate.

8. The display substrate according to claim 7, wherein: The first signal line includes: a third scanning signal line, an initial signal line, a first power line and a light-emitting signal line; the first transistor is connected to the third scanning signal line and the initial signal line respectively, and the fifth transistor is connected to the first power line and the light-emitting signal line respectively; The orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps with the orthographic projections of the third scanning signal line, the initial signal line, the first power line, the light-emitting signal line, the first plate of the capacitor, the first conductive area and the third conductive area on the substrate.

9. The display substrate according to claim 8, wherein: Along the second direction, a distance between an orthographic projection of the gate electrode of the second transistor on the substrate and an orthographic projection of the second plate of the capacitor on the substrate is smaller than a distance between an orthographic projection of the gate electrode of the second transistor on the substrate and an orthographic projection of the gate electrode of the first transistor on the substrate; The distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the second plate of the capacitor on the substrate is smaller than the distance between the orthographic projection of the gate electrode of the fourth transistor on the substrate and the orthographic projection of the gate electrode of the fifth transistor on the substrate.

10. The display substrate according to claim 8 or 9, wherein: The second electrode plate of the capacitor is provided with a groove, and the groove exposes at least a part of the first electrode plate, the first conductive area and the third conductive area of ​​the capacitor.

11. The display substrate according to claim 10, wherein: In the same sub-pixel, the opening direction of the groove is located at a side away from the second active layer.

12. The display substrate according to claim 10, wherein: The second electrode plate of the capacitor comprises: a capacitor main body, a first capacitor connecting part and a second capacitor connecting part, wherein the first capacitor connecting part and the second capacitor connecting part are respectively located on both sides of the capacitor main body, and the groove is arranged on one side of the capacitor main body; The capacitor main body extends along a first direction, the first capacitor connecting portion at least partially extends along a second direction, and the second capacitor connecting portion extends along the second direction; The average length of the capacitor main body along the first direction is greater than the average length of the first capacitor connecting portion along the first direction, and the average length of the first capacitor connecting portion along the first direction is greater than the average length of the second capacitor connecting portion along the first direction.

13. The display substrate according to claim 12, wherein: The orthographic projection of the capacitor main body on the substrate at least partially overlaps with the orthographic projections of the first electrode plate of the capacitor, the first conductive area and the third conductive area on the substrate; The orthographic projections of the first capacitor connecting portion and the second capacitor connecting portion on the substrate at least partially overlap with the orthographic projections of the first conductive area and the third conductive area on the substrate, and do not overlap with the orthographic projection of the first plate of the capacitor on the substrate.

14. The display substrate according to claim 10, wherein: The first electrode plate of the capacitor includes: a first area and a second area; the first area is the area exposed by the groove of the second electrode plate of the capacitor, and the second area is all areas except the first area; The orthographic projection of the second electrode plate of the capacitor on the substrate covers the orthographic projection of the second region of the first electrode plate of the capacitor on the substrate.

15. The display substrate according to claim 8, wherein: The first signal line further includes: a reference signal line, a first scanning signal line, and a second scanning signal line, the second transistor is connected to the second scanning signal line and the reference signal line respectively, and the fourth transistor is connected to the first scanning signal line; The reference signal line, the second scanning signal line, the initial signal line, the third scanning signal line, the light emitting signal line, the first power line and the first scanning signal line are sequentially arranged along a first direction.

16. The display substrate according to claim 15, further comprising: A second signal line is arranged on the substrate, the second signal line extends along a second direction, and the second signal line includes: a data signal line; The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projections of the first conductive region, the third conductive region, the fourth conductive region and the second electrode plate of the capacitor on the substrate.

17. The display substrate according to claim 16, wherein: The data signal line comprises: a data signal main line and a plurality of data signal connecting lines, the data signal main line extends along the second direction, and the data signal connecting lines extend along the first direction; The orthographic projection of the data signal main line on the substrate at least partially overlaps with the orthographic projection of the first conductive area, the third conductive area and the second plate of the capacitor on the substrate, and the orthographic projection of the data signal connection line on the substrate at least partially overlaps with the orthographic projection of the fourth conductive area on the substrate.

18. The display substrate according to claim 17, further comprising: A driving structure layer disposed on the substrate; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; The semiconductor layer includes at least: an active pattern of a first transistor, an active pattern of a second transistor, an active pattern of a third transistor, an active pattern of a fourth transistor, and an active pattern of a fifth transistor located in at least one sub-pixel; The first conductive layer at least includes: a gate electrode of a first transistor located in at least one sub-pixel, a gate electrode of a second transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, and a first plate of a capacitor; The second conductive layer at least includes: a second plate of a capacitor located in at least one sub-pixel; The third conductive layer at least includes: a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, a reference signal line, a first power line, an initial signal line, and a second electrode of a first transistor located in at least one sub-pixel, a second electrode of a second transistor, a second electrode of a third transistor, and a first electrode and a second electrode of a fourth transistor; The fourth conductive layer at least includes: a data signal line.

19. The display substrate according to claim 18, wherein: The driving structure layer further includes: a first flat layer and a fifth insulating layer located between the third conductive layer and the fourth conductive layer; The fifth insulating layer is located on a side of the first planar layer away from the substrate; The thickness of the first planarizing layer is greater than the thickness of the fifth insulating layer.

20. The display substrate according to claim 19, wherein: The thickness of the first planar layer is 1.4 micrometers to 2.3 micrometers, and the thickness of the fifth insulating layer is 50 nanoangstroms to 2500 nanoangstroms.

21. The display substrate according to claim 18, wherein: The thickness of the third conductive layer is greater than the thickness of the first conductive layer or the second conductive layer; The resistivity of the fourth conductive layer is lower than that of the first conductive layer.

22. A display device, comprising: A display substrate as claimed in any one of claims 1 to 21.

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