Integrated circuit (IC) packages employing on-package tunable inductors formed in redistribution layer (RDL) for impedance tuner circuits and related methods

Abstract

Integrated circuit (IC) packages and related methods employing on-package tunable inductors formed in redistribution layers (RDLs) for impedance tuner circuits. The IC package (300) includes an impedance tuner circuit that includes a tunable inductor (304) that can be tuned to vary a frequency response of the impedance tuner circuit. To reduce the circuit area, the tunable inductor is formed in an RDL (306) of a package substrate (308) of the IC package. The IC package also includes a semiconductor die (316) including other components coupled to the impedance tuner circuit of the tunable inductor by coupling the die to the package substrate. In this manner, by forming the tunable inductor in the RDL in the package substrate, a signal path length between the tunable inductor and other components of the tunable impedance circuit is reduced, thereby reducing inductive path resistance and improving a quality (Q) factor of the tunable inductor.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 664,727, filed on May 24, 2022, entitled "INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING ON-PACKAGE TUNABLE INDUCTOR FORMED INREDISTRIBUTION LAYER (RDL) FOR IMPEDANCE TUNER CIRCUIT, AND RELATED METHODS," which is incorporated herein by reference in its entirety. background

[0004] I. Technical field

[0005] The field of the present disclosure relates to impedance tuners that may be employed in transceiver circuits to filter radio frequency (RF) signals, wherein the impedance tuners employ tunable resistor, capacitor, and inductor networks to filter specific frequency bands.

[0006] II. Background Technology

[0007] A radio frequency (RF) transceiver includes an RF transmit circuit chain, which conventionally includes an RF power amplifier (PA) to amplify an RF signal for transmission as an output RF signal within a given frequency band. The RF transmit circuit chain may also include an output impedance tuner circuit to filter the output RF signal in a desired frequency range or bandwidth. The RF transceiver also includes an RF receive circuit chain, which conventionally includes a low noise amplifier (LNA) coupled to an antenna that receives an input RF signal. The RF receiver circuit chain may also include an input impedance tuner circuit to filter the input RF signal to a desired bandwidth frequency range. The impedance tuner circuit conventionally includes a resistor, a capacitor, and an inductor network to filter the RF signal. The impedance tuner circuit may also include a switched variable capacitor and a series of switches that can be programmed to selectively couple an inductor into the RF signal path in order to control filtering performance.

[0008] It may be desirable to integrate an RF transceiver in an integrated circuit (IC) package that can be coupled to a printed circuit board (PCB) to save area. This is in contrast to discrete components that are provided and coupled to the RF transceiver on the PCB. However, discrete inductors for impedance tuners are mounted on the PCB outside the IC package due to their size. These discrete inductors are coupled to the impedance tuner in the IC package through programmable switches. The external pins of the IC package are coupled to electrical traces in the PCB, which couple the discrete inductors to the impedance tuner circuit in the IC package. However, the discrete inductors located outside the IC package increase the length of the conductive path that couples the discrete inductor to the impedance tuner circuit, thereby increasing the resistance in the inductive path. Increasing the resistance in the inductive path reduces the quality (Q) factor of the discrete inductor, thereby reducing the filtering performance of the impedance tuner circuit. Summary of the invention

[0009] Various aspects disclosed herein include an integrated circuit (IC) package that employs an on-package tunable inductor formed in a redistribution layer (RDL) for an impedance tuner circuit. Related methods are also disclosed. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. In order to reduce the circuit area required to provide the tunable inductor, the tunable inductor is integrated in the IC package. In an exemplary aspect, the tunable inductor is formed in the RDL of a packaging substrate of the IC package. The IC package also includes a semiconductor die ("die") that includes other components of the impedance tuner circuit coupled to the tunable inductor by coupling the die to the packaging substrate. In this way, by forming a tunable inductor in the RDL in the packaging substrate, the signal path length between the tunable inductor and other components of the tunable impedance circuit is reduced, thereby reducing the inductance path resistance and improving the quality (Q) factor of the tunable inductor. Furthermore, by forming the tunable inductor in the RDL of the IC package, the tunable inductor can be formed to have a desired geometry to provide a desired inductance frequency response.

[0010] In an exemplary aspect, a tunable inductor may be formed in an RDL of a packaging substrate of an IC package as a metal line having a first terminal and a second terminal, which metal line may be coupled to a circuit to couple the inductance of the tunable inductor to the circuit. The tunable inductor is also formed in the RDL to have one or more shunt taps. The shunt taps are two metal lines formed in the tunable inductor, which have ends adjacent to each other but form a short circuit. One or more switches in an active semiconductor layer in a front end process (FEOL) of a die as part of an impedance tuner circuit are coupled to corresponding shunt taps in the tunable inductor through a signal path routed between the die in the packaging substrate and the tunable inductor in the RDL. The switches in the die may be programmed / controlled to shunt the shunt taps or to keep their corresponding coupled shunt taps as an open circuit so as to change the inductance of the inductor and shift the frequency response of the impedance tuner circuit. In this way, the switch allows the inductance of the inductor to be tuned by controlling the shunting or non-shunting of one or more shunt taps in the inductor. The tunable inductor disposed in the RDL in the packaging substrate of the IC package positions the shunt taps closer to the corresponding switches in the die to reduce the inductor path length, thereby reducing resistance and improving the inductor Q factor. Moreover, because the inductor is formed as a metal line in the RDL, the inductor and its shunt taps can be formed in the RDL as part of manufacturing the packaging substrate to have a desired geometry and connectivity arrangement to provide the desired inductance tunability of the inductor.

[0011] In other exemplary aspects, the tunable inductor is formed as a two-dimensional (2D) inductor, such that the tunable inductor is formed in a single RDL in a packaging substrate of an IC package. In another exemplary aspect, the tunable inductor is formed as a three-dimensional (3D) inductor, such that the tunable inductor is formed in multiple RDLs of a packaging substrate of an IC package.

[0012] In this regard, in one exemplary aspect, an IC package is provided. The IC package includes an impedance tuner circuit, the impedance tuner circuit including: a first switch; and an inductor, the inductor including a first terminal and a second terminal. The IC package also includes a packaging substrate, the packaging substrate including a first RDL, the first RDL including the inductor. The IC package also includes a die, the die coupled to the packaging substrate, the die including the first switch. The inductor includes: a first metal line in the first RDL, the first metal line including the first terminal and the second terminal; and a first shunt tap, the first shunt tap being located in the first RDL. The first shunt tap is coupled to the first terminal and the second terminal. The first switch is coupled to the first shunt tap.

[0013] In another exemplary aspect, a method of manufacturing an IC package is provided. The method includes forming a first switch in a tube core. The method also includes forming an inductor in a package substrate, including: forming a first metal line of the inductor in the first redistribution layer (RDL) in the package substrate, the first metal line including a first terminal and a second terminal; and forming a first shunt tap of the inductor in the first RDL, the first shunt tap coupled to the first terminal and the second terminal. The method also includes coupling the tube core to the package substrate. The method also includes coupling the first switch to the first shunt tap. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of an exemplary impedance tuner circuit including a switchable inductor that is programmable to change the frequency response of the impedance tuner circuit;

[0015] Figure 2A and Figure 2B is exemplified as Figure 1 A graph of inductance and quality (Q) factor as a function of frequency of an inductive path in an impedance tuner circuit;

[0016] Figure 3A and Figure 3B is a side view of an integrated circuit (IC) package including an impedance tuner circuit including a tunable inductor formed in a redistribution layer (RDL) in a package substrate, wherein the tunable inductor includes a plurality of complementary conductive segments, the plurality of complementary conductive segments each including ends adjacent to each other to form complementary shunt taps configured to be shunted by respective switches of the impedance tuner circuit in a semiconductor die (“die”) coupled to the package substrate;

[0017] Figure 4 Can be set in Figure 3A and Figure 3B a circuit diagram of an exemplary impedance tuner circuit in an IC package in;

[0018] Figure 5A and Figure 5B is exemplified as Figure 3A and Figure 3B a graph of inductance and Q factor as a function of frequency of an inductive path of an impedance tuner circuit in an IC package;

[0019] Fig. 6A is a perspective view of another exemplary two-dimensional (2D) tunable inductor that may be formed in an RDL of an IC package;

[0020] Figure 6Bis a side view of another exemplary IC package including an impedance tuner circuit including Fig. 6A Tunable inductor in;

[0021] Fig. 7A is a perspective view of another exemplary three-dimensional (3D) tunable inductor that may be formed in multiple RDLs of an IC package;

[0022] Figure 7B is a side view of another exemplary IC package including an impedance tuner circuit including Fig. 7A Tunable inductor in;

[0023] Fig. 8A is a perspective view of another exemplary 3D tunable inductor that may be formed in multiple RDLs of an IC package;

[0024] Figure 8B is a side view of another exemplary IC package including an impedance tuner circuit including Fig. 8A Tunable inductor in;

[0025] Fig. 9 is a flow chart illustrating an exemplary process of manufacturing an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate, wherein the tunable inductor includes one or more shunt taps configured to be shunted by corresponding switches coupled to the impedance tuner circuit in a die of the package substrate;

[0026] FIG. 10A to FIG. 10D is a flow chart illustrating another exemplary manufacturing process for manufacturing an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate, wherein the tunable inductor includes one or more shunt taps configured to shunt current through corresponding switches coupled to the impedance tuner circuit in a die of the package substrate, including but not limited to FIG. 3A to FIG. 4 and FIG. 6A to FIG. 8B IC packages in;

[0027] FIG. 11A to FIG. 11G Illustrated based on FIG. 10A to FIG. 10D exemplary manufacturing stages of an exemplary IC package manufacturing process in; and

[0028] Fig.12 is a block diagram of an exemplary wireless communication device that may include an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate of the IC package, including but not limited to FIG. 3A to FIG. 4 , FIG. 6A to FIG. 8B and FIG. 11A to FIG. 11G IC package. DETAILED DESCRIPTION

[0029] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0030] Various aspects disclosed herein include an integrated circuit (IC) package that employs an on-package tunable inductor formed in a redistribution layer (RDL) for an impedance tuner circuit. Related methods are also disclosed. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. In order to reduce the circuit area required to provide the tunable inductor, the tunable inductor is integrated in the IC package. In an exemplary aspect, the tunable inductor is formed in the RDL of a packaging substrate of the IC package. The IC package also includes a semiconductor die ("die") that includes other components of the impedance tuner circuit coupled to the tunable inductor by coupling the die to the packaging substrate. In this way, by forming a tunable inductor in the RDL in the packaging substrate, the signal path length between the tunable inductor and other components of the tunable impedance circuit is reduced, thereby reducing the inductance path resistance and improving the quality (Q) factor of the tunable inductor. Furthermore, by forming the tunable inductor in the RDL of the IC package, the tunable inductor can be formed to have a desired geometry to provide a desired inductance frequency response.

[0031] In an exemplary aspect, a tunable inductor may be formed in an RDL of a packaging substrate of an IC package as a metal line having a first terminal and a second terminal, which metal line may be coupled to a circuit to couple the inductance of the tunable inductor to the circuit. The tunable inductor is also formed in the RDL to have one or more shunt taps. The shunt taps are two metal lines formed in the tunable inductor, which have ends adjacent to each other but form a short circuit. One or more switches in an active semiconductor layer in a front end process (FEOL) of a die as part of an impedance tuner circuit are coupled to corresponding shunt taps in the tunable inductor through a signal path routed between the die in the packaging substrate and the tunable inductor in the RDL. The switches in the die may be programmed / controlled to shunt the shunt taps or to keep their corresponding coupled shunt taps as an open circuit so as to change the inductance of the inductor and shift the frequency response of the impedance tuner circuit. In this way, the switch allows the inductance of the inductor to be tuned by controlling the shunting or non-shunting of one or more shunt taps in the inductor. The tunable inductor disposed in the RDL in the packaging substrate of the IC package positions the shunt taps closer to the corresponding switches in the die to reduce the inductor path length, thereby reducing resistance and improving the inductor Q factor. Moreover, because the inductor is formed as a metal line in the RDL, the inductor and its shunt taps can be formed in the RDL as part of manufacturing the packaging substrate to have a desired geometry and connectivity arrangement to provide the desired inductance tunability of the inductor.

[0032] In from Figure 3A Before discussing examples of IC packages that employ on-package tunable inductors formed in redistribution layers (RDLs) for impedance tuner circuits, the following first describes Figures 1 to 2B An exemplary impedance tuner circuit and its performance in FIG.

[0033] In this regard, Figure 1 FIG. 1 is a schematic diagram of an exemplary impedance tuner circuit 100 that may be employed in an RF transceiver circuit. The impedance tuner circuit 100 includes a switchable inductor L 1 -L 4 , each of the switchable inductors can be switched by a corresponding switch SW included in the impedance tuner circuit 100 1 -SW 4 can be individually selected to change the frequency response of the impedance tuner circuit 100. Figure 1 As shown, the impedance tuner circuit 100 includes an input node 102 configured to receive a radio frequency (RF) signal 104 and an output node 106. The impedance tuner circuit 100 depends on a passive filtering component (including a switchable inductor L 1 -L 4) filters the RF signal 104 received at the input node 102 into a filtered RF signal 104F at the output node 106. In this regard, the impedance tuner circuit 100 has a signal path 108 between the input node 102 and the output node 106, which includes a first variable capacitor C connected in series. 1 The second fixed capacitor C 2 With the first variable capacitor C 1 Connect in parallel. Switch S 5 With variable capacitor C 1 , input node 102 and output node 106 are connected in parallel. When switch S 5 When closed, the input node 102 is shorted to the output node 106, thereby allowing the RF signal 104 to bypass the variable capacitor C 1 and fixed capacitor C 2 When the switch S 5 When disconnected, the variable capacitor C 1 and fixed capacitor C 2 Present in signal path 108, thereby facilitating filtering of RF signal 104 into filtered RF signal 104F.

[0034] Continue to refer Figure 1 , the impedance tuner circuit 100 includes an inductor L 1 -L 4 The inductor L is connected in series between the corresponding input node 102 and the output node 106. 1 -L 4 Switch S 1 -S 4 In this regard, when the switch S 1 -S 4 When any one of them is closed, its corresponding coupled inductor L 1 -L 4 are connected in parallel to the respective input node 102 and the output node 106, thereby affecting the filtering of the RF signal 104 into a filtered RF signal 104F. 1 -S 4 When any one of them is disconnected, its corresponding coupled inductor L 1 -L 4 The impedance tuner circuit 100 is disconnected from the corresponding input node 102 and the output node 106, and thus does not affect the filtering of the RF signal 104 into the filtered RF signal 104F. Therefore, the frequency response of the impedance tuner circuit 100 can be based on selectively controlling the switch S 1 -S 5 The ability to open or close can be programmed.

[0035] Figure 2A and Figure 2B are respectively exemplified as Figure 1 The inductor L in the impedance tuner circuit 100 1 Graphs 200 , 202 of inductance and quality (Q) factor as a function of frequency of an inductive path. Figure 2A Curve 204 in graph 200 in FIG. 2 illustrates the situation in which the switch SW is not present. 1 And the inductor L 1 The current from the inductor L as a function of frequency (f) when coupled directly to the input node 102 1 The inductance (L) at the input node 102 of the impedance tuner circuit 100 is denoted as follows. Figure 2B Curve 206 in graph 202 in FIG. 2 illustrates the relationship between the presence of a closed switch SW 1 Thus, through the switch SW 1 The inductor L 1 The coupling to the input node 102 produces an increase in the inductance at the input node 102 . Figure 2B Curve 208 in graph 202 in FIG. 200 illustrates the situation in which the switch SW is not present. 1 And the inductor L 1 The current from the inductor L as a function of frequency (f) when coupled directly to the input node 102 1 The quality (Q) factor of the inductance (L) at the input node 102 of the impedance tuner circuit 100 is denoted as FIG. Figure 2B Curve 208 in graph 202 in FIG. 200 illustrates the situation in which the switch SW is not present. 1 And the inductor L 1 The current from the inductor L as a function of frequency (f) when coupled directly to the input node 102 1 The quality (Q) factor of the inductance (L) at the input node 102 of the impedance tuner circuit 100 is shown in FIG. 210 . The curve 210 illustrates the quality (Q) factor of the inductance (L) at the input node 102 of the impedance tuner circuit 100 according to the presence of a closed switch SW 1 And through the switch SW 1 The inductor L 1 The Q factor of the inductor (L) coupled to the input node 102 is generated at the input node 102. Therefore, when the inductor L 1 The curve 208 from the inductor L when directly coupled to the input node 102 1 The Q factor of the impedance at the input node 102 is compared, as Figure 2B As shown in the curve 210, the inductor L 1 The Q factor of the impedance at the input node 102 is due to the switch SW 1 decreases due to its existence.

[0036] therefore, Figure 1 The switch SW in the impedance tuner circuit 100 1Provides the inductor L 1 The inductor of the switch SW is selectively coupled or uncoupled to the input node 102 for tuning the frequency response of the impedance tuner circuit 100. However, the switch SW 1 The presence of the input node 102 increases the inductor L 1 The path length between the two is due to the inductor L 1 The increase in resistance in the inductive path causes the inductor L at the input node 102 to 1 The Q factor is reduced. Since the inductor L 1 -L 4 The size, Figure 1 The inductor L in the impedance tuner circuit 100 1 -L 4 Located including switch SW 2 -SW 4 and Figure 1 The other components of the impedance tuner circuit 100 are external to the IC package 112. Also, the switch SW 1 The loss in the input node 102 causes the inductor L 1 The Q factor is reduced. Figure 1 The corresponding switch SW in the impedance tuner circuit 100 2 -SW 4 The presence of the inductor L at the corresponding input node 102 and output node 106 also occurs 2 -L 4 It is desirable to reduce these losses to improve impedance tuner circuits such as Figure 1 The Q factor of the inductor in the impedance tuner circuit 100) can be increased without losing the ability to select the tuning inductor to tune the frequency response of the impedance tuner circuit 100.

[0037] In this regard, Figure 3A and Figure 3B 3 is a side view of an IC package 300 including an impedance tuner circuit 302 including a tunable inductor 304 (“inductor 304 ”) formed in an RDL 306 of a package substrate 308 . Figure 3A is a functional diagram of the IC package 300 . Figure 3B is from Figure 3A Cross-section line A 1 -A 1' is a schematic diagram of a side view of the IC package 300 viewed from above. As discussed in more detail below, the inductor 304 can be tuned to change the inductance and frequency response of the impedance tuner circuit 302. The inductor 304 is integrated into the IC package 300, and more particularly, integrated into the RDL 306 of the packaging substrate 308 of the IC package 300. The RDL can be an additional metallization layer formed in the packaging substrate that includes formed metal lines for redistributing metal pads to make external connections to other locations in the packaging substrate. The manufacturing techniques used to form metal lines in the RDL can also be used to form the inductor 304 in the RDL 306 of the packaging substrate 308 of the IC package 300. As shown in FIG. Figure 3B As shown, the impedance tuner circuit 302 can be completely disposed within the IC package 300 by forming the inductor 304 in the RDL 306 of the package substrate 308 of the IC package 300. The IC package 300 can be coupled to a printed circuit board (PCB) 310 via external interconnects 312 (e.g., solder balls) coupled to the package substrate 308 to couple the impedance tuner circuit 302 to other circuits coupled to the PCB 310.

[0038] Continue to refer Figure 3A and Figure 3B As also discussed in more detail below, the inductor 304 in the RDL 306 of the package substrate 308 is coupled to switches 314(1), 314(2) formed in the die 316 of the IC package 300. Figure 3B Cross-section line A 1 -A 1 ' side view, Figure 3B Only shown Figure 3A314(1), 314(2). The opening and closing of the switches 314(1), 314(2) are controllable to selectively shunt or unshunt corresponding shunt taps 318(1), 318(2) formed in the inductor 304 to shift the inductance frequency response of the impedance tuner circuit 302. In this example, two shunt taps 318(1), 318(2) are formed in the inductor 304, but it is noted that one (1) or more than two (2) shunt taps may be formed in the inductor 304. The number of shunt taps formed in the inductor 304 affects the number of programmable settings for inductance shifting the inductance frequency response of the inductor 304. In this manner, by forming the inductor 304 in the RDL 306 of the package substrate 308 of the IC package 300, the signal path length between the inductor 304 and the corresponding switches 314(1), 314(2) is reduced, thereby reducing the inductive path resistance of the shunt taps 318(1), 318(2) and improving the Q factor of the inductor 304. Moreover, as discussed in more detail below, by forming the inductor 304 in the RDL 306 of the IC package 300, the inductor 304 can be formed to have a desired geometry to provide a desired inductive frequency response. In this example, because the inductor 304 is formed in a single RDL 306 of the IC package 300, the inductor 304 is a two-dimensional (2D) inductor 304.

[0039] Continue to refer Figure 3A and Figure 3B In this example, an inductor 304 formed in an RDL 306 of a package substrate 308 of an IC package 300 is formed as a metal line 320 having a first terminal 322(1) and a second terminal 322(2) that is coupled to the impedance tuner circuit 100. Shunt taps 318(1), 318(2) are both coupled in parallel to the first terminal 322(1) and the second terminal 322(2). The shunt taps 318(1), 318(2) are each formed by two (2) corresponding shunt metal lines 324(1)-324(2), 326(1)-326(2) that are formed in the inductor 304 and have first and second ends 328(1)-328(2) and first and second ends 330(1)-330(2) that are adjacent to each other but form a short circuit. As shown in FIG. Figure 3AAs shown, switches 314(1), 314(2) in an active semiconductor layer 332 in a front end of line (FEOL) 334 of a die 316 as part of an impedance tuner circuit 302 are coupled to respective ends 328(1)-328(2), 330(1)-330(2) of respective shunt taps 318(1), 318(2) in an inductor 304. The switches 314(1), 314(2) each include respective first and second switch terminals 331(1)-331(2), 333(1), 333(2) coupled to respective first and second ends 328(1)-328(2) of respective shunt taps 318(1)-318(2) and first and second ends 330(1)-330(2). As shown in FIG. Figure 3A and Figure 3B As shown, switches 314(1), 314(2) are coupled to respective ends 328(1)-328(2), 330(1)-330(2) of respective shunt taps 318(1), 318(2) via signal paths routed between die 316 in package substrate 308 and inductor 304 in RDL 306. In this example, Figure 3B As shown, the package substrate 308 includes a metallization layer 336 adjacent to the RDL 306 and disposed in the vertical direction (Z-axis direction) between the RDL 306 and the die 316. The metallization layer 336 includes metal interconnects located behind metal interconnects 338(1), 338(2) in the Y-axis direction, which are coupled to the respective ends 328(1)-328(2), 330(1)-330(2) of the respective shunt taps 318(1), 318(2) and to the die interconnect 340 of the die 316, which is coupled to the respective switches 314(1), 314(2) to couple the shunt taps 318(1), 318(2) of the inductor 304 to the switches 314(1), 314(2).

[0040] In this way, Figure 3A and Figure 3BAs shown, the switches 314(1), 314(2) in the die 316 can be programmed / controlled to shunt the shunt taps 318(1), 318(2) or to maintain their corresponding coupled shunt taps 318(1), 318(2) in an open circuit or a mixture thereof to shift the inductance of the inductor 304 and its inductance frequency response in the impedance tuner circuit 302. In this manner, the switches 314(1), 314(2) allow the inductance of the inductor 304 to be tuned by controlling whether one or more of the shunt taps 318(1), 318(2) in the inductor 304 is shunted or not. The inductor 304 disposed in the RDL 306 in the packaging substrate 308 of the IC package 300 positions the shunt taps 318(1), 318(2) closer to the corresponding switches 314(1), 314(2) in the die 316 to reduce the inductive path length, thereby reducing the resistance and improving the inductive Q factor of the inductor 304. Moreover, because the inductor 304 is formed as a metal line 320 in the RDL 306, the inductor 304 and its shunt taps 318(1), 318(2) can be formed in the RDL 306 with a desired geometry and connectivity arrangement as part of manufacturing the packaging substrate 308 to provide a desired inductive tunability of the inductor 304.

[0041] It should be noted that the metal lines 342(1), 342(2) in the inductor 304 can be classified as shunt taps, where switches can be coupled to the metal lines 342(1), 342(2) to control the shunting of the metal lines 342(1), 342(2). The shunting of the inductor 304 can be controlled to control the inductance while having two (2) terminal connections to the circuit depending on the circuit in which the inductor 304 is included. It should be noted that as Figure 3A As shown, the first terminal 322 (1) and the second terminal 322 (2) are formed along the longitudinal axis L 1 The shunt taps 318(1), 318(2) are each arranged along a direction parallel to the longitudinal axis L. 1 The longitudinal axis L 2 , L 3 However, as discussed in other examples of tunable inductors below, the shunt taps in the tunable inductor may extend on non-parallel axes to the metal lines in which the first and second terminals of the tunable inductor are formed.

[0042] Figure 4 Yes Figure 3A and Figure 3B FIG. 3 is a circuit diagram of an impedance tuner circuit 302 of an inductor 304 in an IC package 300. Figure 4As shown, the impedance tuner circuit 302 includes an input node 400 configured to receive an RF signal 402 and an output node 404 configured to provide a filtered RF signal 402F. The die 316 includes switches 314(1), 314(2) as part of the impedance tuner circuit 302, which are coupled to respective shunt taps 318(1), 318(2) of the tunable inductor 304 in the package substrate 308. The optional external inductor L 5 Coupled to first terminal 322(1). Optional resistor R 1 318(1), 318(2) is coupled to the second terminal 322(2) of the inductor 304. The switch 314(3) is coupled to the shunt tap 318(1) and the first node 406(1). The switch 314(4) is coupled to the shunt tap 318(2) and the second node 406(2). The switches 314(1), 314(2) can be controlled to be open or closed so as to not shunt or shunt the corresponding shunt tap 318(1), 318(2) in the inductor 304 to shift the inductance frequency response of the inductor 304. The impedance tuner circuit 302 also includes a variable capacitor C 3 , the variable capacitor is configured to be selectively coupled in series or bypassed between the input node 400 and the output node 404 .

[0043] Figure 5A and Figure 5B are respectively exemplified as FIG. 3A to FIG. 4 Graphs 500 , 502 of inductance and Q factor as a function of frequency of the inductive path of the inductor 304 in the impedance tuner circuit 302 . Figure 5A Curves 504(1)-504(4) in graph 500 in FIG. 5 illustrate the frequency of the current as a function of the frequency based on the combination of on (“1”) and off (“0”) states of switches 314(1), 314(2) coupled to shunt taps 318(1), 318(2). Figure 4 The inductance (L) of the impedance tuner circuit 302 is shown in the figure. Figure 5A As shown, control of switches 314 ( 1 ), 314 ( 2 ) in different on / off states shifts the inductance (L) of the impedance tuner circuit 302 . Figure 5A Curve 504(5) in graph 500 in FIG. 5 illustrates the effect of the inductor L on the 5 (without inductor 304) as a function of frequency Figure 4 The inductance (L) at the input node 400 of the impedance tuner circuit 302 in FIG.

[0044] Figure 5B Curves 506(1)-506(4) in graph 502 in FIG. 506 illustrate the Figure 2AThe Q factor of the inductance (L) of the impedance tuner circuit 100 from the inductor 304 as a function of the frequency (f) for the same combination of on (“1”) and off (“0”) of the switches 314 (1), 314 (2) associated with the corresponding inductance curves 504 (1)-504 (4) in FIG. Figure 5B As shown, control of switches 314 ( 1 ), 314 ( 2 ) in different on / off states shifts the inductance (L) of the impedance tuner circuit 302 . Figure 5B Curve 506(5) in graph 502 in FIG. 5 illustrates the effect of the inductor L on the 5 (without inductor 304) as a function of frequency Figure 4 5. The Q factor of the inductance (L) of the impedance tuner circuit 302 in FIG. 5. It should be noted that the Q factor in curves 506(1)-506(4) is higher compared to curve 506(5).

[0045] Fig. 6A is a perspective view of another exemplary 2D tunable inductor 604 (“inductor 604 ”) that may be formed in an RDL of an IC package. Figure 6B is included with Figure 3B 8 is a side view of another exemplary IC package 600 having an impedance tuner circuit 602 that is similar to the impedance tuner circuit 302 in the IC package 300 in FIG. Figure 6B The IC package 600 in FIG. 6 includes an RDL 606 including Fig. 6A Inductor 604 in. Figure 6B is from Fig. 6A The cross-sectional line A of the inductor 604 in FIG. 2 -A 2 'A schematic diagram of a side view of IC package 600 as viewed. Figure 3B The IC package 300 and Figure 6B The common elements between the IC packages 600 in FIG. 1 are shown with common element numbers and are not described again. Fig. 6A As shown, Figure 3A and Figure 3B Similar to the inductor 304 in FIG. 1 , the first terminal 322 ( 1 ) and the second terminal 322 ( 2 ) of the inductor 604 are formed along the longitudinal axis L 1 In the corresponding metal lines 342 (1), 342 (2) extending in the X-axis direction. Fig. 6A As shown in FIG. 1 , in this example of the inductor 604, its shunt taps 618 ( 1 ), 618 ( 2 ) are each oriented along the longitudinal axis L 1 Orthogonal longitudinal axis L 4 , L 5 By extension, this Figure 3A and Figure 3BThe opposite is true for the parallel inductor 304 in FIG.

[0046] refer to Fig. 6A and Figure 6B , the inductor 604 in the RDL 606 of the package substrate 608 is coupled to the switches 314(1), 314(2) formed in the die 316 of the IC package 600. Figure 6B The cross-sectional line A of the inductor 604 in FIG. 2 -A 2 ' side view, Figure 6B Only shown Figure 3A Schematic diagram of switch 314(1) of switches 314(1), 314(2) is shown. The opening and closing of switches 314(1), 314(2) are controllable to selectively shunt or unshunt corresponding shunt taps 618(1), 618(2) formed in inductor 604 to shift the inductance frequency response of impedance tuner circuit 302.

[0047] like Fig. 6A As shown, an inductor 604 formed in an RDL 606 of a package substrate 608 of an IC package 600 is formed as a metal line 620 having a first terminal 322(1) and a second terminal 322(2) coupled to an impedance tuner circuit 602. In this example, shunt taps 618(1), 618(2) are each coupled in series to the first terminal 322(1) and the second terminal 322(2). The shunt taps 618(1), 618(2) are each formed by two (2) corresponding shunt metal lines 624(1)-624(2), 626(1)-626(2) formed in the inductor 604 and having first and second ends 628(1)-628(2) and first and second ends 630(1)-630(2) adjacent to each other but forming a short circuit. The switches 314(1), 314(2) are coupled to respective ends 628(1)-628(2), 630(1)-630(2) of respective shunt taps 618(1), 618(2) via signal paths routed between the die 316 in the package substrate 608 and the inductor 604 in the RDL 606. The switches 314(1), 314(2) in the die 316 can be programmed / controlled to shunt the shunt taps 618(1), 618(2) or to maintain their respective coupled shunt taps 618(1), 618(2) in an open circuit or a mixture thereof to shift the inductance of the inductor 604 and its inductive frequency response in the impedance tuner circuit 602.

[0048] It should be noted that similar to Figure 3A and Figure 3BInductor 304 in FIG. 6A , metal lines 342(1), 324(2) in inductor 604 may be classified as shunt taps, where switches may be coupled to metal lines 342(1), 342(2) to control the shunting of metal lines 342(1), 342(2). The shunting of inductor 604 may be controlled depending on the circuit in which inductor 604 is included to control the inductance while having two (2) terminal connections to the circuit.

[0049] Fig. 7A is a perspective view of an exemplary 3D tunable inductor 704 (“inductor 704 ”) that may be formed in multiple RDLs of an IC package. Figure 7B is included with Figure 3B 3. A side view of another exemplary IC package 700 having an impedance tuner circuit 702 similar to the impedance tuner circuit 302 in the IC package 300 in FIG. Figure 7B The IC package 700 includes the RDL 306 and includes Fig. 7A An additional RDL 706 for the inductor 704 in FIG. Figure 7B is from Fig. 7A The cross-sectional line A of the inductor 704 in FIG. 3 -A 3 'A schematic diagram of a side view of IC package 700 as viewed. Figure 7B The IC package 700 and Figure 3B Common elements between the IC packages 300 in FIG. 1 are shown with common element numbers and are not described again. Fig. 7A The inductor 704 in is similar to Figure 3A and Figure 3B However, as discussed below and as Fig. 7A and Figure 7B As shown, the inductor 704 also includes an additional shunt tap 718 disposed in a second RDL 706 adjacent to the first RDL 306 in the package substrate 708 of the IC package 700. Fig. 7A As shown, in this example of the inductor 704, the shunt tap 718 disposed in the second RDL 706 is disposed along the longitudinal axis L between the first terminal 322(1) and the second terminal 322(2). 1 Intersecting longitudinal axis L 6 extend.

[0050] refer to Fig. 7A and Figure 7B , the inductor 704 in the RDL 306, 706 of the package substrate 708 is coupled to the switches 314(1), 314(2) formed in the die 316 of the IC package 700. Figure 7B The cross-sectional line A of the inductor 704 in FIG. 3-A 3 ' side view, Figure 7B Only switch 314(1) of the switches 314(1), 314(2) is shown. An additional switch 714 disposed in die 316 is coupled to a third shunt tap 718 of inductor 704. The opening and closing of switches 314(1), 314(2), 714 are controllable to selectively shunt or unshunt the corresponding shunt tap 318(1), 318(2), 718 formed in inductor 704 to shift the inductance frequency response of impedance tuner circuit 702.

[0051] like Fig. 7A As shown, the inductor 704 formed in the RDL 306, 706 of the package substrate 708 of the IC package 700 is formed as a corresponding metal line 320 having a first terminal 322(1) and a second terminal 322(2) and a metal line 720 coupled to the impedance tuner circuit 702. In this example, a shunt tap 718 is coupled in parallel to the first terminal 322(1) and the second terminal 322(2) of the inductor 704. The shunt tap 718 is formed by two (2) shunt metal lines 724(1), 724(2) formed in the inductor 704 and having a first end 728(1) and a second end 728(2) adjacent to each other but forming a short circuit. Vias 730(1), 730(2) couple the corresponding first end 728(1) and the second end 728(2) of the shunt tap 718 to the corresponding first terminal 322(1) and the second terminal 322(2). The switches 714 are coupled to respective ends 728(1), 728(2) of the shunt taps 718 via signal paths routed between the die 316 in the package substrate 708 and the inductor 704 in the first RDL 306 and the second RDL 706. The switches 314(1), 314(2), 714 in the die 316 can be programmed / controlled to shunt the shunt taps 318(1), 318(2), 718 or to maintain their respective coupled shunt taps 318(1), 318(2), 718 in an open circuit or a mixture thereof to shift the inductance of the inductor 704 and its inductive frequency response in the impedance tuner circuit 702.

[0052] It should be noted that the metal lines 342(1), 324(2) in the inductor 704 can be classified as shunt taps, where switches can be coupled to the metal lines 342(1), 342(2) to control the shunting of the metal lines 342(1), 342(2). The shunting of the inductor 704 can be controlled depending on the circuit in which the inductor 704 is included to control the inductance while having two (2) terminal connections to the circuit.

[0053] Fig. 8Ais a perspective view of another exemplary 3D tunable inductor 804 (“inductor 804 ”) that may be formed in multiple RDLs of an IC package. Figure 8B is included with Figure 7B 8 is a side view of another exemplary IC package 800 having an impedance tuner circuit 802 that is similar to the impedance tuner circuit 302 in the IC package 700 . Figure 8B The IC package 800 includes the RDL 306 and includes Fig. 8A An additional RDL 806 for the inductor 804 in FIG. Figure 8B is from Fig. 8A The cross-sectional line A of the inductor 804 in FIG. 4 -A 4 'A schematic diagram of a side view of IC package 800 as viewed. Figure 8B The IC package 800 and Figure 3B and Figure 7B Common elements between the IC packages 300 , 700 are shown with common element numbers and are not described again. Fig. 8A The inductor 804 in is similar to Figure 3B and Figure 7B However, as discussed below and as Fig. 8A and Figure 8B As shown, the inductor 804 also includes two additional shunt taps 818 (1), 818 (2), which are disposed in a second RDL 806 adjacent to the first RDL 306 in the package substrate 808 of the IC package 800. Fig. 8A As shown, in this example of the inductor 804, the shunt taps 818(1), 818(2) disposed in the second RDL 806 are arranged along a longitudinal axis L parallel to the shunt taps 318(1), 318(2). 7 , L 8 The longitudinal axis L 7 , L 8 extend.

[0054] refer to Fig. 8A and Figure 8B , the inductor 804 in the RDL 306, 806 of the package substrate 808 is coupled to the switches 314(1), 314(2), 814(1), 814(2) formed in the die 316 of the IC package 800. Figure 8B The cross-sectional line A of the inductor 804 in FIG. 4 -A 4 ' side view, Figure 7BOnly switch 314(1) is shown among switches 314(1), 314(2), 814(1), 814(2). Switches 814(1), 814(2) disposed in die 316 are coupled to third shunt taps 818(1) and fourth shunt taps 818(2) of inductor 804 in second RDL 806. The opening and closing of switches 314(1), 314(2), 814(1), 814(2) are controllable to selectively shunt or not shunt the corresponding shunt taps 318(1), 318(2), 818(1), 818(2) formed in inductor 804 to shift the inductance frequency response of impedance tuner circuit 802.

[0055] like Fig. 8A As shown, an inductor 804 formed in an RDL 306, 806 of a package substrate 808 of an IC package 800 is formed as a metal line 320 having a first terminal 322(1) and a second terminal 322(2) and a metal line 820 coupled to an impedance tuner circuit 802. In this example, shunt taps 818(1), 818(2) are coupled in parallel to the first terminal 322(1) and the second terminal 322(2) of the inductor 804. The shunt taps 818(1), 818(2) are formed by two (2) respective shunt metal lines 824(1)-824(2), 826(1)-826(2) formed in the inductor 804 and having first and second ends 828(1)-828(2), 830(1)-830(2) adjacent to each other but forming a short circuit. The via 830 couples the respective first terminal 322(1) to the metal line 820 in the second RDL 806. The switches 814(1), 814(2) are coupled to respective ends 828(1)-828(2), 830(1)-830(2) of the respective shunt taps 818(1), 818(2) through signal paths routed between the die 316 in the package substrate 808 and the inductor 804 in the first RDL 306 and the second RDL 806. The switches 314(1), 314(2), 814(1), 814(2) in die 316 may be programmed / controlled to shunt taps 318(1), 318(2), 818(1), 818(2) or to maintain their corresponding coupled shunt taps 318(1), 318(2), 818(1), 818(2) as an open circuit or a mixture thereof to shift the inductance of inductor 804 and its inductance frequency response in impedance tuner circuit 802.

[0056] It should be noted that the metal lines 342(1), 324(2) in the inductor 804 can be classified as shunt taps, where switches can be coupled to the metal lines 342(1), 342(2) to control the shunting of the metal lines 342(1), 342(2). The shunting of the inductor 804 can be controlled depending on the circuit in which the inductor 804 is included to control the inductance while having two (2) terminal connections to the circuit.

[0057] Fig. 9 1 is a flow chart illustrating an exemplary manufacturing process 900 for manufacturing an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate. The tunable inductor includes one or more shunt taps configured to shunt current through corresponding switches disposed in a die coupled to the package substrate. Figure 3A and Figure 3B The process 900 is discussed in detail with reference to the IC package 300 in FIG. 1 , but it should be noted that the process 900 is not limited to Figure 3A and Figure 3B The IC package 300 in FIG. Fig. 9 The process 900 may be used to manufacture FIG. 6A to FIG. 8B IC packages 600, 700 and 800 in FIG.

[0058] In this regard, if Fig. 9 As shown, the first step of the manufacturing process 900 is to form a first switch 314 (1) in the tube die 316 ( Fig. 9 The next step in the manufacturing process 900 is to form the inductor 304 in the packaging substrate 308 ( Fig. 9 904 in the figure). Forming the inductor 304 may include the following steps: forming a first metal line 320 in the RDL 306 of the package substrate 308, the first metal line 320 including a first terminal 322 (1) and a second terminal 322 (2) ( Fig. 9 906 in the block); and forming a first shunt tap 318(1) in the RDL 306, the first shunt tap 318(1) coupled to the first terminal 322(1) and the second terminal 322(2) ( Fig. 9 The next step in the manufacturing process 900 is to couple the die 316 to the packaging substrate 308 ( Fig. 9 The next step in the manufacturing process 900 is to couple the first switch 314(1) to the first shunt tap 318(1) ( Fig. 9 912 in the figure).

[0059] An IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate may be manufactured in other manufacturing processes, including but not limited to FIG. 3A to FIG. 3B and FIG. 6A to FIG. 8B The IC packages 300, 600, 700 and 800 in FIG. FIG. 10A to FIG. 10D is a flow chart illustrating an exemplary manufacturing process 1000 for manufacturing an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate. FIG. 11A to FIG. 11G Illustrated based on FIG. 10A to FIG. 10D 1000A-1100G of the exemplary manufacturing process 1000. Figure 3A and Figure 3B Discussion of IC Package 300 FIG. 10A to FIG. 10D The manufacturing process 1000 in the present invention is not limited to manufacturing Figure 3A and Figure 3B The IC package 300 in FIG.

[0060] In this regard, if Fig.11A As shown in the exemplary manufacturing stage 1100A in FIG. 1 , the first step of the manufacturing process 1000 may be to produce a die 316 and form switches 314 ( 1 ), 314 ( 2 ) ( Fig. 10A Then, as in box 1002 in FIG. Fig. 11B As shown in the exemplary manufacturing stage 1100B in FIG. 1 , the next step in the manufacturing process 1000 may be to form a metal interconnect 1102 in the metallization layer 1104 of the die 316 coupled to the switches 314 ( 1 ), 314 ( 2 ), and then to form a die interconnect 340 ( Fig. 10A Some of the die interconnects 340 are coupled to metal interconnects 1102, which are coupled to switches 314(1), 314(2) to provide signal routing paths between switches 314(1), 314(2) and shunt taps 318(1), 318(2) in the package substrate 308 to which the die 316 is to be coupled.

[0061] like Fig. 11C As shown in the exemplary manufacturing stage 1100C in FIG. 1 , the next step in the manufacturing process 1000 may be to Figure 3B The inductor 304 is formed in the RDL 306 of the package substrate 308 of the IC package 300 ( Fig. 10A The packaging substrate 308 is Fig. 11C Not shown, but in Figure 3BThe inductor is formed by forming a metal line 320 having a first terminal 322 (1) and a second terminal 322 (2). Then, as shown in FIG. Fig.11D As shown in the exemplary manufacturing stage 1100D in FIG. 1 , the next step in the manufacturing process 1000 may be to form shunt taps 318 ( 1 ), 318 ( 2 ) in the inductor 304 ( Fig. 10B Box 1008 and Fig. 10C In the box 1010 in Fig.11D In the manufacturing stage 1100D of FIG. 1 , only the first shunt tap 318 ( 1 ) is shown as being formed in the inductor 304 , but it should be noted that in Fig.11E In the manufacturing stage 1100E, the second shunt tap 318 (2) may also be formed as shown. Fig.11D As shown, the shunt tap 318(1) is formed by forming shunt metal lines 324(1), 324(2) coupled to respective first and second terminals 322(1), 322(2), wherein the ends 328(1), 328(2) of the shunt metal lines are adjacent to each other. The second shunt tap 318(2) is similarly formed in the inductor 304, as shown in FIG. Fig.11E Thus, when the die 316 is coupled to the package substrate 308 including the RDL 306 having the inductor 304, the die interconnect 340 coupled to the switches 314(1), 314(2) is coupled to the respective shunt taps 318(1), 318(2) of the inductor.

[0062] Then, if Fig.11F As shown in the exemplary manufacturing stage 1100F in FIG. 1 , the next step in the manufacturing process 1000 is to couple the die 316 to the packaging substrate 308 to couple the switches 314 ( 1 ), 314 ( 2 ) in the die 316 to the corresponding shunt taps 318 ( 1 ), 318 ( 2 ) in the RDL 306 of the packaging substrate 308 ( Fig. 10C Then, as in box 1012. Fig.11G As shown in the exemplary manufacturing stage 1100G in FIG. 1 , the next step in the manufacturing process 1000 is to form an external interconnect 312 coupled to the package substrate 308 and to mount the IC package 300 to the PCB 310 ( Fig. 10D It should be noted that the external inductor 1106 may also be coupled to the PCB 310 and coupled to the impedance tuner circuit 302 in the IC package 300 via metal lines routed through the PCB 310 and to the external interconnects 312.

[0063] The term "coupled" as used herein may refer to electrical coupling and / or physical coupling. Fig. 9 and FIG. 10A to FIG. 10DThe exemplary manufacturing processes 900, 1000 of the present invention and according to any aspect disclosed herein, an IC package including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate can be provided in or integrated into any electronic device, the IC package including but not limited to FIG. 3A to FIG. 3B and FIG. 6A to FIG. 8B 300, 600, 700, and 800 in the IC packages 300, 600, 700, and 800. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0064] In this regard, Fig.12 An exemplary wireless communication device 1200 is illustrated as an electronic device including RF components formed of one or more integrated circuits (ICs) 1202, wherein any of the ICs 1202 may be included in an IC package 1203 including an impedance tuner circuit including a tunable inductor formed in an RDL of a package substrate, the IC package including, but not limited to, FIG. 3A to FIG. 3B and FIG. 6A to FIG. 8B The IC packages 300, 600, 700 and 800 in FIG. Fig.12 As shown, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include a memory for storing data and program codes. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 that support two-way communication. In general, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0065] The transmitter 1208 or the receiver 1210 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.12 In the wireless communication device 1200 in FIG. 1 , the transmitter 1208 and the receiver 1210 are implemented using a direct conversion architecture.

[0066] In the transmit path, the data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1), 1212(2) to convert the digital signals generated by the data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0067] Within the transmitter 1208, low pass filters 1214(1), 1214(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1216(1), 1216(2) amplify the signals from the low pass filters 1214(1), 1214(2), respectively, and provide I and Q baseband signals. An up converter 1218 upconverts the I and Q baseband signals with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 1222 via mixers 1220(1), 1220(2) to provide upconverted signals 1224. A filter 1226 filters the upconverted signals 1224 to remove undesired signals caused by the upconversion and noise in the receive band. A PA 1228 amplifies the upconverted signals 1224 from the filter 1226 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1230 and transmitted via an antenna 1232 .

[0068] In the receive path, antenna 1232 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1230 and provided to a low noise amplifier (LNA) 1234. The duplexer or switch 1230 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Down-conversion mixers 1238 (1), 1238 (2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1), 1242(2) and further filtered by low pass filters 1244(1), 1244(2) to obtain I and Q analog input signals, which are provided to the data processor 1206. In this example, the data processor 1206 includes analog-to-digital converters (ADCs) 1246(1), 1246(2) to convert the analog input signals into digital signals to be further processed by the data processor 1206.

[0069] exist Fig.12 In the wireless communication device 1200 of the embodiment of the present invention, the TX LO signal generator 1222 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1222. Similarly, the RX PLL circuit 1250 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1240.

[0070] It will be further understood by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. For example, the master device and slave device described herein may be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0071] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0072] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0073] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operation can be performed in many different orders except for the illustrated order. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. It will be equally understood by those skilled in the art that any of a variety of different technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0074] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0075] Various implementation examples are also described in the following numbered clauses:

[0076] 1. An integrated circuit (IC) package, comprising:

[0077] An impedance tuner circuit, the impedance tuner circuit comprising:

[0078] a first switch; and

[0079] an inductor comprising a first terminal and a second terminal; and

[0080] a packaging substrate comprising a first redistribution layer (RDL), the first RDL comprising the inductor; and

[0081] a die coupled to the package substrate, the die comprising the first switch;

[0082] The inductor comprises:

[0083] a first metal line in the first RDL, the first metal line comprising the first terminal and the second terminal; and

[0084] a first shunt tap in the first RDL, the first shunt tap coupled to the first terminal and the second terminal; and

[0085] A first switch is coupled to the first shunt tap.

[0086] 2. The IC package of clause 1, wherein the first switch is configured to close to shunt the first shunt tap.

[0087] 3. The IC package of clause 1 or 2, wherein the first switch is configured to open to provide an open circuit in the first shunt tap.

[0088] 4. An IC package according to any one of clauses 1 to 3, wherein:

[0089] The first switch includes a first switch terminal and a second switch terminal;

[0090] The first shunt tap comprises:

[0091] a first shunt metal line coupled to the first terminal; and

[0092] a second shunt metal line coupled to the second terminal; and

[0093] The first switch terminal is coupled to the first shunt metal line, and the second switch terminal is coupled to the second shunt metal line.

[0094] 5. The IC package of clause 4, wherein:

[0095] The first shunt metal line includes a first end portion and a second end portion coupled to the first terminal; and

[0096] The second shunt metal line includes a third end coupled to the second terminal and a fourth end adjacent to the second end.

[0097] 6. An IC package according to any one of clauses 1 to 5, wherein:

[0098] The first metal wire extends along a first longitudinal axis; and

[0099] The first splitter tap extends along a second longitudinal axis parallel to the first longitudinal axis.

[0100] 7. An IC package according to any one of clauses 1 to 5, wherein:

[0101] The first metal wire extends along a first longitudinal axis; and

[0102] The first splitter tap extends along a second longitudinal axis orthogonal to the first longitudinal axis.

[0103] 8. An IC package according to any one of clauses 1 to 7, wherein:

[0104] The impedance tuner circuit also includes a second switch; and

[0105] The die also includes the second switch;

[0106] The inductor also includes a second shunt tap coupled to the first terminal and the second terminal; and

[0107] A second switch is coupled to the second shunt tap.

[0108] 9. The IC package of clause 8, wherein:

[0109] The second switch includes a third switch terminal and a fourth switch terminal;

[0110] The second shunt tap comprises:

[0111] a third shunt metal line coupled to the first terminal; and

[0112] a fourth shunt metal line coupled to the second terminal; and

[0113] The third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

[0114] 10. An IC package according to any one of clauses 1 to 10, wherein:

[0115] The impedance tuner circuit also includes a second switch;

[0116] The die also includes the second switch;

[0117] The packaging substrate further includes a second RDL; and

[0118] The inductor further comprises:

[0119] a second shunt tap, the second shunt tap being located in the second RDL;

[0120] a first via coupling the second shunt tap to the first terminal; and

[0121] A second via couples the second shunt tap to the second terminal.

[0122] 11. The IC package of clause 10, wherein:

[0123] The second switch includes a third switch terminal and a fourth switch terminal;

[0124] The second shunt tap comprises:

[0125] a third shunt metal line coupled to the first terminal; and

[0126] a fourth shunt metal line coupled to the second terminal; and

[0127] The third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

[0128] 12. The IC package of clause 10 or 11, wherein:

[0129] The first metal wire extends along a first longitudinal axis;

[0130] The first splitter tap extends along a second longitudinal axis parallel to the first longitudinal axis; and

[0131] The second splitter tap extends along a third longitudinal axis that intersects the first longitudinal axis.

[0132] 13. An IC package according to any one of clauses 1 to 12, wherein:

[0133] The die includes an active semiconductor layer; and

[0134] The first switch is disposed in the active semiconductor layer.

[0135] 14. The IC package of clause 4, wherein:

[0136] the first switch terminal being coupled to a first die interconnect of the die;

[0137] the second switch terminal being coupled to a second die interconnect of the die;

[0138] the first die interconnect is coupled to a first metal interconnect of the package substrate coupled to the first shunt metal line; and

[0139] The second die interconnect is coupled to a second metal interconnect of the package substrate coupled to the second shunt metal line.

[0140] 15. The IC package of clause 14, wherein:

[0141] The packaging substrate includes a metallization layer adjacent to the first RDL; and

[0142] The metallization layer includes the first metal interconnect and the second metal interconnect.

[0143] 16. An IC package according to any one of clauses 1 to 15, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multirotor aircraft.

[0144] 17. A method of manufacturing an integrated circuit (IC) package, comprising:

[0145] forming a first switch in the die;

[0146] An inductor is formed in a package substrate, comprising:

[0147] forming a first metal line of the inductor in the first redistribution layer (RDL) in the package substrate, the first metal line comprising a first terminal and a second terminal; and

[0148] forming a first shunt tap of the inductor in the first RDL, the first shunt tap coupled to the first terminal and the second terminal;

[0149] coupling the die to the packaging substrate; and

[0150] The first switch is coupled to the first shunt tap.

[0151] 18. The method of clause 17, wherein forming the die comprises:

[0152] providing an active semiconductor layer on a substrate; and

[0153] The first switch is formed in the active semiconductor layer.

[0154] 19. The method according to clause 17 or 18, further comprising forming the packaging substrate, the method comprising:

[0155] forming a first metal interconnection of a first shunt metal line coupled to the first shunt tap; and

[0156] forming a second metal interconnect coupled to a second shunt metal line of the first shunt tap; and

[0157] The method further comprises:

[0158] coupling a first die interconnect to a first switch terminal of the first switch;

[0159] coupling a second die interconnect to a second switch terminal of the second switch; and

[0160] Wherein coupling the die to the packaging substrate comprises:

[0161] coupling the first die interconnect to the first metal interconnect; and

[0162] The second die interconnect is coupled to the second metal interconnect.

[0163] 20. A method according to clause 19, wherein:

[0164] Forming the package substrate further includes forming a metallization layer adjacent to the first RDL;

[0165] Forming the first metal interconnect comprises forming the first metal interconnect in the metallization layer; and

[0166] Forming the second metal interconnect includes forming the second metal interconnect in the metallization layer.

[0167] 21. A method according to any one of clauses 17 to 20, wherein:

[0168] The first switch includes a first switch terminal and a second switch terminal;

[0169] Forming the first shunt tap comprises:

[0170] forming a first shunt metal line coupled to the first terminal in the first RDL; and

[0171] forming a second shunt metal line coupled to the second terminal in the first RDL; and

[0172] Coupling the die to the packaging substrate comprises:

[0173] The first switch terminal is coupled to the first shunt metal line; and the second switch terminal is coupled to the second shunt metal line.

[0174] 22. The method of any of clauses 17 to 21, wherein forming the inductor in the first RDL further comprises forming a second shunt tap in the first RDL, the second shunt tap coupled to the first terminal and a second terminal; and

[0175] The method further comprises:

[0176] forming a second switch in the die; and

[0177] The second switch is coupled to the second shunt tap.

[0178] 23. The method according to any one of clauses 17 to 22, further comprising:

[0179] forming a second switch in the die; and

[0180] Forming the inductor further includes:

[0181] forming a second shunt tap in a second RDL in the package substrate, the first shunt tap being coupled to the first terminal and the second terminal;

[0182] forming a first via coupling the second shunt tap to the first terminal; and

[0183] forming a second via coupling the second shunt tap to the second terminal; and

[0184] The second switch is coupled to the second shunt tap.

Claims

1. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: An impedance tuner circuit, the impedance tuner circuit comprising: a first switch; and an inductor comprising a first terminal and a second terminal; and a packaging substrate comprising a first redistribution layer (RDL), the first RDL comprising the inductor; and a die coupled to the package substrate, the die comprising the first switch; The inductor comprises: a first metal line in the first RDL, the first metal line comprising the first terminal and the second terminal; and a first shunt tap in the first RDL, the first shunt tap coupled to the first terminal and the second terminal; and The first switch is coupled to the first shunt tap. 2 . The IC package of claim 1 , wherein the first switch is configured to be closed to shunt the first shunt tap. 3 . The IC package of claim 1 , wherein the first switch is configured to be opened to provide an open circuit in the first shunt tap.

4. The IC package of claim 1, wherein: The first switch includes a first switch terminal and a second switch terminal; The first shunt tap comprises: a first shunt metal line coupled to the first terminal; and a second shunt metal line coupled to the second terminal; and The first switch terminal is coupled to the first shunt metal line, and the second switch terminal is coupled to the second shunt metal line.

5. The IC package of claim 4, wherein: The first shunt metal line includes a first end portion and a second end portion coupled to the first terminal; and The second shunt metal line includes a third end coupled to the second terminal and a fourth end adjacent to the second end.

6. The IC package of claim 1, wherein: The first metal wire extends along a first longitudinal axis; and The first splitter tap extends along a second longitudinal axis parallel to the first longitudinal axis.

7. The IC package of claim 1, wherein: The first metal wire extends along a first longitudinal axis; and The first splitter tap extends along a second longitudinal axis orthogonal to the first longitudinal axis.

8. The IC package of claim 1, wherein: The impedance tuner circuit also includes a second switch; and The die also includes the second switch; The inductor also includes a second shunt tap coupled to the first terminal and the second terminal; and The second switch is coupled to the second shunt tap.

9. The IC package of claim 8, wherein: The second switch includes a third switch terminal and a fourth switch terminal; The second shunt tap comprises: a third shunt metal line coupled to the first terminal; and a fourth shunt metal line coupled to the second terminal; and The third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

10. The IC package of claim 1, wherein: The impedance tuner circuit also includes a second switch; The die also includes the second switch; The packaging substrate also includes a second RDL; and The inductor further comprises: a second shunt tap, the second shunt tap being located in the second RDL; a first via coupling the second shunt tap to the first terminal; and A second via couples the second shunt tap to the second terminal.

11. The IC package of claim 10, wherein: The second switch includes a third switch terminal and a fourth switch terminal; The second shunt tap comprises: a third shunt metal line coupled to the first terminal; and a fourth shunt metal line coupled to the second terminal; and The third switch terminal is coupled to the third shunt metal line, and the fourth switch terminal is coupled to the fourth shunt metal line.

12. The IC package of claim 10, wherein: The first metal wire extends along a first longitudinal axis; The first splitter tap extends along a second longitudinal axis parallel to the first longitudinal axis; and The second splitter tap extends along a third longitudinal axis that intersects the first longitudinal axis.

13. The IC package of claim 1, wherein: The die includes an active semiconductor layer; and The first switch is disposed in the active semiconductor layer.

14. The IC package of claim 4, wherein: the first switch terminal being coupled to a first die interconnect of the die; the second switch terminal being coupled to a second die interconnect of the die; the first die interconnect coupled to a first metal interconnect of the package substrate coupled to the first shunt metal line; and The second die interconnect is coupled to a second metal interconnect of the package substrate coupled to the second shunt metal line.

15. The IC package of claim 14, wherein: The packaging substrate includes a metallization layer adjacent to the first RDL; and The metallization layer includes the first metal interconnect and the second metal interconnect.

16. The IC package of claim 1, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

17. A method of manufacturing an integrated circuit (IC) package, the method comprising: forming a first switch in the die; An inductor is formed in a package substrate, comprising: forming a first metal line of the inductor in the first redistribution layer (RDL) in the package substrate, the first metal line comprising a first terminal and a second terminal; and forming a first shunt tap of the inductor in the first RDL, the first shunt tap coupled to the first terminal and the second terminal; coupling the die to the packaging substrate; and The first switch is coupled to the first shunt tap.

18. The method of claim 17, wherein forming the die comprises: An active semiconductor layer is provided on a substrate; as well as The first switch is formed in the active semiconductor layer.

19. The method according to claim 18, further comprising forming the packaging substrate, the method comprising: forming a first metal interconnect coupled to a first shunt metal line of the first shunt tap; as well as forming a second metal interconnect coupled to a second shunt metal line of the first shunt tap; and The method further comprises: coupling a first die interconnect to a first switch terminal of the first switch; coupling a second die interconnect to a second switch terminal of the second switch; and Wherein coupling the die to the packaging substrate comprises: coupling the first die interconnect to the first metal interconnect; and The second die interconnect is coupled to the second metal interconnect.

20. The method of claim 19, wherein: Forming the package substrate further includes forming a metallization layer adjacent to the first RDL; forming the first metal interconnect comprises forming the first metal interconnect in the metallization layer; and Forming the second metal interconnect includes forming the second metal interconnect in the metallization layer.

21. The method of claim 17, wherein: The first switch includes a first switch terminal and a second switch terminal; Forming the first shunt tap comprises: forming a first shunt metal line coupled to the first terminal in the first RDL; and forming a second shunt metal line coupled to the second terminal in the first RDL; and Coupling the die to the packaging substrate comprises: coupling the first switch terminal to the first shunt metal line; and The second switch terminal is coupled to the second shunt metal line.

22. The method of claim 17, wherein forming the inductor in the first RDL further comprises forming a second shunt tap in the first RDL, the second shunt tap coupled to the first terminal and a second terminal; and The method further comprises: forming a second switch in the die; as well as The second switch is coupled to the second shunt tap.

23. The method according to claim 17, further comprising: forming a second switch in the die; and Forming the inductor further includes: forming a second shunt tap in a second RDL in the package substrate, the first shunt tap being coupled to the first terminal and the second terminal; forming a first via coupling the second shunt tap to the first terminal; and forming a second via coupling the second shunt tap to the second terminal; and The second switch is coupled to the second shunt tap.

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