Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a plurality of pixel driving circuits, each pixel driving circuit comprises a second transistor and a driving transistor, the first electrode of the second transistor is connected with the grid electrode of the driving transistor, and the second electrode is connected with the first electrode of the driving transistor; the display panel further comprises a substrate, an active layer, a first metal layer and a second metal layer, the active layer is located on one side of the substrate and comprises a second active part and a third active part, and the second active part is used for forming a channel region of the second transistor; the third active part is connected with the second active part and is used for forming a channel region of the driving transistor; the first metal layer is located between the substrate and the active layer; the second metal layer is located on the side, away from the substrate, of the active layer; wherein the orthographic projection of the first metal layer on the substrate covers the orthographic projection of the second active part and the orthographic projection of the third active part on the substrate, and the orthographic projection of the second metal layer on the substrate at least covers the orthographic projection of the second active part on the substrate.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, and flexibility. OLED displays are increasingly being used, but related technologies have been plagued by color shift issues when exposed to strong light.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, which includes a plurality of pixel driving circuits, wherein the pixel driving circuit includes a second transistor and a driving transistor, wherein the first electrode of the second transistor is connected to the gate electrode of the driving transistor, and the second electrode is connected to the first electrode of the driving transistor; the display panel also includes: a substrate; an active layer located on one side of the substrate, the active layer including: a second active portion for forming a channel region of the second transistor; a third active portion connected to the second active portion, the third active portion being used to form the channel region of the driving transistor; a first metal layer located between the substrate and the active layer; and a second metal layer located on the side of the active layer facing away from the substrate; wherein the orthographic projections of the first metal layer and the second metal layer on the substrate at least partially overlap with the orthographic projections of the second active portion and the third active portion on the substrate.

[0007] In an exemplary embodiment of the present disclosure, the first metal layer is connected to a constant voltage source; the second active portion includes a first sub-active portion and a second sub-active portion; the active layer also includes: a ninth active portion, connected between the first sub-active portion and the second sub-active portion; wherein the orthographic projection of the first metal layer on the base substrate overlaps with the orthographic projection of the second active portion and the third active portion on the base substrate, and does not overlap with the orthographic projection of the ninth active portion on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, the first metal layer includes a plurality of shielding units, and one shielding unit corresponds to one pixel driving circuit; the shielding unit includes: a first shielding portion, which is arranged corresponding to the second active portion, the first shielding portion having a notch, the orthographic projection of the first shielding portion on the substrate overlaps with the orthographic projection of the second active portion on the substrate, and the orthographic projection of the ninth active portion on the substrate is located within the orthographic projection of the notch on the substrate; a second shielding portion, which is arranged corresponding to the third active portion and connected to the first shielding portion, the orthographic projection of the second shielding portion on the substrate overlaps with the orthographic projection of the third active portion on the substrate.

[0009] In an exemplary embodiment of the present disclosure, the first metal layer is connected to a constant voltage source; the display panel includes a plurality of pixel driving circuits, and the first metal layer includes a plurality of shielding units, one shielding unit corresponding to one pixel driving circuit; the shielding unit includes: a second shielding portion, which is arranged corresponding to the third active portion and connected to the first shielding portion, and the orthographic projection of the second shielding portion on the substrate overlaps with the orthographic projection of the third active portion on the substrate; the display panel also includes: a first conductive layer, which is located on the side of the active layer away from the substrate, and the first conductive layer includes: a first conductive block for forming the gate of the driving transistor, and the orthographic projection of the first conductive block on the substrate covers the orthographic projection of the third active portion on the substrate and overlaps with the orthographic projection of the second shielding portion on the substrate.

[0010] In an exemplary embodiment of the present disclosure, an orthographic projection of the first conductive block on the base substrate covers an orthographic projection of the second shielding portion on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, an orthographic projection of the first conductive block on the base substrate overlaps with an orthographic projection of the second shielding portion on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the first metal layer is connected to a constant voltage source; the display panel includes a plurality of pixel driving circuits, the first metal layer includes a plurality of shielding units, and one shielding unit corresponds to one pixel driving circuit; the shielding unit includes: a first shielding portion, which is arranged corresponding to the second active portion, the first shielding portion has a notch, the orthographic projection of the first shielding portion on the substrate overlaps with the orthographic projection of the second active portion on the substrate, and the orthographic projection of the ninth active portion on the substrate is located within the orthographic projection of the notch on the substrate; a second shielding portion, which is arranged corresponding to the third active portion and connected to the first shielding portion, the orthographic projection of the second shielding portion on the substrate overlaps with the orthographic projection of the third active portion on the substrate; a first connecting portion, which connects The first shielding portion, the first connecting portion extends in the column direction on the orthographic projection of the substrate; the second connecting portion is connected to a side of the second shielding portion in the column direction away from the first shielding portion, and the orthographic projection of the substrate extends in the column direction; the third connecting portion is connected to a side of the second shielding portion in the row direction and the orthographic projection of the substrate extends in the row direction; the fourth connecting portion is connected to a side of the second shielding portion in the row direction away from the third connecting portion and the orthographic projection of the substrate extends in the row direction; wherein, in two adjacent shielding units in the row direction, the third connecting portion in one shielding unit is connected to the fourth connecting portion in the other shielding unit; in two adjacent shielding units in the column direction, the first connecting portion of one shielding unit is connected to the second connecting portion in the other shielding unit.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a first transistor, the second electrode of which is connected to the gate of the driving transistor; the active layer also includes: a first active portion, used to form a channel region of the first transistor, the first active portion including a fifth sub-active portion and a sixth sub-active portion; wherein, the first connecting portion includes a first component portion and a second component portion, the first component portion is connected between the first shielding portion and the second component portion, the orthographic projection of the first component portion on the substrate extends along the row direction, the orthographic projection of the second component portion on the substrate extends along the column direction, and the orthographic projection of the second component portion on the substrate is located between the orthographic projection of the fifth sub-active portion and the sixth sub-active portion on the substrate.

[0014] In an exemplary embodiment of the present disclosure, the second connecting portion includes a third component, a fourth component and a fifth component, the fourth component is connected between the third component and the fifth component, the orthographic projections of the third component and the fifth component on the substrate extend along the column direction and are staggered in the row direction; in two adjacent shielding units in the column direction, the fifth component in the shielding unit in this row is connected to the second component in the shielding unit in the next row.

[0015] In an exemplary embodiment of the present disclosure, the display panel also includes: a second source-drain metal layer, located on the side of the first conductive layer away from the base substrate, the second source-drain metal layer includes: a first power line, extending along the column direction of the positive projection of the base substrate, the first power line and at least one of the first connection part, the second connection part, the third connection part and the fourth connection part in the first metal layer are connected in the non-display area of ​​the display panel through a via.

[0016] In an exemplary embodiment of the present disclosure, the second active portion includes a first sub-active portion and a second sub-active portion; the display panel further includes: a first conductive layer, located on a side of the active layer away from the base substrate, the first conductive layer including: a gate signal line, including a main extension portion and a secondary extension portion connected to one side of the main extension portion, the main extension portion extending in a row direction on the orthographic projection of the base substrate and covering the orthographic projection of the first sub-active portion on the base substrate, the secondary extension portion extending in a column direction on the orthographic projection of the base substrate and covering the orthographic projection of the second sub-active portion on the base substrate, a partial structure of the main extension portion and the secondary extension portion are used to form the gate of the second transistor; wherein the first metal layer includes a plurality of shielding units, one shielding unit corresponding to one pixel driving circuit, the shielding unit including a first shielding portion arranged corresponding to the second active portion, the first shielding portion The orthographic projection of the substrate overlaps with the orthographic projection of the second active portion on the substrate; the first shielding portion includes a first sub-shielding portion and a second sub-shielding portion, the first sub-shielding portion corresponds to the first sub-active portion, and the second sub-shielding portion corresponds to the second sub-active portion, the orthographic projection of the first sub-shielding portion on the substrate substrate extends along the row direction and has a fifth width in the column direction, the main extension portion and the first sub-shielding portion have a first overlapping portion on the orthographic projection of the substrate substrate, and the first overlapping portion has a seventh width in the column direction, and the fifth width is greater than the seventh width; the second sub-shielding portion extends along the column direction and has a sixth width in the row direction, the secondary extension portion and the second sub-active portion have a second overlapping portion on the orthographic projection of the substrate substrate, and the second overlapping portion has an eighth width in the row direction, and the sixth width is greater than the eighth width.

[0017] In an exemplary embodiment of the present disclosure, a ratio of the seventh width to the fifth width and a ratio of the eighth width to the sixth width are both greater than or equal to 50%.

[0018] In an exemplary embodiment of the present disclosure, the second overlapping portion has a first length in the column direction; the secondary extending portion has a second length in the column direction when projected onto the base substrate, and the first length is smaller than the second length.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes: a first electrode layer, located on the side of the active layer facing away from the base substrate, the first electrode layer including a plurality of first electrodes, one first electrode corresponding to one pixel driving circuit; wherein, the display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, one sub-pixel corresponds to one pixel driving circuit, and the first electrode of the first sub-pixel and the first electrode of the third sub-pixel are located in a first pixel column, the first electrode of the second sub-pixel is located in a second pixel column, and the first pixel column and the second pixel column are alternately distributed in the row direction.

[0020] In an exemplary embodiment of the present disclosure, the second metal layer is the first electrode layer; the second active portion includes a first sub-active portion and a second sub-active portion; the active layer also includes: a ninth active portion, connected between the first sub-active portion and the second sub-active portion; wherein, at least part of the first electrode's orthographic projection on the substrate covers the orthographic projections of the second active portion, the third active portion and the ninth active portion on the substrate.

[0021] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of first repeating units arrayed in row and column directions, the first repeating unit including a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; in any first repeating unit, the orthographic projection of the first electrode connected to the first pixel driving circuit on the substrate covers the orthographic projection of the second active portion and the ninth active portion in the first pixel driving circuit on the substrate and partially overlaps with the orthographic projection of the third active portion on the substrate, the orthographic projection of the first electrode connected to the first pixel driving circuit on the substrate also at least partially overlaps with the orthographic projection of the second active portion and the ninth active portion in the second pixel driving circuit on the substrate; the orthographic projection of the first electrode connected to the second pixel driving circuit on the substrate partially overlaps with the orthographic projection of the third active portion in the second pixel driving circuit on the substrate.

[0022] In an exemplary embodiment of the present disclosure, in any first repeating unit, the orthographic projection of the first electrode connected to the first pixel driving circuit on the substrate also covers the orthographic projection of the third active portion in the first pixel driving circuit on the substrate and / or also covers the orthographic projection of the second active portion and the ninth active portion in the second pixel driving circuit on the substrate.

[0023] In an exemplary embodiment of the present disclosure, the first sub-pixel and the third sub-pixel both correspond to the first pixel driving circuit, and the second sub-pixel corresponds to the second pixel driving circuit.

[0024] In an exemplary embodiment of the present disclosure, the ninth active portion includes a third sub-active portion and a fourth sub-active portion, the third sub-active portion is connected to the first sub-active portion, and the fourth sub-active portion is connected to the second sub-active portion; the first electrodes in the first sub-pixel and the third sub-pixel each include a main portion and an additional portion, and the additional portion is connected to one side of the main portion along the row direction; the display panel further includes: a first conductive layer located between the active layer and the first electrode layer, the first conductive layer including: a gate signal line including a main extension portion and a secondary extension portion, the main extension portion extending in the row direction of the positive projection of the substrate and covering the positive projection of the first sub-active portion on the substrate, the secondary extension portion extending in the column direction of the positive projection of the substrate and covering the positive projection of the second sub-active portion on the substrate, a partial structure of the main extension portion and the secondary extension portion being used to form the gate of the second transistor; wherein the display panel includes a plurality of first repeating units arrayed in the row and column directions, the first repeating unit including a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction, the first pixel driving circuit being located in the first a pixel column, the second pixel driving circuit is located in the second pixel column; in the same first repeating unit, the orthographic projection of the first electrode main portion of the first sub-pixel on the substrate covers the orthographic projection of the second active portion, the third active portion and the ninth active portion in the first pixel driving circuit on the substrate and also covers the orthographic projection of the first sub-active portion and the third sub-active portion in the second pixel driving circuit on the substrate; the orthographic projection of the first electrode extension portion of the first sub-pixel on the substrate covers the orthographic projection of the second sub-active portion and the fourth sub-active portion in the second pixel driving circuit on the substrate; in the same first repeating unit, the orthographic projection of the first electrode main portion of the third sub-pixel on the substrate covers the orthographic projection of the second active portion and the ninth active portion in the first pixel driving circuit on the substrate and at least partially overlaps with the orthographic projection of the third active portion on the substrate; the orthographic projection of the first electrode extension portion of the third sub-pixel on the substrate covers the orthographic projection of the second sub-active portion and the ninth active portion in the second pixel driving circuit on the substrate and at least partially overlaps with the orthographic projection of the first sub-active portion on the substrate.

[0025] In an exemplary embodiment of the present disclosure, the second metal layer is a second source-drain metal layer, which is located between the active layer and the first electrode layer; the second source-drain metal layer includes: an electrode flat portion, which is arranged corresponding to the first electrode of the corresponding sub-pixel, and the orthographic projection of the first electrode on the substrate is located on the orthographic projection of the electrode flat portion on the substrate, and the orthographic projection of the electrode flat portion on the substrate also at least partially overlaps with the orthographic projections of the second active portion and the third active portion in the same pixel driving circuit on the substrate.

[0026] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of first repeating units arrayed in row and column directions, the first repeating unit including a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; the ninth active portion includes a third sub-active portion and a fourth sub-active portion, the third sub-active portion is connected to the first sub-active portion, and the fourth sub-active portion is connected to the second sub-active portion; the display panel also includes: a first conductive layer located between the active layer and the second source-drain metal layer, the first conductive layer including: a gate signal line including a main extension portion and a secondary extension portion, the main extension portion extending in the row direction on the orthographic projection of the substrate and covering the orthographic projection of the first sub-active portion on the substrate, the secondary extension portion extending in the column direction on the orthographic projection of the substrate and covering the The second sub-active portion is an orthographic projection of the substrate; wherein the electrode flat portion includes a second flat portion located in the second pixel column, and the second flat portion includes a first extension portion, a second extension portion and a third extension portion connected in sequence in the column direction; in the same first repeating unit, the orthographic projection of the first extension portion on the substrate covers the orthographic projections of the second sub-active portion and the fourth sub-active portion in the same pixel driving circuit on the substrate substrate and overlaps with the orthographic projections of the first sub-active portion and the third sub-active portion on the substrate substrate, the orthographic projection of the second extension portion on the substrate substrate overlaps with the orthographic projection of the third active portion in the same pixel driving circuit on the substrate substrate, and the orthographic projection of the third extension portion on the substrate substrate is located within the orthographic projection of the first electrode of the corresponding sub-pixel on the substrate substrate.

[0027] In an exemplary embodiment of the present disclosure, a hollow portion is defined between the first extension portion and the second extension portion, and the hollow portion is configured to expose at least a portion of a gap between the second transistor and the driving transistor.

[0028] In an exemplary embodiment of the present disclosure, the first extension portion has a first width in the row direction of the orthographic projection of the substrate substrate, the second extension portion has a second width in the row direction of the orthographic projection of the substrate substrate, and the third extension portion has a third width in the row direction of the orthographic projection of the substrate substrate, and the second width is smaller than the first width and smaller than the third width.

[0029] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of first repeating units arranged in an array in row and column directions, the first repeating unit including a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; the electrode flat portion includes: a first flat portion located in the first pixel column and arranged corresponding to the first sub-pixel, the first flat portion having an orthographic projection on the substrate covering the second sub-active portion, the fourth sub-active portion, and the third active portion in the same pixel driving circuit on the substrate, the first electrode of the first sub-pixel having an orthographic projection on the substrate covering the orthographic projection of the first flat portion on the substrate ; A second flat portion is located in the second pixel column, and the orthographic projection of the second flat portion on the substrate partially overlaps with the second active portion, the third active portion and the ninth active portion in the same pixel driving circuit; a third flat portion is located in the first pixel column and is arranged corresponding to the third sub-pixel, and the orthographic projection of the third flat portion on the substrate covers the orthographic projections of the second sub-active portion and the fourth sub-active portion in the same pixel driving circuit on the substrate substrate and at least partially overlaps with the orthographic projection of the third active portion on the substrate substrate, and the orthographic projection of the first electrode of the third sub-pixel on the substrate substrate covers the orthographic projection of the third flat portion on the substrate substrate.

[0030] In an exemplary embodiment of the present disclosure, the first electrode of the first sub-pixel has a first area in its orthographic projection on the substrate, the first electrode of the second sub-pixel has a second area in its orthographic projection on the substrate, and the first electrode of the third sub-pixel has a third area in its orthographic projection on the substrate, and the first area is greater than the third area and greater than the second area; the first flat portion has a first extension length in the column direction, the second flat portion has a second extension length in the column direction, and the third flat portion has a third extension length in the column direction, and the second extension length is greater than the first extension length and greater than the third extension length.

[0031] In an exemplary embodiment of the present disclosure, in any first repeating unit, the orthographic projections of the first electrode of the first sub-pixel and the first electrode of the third sub-pixel on the substrate both cover the orthographic projections of the second active portion, the ninth active portion and the third active portion in the corresponding first pixel driving circuit on the substrate, and the orthographic projection of the first electrode of the first sub-pixel on the substrate also covers the orthographic projections of the second active portion and the ninth active portion in the corresponding second pixel driving circuit on the substrate, and the orthographic projection of the first electrode of the third sub-pixel on the substrate at least partially overlaps with the orthographic projections of the second active portion and the ninth active portion in the corresponding second pixel driving circuit on the substrate.

[0032] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of second repeating units arrayed in row and column directions, the second repeating unit including a third pixel driving circuit and a fourth pixel driving circuit adjacently arranged in the row direction; the display panel also includes a first conductive layer and a second conductive layer stacked on the side of the active layer away from the base substrate; wherein, in the same second repeating unit, the first metal layer structure, active layer structure, first conductive layer structure and second conductive layer structure in the third pixel driving circuit are mirror images of each other, and in any two adjacent second repeating units in the row direction, the first metal layer structure, active layer structure, first conductive layer structure and second conductive layer structure in one second repeating unit are mirror images of each other, and the first metal layer structure, active layer structure, first conductive layer structure and second conductive layer structure in the other second repeating unit are mirror images of each other.

[0033] In an exemplary embodiment of the present disclosure, the second metal layer is a second source-drain metal layer; the second source-drain metal layer includes: a plurality of electrode flat portions, which are arrayed in row and column directions, and one electrode flat portion is arranged corresponding to one second repeating unit, and in the same repeating unit, the orthographic projection of the electrode flat portion on the substrate at least partially overlaps with the orthographic projections of the two second active portions, the two ninth active portions, and the two third active portions on the substrate.

[0034] In an exemplary embodiment of the present disclosure, the second metal layer is a first electrode layer; each first electrode located in the first sub-pixel row is correspondingly located in one of the second repeating units, and in any second repeating unit, the orthographic projection of the first electrode located in the first sub-pixel row on the substrate covers the orthographic projections of the two second active portions and the two ninth active portions on the substrate, and at least partially overlaps with the orthographic projections of the two third active portions on the substrate.

[0035] In an exemplary embodiment of the present disclosure, in any two adjacent second repeating units in the row direction, the data signal line and the first power line of the third pixel driving circuit in one repeating unit are mirror-symmetrical to the data signal line and the first power line of the fourth pixel driving circuit in the other repeating unit, and the data signal line in one third pixel driving circuit and the data signal line in the other repeating unit that is mirror-symmetrical to it are arranged adjacent to each other, and the first power line in one third pixel driving circuit and the first power line in the other repeating unit that is mirror-symmetrical to it are respectively located on both sides of the two data signal lines; the orthographic projection of the first electrode of the second sub-pixel row on the substrate is located on the orthographic projection of the first power line and the data signal line of the two second repeating units adjacent in the row direction on the substrate.

[0036] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a first transistor, a driving transistor, a fourth transistor and a seventh transistor. The first electrode of the first transistor is connected to the first initialization signal terminal, and the second electrode is connected to the gate of the driving transistor; the first electrode of the fourth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the data signal terminal; the first electrode of the seventh transistor is connected to the second initialization signal terminal, and the second electrode is connected to the first electrode of the light-emitting device; the active layer further includes: an eleventh active portion for forming the second electrode of the first transistor; a twelfth active portion for forming the first electrode of the first transistor; a fourteenth active portion for forming the second electrode of the fourth transistor; a fifteenth active portion for forming the second electrode of the fourth transistor forming the first electrode of the seventh transistor; a seventeenth active portion, used to form the first electrode of the fifth transistor; the display panel further comprises: a first conductive layer, located between the active layer and the first electrode layer, the first conductive layer comprising: a first conductive block, the orthographic projection of the substrate covering the orthographic projection of the third active portion on the substrate, the first conductive block being used to form the gate of the driving transistor; a second conductive layer, located between the first conductive layer and the first electrode layer, the second conductive layer comprising: a first initialization signal line, the orthographic projection of the substrate extending in the row direction; a second initialization signal line, the orthographic projection of the substrate extending in the row direction; a first source-drain metal layer, located between the first conductive layer and the first electrode layer Between the second conductive layer and the first electrode layer, the first source-drain metal layer includes: a first bridge portion, which extends in the column direction of the orthographic projection of the substrate, one end of the first bridge portion is connected to the eleventh active portion through a via, and the other end is connected to the first conductive block through a via, so as to connect the second electrode of the first transistor to the gate of the driving transistor; a second bridge portion, which extends in the column direction of the orthographic projection of the substrate, one end of the second bridge portion is connected to the fifteenth active portion through a via, and the other end is connected to the second initialization signal line through a via, so as to connect the first electrode of the seventh transistor to the second initialization signal line; a third bridge portion, which extends in the column direction of the orthographic projection of the substrate, one end of the third bridge portion is connected to the fifteenth active portion through a via, and the other end is connected to the second initialization signal line through a via, so as to connect the first electrode of the seventh transistor to the second initialization signal line; The twelfth active portion is connected through a via, and the other end is connected to the first initialization signal line through a via, so as to connect the first electrode of the first transistor to the first initialization signal line; a power adapter line, extending in the column direction on the orthographic projection of the base substrate, the power adapter line is connected to the seventeenth active portion through a via to connect to the first electrode of the fifth transistor; a data transfer portion, connected to the fourteenth active portion through a via to connect to the second electrode of the fourth transistor; a second source-drain metal layer, located between the first source-drain metal layer and the first electrode layer, the second source-drain metal layer comprising: a data signal line, extending in the column direction on the orthographic projection of the base substrate, the data signal line being connected to the data transfer portion through a via;A first power line, the orthographic projection of which extends along the column direction of the substrate, is connected to the power adapter line through a via. In any second repeating unit, the two first bridge portions, the two second bridge portions, the two third bridge portions, the two power adapter lines, the two data adapter portions, the two data signal lines, and the two first power lines are all mirror-symmetrical.

[0037] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a seventh transistor, a first electrode of the seventh transistor being connected to a second initialization signal terminal; the display panel includes a first display area and a second display area at least partially surrounding the first display area, the first display area having a greater light transmittance than the second display area, and the first display area including a plurality of pixel rows; the active layer further includes a fifteenth active portion for forming the first electrode of the seventh transistor; the display panel further includes a second conductive layer located between the active layer and the second metal layer, the second conductive layer including a second initialization signal line extending in a row direction as viewed from the orthographic projection of the substrate; a first source-drain metal layer located between the second conductive layer and the second metal layer, the first source-drain metal layer including a second bridge portion extending in a column direction as viewed from the orthographic projection of the substrate, one end of the second bridge portion being connected to the fifteenth active portion through a via, and the other end being connected to the second initialization signal line through a via, so as to connect the first electrode of the seventh transistor to the second initialization signal line; and a first connecting line located in the second display area and extending in the column direction as viewed from the orthographic projection of the substrate, the first connecting line connecting the second bridge portions of two adjacent rows.

[0038] According to a second aspect of the present disclosure, a display device is further provided, comprising the display panel described in any embodiment of the present disclosure.

[0039] In the display panel provided by the present disclosure, the first metal layer only blocks the second active portion and the third active portion from below the active layer, reducing the blocking area of ​​the first metal layer on the active layer, thereby reducing the amount of light reflected from the first metal layer to the active layer, and further reducing photo-induced leakage, thereby improving the color deviation problem caused by strong light exposure. The second metal layer blocks the second active portion and the third active portion above the active layer, thereby reducing the amount of incident light, and correspondingly reducing the amount of light reflected from the first metal layer to the active layer, reducing photo-induced leakage, and thus also improving the color deviation problem caused by strong light exposure. The present disclosure can fully enhance the effect of improving the color deviation caused by strong light exposure by having the first metal layer and the second metal layer act simultaneously on the upper and lower sides of the active layer.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0042] FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure;

[0043] FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1 ;

[0044] FIG3 is a schematic diagram showing the principle of color shift caused by the bottom metal layer in the related art;

[0045] FIG4 is a structural diagram of a display panel according to an embodiment of the present disclosure;

[0046] FIG5 is a structural diagram of the first metal layer in FIG4 ;

[0047] FIG6 is a structural diagram of the active layer in FIG4 ;

[0048] FIG7 is a structural diagram of the first conductive layer in FIG4 ;

[0049] FIG8 is a stacked layout of the first metal layer, the active portion, and the first conductive layer in FIG4 ;

[0050] FIG9 is a partial enlarged view of the second transistor in FIG8 ;

[0051] FIG10 is a schematic diagram showing the connection of the first metal layer in row and column directions in FIG4 ;

[0052] FIG11 is a partial enlarged view of a stack of a first metal layer, an active layer, and a first conductive layer in the related art;

[0053] FIG12 is a structural diagram of the second conductive layer in FIG4 ;

[0054] FIG13 is a structural diagram of the first source / drain metal layer in FIG4 ;

[0055] FIG14 is a structural diagram of the second source / drain metal layer in FIG4 ;

[0056] FIG15 is a structural diagram of the first electrode layer in FIG4 ;

[0057] FIG16 is a stacked layout of the first source / drain metal layer, the second source / drain metal layer, and the first electrode layer in FIG4 ;

[0058] FIG17 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

[0059] FIG18 is a schematic diagram of an arrangement of sub-pixels according to an embodiment of the present disclosure;

[0060] FIG19 is a schematic diagram of an arrangement of sub-pixels according to another embodiment of the present disclosure;

[0061] FIG20 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0062] FIG21 is a structural diagram of the first electrode layer in FIG20;

[0063] FIG22 is a stacked layout of the active layer, the first conductive layer, and the first electrode layer in FIG20 ;

[0064] FIG23 is a partial enlarged view corresponding to the first electrode of the first pixel driving circuit extending to the second transistor of the second pixel driving circuit in FIG22;

[0065] FIG24 is a structural diagram of a first metal layer according to an embodiment of the present disclosure;

[0066] FIG25 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0067] FIG26 is a structural diagram of the second source / drain metal layer in FIG25 ;

[0068] FIG27 is a stacking layout of the active layer and the second source / drain metal layer in FIG25 ;

[0069] FIG28 is a stacked layout of the active layer, the second source / drain metal layer, and the first electrode layer in FIG25 ;

[0070] FIG29 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0071] FIG30 is a structural layout diagram of the first metal layer in FIG29;

[0072] FIG31 is a structural layout diagram of the active layer in FIG29;

[0073] FIG32 is a structural layout diagram of the first conductive layer in FIG29;

[0074] FIG33 is a structural layout diagram of the second conductive layer in FIG29;

[0075] FIG34 is a structural layout diagram of the first source / drain metal layer in FIG29 ;

[0076] FIG35 is a structural layout diagram of the second source / drain metal layer in FIG29 ;

[0077] FIG36 is a structural diagram of the first electrode layer in FIG29;

[0078] FIG37 is a stacking layout of the active layer and the second source / drain metal layer in FIG29;

[0079] FIG38 is a stacked layout of the active layer, the second source / drain metal layer, and the first electrode layer in FIG29;

[0080] FIG39 is a cross-sectional view along the AA direction in FIG4 . DETAILED DESCRIPTION

[0081] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0082] FIG1 is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the first node N1, and the gate is connected to the first reset signal terminal Reset n; the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the gate signal terminal Gate; the gate of the driving transistor T3 is connected to the first node N1; the second electrode of the fourth transistor T4 is connected to the data signal terminal V Data, the first electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the gate signal terminal Gate; the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor T3, the first electrode is connected to the first power supply terminal VDD, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the second reset signal terminal Reset(n+1). The first electrode of the storage capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, each transistor disclosed in the present invention can be a P-type transistor. For example, the first transistor T1 to the seventh transistor T7 can all be P-type low-temperature polycrystalline silicon transistors. P-type low-temperature polycrystalline silicon transistors have high carrier mobility, which is conducive to realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals according to actual conditions.

[0083] It should be noted that the transistors used in each embodiment of the present disclosure can be thin film transistors, field effect transistors, or other devices with the same characteristics. In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0084] FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1. ​​As shown in FIG2, G1 represents the timing of the gate signal terminal Gate, Re1 represents the timing of the first reset signal terminal Reset n, Re2 represents the timing of the second reset signal terminal Reset(n+1), EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal V Data The driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase t3, and a light emitting phase t4. In the first reset phase t1: the first reset signal terminal Reset n outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the first node N1. In the compensation phase t2: the gate signal terminal Gate outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal V DataA data signal is output to write a voltage Vdata+Vth (i.e., the sum of the voltages Vdata and Vth) to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the driver transistor T3. During the second reset phase t3, the second reset signal terminal Reset(n+1) outputs a low-level signal, turning on the seventh transistor T7. The second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. During the light-emitting phase t4, the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. The driver transistor T3 emits light in response to the voltage Vdata+Vth stored in the storage capacitor C.

[0085] According to the output current formula of the driving transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility; Cox is the gate storage capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0086] In the related art, the luminous efficiency of light-emitting devices is getting higher and higher to meet the needs of longer life and lower power consumption of display devices. However, the excessively high luminous efficiency makes it more sensitive to changes in the characteristics of TFT, which will affect the TFT characteristics in the panel after the reliability test. Because the luminous efficiency of each device is different, the panel after the reliability test will have a color shift problem. For this reason, a metal layer is usually set at the bottom of the semiconductor layer to solve the problem of color shift in the reliability test. However, as shown in Figure 3, after the metal layer is set at the bottom, strong light will be reflected to the active layer Polly through the bottom metal layer, generating photogenerated carriers and causing leakage in the pixel driving circuit, which will reduce the display brightness of each RGB sub-pixel, and the second sub-pixel G will attenuate more, causing the local area of ​​the display panel to appear reddish and pink. The display panel disclosed in the present invention is used to solve the above-mentioned color shift problem caused by strong light exposure.

[0087] The display panel provided by the present disclosure may include a plurality of pixel driving circuits distributed in an array along the row direction X and the column direction Y. The pixel driving circuit is used to drive the light-emitting device to emit light. The pixel driving circuit may be as shown in FIG1 . Of course, in other exemplary embodiments, the pixel driving circuit in the display panel may also be other structures, for example, 8T1C, 9T1C, etc. Figure 4 is a structural layout diagram of a display panel according to an embodiment of the present disclosure. As shown in Figure 4, the display panel of the present disclosure may include a base substrate, an active layer Polly, a first metal layer BSM and a second metal layer. The active layer Polly is located on one side of the base substrate. The active layer Polly may include a second active portion POL2 and a third active portion POL3. The second active portion POL2 can be used to form a channel region of the second transistor T2; the third active portion POL3 is connected to the second active portion POL2, and the third active portion POL3 can be used to form a channel region of the driving transistor T3; the first metal layer BSM is located between the base substrate and the active layer Polly; the second metal layer is located on a side of the active layer Polly facing away from the base substrate; wherein the orthographic projection of the first metal layer BSM on the base substrate covers the orthographic projections of the second active portion POL2 and the third active portion POL3 on the base substrate, and the orthographic projection of the second metal layer on the base substrate at least covers the orthographic projection of the second active portion POL2 on the base substrate.

[0088] In the display panel provided by the present disclosure, the first metal layer BSM only blocks the second active part POL2 and the third active part POL3 from below the active layer Polly, reducing the blocking area of ​​the first metal layer BSM for the active layer Polly, thereby reducing the amount of light reflected from the first metal layer BSM to the active layer Polly, thereby reducing photo-induced leakage, and improving the color deviation problem caused by strong light exposure. The second metal layer blocks the second active part POL2 and the third active part POL3 above the active layer Polly, thereby reducing the amount of incident light, and correspondingly reducing the amount of light reflected from the first metal layer BSM to the active layer Polly, reducing photo-induced leakage, and thus can also improve the color deviation problem caused by strong light exposure. The present disclosure can fully enhance the effect of improving the color deviation caused by strong light exposure by having the first metal layer BSM and the second metal layer act simultaneously on the upper and lower sides of the active layer Polly.

[0089] The substrate disclosed herein can be a flexible substrate, such as a flexible substrate made of PI material. A large amount of free charge exists in the flexible substrate. When the temperature rises, the free charge diffuses into the transistor channel region, causing the transistor threshold voltage to shift positively. Taking the pixel drive circuit shown in FIG1 as an example, after the threshold voltages of the second transistor T2 and the driving transistor T3 shift positively, the voltage at the first node N1 decreases, thereby decreasing the gate-source voltage of the driving transistor T3. This increases the drive current provided by the pixel drive circuit, causing the screen to appear brighter than before the reliability test and the copper rod test. Furthermore, because the second subpixel G has the highest luminous efficiency, the brighter display after the friction test typically manifests as a greenish tint. This phenomenon is more noticeable to the human eye at low grayscale levels. The present disclosure provides a first metal layer (BSM) below the active layer (Polly). This first metal layer (BSM) blocks free charge at the bottom, thereby resolving the color shift issue after the high-temperature reliability test. On this basis, because the orthographic projection of the first metal layer BSM on the base substrate only covers the orthographic projection of the second active part POL2 and the third active part POL3 on the base substrate, that is, the first metal layer BSM only blocks the channels of the second transistor T2 and the driving transistor T3 in the pixel driving circuit, the blocking area of ​​the first metal layer BSM for the active layer Polly is reduced. In this way, the light incident from the display side to the bottom first metal layer BSM is reduced, thereby reducing the amount of light reflected by the first metal layer BSM to the active layer Polly, thereby reducing the photogenerated carriers, thereby further solving the display color deviation problem caused by the generation of photogenerated carriers due to strong light irradiation.

[0090] The orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projections of the second active portion and the third active portion on the substrate, that is, the orthographic projection of the first metal layer on the substrate overlaps with the orthographic projections of the second active portion and the third active portion on the substrate. In some embodiments, the orthographic projection of the first metal layer on the substrate can completely cover the orthographic projections of the second active portion and the third active portion on the substrate. The orthographic projection of a certain structure A described in the present disclosure on the substrate covers the orthographic projection of another structure B on the substrate, which can be understood as the outline of the projection of structure B on the substrate plane completely lying within the outline of the projection of structure A on the same plane. For example, the orthographic projection of the first metal layer BSM on the substrate covers the orthographic projection of the second active portion POL2 on the substrate, that is, the outline of the orthographic projection of the second active portion POL2 on the substrate completely lies within the outline of the orthographic projection of the first metal layer BSM on the substrate. In this way, it is equivalent to the first metal layer BSM completely blocking the channel region of the second transistor T2 and the channel region of the driving transistor T3 at the bottom of the active layer Polly. In other words, the orthographic projection of the first metal layer BSM on the base substrate covers the orthographic projection of the second active part POL2 on the base substrate, which is equivalent to having a first metal layer structure opposite to and larger in area than the second active part POL2 below the second active part POL2, that is, the boundary of the first metal layer structure must exceed the boundary of the second active part POL2.

[0091] In other embodiments, the orthographic projection of the first metal layer on the substrate may partially overlap the orthographic projections of the second active portion and the third active portion on the substrate, i.e., a portion of the orthographic projection of the second active portion on the substrate is located within the outline of the orthographic projection of the first metal layer on the substrate, and another portion is located outside the outline of the orthographic projection of the first metal layer on the substrate, and a portion of the orthographic projection of the third active portion on the substrate is located within the outline of the orthographic projection of the first metal layer on the substrate, and another portion is located outside the outline of the orthographic projection of the first metal layer on the substrate. In this exemplary embodiment, the ratio of the overlapping area of ​​the second active portion and the orthographic projection of the first metal layer on the substrate to the area of ​​the orthographic projection of the second active portion on the substrate may be greater than or equal to 50%, for example, 50%, 60%, 70%, 80%, 90%, etc., to enhance the shielding effect of the first metal layer on the second active portion. Similarly, the ratio of the overlapping area of ​​the third active portion and the first metal layer on the base substrate to the area of ​​the third active portion on the base substrate can be greater than or equal to 50%, for example, it can be 50%, 60%, 70%, 80%, 90%, etc.

[0092] Similarly, the orthographic projection of the second metal layer on the base substrate at least partially overlaps with the orthographic projections of the second active portion and the third active portion on the base substrate. The orthographic projection of the second metal layer on the base substrate may cover the orthographic projections of the second active portion and the third active portion on the base substrate; or the orthographic projections of the second active portion and the third active portion on the base substrate may both partially overlap with the orthographic projection of the second metal layer on the base substrate.

[0093] As can be seen, the second metal layer is located above the active layer Polly, that is, on the display side, so that the second metal layer blocks the second active part POL2 above the active layer Polly, that is, on the display side. In this way, the light incident from the side of the display side needs a larger angle to be incident on the first metal layer BSM at the bottom. In other words, the amount of light that can be incident on the first metal layer BSM is reduced, and the light reflected from the first metal layer BSM to the active layer Polly is also reduced accordingly. This can reduce photogenerated carriers and significantly improve the color deviation problem caused by strong light exposure.

[0094] The second metal layer of the present disclosure can be the second source-drain metal layer SD2 or the first electrode layer ANOL. Using one or more metal layers to shield the second transistor T2 and the driving transistor T3 can improve color deviation. The present disclosure is further described below with reference to the accompanying drawings.

[0095] Figure 5 is a structural layout of the first metal layer in Figure 4, Figure 6 is a structural layout of the active layer in Figure 4, Figure 7 is a structural layout of the first conductive layer in Figure 4, Figure 8 is a stacked layout of the first metal layer, the active part and the first conductive layer in Figure 4, Figure 9 is a local enlarged view of the second transistor in Figure 8, and Figure 10 is a schematic diagram of the connections of the first metal layer in the row and column directions in Figure 4.

[0096] As shown in Figures 4 and 6, the active layer Polly may include first to fifteenth active portions POL1 to POL15. The first active portion POL1 may be used to form the channel region of the first transistor T1, the second active portion POL2 may be used to form the channel region of the second transistor T2, the third active portion POL3 may be used to form the channel region of the driving transistor T3, and the fourth to seventh active portions POL4 to POL7 may be used to form the channel regions of the fourth to seventh transistors T4 to T7, respectively. The active layer Polly of the present disclosure may be formed of polycrystalline silicon semiconductor material. Accordingly, the transistors in the display panel of the present disclosure may be P-type low-temperature polycrystalline silicon thin film transistors.

[0097] As shown in FIG6 , in this exemplary embodiment, the first transistor T1 and the second transistor T2 may have a dual-gate structure. Therefore, the second active portion POL2 may include a first sub-active portion POL2-1 and a second sub-active portion POL2-2. The first sub-active portion POL2-1 and the second sub-active portion POL2-2 are each used to form a dual channel of the second transistor T2. The first sub-active portion POL2-1 and the second sub-active portion POL2-2 are connected via a ninth active portion POL9. After being conductively conductive, the ninth active portion POL9 forms the conductive structure T2M of the second transistor T2. Furthermore, the ninth active portion POL9 may include a third sub-active portion POL9-3 and a fourth sub-active portion POL9-4. The third sub-active portion POL9-3 is connected to the first sub-active portion POL2-1, and the fourth sub-active portion POL9-4 is connected to the second sub-active portion POL2-2.

[0098] The first active portion POL1 may include a fifth sub-active portion POL1-5 and a sixth sub-active portion POL1-6, each for forming a double channel of the first transistor T1, and the fifth sub-active portion POL1-5 and the sixth sub-active portion POL1-6 may be connected through a tenth active portion POL10.

[0099] The eleventh active portion POL11 is connected between the second sub-active portion POL2-2 and the sixth sub-active portion POL1-6 and can be used to form the second electrode of the first transistor T1 and the first electrode of the second transistor T2. The eleventh active portion POL11 can be connected to the first bridge portion 31 of the first source-drain metal layer SD1 through a via, thereby connecting the second electrode of the first transistor T1 and the first electrode of the second transistor T2 to the gate of the driving transistor T3 through the first bridge portion 31.

[0100] The twelfth active portion POL12 is connected to one side of the fifth sub-active portion POL1-5. The twelfth active portion POL12 can be used to form the first electrode of the first transistor T1. The twelfth active portion POL12 can be connected to the third bridge portion 33 of the first source-drain metal layer SD1 through a via, so as to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1 through the third bridge portion 33.

[0101] The thirteenth active portion POL13 is connected between the first sub-active portion POL2 - 1 , the third active portion POL3 and the sixth active portion POL6 , and can be used to form the second electrode of the second transistor T2 , the first electrode of the sixth transistor T6 and the first electrode of the driving transistor T3 .

[0102] The fourteenth active portion POL14 is connected to a side of the fourth active portion POL4 away from the sixteenth active portion POL16. The fourteenth active portion POL14 is used to form the second electrode of the fourth transistor T4. The fourteenth active portion POL14 can be connected to the data transfer portion VdataL of the first source-drain metal layer SD1 through a via, so as to connect the second electrode of the fourth transistor T4 to the data signal line Vdata through the data transfer portion VdataL.

[0103] The sixteenth active portion POL16 is connected between the fourth active portion POL4 , the fifth active portion POL5 , and the third active portion POL3 , and may be used to form the second electrode of the driving transistor T3 , the first electrode of the fourth transistor T4 , and the second electrode of the fifth transistor T5 .

[0104] The seventeenth active portion POL17 is connected to a side of the fifth active portion POL5 away from the sixteenth active portion POL16. The seventeenth active portion POL17 can be used to form the first electrode of the fifth transistor T5. The seventeenth active portion POL17 can be connected to the power transfer line VDDL of the first source-drain metal layer SD1 through a via, thereby connecting the first electrode of the fifth transistor T5 to the first power line VDD through the power transfer line.

[0105] The eighteenth active portion POL18 is connected between the sixth active portion POL6 and the seventh active portion POL7. The eighteenth active portion POL18 can be used to form the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighteenth active portion POL18 can be connected to the first transition portion 301 of the first source-drain metal layer SD1 through a via, so as to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the anode of the light-emitting device through the first transition portion 301.

[0106] The fifteenth active portion POL15 is connected to the other side of the seventh active portion POL7. The fifteenth active portion POL15 can be used to form the first electrode of the seventh transistor T7. The fifteenth active portion POL15 can be connected to the second bridge portion 32 of the first source-drain metal layer SD1 through a via, so as to connect the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2 through the second bridge portion 32.

[0107] As shown in Figures 4 and 5, in an exemplary embodiment, the first metal layer BSM may include a plurality of shielding units BSM0, which may be provided in a one-to-one correspondence with a plurality of pixel driving circuits. The shielding unit BSM0 may include a first shielding portion B1 and a second shielding portion B2. The first shielding portion B1 is provided corresponding to the second active portion POL2. The first shielding portion B1 has a notch B0. The orthographic projection of the first shielding portion B1 on the substrate covers the orthographic projection of the second active portion POL2 on the substrate, and the orthographic projection of the ninth active portion POL9 on the substrate is located within the orthographic projection of the notch B0 on ​​the substrate. Thus, the first shielding portion B1 avoids the conductive structure T2M between the dual channels of the second transistor T2 through the gap B0. In other words, the shielding unit BSM0 only blocks the channel region of the second transistor T2 at the position corresponding to the second transistor T2, but does not block the conductive structure T2M connecting the dual channels of the second transistor T2. Compared with the solution in the prior art in which the first metal layer BSM blocks both the channel and the conductive structure T2M of the second transistor T2 at the second transistor T2, this exemplary embodiment further reduces the area of ​​the first metal layer BSM, thereby improving or eliminating the reddish or pinkish color shift problem caused by strong light exposure.

[0108] The second shielding portion B2 is arranged corresponding to the third active portion POL3 and is connected to the first shielding portion B1. The orthographic projection of the second shielding portion B2 on the substrate covers the orthographic projection of the third active portion POL3 on the substrate, that is, the second shielding portion B2 is used to block the channel region of the driving transistor T3. As described above, the display panel of the present disclosure can use the first conductive layer Gate1 as a mask to perform conductor processing on the active layer Polly, that is, the active layer Polly covered by the first conductive layer Gate1 forms the channel region of the transistor, and the area not covered by the first conductive layer Gate1 forms a conductor structure. Because the first conductive layer Gate1 has already overlaid the channel region of the active layer Polly, the first metal layer BSM of the present disclosure does not need to overlay the first conductive layer Gate1 at the driving transistor T3, thereby further reducing the area of ​​the first metal layer BSM at the driving transistor T3.

[0109] Specifically, as shown in FIG7 , the first conductive layer Gate1 may include a first conductive block 11. The orthographic projection of the first conductive block 11 on the base substrate may overlap the orthographic projection of the third active portion POL3 on the base substrate, thereby forming the gate of the driving transistor T3. In actual products, the first conductive block 11 typically overlays the third active portion POL3, meaning that the actual boundary of the first conductive block 11 is larger than the boundary of the third active portion POL3. For example, the stackup diagram shown in FIG8 shows the boundary indicated by the dashed box, which represents the boundary of the third active portion POL3. As can be seen, because the first conductive block 11 overlays the third active portion POL3, in actual products, the boundary of the third active portion POL3 does not overlap with the boundary of the first conductive block 11 but rather lies within the boundary of the first conductive block 11. Furthermore, the orthographic projection of the second shield portion B2 on the base substrate may lie within the orthographic projection of the first conductive block 11 on the base substrate, meaning that the area covered by the second shield portion B2 lies within the area covered by the first conductive block 11. Figure 11 is a local enlarged view of the stack of the first metal layer, the active layer and the first conductive layer in the related art. By comparing Figures 8 and 11, it can be seen that compared with the related art in which the first metal layer BSM overlays the first conductive block 11 at the driving transistor T3, the first metal layer BSM of this exemplary embodiment can block the channel region of the driving transistor T3 while further reducing the area of ​​the second shielding portion B2, so that the area of ​​the first metal layer BSM is further reduced, thereby further enhancing the improvement effect of the color shift of the display panel caused by strong light exposure.

[0110] In some embodiments, the orthographic projection of the second shielding portion B2 on the base substrate and the orthographic projection of the first conductive block 11 on the base substrate may partially overlap. For example, the orthographic projection of the second shielding portion B2 and the first conductive block 11 on the base substrate may have the same shape and some of their side edges may be aligned and overlap, and the remaining side edge of the orthographic projection of the second shielding portion B2 is located within the orthographic projection of the first conductive block 11. This structure also has the effect of reducing the area of ​​the first metal layer and improving color deviation.

[0111] Continuing with reference to FIG8 , in an exemplary embodiment, the orthographic projection of the second shielding portion B2 on the base substrate may overlap with the orthographic projection of the first conductive block 11 on the base substrate, that is, the first metal layer BSM is configured at a position corresponding to the driving transistor T3 to have the same shape as the gate of the driving transistor T3 and the corresponding edges overlap. In other words, the first metal layer BSM is configured at a position corresponding to the driving transistor T3 to have a flush edge structure with the gate of the driving transistor T3, thereby achieving the purpose of reducing the area of ​​the first metal layer BSM at the driving transistor T3.

[0112] As shown in Figures 4 and 5, in an exemplary embodiment, the shielding unit BSM0 may further include a first connection portion B11 to a fourth connection portion B14, the first connection portion B11 is connected to the first shielding portion B1, and the orthographic projection of the first connection portion B11 on the substrate extends along the column direction Y; the second connection portion B12 is connected to a side of the second shielding portion B2 in the column direction Y away from the first shielding portion B1, and the orthographic projection of the second connection portion B12 on the substrate extends along the column direction Y; the third connection portion B13 is connected to a side of the second shielding portion B2 in the row direction X, and the orthographic projection of the substrate extends along the row direction X; the fourth connection portion B14 is connected to a side of the second shielding portion B2 in the row direction X away from the third connection portion B13, and the orthographic projection of the substrate extends along the row direction X.

[0113] A certain structure A described in the present disclosure extends along direction B, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0114] As shown in Figure 10, in two adjacent shielding units BSM0 in the row direction X, the third connection portion B13 of one shielding unit BSM0 connects to the fourth connection portion B14 of the other shielding unit BSM0; in two adjacent shielding units BSM0 in the column direction Y, the first connection portion B11 of one shielding unit BSM0 connects to the second connection portion B12 of the other shielding unit BSM0. In this way, each shielding unit BSM0 forms a metal grid structure in the row and column directions. This grid structure can reduce the IR drop of the constant voltage source connected to the first metal layer BSM, thereby reducing voltage drop losses. Furthermore, the metal grid structure forms an equipotential surface in the first metal layer BSM, which can enhance the shielding effect of free charges, facilitate the stabilization of the characteristics of each transistor in the pixel driver circuit, and improve the voltage holding ratio of the pixel driver circuit, thereby improving the display effect.

[0115] In an exemplary embodiment, the first power line VDD of the second source-drain metal layer SD2 can be used to provide a constant voltage source for the first metal layer BSM. Exemplarily, the first power line VDD can be connected to at least one of the first connection part B11, the second connection part B12, the third connection part B13 and the fourth connection part B14 in the first metal layer BSM through a via in the non-display area of ​​the display panel to connect the first metal layer BSM to the constant voltage source. For example, the first power line VDD can be arranged circumferentially in the non-display area to form a ring, so that any one or more of the first connection part B11 to the fourth connection part B14 can be connected to the first power line VDD through a via. Of course, in other embodiments, a constant voltage source can also be provided to the first metal layer BSM through other signal lines. For example, a constant voltage source can be provided to the first metal layer BSM through the first initialization signal line Vinit1, etc., which will not be described in detail here.

[0116] Further, as shown in Figures 5 and 10, in this exemplary embodiment, the first connecting portion B11 includes a first component portion B11-1 and a second component portion B11-2, the first component portion B11-1 is connected between the first shielding portion B1 and the second component portion B11-2, the orthographic projection of the first component portion B11-1 on the substrate extends along the row direction, the orthographic projection of the second component portion B11-2 on the substrate extends along the column direction, and the orthographic projection of the second component portion B11-2 on the substrate is located between the orthographic projections of the fifth sub-active portion POL1-5 and the sixth sub-active portion POL1-6 on the substrate. The orthographic projection of the first component B11-1 on the substrate extends along the row direction, so that the second component B11-2 is offset by a certain distance in the row direction, so that the orthographic projection of the second component B11-2 on the substrate passes between the orthographic projections of the fifth sub-active portion POL1-5 and the sixth sub-active portion POL1-6 on the substrate, that is, the second component B11-2 does not block the dual channel of the first transistor T1 but avoids the dual channel of the first transistor T1, thereby reducing the blocking area of ​​the active layer.

[0117] Continuing with reference to Figures 5 and 10, in this exemplary embodiment, the second connecting portion B12 includes a third component B12-3, a fourth component B12-4, and a fifth component B12-5. The fourth component B12-4 is connected between the third component B12-3 and the fifth component B12-5. The orthographic projections of the third component B12-3 and the fifth component B12-5 on the substrate extend in the column direction and are staggered in the row direction. The third component B12-3 is connected to the second shielding portion B2, and the fourth component B12-4 is connected between the third component B12-3 and the fifth component B12-5. This creates a certain distance between the fifth component B12-5 and the third component B12-3 in the row direction. In other words, the fifth component B12-5 is offset so that the fifth component B12-5 extends in the column direction to the second component of the next row and connects thereto, thereby connecting two adjacent shielding units in the column direction.

[0118] The display panel disclosed herein may further include a first conductive layer Gate1, a second conductive layer Gate2, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a first electrode layer ANOL. The substrate, first metal layer BSM, active layer Polly10, first conductive layer Gate1, second conductive layer Gate2, first source / drain metal layer SD1, second source / drain metal layer SD2, and first electrode layer ANOL are sequentially stacked, and an insulating layer may be provided between the aforementioned functional layers. Figure 12 is a structural layout diagram of the second conductive layer in Figure 4 , Figure 13 is a structural layout diagram of the first source / drain metal layer in Figure 4 , Figure 14 is a structural layout diagram of the second source / drain metal layer in Figure 4 , Figure 15 is a structural layout diagram of the first electrode layer in Figure 4 , and Figure 16 is a stacked layout diagram of the first source / drain metal layer, the second source / drain metal layer, and the first electrode layer in Figure 4 .

[0119] As shown in Figures 4 and 7 , as described above, the first conductive layer Gate1 may include a first conductive block 11. The orthographic projection of the first conductive block 11 on the base substrate may overlap the orthographic projection of the third active portion POL3 on the base substrate. The first conductive block 11 may be used to form the gate of the driving transistor T3 and the first electrode of the storage capacitor Cst. As described above, the present disclosure may arrange the orthographic projection of the first conductive block 11 on the base substrate to overlap with the orthographic projection of the second shielding portion B2 on the base substrate. That is, the first conductive block 11 is arranged flush with the second shielding portion B2 in the first metal layer BSM, thereby reducing the area of ​​the first metal layer BSM and thereby resolving the color shift problem caused by strong light exposure on the display panel.

[0120] As shown in Figures 4 and 7, in an exemplary embodiment, the first conductive layer Gate1 may further include a first reset signal line Reset n, a gate signal line Gate, an enable signal line EM, and a second reset signal line Reset(n+1). The orthographic projections of the first reset signal line Reset n, the gate signal line Gate, and the enable signal line EM on the substrate may all extend along the row direction X and be spaced apart in the column direction Y. The first reset signal line Reset n and the gate signal line Gate are located on the same side of the first conductive block 11, and the enable signal line EM and the second reset signal line Reset(n+1) are located on the other side of the first conductive block 11. That is, in the layout structure, the first reset signal line Reset n and the gate signal line Gate are located on the same side of the driving transistor T3, and the enable signal line EM and the second reset signal line Reset(n+1) are located on the other side of the driving transistor T3.

[0121] The first reset signal line Reset n can be used to provide the first reset signal terminal shown in Figure 1, and the second reset signal line Reset(n+1) can be used to provide the second reset signal terminal shown in Figure 1. The orthographic projection of the first reset signal line Reset n on the substrate can overlap the orthographic projections of the fifth sub-active portion POL1-5 and the sixth sub-active portion POL1-6 on the substrate. As a result, a portion of the first reset signal line Reset n forms the gate of the first transistor T1, thus forming a dual-gate structure for the first transistor T1. The orthographic projection of the second reset signal line Reset(n+1) on the substrate can overlap the orthographic projection of the seventh active portion POL7 on the substrate. As a result, a portion of the second reset signal line Reset(n+1) forms the gate of the seventh transistor T7. In this exemplary embodiment, the second reset signal line Reset(n+1) in one row can be reused as the first reset signal line Reset n in the next row. This signal line multiplexing can reduce the number of signal lines and simplify the layout.

[0122] The gate signal line Gate can be used to provide the gate signal terminal in Figure 1. In this exemplary embodiment, the second transistor T2 includes a dual channel, and the gate signal line Gate can include a main extension portion Gate0 and a secondary extension portion Gate1. The orthographic projection of the main extension portion Gate0 on the substrate can extend along the row direction X, and the orthographic projection of the secondary extension portion Gate1 on the substrate can extend along the column direction Y. The orthographic projection of the main extension portion Gate0 on the substrate can cover the orthographic projection of the first sub-active portion POL2-1 on the substrate, and the orthographic projection of the secondary extension portion Gate1 on the substrate can cover the orthographic projection of the second sub-active portion POL2-2 on the substrate. In this way, a partial structure of the gate signal line Gate can form a dual gate of the second transistor T2.

[0123] A certain structure A described in the present disclosure extends along direction B, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0124] 5 , 8 , and 9 , in this exemplary embodiment, the first shield portion B1 includes a first sub-shielding portion B1-1 and a second sub-shielding portion B1-2. The first sub-shielding portion B1-1 corresponds to the first sub-active portion POL2-1, and the second sub-shielding portion B1-2 corresponds to the second sub-active portion POL2-2. The orthographic projection of the first sub-shielding portion B1-1 on the base substrate extends along the row direction X and has a fifth width d5 ​​in the column direction Y. The orthographic projection of the main extension portion Gate0 and the first sub-shielding portion B1-1 on the base substrate has a first overlapping portion, and the first overlapping portion has a seventh width d7 in the column direction Y, and the fifth width d5 ​​is greater than the seventh width d7. The orthographic projection of the second sub-shielding portion B1-2 on the base substrate extends along the column direction Y and has a sixth width d6 in the row direction X. The orthographic projection of the secondary extension portion Gate1 and the second sub-active portion POL2-2 on the base substrate has a second overlapping portion, and the second overlapping portion has an eighth width d8 in the row direction X, and the sixth width d6 is greater than the eighth width d8.

[0125] Specifically, the first shield portion B1 shields the first sub-active portion POL2-1 via the first sub-shielding portion B1-1 and shields the second sub-active portion POL2-2 via the second sub-shielding portion B1-2. The width d5 ​​of the first sub-shielding portion B1-1 in the column direction Y is greater than the width d7 of the gate signal line Gate at the corresponding position. That is, the first metal layer BSM overlays the gate signal line Gate at the position corresponding to the first sub-active portion POL2-1, so that the first metal layer BSM not only shields the first sub-active portion POL2-1 but also shields the gate signal line Gate at that position. In an exemplary embodiment, the ratio of the width d7 of the gate signal line Gate at the position corresponding to the first sub-active portion POL2-1 to the width d5 ​​of the first sub-shielding portion B1-1 can be greater than or equal to 50%, for example, 50%, 55%, 60%, 70%, 80%, 90%, etc.

[0126] Similarly, the width d6 of the second sub-shielding portion B1-2 is greater than the width d8 of the secondary extension Gate1 of the gate signal line Gate, thereby overlaying the secondary extension Gate1 of the gate signal line Gate with the first metal layer BSM. Similarly, the ratio of the width of the secondary extension Gate1 of the gate signal line Gate to the width of the second sub-shielding portion B1-2 can be greater than or equal to 50%, for example, 50%, 55%, 60%, 70%, 80%, 90%, etc.

[0127] Furthermore, as shown in FIG8 , in this exemplary embodiment, the secondary extension Gate1 and the second sub-shielding portion B1-2 have a third overlapping portion when projected onto the base substrate. The third overlapping portion has a first length L1 in the column direction Y. The orthographic projection of the secondary extension Gate1 onto the base substrate has a second length L2 in the column direction Y, and the first length L1 is less than the second length L2. In other words, a portion of the secondary extension Gate1 of the gate signal line Gate extends beyond the boundary of the second sub-shielding portion B1-2, thereby partially shielding the secondary extension Gate1 of the gate signal line Gate.

[0128] The length / width of a certain structure A described in the present disclosure in direction B can be determined by the following method: the structure A has a first side and a second side arranged opposite to each other in direction B, a straight line passing through any first node on the first side and extending along direction B intersects the second side at the second node, and the distance between the first node and the second node is the length / width of the structure A in direction B.

[0129] The enable signal line EM can be used to provide the enable signal terminal in Figure 1. The orthographic projection of the enable signal line EM on the substrate can respectively cover the orthographic projections of the fifth active portion POL5 and the sixth active portion POL6 on the substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and part of the structure can be used to form the gate of the sixth transistor T6.

[0130] The display panel disclosed herein can use the first conductive layer Gate1 as a mask to perform conductor processing on the active layer Polly, that is, the active layer Polly covered by the first conductive layer Gate1 forms the channel region of the transistor, and the area not covered by the first conductive layer Gate1 forms a conductor structure. It should also be understood that in actual products, the structure of the transistor gate formed by the first conductive layer will usually overlay the active portion blocked by it, that is, in actual products, the structure of the transistor gate formed in the first conductive layer has a slightly larger orthographic projection area on the substrate than the active portion covered by it. In other words, the gate structure corresponding to the active portion in the orthographic projection area of ​​the substrate is within the orthographic projection area of ​​the substrate.

[0131] As shown in Figures 4 and 12, in an exemplary embodiment, the second conductive layer Gate2 may include a second conductive block 22. The orthographic projection of the second conductive block 22 on the substrate may be located on the orthographic projection of the first conductive block 11 on the substrate. The second conductive block 22 may be used to form the second electrode of the storage capacitor Cst. The second conductive block 22 may have a hollow portion that exposes a portion of the first conductive block 11. This allows the first conductive block 11 to be connected to the first bridge portion 31 of the first source-drain metal layer SD1 through the hollow portion, thereby connecting the gate of the drive transistor T3 to the second electrode of the first transistor T1 through the first bridge portion 31.

[0132] The second conductive block 22 can be connected to the power adapter line VDDL located in the first source-drain metal layer SD1 through a via, and then connected to the first power line VDD of the second source-drain metal layer SD2 through the power adapter line VDDL, thereby connecting the second conductive block 22 to the first power line VDD.

[0133] In this exemplary embodiment, two adjacent second conductive blocks 22 in the row direction X are connected to each other, so that the first power line VDD forms a grid structure with staggered rows and columns through the transversely extending second conductive blocks 22. The first power line VDD in the grid structure can reduce the impedance of the first power line VDD, thereby reducing the RC load of the first power line VDD, and further reducing the power consumption of the display panel.

[0134] As shown in Figure 12, in an exemplary embodiment, the second conductive layer Gate2 may further include a first initialization signal line Vinit1 and a second initialization signal line Vinit2. The first initialization signal line Vinit1 and the second initialization signal line Vinit2 may both extend along the row direction X. The first initialization signal line Vinit1 may be used to provide the first initialization signal terminal in Figure 1. The first initialization signal line Vinit1 may be connected to the third bridge portion 33 of the first source-drain metal layer SD1 through a via, so as to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1 through the third bridge portion 33.

[0135] The second initialization signal line Vinit2 can be used to provide the second initialization signal terminal in Figure 1. The second initialization signal line Vinit2 can be located between the first initialization signal line Vinit1 of the next row and the enable signal line EM of the current row, and the second initialization signal line Vinit2 can be connected to the second bridge portion 32 of the first source-drain metal layer SD1 through a via, so as to connect the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2 through the second bridge portion 32.

[0136] As shown in FIG12 , in an exemplary embodiment, the second conductive layer Gate2 may further include a third conductive block 23. The third conductive block 23 may be connected to a constant voltage source, for example, the first power line VDD via a via. The third conductive block 23 may include a first sub-conductive portion 231. The orthographic projection of the first sub-conductive portion 231 on the substrate may extend along the column direction Y. The orthographic projection of the first sub-conductive portion 231 on the substrate may be located on the orthographic projection of the ninth active portion POL9 on the substrate. Thus, the first sub-conductive portion 231 may be used to stabilize the voltage of the ninth active portion POL9, thereby reducing leakage of the second transistor T2 and preventing the influence of pixel data voltage changes in adjacent columns on the pixel. This reduces voltage fluctuations in the pixel driver circuit driving transistor T3 during the light-emitting phase, thereby improving image quality.

[0137] The third conductive block 23 may further include a second sub-conductive portion 232, wherein the orthographic projection of the second sub-conductive portion 232 on the base substrate at least partially overlaps with the orthographic projection of the eleventh active portion POL11 on the base substrate (for example, the width of the second sub-conductive portion 232 in the row direction X may be set to be greater than the width of the eleventh active portion POL11 in the row direction X). Thus, the second sub-conductive portion 232 can stabilize the voltage of the eleventh active portion POL11, thereby eliminating or reducing the impact of noise from the data signal line Vdata or other signal lines on the eleventh active portion POL11. Because the eleventh active portion POL11 is connected to the gate of the driving transistor T3, the voltage stabilization of the eleventh active portion POL11 can reduce voltage fluctuations of the driving transistor T3 of the pixel driving circuit during the light-emitting stage.

[0138] In addition, the third conductive block 23 may further include a third sub-conductive portion 233. The third sub-conductive portion 233 is connected to the second sub-conductive portion 232 to connect to a constant voltage source. The orthographic projection of the third sub-conductive portion 233 on the substrate may extend along the column direction Y. The orthographic projection of the third sub-conductive portion 233 on the substrate is located between the orthographic projection of the eleventh active portion POL11 on the substrate and the orthographic projection of the data signal line Vdata on the substrate. This can shield the alternating voltage of the data signal line Vdata from interfering with the eleventh active portion POL11, thereby improving the voltage stabilization effect of the third conductive block 23 on the eleventh active portion POL11. Furthermore, it should be understood that a conductive connection portion is provided between the third sub-conductive portion 233 and the second sub-conductive portion 232.

[0139] As shown in Figures 4 and 13, in an exemplary embodiment, the first source-drain metal layer SD1 may include a power adapter line VDDL. The orthographic projection of the power adapter line VDDL on the substrate may extend along the column direction Y. The power adapter line VDDL may connect to the second conductive block 22 of the second conductive layer Gate2 and the seventeenth active portion POL17 of the active layer Polly via a via. Furthermore, the power adapter line VDDL may connect to the first power line VDD of the second source-drain metal layer SD2 via a via, thereby connecting the second electrode of the storage capacitor Cst and the first electrode of the fifth transistor T5 to the first power line VDD. The power adapter line VDDL forms a parallel structure with the first power line VDD. This reduces the line resistance of the first power line VDD, thereby reducing the voltage drop loss on the first power line VDD. Furthermore, when the first power line VDD is broken, a path is formed through the power adapter line VDDL. This prevents the pixel driving circuit from malfunctioning due to the broken first power line VDD, thereby improving the reliability of the display panel.

[0140] As shown in Figure 13, in an exemplary embodiment, the first source-drain metal layer SD1 may further include a first bridge portion 31, a second bridge portion 32 and a third bridge portion 33. The first bridge portion 31, the second bridge portion 32 and the third bridge portion 33 may all extend along the column direction Y. One end of the first bridge portion 31 may be connected to the first conductive block 11 through a via, and the other end may be connected to the eleventh active portion POL11 through a via to connect the second electrode of the first transistor T1 to the gate of the driving transistor T3.

[0141] One end of the second bridge portion 32 can be connected to the fifteenth active portion POL15 through a via to connect to the first electrode of the seventh transistor T7, and the other end of the second bridge portion 32 can be connected to the second initialization signal line Vinit2 through a via, thereby connecting the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2.

[0142] One end of the third bridge portion 33 can be connected to the twelfth active portion POL12 through a via to connect to the first electrode of the first transistor T1, and the other end of the third bridge portion 33 can be connected to the first initialization signal line Vinit1 through a via, thereby connecting the first electrode of the first transistor T1 to the first initialization signal line Vinit1 through the third bridge portion 33.

[0143] FIG17 is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. As shown in FIG17 , the display panel of the present disclosure may include a first display area 101 and a second display area 102 at least partially surrounding the first display area 101. The first display area 101 has a greater light transmittance than the second display area 102, and the first display area 101 includes multiple pixel rows. For example, the first display area 101 may be an FDC (Full Display with Camera) area, a fingerprint area, or the like, and the second display area 102 may be a normal display area AA. The position of the first display area 101 within the second display area 102 is not limited and may be located above or below the second display area 102, or at an edge of the second display area 102. In this exemplary embodiment, within a plane parallel to the display substrate, the shape of the first display area 101 may be any one or more of the following: square, rectangular, polygonal, circular, and elliptical. Optical devices such as a fingerprint recognition device, a camera device, or an optical sensor for 3D imaging may be placed within the first display area 101.

[0144] It can be understood that the signal lines extending in the row direction X are disconnected in the first display area 101, resulting in uneven loads on the signal lines extending in the row direction X. As shown in FIG13 , in this exemplary embodiment, the first source / drain metal layer SD1 may further include a first connecting line 35 . The first connecting line 35 may be located in the second display area 102 . The orthographic projection of the first connecting line 35 on the substrate may extend along the column direction Y. The first connecting line 35 may connect the second bridge portion 32 in the pixel driving circuit of the current row with the second bridge portion 32 in the pixel driving circuit of the next row, thereby connecting the second bridge portions 32 in each pixel driving circuit in the same column. This allows the second initialization signal line Vinit2 to form a grid structure with staggered rows and columns. This grid structure can reduce the impedance of the second initialization signal line Vinit2 and reduce the RC load of the second initialization signal line Vinit2, thereby facilitating reduced power consumption. In addition, the second initialization signal line Vinit2 is set to a grid structure, which can connect the disconnected second initialization signal line Vinit2, so that the RC load on the second initialization signal line Vinit2 is more uniform, thereby eliminating the problem of uneven display brightness caused by the disconnection of the second initialization signal line Vinit2 and improving display uniformity.

[0145] As shown in FIG13 , in an exemplary embodiment, the first source-drain metal layer SD1 may further include a first transition portion 301. The first transition portion 301 may be connected to the second transition portion 402 of the second source-drain metal layer SD2 via a via and to the eighteenth active portion POL18 via a via, thereby connecting the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the first electrode of the light-emitting device. It is worth noting that in this exemplary embodiment, considering that the first electrodes ANO of different sub-pixels have different sizes, the offset positions of the first electrodes ANO of different sub-pixels relative to the sixth transistor T6 and the seventh transistor T7 in the pixel driving circuit may vary. For example, the display panel may include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. The first sub-pixel may be, for example, an R sub-pixel, the second sub-pixel may be, for example, a G sub-pixel, and the third sub-pixel may be, for example, a B sub-pixel. Of course, in other embodiments, the sub-pixels may have other arrangements. This exemplary embodiment is illustrative only by using the example of the first sub-pixel being an R sub-pixel, the second sub-pixel being, for example, a G sub-pixel, and the third sub-pixel being a B sub-pixel. The first electrode ANO-R of the first subpixel R has the largest area, while the first electrode ANO of the second subpixel G has the smallest area. The first subpixel R and the third subpixel B can be located in the first pixel column, and the second subpixel G can be located in the second pixel column, with the first and second pixel columns alternating in the row direction. In the first pixel column, the first transition portion 301 can directly connect to the second transition portion 402 of the second source / drain metal layer SD2 via a via to connect to the first electrode ANO at the corresponding position. In the second pixel column, the first source / drain metal layer SD1 can further include a sub-connection portion 322. The first transition portion 301 can include a first sub-transition portion 3011 and a second sub-transition portion 3012, which can be connected via the sub-connection portion. The second transition portion 402 can be bent to connect the second sub-transition portion 3012 located below the first electrode ANO in the second pixel column to the first sub-transition portion 3011 located above the second electrode of the sixth transistor T6.

[0146] As shown in Figure 13, in an exemplary embodiment, the first source-drain metal layer SD1 may further include a data transfer portion VdataL, which may be connected to the fourteenth active portion POL14 through a via to connect to the second electrode of the fourth transistor T4 and to the data signal line Vdata of the second source-drain metal layer SD2 through a via, thereby connecting the second electrode of the fourth transistor T4 to the data signal line Vdata.

[0147] As shown in Figures 4 and 14, in an exemplary embodiment, the second source-drain metal layer SD2 may include a first power line VDD and a data signal line Vdata, and the orthographic projections of the first power line VDD and the data signal line Vdata on the substrate may extend along the column direction Y, wherein the first power line VDD may be used to provide the first power terminal in Figure 1, and the first power line VDD may be connected to the power transfer line VDDL of the first source-drain metal layer SD1 through a via to connect the second electrode of the storage capacitor Cst and the first electrode of the fifth transistor T5 through the power transfer line VDDL.

[0148] The data signal line Vdata can be used to provide the data signal end in Figure 1. The data signal line Vdata can be connected to the data transfer portion VdataL of the first source-drain metal layer SD1 through a via, so as to connect the data signal line Vdata to the second electrode of the fourth transistor T4 through the data transfer portion VdataL.

[0149] As shown in Figure 14, in an exemplary embodiment, the second source-drain metal layer SD2 may also include a second transition portion 402, which can be connected to the first transition portion 301 of the first source-drain metal layer SD1 through a via and to the first electrode ANO of the first electrode layer ANOL through a via, thereby connecting the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the first electrode ANO of the light-emitting device.

[0150] As shown in Figure 14, in an exemplary embodiment, the second source-drain metal layer SD2 may further include an electrode flat portion 40, the electrode flat portion 40 may be connected to the first power line VDD, and the electrode flat portion 40 may be located below the first electrode ANO to flatten the first electrode ANO below the first electrode ANO. For example, the orthographic projection of the first electrode ANO on the base substrate may cover the orthographic projection of the electrode flat portion 40 on the base substrate, thereby preventing the first electrode ANO from tilting, thereby ensuring that the light-emitting device can display normally.

[0151] As shown in FIG. 15 , in an exemplary embodiment, the first electrode layer ANOL may include a plurality of first electrodes ANO. The first electrode ANO may be, for example, an anode of a light-emitting device. In other embodiments, the first electrode ANO may also be a cathode of the light-emitting device, without particular limitation. This disclosure only uses the first electrode ANO as an anode of a light-emitting device for exemplary description.

[0152] The first electrode ANO may be connected to the second transfer portion 402 of the second source / drain metal layer SD2 through a via hole, so as to connect the first electrode ANO of the light-emitting device to the second electrodes of the sixth transistor T6 and the seventh transistor T7 through the second transfer portion 402 .

[0153] The display panel disclosed herein may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, each sub-pixel being arranged in a one-to-one correspondence with a pixel driving circuit, and the first electrode of the first sub-pixel and the first electrode of the third sub-pixel being located in a first pixel column, the first electrode of the second sub-pixel being located in a second pixel column, and the first pixel column and the second pixel column being alternately distributed in the row direction.

[0154] Exemplarily, Figure 18 is a schematic diagram of the arrangement of sub-pixels according to an embodiment of the present disclosure. As shown in Figure 18, the first sub-pixel can be an R sub-pixel, the second sub-pixel can be a G sub-pixel, and the third sub-pixel can be a B sub-pixel. A pixel unit includes a first sub-pixel R, a second sub-pixel G and a third sub-pixel B. The first sub-pixel R and the third sub-pixel B of each pixel unit are located in the same row, namely the first sub-pixel row X1, and the second sub-pixel G of each pixel unit is located in the same row to form the second sub-pixel row X2. The first sub-pixel R and the third sub-pixel B are located in the first pixel column Y1, and the second sub-pixel G is located in the second pixel column Y2, thereby forming an RGBG pixel arrangement.

[0155] FIG19 is a schematic diagram of a sub-pixel arrangement according to another embodiment of the present disclosure. As shown in FIG19 , the first sub-pixel may be an R sub-pixel, the second sub-pixel may be a B sub-pixel, and the third sub-pixel may be a G sub-pixel. In this arrangement, the first sub-pixel R and the third sub-pixel G are located in the first pixel column Y1, and the second sub-pixel B is located in the second pixel column Y2. The first pixel column Y1 and the second pixel column Y2 are alternately distributed in the row direction, thereby forming an RGB pixel arrangement. It should be understood that in other embodiments, the sub-pixels may also have other arrangements. As long as the sub-pixels form two pixel columns arranged alternately in the row direction, they are applicable to the disclosed solution, and they are not listed here one by one.

[0156] In conjunction with Figures 18, 19 and 15, in the same column of sub-pixels, the first electrode ANO of the first sub-pixel and the first electrode ANO of the third sub-pixel are located in the first pixel column, the first electrode ANO of the second sub-pixel is located in the second pixel column, and the first pixel column and the second pixel column are alternately distributed in the row direction X. Below, only the first sub-pixel is an R sub-pixel, the second sub-pixel is a G sub-pixel, the third sub-pixel is a B sub-pixel, and the first electrode of the first sub-pixel is represented as ANO-R, the first electrode of the second sub-pixel is represented as ANO-G, and the first electrode of the third sub-pixel is represented as ANO-B as an example, and the pixel electrode arrangement shown in Figure 15 is further explained to illustrate the scheme of the present disclosure. It should be understood that the sub-pixels can also eliminate or reduce the problem of display color deviation under strong light illumination based on the inventive concept of the present disclosure in other arrangements, and the present disclosure will not list them one by one.

[0157] Based on the above embodiment, Figure 20 is a structural layout diagram of a display panel according to another embodiment of the present disclosure. Figure 21 is a structural layout diagram of the first electrode layer in Figure 20. Figure 22 is a stacked layout diagram of the active layer, first conductive layer, and first electrode layer in Figure 20. Figure 23 is a partial enlarged view of the portion corresponding to the first electrode of the first pixel driving circuit extending to the second transistor of the second pixel driving circuit in Figure 22. It should be understood that the layout structure shown in Figure 20 can have all the features of the first metal layer BSM, active layer Polly, first conductive layer Gate1, second conductive layer Gate2, first source and drain metal layer SD1, and first electrode layer ANOL in the layout structure shown in Figure 4, and will not be described in detail here. In addition, the first metal layer BSM may also have other structures. For example, as shown in Figure 24, the first metal layer BSM may also block the conductive structure T2M between the dual channels of the second transistor T2 at the second transistor T2, that is, the first shielding part B1 no longer has a gap B0, but completely blocks the channel area of ​​the second transistor T2 and the conductive structure T2M between the dual channels. This exemplary embodiment does not specifically limit the structure of the first metal layer BSM.

[0158] In an exemplary embodiment, the second metal layer may be the first electrode layer ANOL, that is, the metal of the first electrode layer ANOL is used to shield the second transistor T2 and the driving transistor T3.

[0159] As shown in Figures 20 and 21 , the display panel includes a plurality of first repeating units Q1 arranged in an array in the row and column directions. The first repeating unit Q1 includes a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently arranged in the row direction X. The figure shows four first repeating units Q1, across two rows and four columns. In this exemplary embodiment, the first pixel driving circuit P1 can be provided in a one-to-one correspondence with the first subpixel R and the third subpixel B, and the second pixel driving circuit P2 can be provided in a one-to-one correspondence with the second subpixel G. That is, the pixel driving circuit driving the first subpixel R and the third subpixel B is the first pixel driving circuit P1, and the pixel driving circuit driving the second subpixel G is the second pixel driving circuit P2.

[0160] In combination with Figures 21, 22 and 23, in any first repeating unit Q1, the orthographic projection of the first electrode ANO connected to the first pixel driving circuit P1 on the substrate covers the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the first pixel driving circuit P1 on the substrate and overlaps with the orthographic projection of the third active portion POL3 on the substrate, and also at least partially overlaps with the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the second pixel driving circuit P2 on the substrate; the orthographic projection of the first electrode ANO connected to the second pixel driving circuit P2 on the substrate partially overlaps with the orthographic projection of the third active portion POL3 in the second pixel driving circuit P2 on the substrate.

[0161] Exemplarily, the orthographic projection of the first electrode ANO of the first subpixel R on the substrate can cover the orthographic projection of the third active portion POL3 in the corresponding pixel driving circuit on the substrate, and can also cover the orthographic projection of the second active portion POL2 and the ninth active portion POL9 in the adjacent second pixel driving circuit P2 on the substrate. That is, the first electrode ANO of the first subpixel R completely blocks the second transistor T2 and the driving transistor T3 in the corresponding pixel driving circuit, and can also completely block the second transistor T2 in the adjacent driving circuit, thereby improving the shielding effect on the active layer Polly. It should be understood that the pixel driving circuit corresponding to the first electrode ANO described in the present disclosure refers to the pixel driving circuit connected to the first electrode.

[0162] The orthographic projection of the first electrode ANO of the third sub-pixel B on the substrate can cover the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the corresponding pixel driving circuit on the substrate and can partially overlap with the orthographic projection of the third active portion POL3 on the substrate. For example, the ratio of the area of ​​the overlapping portion to the area of ​​the third active portion POL3 can be greater than or equal to 75%, such as 75%, 80%, 85%, 90%, 95%, etc., that is, the first electrode ANO of the third sub-pixel B can completely block the second transistor T2 in the corresponding pixel driving circuit and partially block the driving transistor T3. At the same time, the orthographic projection of the first electrode ANO of the third subpixel B on the substrate can cover the orthographic projection of the ninth active portion POL9 in the adjacent second pixel driving circuit P2 on the substrate substrate and partially overlap with the orthographic projection of the second active portion POL2 on the substrate substrate. For example, the ratio of the area of ​​the overlapping portion to the area of ​​the second active portion POL2 can be greater than or equal to 50%, such as 50%, 60%, 75%, 80%, 85%, 90%, 95%, etc., that is, the first electrode ANO of the third subpixel B can also partially block the second transistor T2 in the pixel driving circuit of the adjacent second subpixel G. Of course, in some embodiments of the present disclosure, the orthographic projection of the first electrode ANO of the third subpixel B on the substrate substrate can also cover the orthographic projection of the third active portion POL3 in the corresponding pixel driving circuit on the substrate substrate and the orthographic projection of the second active portion POL2 in the pixel driving circuit of the adjacent second subpixel on the substrate substrate, that is, the first electrode ANO of the third subpixel B can also completely block the driving transistor T3 in the corresponding pixel driving circuit and the second transistor T2 in the adjacent pixel driving circuit.

[0163] In an exemplary embodiment, as shown in Figures 19 and 22, the first electrode ANO in the first sub-pixel R and the third sub-pixel B each includes a main portion ANO-1 and an additional portion ANO-2, the additional portion ANO-2 is connected to one side of the main portion ANO-1 along the row direction X, and the additional portion extends along the row direction X to the second transistor T2 of the second pixel driving circuit P2 in the same repeating unit. In the same first repeating unit Q1, the orthographic projection of the main portion ANO-1 of the first subpixel R on the base substrate covers the orthographic projections of the second active portion POL2, the third active portion POL3, and the ninth active portion POL9 in the first pixel driving circuit P1, and also covers the orthographic projections of the first sub-active portion POL2-1 and the third sub-active portion POL9-3 in the second pixel driving circuit P2. The orthographic projection of the additional portion ANO-2 of the first subpixel R on the base substrate covers the orthographic projections of the second sub-active portion POL2-2 and the fourth sub-active portion POL9-4 in the second pixel driving circuit P2. In other words, the first electrode ANO of the first subpixel R shields the second transistor T2 and the driving transistor T3 in the corresponding pixel driving circuit, as well as the first channel region of the second transistor T2 in the adjacent pixel driving circuit, through its main portion ANO-1. Furthermore, the additional portion ANO-2 shields the second channel region and the conductive structure T2M of the second transistor T2 in the adjacent pixel driving circuit.

[0164] In the same first repeating unit Q1, the orthographic projection of the main portion ANO-1 of the first electrode ANO of the third subpixel B on the substrate covers the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the first pixel driving circuit P1 on the substrate and overlaps with the orthographic projection of the third active portion POL3 on the substrate. The orthographic projection of the additional portion ANO-2 of the first electrode ANO of the third subpixel B on the substrate covers the orthographic projections of the second sub-active portion POL2-2 and the ninth active portion POL9 in the second pixel driving circuit P2 on the substrate and partially overlaps with the orthographic projection of the first sub-active portion POL2-1 on the substrate. In other words, the first electrode ANO of the third subpixel B can completely block the second transistor T2 in the corresponding pixel driving circuit through its main portion ANO-1 and can partially block the driving transistor T3 in the corresponding pixel driving circuit. The first electrode ANO of the third subpixel B can partially block the second transistor T2 in the adjacent driving circuit through its additional portion ANO-2. Of course, in some embodiments, the orthographic projection of the first electrode ANO of the third sub-pixel on the substrate can also cover the orthographic projection of the third active part POL3 in the corresponding pixel driving circuit on the substrate and the orthographic projection of the first sub-active part in the adjacent pixel driving circuit on the substrate, that is, the first electrode ANO of the third sub-pixel can also completely block the driving transistor T3 in the corresponding pixel driving circuit and the second transistor T2 in the adjacent pixel driving circuit.

[0165] This exemplary embodiment is equivalent to enlarging the first electrodes ANO-B of both the first subpixel R and the third subpixel B, so that the first electrodes ANO-R of the first subpixel R and the first electrodes ANO-B of the third subpixel B block the second transistor T2 in both the pixel drive circuit and the adjacent pixel drive circuit for driving the second subpixel G. This effectively avoids the influence of external light sources and improves or eliminates the color shift problem caused by strong light exposure. In this exemplary embodiment, the extended portion ANO-2 of the first electrode ANO-R of the first subpixel R is smaller than the extended portion ANO-B of the first electrode ANO-B of the third subpixel B. That is, the enlarged area of ​​the first electrode ANO-B of the third subpixel B is larger than the enlarged area of ​​the first electrode ANO-R of the first subpixel R, so that the first electrode ANO-B of the third subpixel B can effectively block the second transistor T2 in the adjacent pixel drive circuit for driving the second subpixel G.

[0166] Based on the above embodiment, Figure 25 is a structural layout diagram of a display panel according to another embodiment of the present disclosure, Figure 26 is a structural layout diagram of the second source / drain metal layer in Figure 25, Figure 27 is a stacking layout diagram of the active layer and the second source / drain metal layer in Figure 25, and Figure 28 is a stacking layout diagram of the active layer, the second source / drain metal layer, and the first electrode layer in Figure 25. It should be understood that the layout structure shown in Figure 25 can have all the features of the first metal layer BSM, the active layer Polly, the first conductive layer Gate1, the second conductive layer Gate2, the first source / drain metal layer SD1, and the first electrode layer ANOL in the above embodiment, and will not be described in detail here.

[0167] As described above, the second source-drain metal layer SD2 may include an electrode flat portion 40. This exemplary embodiment may utilize the electrode flat portion 40 in conjunction with the first electrode ANO to shield the second transistor T2 and the driving transistor T3 to shield light incident from the display side to the second transistor T2 and the driving transistor T3.

[0168] As shown in Figures 25 to 28, in an exemplary embodiment, the electrode flat portion 40 in the second source / drain metal layer SD2 may include a first flat portion 411, a second flat portion 412, and a third flat portion 413. The first flat portion 411 is provided in a one-to-one correspondence with the first sub-pixel R, the second flat portion 412 is provided in a one-to-one correspondence with the second sub-pixel G, and the third flat portion 413 is provided in a one-to-one correspondence with the third sub-pixel B. That is, the second flat portion 412 is located in the second pixel driving circuit P2, and the first flat portion 411 and the third flat portion 413 are both located in the first pixel driving circuit P1 in corresponding repeating units. The first flat portion 411 and the third flat portion 413 are located in the first pixel column, and the second flat portion 412 is located in the second pixel column.

[0169] The display panel may include a plurality of first repeating units Q1 arranged in an array in row and column directions. The first repeating unit Q1 includes a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently arranged in the row direction X.

[0170] As shown in Figures 26 to 28, the second flat portion 412 may include a first extension portion 4121, a second extension portion 4122, and a third extension portion 4123 sequentially connected in the column direction Y. In the same first repeating unit Q1, the orthographic projection of the first extension portion 4121 on the substrate may overlap with the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the same pixel driving circuit on the substrate. For example, it may cover the orthographic projections of the second sub-active portion POL2-2 and the fourth sub-active portion POL9-4 in the same pixel driving circuit on the substrate and overlap with the orthographic projections of the first sub-active portion POL2-1 and the third sub-active portion POL9-3 on the substrate. The ratio of the overlapping area to the area of ​​the first sub-active portion POL2-1 may be greater than or equal to 5, for example. %, such as 5%, 10%, 20%, 25%, 30%, 35%, 40%, 50%, 60%, 70%, etc. Similarly, the ratio of the overlapping area of ​​the first extension portion 4121 and the first extension portion 4121 to the area of ​​the first extension portion 4121 can be greater than or equal to 5%; the orthographic projection of the second extension portion 4122 on the substrate overlaps with the orthographic projection of the third active portion POL3 in the same pixel driving circuit on the substrate, for example, the ratio of the area of ​​the overlapping portion to the area of ​​the electrically active portion POL3 can be greater than or equal to 5%, such as 5%, 10%, 20%, 25%, 30%, 35%, 40%, 50%, 60%, 70%, etc.; the orthographic projection of the third extension portion 4123 on the substrate is located within the orthographic projection of the first electrode ANO of the corresponding sub-pixel on the substrate. Specifically, because in the second sub-pixel G, the second transistor T2 and the driving transistor T3 are not in the pixel opening area, this exemplary embodiment is equivalent to extending the electrode flat portion 40 in the pixel driving circuit corresponding to the second sub-pixel G in the column direction, so that the electrode flat portion 40 in the second sub-pixel G can block part of the second transistor T2 and part of the driving transistor T3 in this pixel driving circuit, thereby improving the blocking effect on the second transistor T2 and the driving transistor T3, and further improving the color deviation problem caused by strong light exposure.

[0171] Further, as shown in Figure 28, in any first repeating unit Q1, the orthographic projections of the first electrode ANO-R of the first sub-pixel R and the first electrode ANO-B of the third sub-pixel B on the substrate cover the orthographic projections of the second active portion POL2, the ninth active portion POL9 and the third active portion POL3 in the corresponding first pixel driving circuit P1 on the substrate, and the orthographic projection of the first electrode ANO-R of the first sub-pixel R on the substrate also covers the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the corresponding second pixel driving circuit P2 on the substrate, and the orthographic projection of the first electrode ANO-B of the third sub-pixel B on the substrate at least partially overlaps with the orthographic projections of the second active portion POL2 and the ninth active portion POL9 in the corresponding second pixel driving circuit P2 on the substrate, for example, it can cover the orthographic projections of the second sub-active portion POL2-2 and the ninth active portion POL9 in the corresponding second pixel driving circuit P2 on the substrate. That is, the first electrode ANO-R of the first subpixel R not only blocks the second transistor T2 and the driving transistor T3 in its own pixel driving circuit, but also blocks the second transistor T2 corresponding to the adjacent second subpixel G in the row direction X. This compensates for the inability of the flat electrode portion 40 in the second subpixel G to completely block the second transistor T2, further improving the pixel driving circuit's ability to suppress leakage current and alleviating color shift issues on the display panel under strong light. The first electrode ANO-B of the third subpixel B is smaller in area. In addition to blocking the second transistor T2 and the driving transistor T3 in its own pixel driving circuit, the first electrode ANO-B of the third subpixel B also partially blocks the second transistor T2 corresponding to the adjacent second subpixel G in the row direction X, similarly alleviating color shift issues caused by strong light.

[0172] As shown in Figures 26 and 27, in an exemplary embodiment, in the second flat portion 412, a hollow portion HOL is provided between the first extension portion 4121 and the second extension portion 4122, and the hollow portion HOL is used to expose at least part of the gap between the second transistor T2 and the driving transistor T3. It can be known that a transistor is generally composed of a plurality of structures distributed across two or more functional film layers. Accordingly, the area covered on the substrate by all the structures distributed across the plurality of functional film layers for forming a transistor is the area occupied by the transistor. Therefore, the gap between the second transistor T2 and the driving transistor T3 described in the present disclosure can be specifically understood as follows: the entire structure distributed across the plurality of functional film layers for forming the second transistor T2 covers the first area on the substrate, and the entire structure distributed across the plurality of functional film layers for forming the driving transistor T3 covers the second area on the substrate, and the blank area between the first area and the second area is the gap between the second transistor T2 and the driving transistor T3.

[0173] In this exemplary embodiment, the second flat portion 412 exposes the gap between the second transistor T2 and the driving transistor T3, thereby ensuring the light transmittance of the first display area 101. This prevents the light transmittance of the first display area 101 from being less than the designed value due to complete obstruction by the metal. For example, by exposing the second flat portion 412 to the gap between the second transistor T2 and the driving transistor T3, the light transmittance of the first display area 101 can be increased to greater than or equal to 2%, thereby meeting the light transmittance requirements of the first display area 101. In addition, by exposing the second flat portion 412 to the gap between the second transistor T2 and the driving transistor T3, the pixel capacitance of the second sub-pixel G can be adjusted, making the pixel capacitance of different sub-pixels more uniform.

[0174] As shown in FIG26 , in this exemplary embodiment, the first extension 4121 has a first width d1 when projected onto the substrate in the row direction X. The second extension 4122 has a second width d2 when projected onto the substrate in the row direction X. The third extension 4123 has a third width d3 when projected onto the substrate in the row direction X. The second width d2 is smaller than the first width d1 and smaller than the third width d3. In other words, the second flat portion 412 is wider at both ends and narrower in the middle in the row direction X. The third extension 4123 is located below the first electrode ANO of the second subpixel G and supports the first electrode ANO in the row direction X, thereby flattening the first electrode ANO. The second extension portion 4122 is located below the driving transistor T3. The width of the second extension portion 4122 in the row direction X is reduced to avoid the first electrode ANO transition portion on the same layer. In this exemplary embodiment, the orthographic projection of the second extension portion 4122 on the substrate overlaps at least partially with the orthographic projection of the third active portion POL3 on the substrate, that is, the second extension portion 4122 can block part of the channel region of the driving transistor T3. The first extension portion 4121 extends below the second transistor T2 to block the second transistor T2. The first extension portion 4121 also blocks the conductive structure T2M connected between the dual channels of the second transistor T2, thereby increasing the blocking area for the second transistor T2 and improving the color shift caused by photogenerated carriers generated by strong light exposure. It is worth noting that the width of a certain extension portion M in the direction C described in this disclosure refers to the width of the main part of the extension portion M in the direction C.

[0175] As shown in Figure 28, in an exemplary embodiment, the orthographic projection of the first flat portion 411 on the base substrate may partially overlap with the orthographic projections of the second active portion POL2, the third active portion POL3 and the ninth active portion POL9 in the same pixel driving circuit on the base substrate. For example, it may cover the orthographic projections of the second sub-active portion POL2-2, the fourth sub-active portion POL9-4 and the third active portion POL3 in the same pixel driving circuit on the base substrate, and may partially overlap with the orthographic projections of the first sub-active portion POL2-1 and the third sub-active portion POL9-3 on the base substrate. Because the electrode flat portion 40 needs to avoid the data signal line Vdata on the left side of the same layer to avoid adhesion with the data signal line Vdata, the electrode flat portion 40 cannot completely block the second transistor T2. Similarly, the orthographic projection of the third flat portion 413 on the substrate can partially overlap with the orthographic projections of the second active portion POL2, the third active portion POL3 and the ninth active portion POL9 in the same pixel driving circuit on the substrate. For example, it can cover the orthographic projections of the second sub-active portion POL2-2 and the fourth sub-active portion POL9-4 in the same pixel driving circuit on the substrate and at least partially overlap with the orthographic projection of the third active portion POL3 on the substrate, that is, the first electrode ANO-B of the third sub-pixel B also has to avoid the data signal line Vdata and cannot completely block the second transistor T2.

[0176] The orthographic projections of the first electrode ANO-B of the third subpixel B and the third active portion POL3 on the substrate at least partially overlap. For example, the overlapping area can be greater than or equal to 85%. This means that the first electrode ANO-B of the third subpixel B can effectively block most of the structure of the driving transistor T3, thereby improving the color shift improvement effect. Furthermore, it will be understood that the orthographic projections of the first electrode ANO-R of the first subpixel R and the first electrode ANO-B of the third subpixel B on the substrate both overlap the orthographic projections of the first flat portion 411 in the corresponding pixel driving circuit on the substrate, enabling the flat electrode portion 40 to provide planar support for the first electrode ANO located thereon.

[0177] As shown in Figure 26, in an exemplary embodiment, the orthographic projection of the first electrode ANO-R of the first sub-pixel R on the substrate has a first area, the orthographic projection of the first electrode ANO of the second sub-pixel G on the substrate has a second area, and the orthographic projection of the first electrode ANO-B of the third sub-pixel B on the substrate has a third area, the first area > the third area > the second area, the first flat portion 411 has a first extension length L1 in the column direction Y, the second flat portion 412 has a second extension length L2 in the column direction Y, and the third flat portion 413 has a third extension length L3 in the column direction Y, and the second extension length L2 > the first extension length L1 > the third extension length L3. That is, the lengths of the electrode flat portions 40 of the first sub-pixel R and the third sub-pixel B remain unchanged, while the electrode flat portion 40 of the second sub-pixel G is lengthened so that the electrode flat portion 40 of the second sub-pixel G is the longest, so that the electrode flat portion 40 of the second sub-pixel G can partially block the second transistor T2 of the second sub-pixel G. For the entire display panel, the blocking area for the second transistor T2 and the driving transistor T3 in the driving backplane is increased, thereby reducing photogenerated carriers and leakage current, thereby solving the problem of color shift caused by strong light exposure on the display panel.

[0178] Based on the above embodiments, Figure 29 is a structural layout of a display panel according to another embodiment of the present disclosure, Figure 30 is a structural layout of the first metal layer in Figure 29, Figure 31 is a structural layout of the active layer in Figure 29, Figure 32 is a structural layout of the first conductive layer in Figure 29, Figure 33 is a structural layout of the second conductive layer in Figure 29, Figure 34 is a structural layout of the first source-drain metal layer in Figure 29, Figure 35 is a structural layout of the second source-drain metal layer in Figure 29, Figure 36 is a structural layout of the first electrode layer in Figure 29, Figure 37 is a stacked layout of the active layer and the second source-drain metal layer in Figure 29, and Figure 38 is a stacked layout of the active layer, the second source-drain metal layer and the first electrode layer in Figure 29.

[0179] It is worth noting that in this exemplary embodiment, the first metal layer BSM, the active layer Polly, the first conductive layer Gate1, and the second conductive layer Gate2 can be mirror-symmetrical structures. Compared with the layout structure of Figure 4, this exemplary embodiment only sets the pixel driving circuit in a mirror-symmetrical manner without changing the specific structure of the transistors and capacitors in each pixel driving circuit. In other words, this exemplary embodiment can have all the structures of the first metal layer BSM, the active layer Polly, the first conductive layer Gate1, and the second conductive layer Gate2 in the layout of Figure 4, which will not be described in detail here.

[0180] In this exemplary embodiment, the display panel may include a plurality of second repeating units Q2, each of which may include a third pixel driving circuit P3 and a fourth pixel driving circuit P4 adjacently disposed in the row direction X. Within the same second repeating unit Q2, the third pixel driving circuit P3 and the fourth pixel driving circuit P4 are mirror images, and any two adjacent second repeating units Q2 in the row direction X are mirror images of each other. It should be understood that a pixel driving circuit includes a plurality of film layers. Therefore, the third pixel driving circuit and the fourth pixel driving circuit described in the present disclosure are mirror images of each other, meaning that any film layer structure in the third pixel driving circuit has a one-to-one corresponding and mirror-symmetrical identical film layer structure in the fourth pixel driving circuit.

[0181] Furthermore, as shown in Figure 34, in this exemplary embodiment, the first source-drain metal layer SD1 may also include a first connecting line 35. The positive projection of the first connecting line 35 on the substrate may extend along the column direction Y. The first connecting line 35 may connect the second bridge portion 32 in the pixel driving circuit of this row with the second bridge portion 32 in the pixel driving circuit of the next row, thereby connecting the second bridge portion 32 in each pixel driving circuit in the first pixel column, so that the second initialization signal line Vinit2 may form a grid structure with staggered rows and columns. It can be understood that the second initialization signal line Vinit2 of the grid structure also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0182] As shown in Figure 35 , in this exemplary embodiment, the second source / drain metal layer SD2 may include a data signal line Vdata, a first power line VDD, and an electrode flat portion 40. The two data signal lines Vdata and the two first power lines VDD within the same repeating unit are mirror-image symmetrical. The two pixel drive circuits within a second repeating unit Q2 may share a single electrode flat portion 40. Specifically, the electrode flat portion 40 may be located in the center of the second repeating unit Q2, such that the two first power lines VDD and the two data signal lines Vdata within the same repeating unit are located on either side of the electrode flat portion 40.

[0183] As shown in FIG37 , the orthographic projection of the electrode flat portion 40 on the base substrate can at least partially overlap with the orthographic projections of the two second active portions POL2, the two third active portions POL3, and the two ninth active portions POL9 in the same pixel driving circuit on the base substrate. For example, it can cover the orthographic projections of the second active portions POL2 and the ninth active portion POL9 in the two pixel driving circuits in the same second repeating unit Q2 on the base substrate and partially overlap with the orthographic projections of the two third active portions POL3 on the base substrate. The ratio of the overlapping area to the area of ​​the third active portion POL3 can be 5%, such as 5%, 10%, 20%, 25%, 30%, 35%, 40%, 50%, 60%, 70%, etc., that is, the electrode flat portion 40 can shield both the two second transistors T2 in the same repeating unit and can symmetrically shield partial structures of the two driving transistors T3. In this exemplary embodiment, no additional shielding metal is required in the second source / drain metal layer SD2, thereby improving the light transmittance of the first display area 101.

[0184] As shown in FIG38 , in this exemplary embodiment, the first electrode ANO of the first electrode layer ANOL can be moved as a whole so that, in a second repeating unit Q2, one first electrode ANO can shield the second transistors T2 of two pixel driving circuits. As described above, the first electrodes ANO-B of the first subpixel R, the second subpixel G, and the third subpixel B in the same row are located in two subpixel rows. The first electrodes ANO-B of the first subpixel R and the third subpixel B in the first subpixel row X1 can be positioned above the electrode flat portion 40 in the second repeating unit Q2 in which they are located. In other words, the first electrode ANO-R of the first subpixel R and the first electrode ANO-B of the third subpixel B can be used to shield the second transistors T2 in the second repeating unit Q2 in which they are located. That is, the orthographic projection of the first electrode ANO located in the first sub-pixel row X1 on the substrate can cover the orthographic projections of the two second active portions POL2 and the two ninth active portions POL9 in the repeating unit on the substrate. In other words, the first electrode ANO-R of the first sub-pixel R and the first electrode ANO-B of the third sub-pixel B respectively block the second transistors T2 of the two pixel driving circuits in the repeating unit.

[0185] Continuing to refer to Figure 38, the orthographic projection of the first electrode ANO of the first sub-pixel row X1 on the substrate also at least partially overlaps with the orthographic projection of the two third active parts POL3 in the repeating unit on the substrate, and the ratio of the overlapping area to the area of ​​the third active part POL3 can be greater than or equal to 35%, such as 35%, 40%, 45%, 50%, 55%, 60%, 70%, 80%, etc., that is, the first electrode ANO-R of the first sub-pixel R and the first electrode ANO-B of the third sub-pixel B also partially block the two driving transistors T3 in the repeating unit. Because the area of ​​the first electrode ANO is larger than the area of ​​the first flat part 411, the first electrode ANO can block more driving transistor T3 structures, thereby improving the blocking effect on the driving transistor T3, thereby further improving the anti-interference performance of the display panel against strong light, and effectively improving the phenomenon of color deviation displayed by the display panel when exposed to strong light.

[0186] As shown in FIG34 , in this exemplary embodiment, the first source-drain metal layer SD1 may include a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, and a power transfer line VDDL extending along the column direction Y. One end of the first bridge portion 31 may be connected to the eleventh active portion POL11 via a via to connect to the second electrode of the first transistor T1, and the other end of the first bridge portion 31 may be connected to the first conductive block 11 via a via to connect the second electrode of the first transistor T1 to the gate of the driving transistor T3. One end of the second bridge portion 32 may be connected to the fifteenth active portion POL15 via a via to connect to the first electrode of the seventh transistor T7, and the other end may be connected to the second initialization signal line Vinit2 via a via to connect the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2. One end of the third bridge portion 33 may be connected to the twelfth active portion POL12 via a via to connect to the first electrode of the first transistor T1, and the other end may be connected to the first initialization signal line Vinit1 via a via to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1. The power adapter line VDDL can be connected to the seventeenth active portion POL17 via a via to connect to the first electrode of the fifth transistor T5. The power adapter line VDDL can also be connected to the first power line VDD of the second source-drain metal layer SD2 via a via, thereby connecting the first electrode of the fifth transistor T5 to the first power line VDD. In addition, the power adapter line VDDL can also be connected to the second conductive block 22 of the second conductive layer Gate2 via a via to connect the second electrode of the storage capacitor Cst to the first power line VDD. In this exemplary embodiment, the first bridge portion 31, the second bridge portion 32, the third bridge portion 33, and the power adapter line VDDL in the two pixel drive circuits of the same second repeating unit Q2 are all arranged in mirror symmetry.

[0187] As shown in Figure 34, in this exemplary embodiment, the first source-drain metal layer SD1 also includes a data transfer portion VdataL, which can connect the fourteenth active portion POL14 and the data signal line Vdata through vias respectively to connect the second electrode of the fourth transistor T4 to the data signal line Vdata.

[0188] As shown in FIG35 , in this exemplary embodiment, the second source / drain metal layer SD2 may include a data signal line Vdata and a first power line VDD extending along the column direction Y. The data signal line Vdata is connected to the data transfer portion VdataL via a via. In two adjacent second repeating units Q2 in the row direction X, the data signal line Vdata in one third pixel driver circuit P3 and the data signal line Vdata in the fourth pixel driver circuit in the other repeating unit are arranged adjacent to each other and are mirror images of each other. That is, in one second repeating unit Q2, the data signal line Vdata is located near the outermost edge of the repeating unit. The first power line VDD may be connected to the power transfer line VDDL via a via. In two adjacent second repeating units Q2 in the row direction X, the first power line VDD in one third pixel driver circuit P3 and the first power line VDD in the fourth pixel driver circuit P4 in the other repeating unit are located on either side of the two data signal lines Vdata, respectively. In other words, in this exemplary embodiment, the data signal lines Vdata in two adjacent second repeating units Q2 in the row direction X are arranged adjacent to each other, and the first power line VDD is located on either side of the two data signal lines Vdata. On this basis, the orthographic projection of the first electrode ANO located in the second sub-pixel row X2 on the substrate is located on the orthographic projection of the first power line VDD and the data signal line Vdata of the two adjacent second repeating units Q2 in the row direction X on the substrate, that is, the first electrode ANO of the second sub-pixel row X2 is planarized and supported by the data signal line Vdata and the first power line VDD in the two repeating units. In this way, there is no need to additionally arrange the electrode flat portion 40 under the second source and drain metal layer SD2 corresponding to the first electrode ANO of the second sub-pixel row X2, which reduces the number of metal flat portions arranged, thereby improving the transmittance of the display panel and facilitating the realization of a narrow frame of the display panel.

[0189] FIG39 is a cross-sectional view taken along the AA direction in FIG4 . The display panel may further include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, a passivation layer 77, and a second dielectric layer 77. The base substrate 71, the metal shielding layer BSM, the buffer layer 72, the active layer Polly, the first insulating layer 73, the first conductive layer Gate1, the second insulating layer 74, the second conductive layer Gate2, the first dielectric layer 75, the first source / drain metal layer SD1, the passivation layer 76, the second dielectric layer 77, the second source / drain metal layer SD2, and the first electrode layer ANOL are sequentially stacked. The first insulating layer 73 may be an organic insulating layer, the second insulating layer 74 may be silicon oxide, the first dielectric layer 75 and the second dielectric layer 77 may be silicon nitride layers, and the passivation layer 77 and the buffer layer 72 may be made of silicon oxide, silicon nitride, or the like. The base substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially. The barrier layer may be an inorganic material. The material of the first conductive layer Gate1 and the second conductive layer Gate2 can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer, etc. The material of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer, etc., or a titanium / aluminum / titanium stacked layer.

[0190] It should be understood that the terms "first", "second" and "third" used in the present disclosure are only used as labels to distinguish the names of different structures, and are not intended to limit the quantity of their objects and have no sequential relationship.

[0191] The present disclosure also provides a display device, which includes the display panel described in any embodiment of the present disclosure.

[0192] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a plurality of pixel driving circuits, wherein the pixel driving circuit includes a second transistor and a driving transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode is connected to a first electrode of the driving transistor; The display panel further includes: substrate substrate; An active layer is located on one side of the substrate, and the active layer includes: a second active portion, used to form a channel region of the second transistor; a third active portion connected to the second active portion, wherein the third active portion is used to form a channel region of the driving transistor; A first metal layer, located between the substrate and the active layer; A second metal layer is located on a side of the active layer away from the substrate; The orthographic projections of the first metal layer and the second metal layer on the base substrate at least partially overlap with the orthographic projections of the second active portion and the third active portion on the base substrate.

2. The display panel according to claim 1, wherein: The first metal layer is connected to a constant voltage source; the second active portion includes a first sub-active portion and a second sub-active portion; The active layer further comprises: a ninth active portion connected between the first sub-active portion and the second sub-active portion; The orthographic projection of the first metal layer on the base substrate overlaps with the orthographic projections of the second active portion and the third active portion on the base substrate, and does not overlap with the orthographic projection of the ninth active portion on the base substrate.

3. The display panel according to claim 2, wherein: The display panel includes a plurality of the pixel driving circuits, the first metal layer includes a plurality of shielding units, and one shielding unit corresponds to one pixel driving circuit; The shielding unit comprises: The first shielding portion is arranged corresponding to the second active portion, the first shielding portion has a notch, the orthographic projection of the first shielding portion on the substrate overlaps with the orthographic projection of the second active portion on the substrate, and the ninth active portion is located at the orthographic projection of the substrate. The notch is within the orthographic projection of the base substrate; The second shielding portion is arranged corresponding to the third active portion and connected to the first shielding portion, and the orthographic projection of the second shielding portion on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate.

4. The display panel according to claim 1, wherein: The first metal layer is connected to a constant voltage source; the display panel includes a plurality of pixel driving circuits, the first metal layer includes a plurality of shielding units, and one shielding unit corresponds to one pixel driving circuit; The shielding unit comprises: a second shielding portion, arranged corresponding to the third active portion and connected to the first shielding portion, wherein an orthographic projection of the second shielding portion on the base substrate overlaps an orthographic projection of the third active portion on the base substrate; The display panel further includes: A first conductive layer is located on a side of the active layer away from the substrate, and the first conductive layer includes: The first conductive block is used to form the gate of the driving transistor, wherein the orthographic projection of the first conductive block on the base substrate covers the orthographic projection of the third active portion on the base substrate and overlaps with the orthographic projection of the second shielding portion on the base substrate.

5. The display panel according to claim 4, wherein: The orthographic projection of the first conductive block on the base substrate covers the orthographic projection of the second shielding portion on the base substrate.

6. The display panel according to claim 4, wherein: An orthographic projection of the first conductive block on the base substrate overlaps with an orthographic projection of the second shielding portion on the base substrate.

7. The display panel according to claim 1, wherein: The first metal layer is connected to a constant voltage source; the display panel includes a plurality of pixel driving circuits, the first metal layer includes a plurality of shielding units, and one shielding unit corresponds to one pixel driving circuit; The shielding unit comprises: The first shielding portion is arranged corresponding to the second active portion, the first shielding portion has a notch, the orthographic projection of the first shielding portion on the substrate overlaps with the orthographic projection of the second active portion on the substrate, and the ninth active portion is located at the orthographic projection of the substrate. The notch is within the orthographic projection of the base substrate; a second shielding portion, arranged corresponding to the third active portion and connected to the first shielding portion, wherein an orthographic projection of the second shielding portion on the base substrate overlaps an orthographic projection of the third active portion on the base substrate; A first connecting portion, connected to the first shielding portion, wherein the orthographic projection of the first connecting portion on the base substrate extends along a column direction; A second connecting portion connected to a side of the second shielding portion away from the first shielding portion in the column direction, wherein an orthographic projection of the second connecting portion on the base substrate extends along the column direction; A third connecting portion, connected to one side of the second shielding portion in the row direction and extending in the row direction on the orthographic projection of the base substrate; A fourth connecting portion, connected to a side of the second shielding portion away from the third connecting portion in the row direction and extending in the row direction on an orthographic projection of the base substrate; Among them, in two shielding units adjacent to each other in the row direction, the third connecting portion in one shielding unit is connected to the fourth connecting portion in the other shielding unit; In two shielding units adjacent to each other in the column direction, the first connection portion of one shielding unit is connected to the second connection portion of the other shielding unit.

8. The display panel according to claim 7, wherein: The pixel driving circuit further comprises a first transistor, a second electrode of the first transistor being connected to a gate electrode of the driving transistor; The active layer further comprises: a first active portion, used to form a channel region of the first transistor, the first active portion comprising a fifth sub-active portion and a sixth sub-active portion; Among them, the first connecting part includes a first component part and a second component part, the first component part is connected between the first shielding part and the second component part, the orthographic projection of the first component part on the base substrate extends along the row direction, the orthographic projection of the second component part on the base substrate extends along the column direction, and the orthographic projection of the second component part on the base substrate is located between the orthographic projections of the fifth sub-active part and the sixth sub-active part on the base substrate.

9. The display panel according to claim 14, wherein: The second connecting portion includes a third component portion, a fourth component portion and a fifth component portion, the fourth component portion is connected between the third component portion and the fifth component portion, and the orthographic projections of the third component portion and the fifth component portion on the base substrate both extend along the column direction and are staggered in the row direction; In two adjacent shielding units in the column direction, the fifth component in the shielding unit in the current row is connected to the second component in the shielding unit in the next row.

10. The display panel according to claim 7, wherein: The display panel further includes: The second source-drain metal layer is located on a side of the first conductive layer away from the substrate, and the second source-drain metal layer includes: The first power line extends along the column direction in the orthographic projection of the base substrate, and is connected to at least one of the first connection part, the second connection part, the third connection part and the fourth connection part in the first metal layer through a via in the non-display area of ​​the display panel.

11. The display panel according to claim 1, wherein: The second active portion includes a first sub-active portion and a second sub-active portion; The display panel further includes: A first conductive layer is located on a side of the active layer away from the substrate, and the first conductive layer includes: A gate signal line, comprising a main extension portion and a secondary extension portion connected to one side of the main extension portion, wherein the main extension portion extends along a row direction on an orthographic projection of the substrate and covers an orthographic projection of the first sub-active portion on the substrate, and the secondary extension portion extends along a column direction on an orthographic projection of the substrate and covers an orthographic projection of the second sub-active portion on the substrate, and a partial structure of the main extension portion and the secondary extension portion are used to form a gate of the second transistor; The first metal layer includes a plurality of shielding units, one shielding unit corresponds to one pixel driving circuit, the shielding unit includes a first shielding portion arranged corresponding to the second active portion, and an orthographic projection of the first shielding portion on the base substrate overlaps with an orthographic projection of the second active portion on the base substrate; The first shielding portion comprises a first sub-shielding portion and a second sub-shielding portion, the first sub-shielding portion corresponds to the first sub-active portion, the second sub-shielding portion corresponds to the second sub-active portion, the first sub-shielding portion extends in a row direction on an orthographic projection of the substrate and has a fifth width in a column direction, the main extension portion and the first sub-shielding portion have a first overlapping portion on an orthographic projection of the substrate, and the first overlapping portion has a seventh width in the column direction, and the fifth width is greater than the seventh width; The second sub-shielding portion extends along the column direction on the orthographic projection of the base substrate and has a sixth width in the row direction, the secondary extension portion and the second sub-active portion have a second overlapping portion on the orthographic projection of the base substrate, and the second overlapping portion has an eighth width in the row direction, and the sixth width is greater than the eighth width.

12. The display panel according to claim 11, wherein: A ratio of the seventh width to the fifth width and a ratio of the eighth width to the sixth width are both greater than or equal to 50%.

13. The display panel according to claim 11, wherein: The second overlapping portion has a first length in the column direction; The secondary extension portion has a second length in the column direction of an orthographic projection of the base substrate, and the first length is smaller than the second length.

14. The display panel according to claim 1, wherein: The display panel further includes: A first electrode layer, located at a side of the active layer away from the substrate, the first electrode layer comprising a plurality of first electrodes, one first electrode corresponding to one pixel driving circuit; In which, the display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, one sub-pixel corresponds to one pixel driving circuit, and the first electrode of the first sub-pixel and the first electrode of the third sub-pixel are located in a first pixel column, the first electrode of the second sub-pixel is located in a second pixel column, and the first pixel column and the second pixel column are alternately distributed in the row direction.

15. The display panel according to claim 14, wherein: The second metal layer is the first electrode layer; the second active portion includes a first sub-active portion and a second sub-active portion; The active layer further comprises: a ninth active portion connected between the first sub-active portion and the second sub-active portion; The orthographic projection of at least part of the first electrode on the base substrate covers the orthographic projections of the second active portion, the third active portion and the ninth active portion on the base substrate.

16. The display panel according to claim 15, wherein: The display panel includes a plurality of first repeating units arranged in an array in row and column directions, wherein the first repeating unit includes a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; In any first repeating unit, the first electrode connected to the first pixel driving circuit is The orthographic projection of the base substrate covers the orthographic projections of the second active portion and the ninth active portion in the first pixel driving circuit on the base substrate and partially overlaps with the orthographic projection of the third active portion on the base substrate, and the orthographic projection of the first electrode connected to the first pixel driving circuit on the base substrate also at least partially overlaps with the orthographic projections of the second active portion and the ninth active portion in the second pixel driving circuit on the base substrate; The orthographic projection of the first electrode connected to the second pixel driving circuit on the base substrate overlaps with the orthographic projection of the third active portion in the second pixel driving circuit on the base substrate.

17. The display panel according to claim 16, wherein: In any first repeating unit, the orthographic projection of the first electrode connected to the first pixel driving circuit on the substrate also covers the orthographic projection of the third active part in the first pixel driving circuit on the substrate and / or also covers the orthographic projection of the second active part and the ninth active part in the second pixel driving circuit on the substrate.

18. The display panel according to claim 16 or 17, wherein: The first sub-pixel and the third sub-pixel both correspond to the first pixel driving circuit, and the second sub-pixel corresponds to the second pixel driving circuit.

19. The display panel according to claim 14, wherein: The ninth active portion includes a third sub-active portion, a fourth sub-active portion, the third sub-active portion is connected to the first sub-active portion, and the fourth sub-active portion is connected to the second sub-active portion; the first electrodes in the first sub-pixel and the third sub-pixel each include a main portion and an additional portion, and the additional portion is connected to one side of the main portion along a row direction; The display panel further includes: A first conductive layer is located between the active layer and the first electrode layer, and the first conductive layer includes: A gate signal line, comprising a main extension portion and a secondary extension portion, wherein the main extension portion extends along a row direction on an orthographic projection of the substrate and covers an orthographic projection of the first sub-active portion on the substrate, and the secondary extension portion extends along a column direction on an orthographic projection of the substrate and covers an orthographic projection of the second sub-active portion on the substrate, and a partial structure of the main extension portion and the secondary extension portion are used to form a gate of the second transistor; The display panel includes a plurality of first repeating single cells arranged in an array in row and column directions. The first repeating unit comprises a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged in a row direction, the first pixel driving circuit is located in a first pixel column, and the second pixel driving circuit is located in a second pixel column; In the same first repeating unit, the orthographic projection of the first electrode main body portion of the first sub-pixel on the base substrate covers the orthographic projections of the second active portion, the third active portion and the ninth active portion in the first pixel driving circuit on the base substrate and also covers the orthographic projections of the first sub-active portion and the third sub-active portion in the second pixel driving circuit on the base substrate, and the orthographic projection of the first electrode additional portion of the first sub-pixel on the base substrate covers the orthographic projections of the second sub-active portion and the fourth sub-active portion in the second pixel driving circuit on the base substrate; In the same first repeating unit, the orthographic projection of the first electrode main portion of the third sub-pixel on the substrate covers the orthographic projections of the second active portion and the ninth active portion in the first pixel driving circuit on the substrate and at least partially overlaps with the orthographic projection of the third active portion on the substrate, and the orthographic projection of the first electrode additional portion of the third sub-pixel on the substrate covers the orthographic projections of the second sub-active portion and the ninth active portion in the second pixel driving circuit on the substrate and at least partially overlaps with the orthographic projection of the first sub-active portion on the substrate.

20. The display panel according to claim 14, wherein: The second metal layer is a second source-drain metal layer, and the second source-drain metal layer is located between the active layer and the first electrode layer; The second source-drain metal layer comprises: The electrode flat portion is arranged corresponding to the first electrode of the corresponding sub-pixel, and the orthographic projection of the first electrode on the substrate is located on the orthographic projection of the electrode flat portion on the substrate. The orthographic projection of the electrode flat portion on the substrate also at least partially overlaps with the orthographic projections of the second active portion and the third active portion in the same pixel driving circuit on the substrate.

21. The display panel according to claim 20, wherein: The display panel includes a plurality of first repeating units arranged in an array in row and column directions, wherein the first repeating unit includes a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; The ninth active portion includes a third sub-active portion, a fourth sub-active portion, the third sub-active portion is connected to the first sub-active portion, and the fourth sub-active portion is connected to the second sub-active portion; The display panel further includes: A first conductive layer is located between the active layer and the second source-drain metal layer, and the first conductive layer includes: A gate signal line, comprising a main extension portion and a secondary extension portion, wherein the main extension portion extends along a row direction on an orthographic projection of the base substrate and covers an orthographic projection of the first sub-active portion on the base substrate, and the secondary extension portion extends along a column direction on an orthographic projection of the base substrate and covers an orthographic projection of the second sub-active portion on the base substrate; The electrode flat portion includes a second flat portion located in the second pixel column, and the second flat portion includes a first extension portion, a second extension portion and a third extension portion sequentially connected in the column direction; In the same first repeating unit, the orthographic projection of the first extension portion on the substrate covers the orthographic projections of the second sub-active portion and the fourth sub-active portion in the same pixel driving circuit on the substrate and overlaps with the orthographic projections of the first sub-active portion and the third sub-active portion on the substrate, the orthographic projection of the second extension portion on the substrate overlaps with the orthographic projection of the third active portion in the same pixel driving circuit on the substrate, and the orthographic projection of the third extension portion on the substrate is located within the orthographic projection of the first electrode of the corresponding sub-pixel on the substrate.

22. The display panel according to claim 21, wherein: A hollow portion is provided between the first extension portion and the second extension portion, and the hollow portion is used to expose at least a portion of a gap between the second transistor and the driving transistor.

23. The display panel according to claim 21, wherein: The first extension portion has a first width in the row direction of the orthographic projection of the base substrate, the second extension portion has a second width in the row direction of the orthographic projection of the base substrate, and the third extension portion has a third width in the row direction of the orthographic projection of the base substrate, and the second width is smaller than the first width and smaller than the third width.

24. The display panel according to claim 20, wherein: The display panel includes a plurality of first repeating units arranged in an array in row and column directions, wherein the first repeating unit includes a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the row direction; The electrode flat portion comprises: a first flat portion, located in the first pixel column and arranged corresponding to the first sub-pixel, the orthographic projection of the first flat portion on the base substrate covering the orthographic projections of the second sub-active portion, the fourth sub-active portion and the third active portion in the same pixel driving circuit on the base substrate, and the orthographic projection of the first electrode of the first sub-pixel on the base substrate covering the orthographic projection of the first flat portion on the base substrate; a second flat portion, located in the second pixel column, wherein the orthographic projection of the second flat portion on the base substrate partially overlaps with the second active portion, the third active portion and the ninth active portion in the same pixel driving circuit; A third flat portion is located in the first pixel column and is arranged corresponding to the third sub-pixel, the orthographic projection of the third flat portion on the substrate covers the orthographic projections of the second sub-active portion and the fourth sub-active portion in the same pixel driving circuit on the substrate and at least partially overlaps with the orthographic projection of the third active portion on the substrate, and the orthographic projection of the first electrode of the third sub-pixel on the substrate covers the orthographic projection of the third flat portion on the substrate.

25. The display panel according to claim 24, wherein: The orthographic projection of the first electrode of the first sub-pixel on the substrate has a first area, the orthographic projection of the first electrode of the second sub-pixel on the substrate has a second area, the orthographic projection of the first electrode of the third sub-pixel on the substrate has a third area, and the first area>the third area>the second area; The first flat portion has a first extension length in the column direction, the second flat portion has a second extension length in the column direction, and the third flat portion has a third extension length in the column direction, wherein the second extension length>the first extension length>the third extension length.

26. The display panel according to claim 24, wherein: In any first repeating unit, the orthographic projections of the first electrode of the first subpixel and the first electrode of the third subpixel on the substrate cover the orthographic projections of the second active portion, the ninth active portion and the third active portion in the corresponding first pixel driving circuit on the substrate, and the orthographic projection of the first electrode of the first subpixel on the substrate also covers the orthographic projections of the second active portion and the ninth active portion in the corresponding second pixel driving circuit on the substrate, and the orthographic projection of the first electrode of the third subpixel on the substrate at least partially overlaps with the orthographic projections of the second active portion and the ninth active portion in the corresponding second pixel driving circuit on the substrate.

27. The display panel according to claim 14, wherein: The display panel includes a plurality of second repeating units arranged in an array in row and column directions, and the second repeating unit includes a third pixel driving circuit and a fourth pixel driving circuit adjacently arranged in the row direction; The display panel further includes a first conductive layer and a second conductive layer stacked on a side of the active layer away from the base substrate; Wherein, in the same second repeating unit, the first metal layer structure, the active layer structure, the first conductive layer structure and the second conductive layer structure in the third pixel driving circuit and the first metal layer structure, the active layer structure, the first conductive layer structure and the second conductive layer structure in the fourth pixel driving circuit are mirror images of each other; In any two adjacent second repeating units in the row direction, the first metal layer structure, active layer structure, first conductive layer structure and second conductive layer structure in one second repeating unit and the first metal layer structure, active layer structure, first conductive layer structure and second conductive layer structure in another second repeating unit are mirror images of each other.

28. The display panel according to claim 27, wherein: The second metal layer is a second source-drain metal layer; the second source-drain metal layer includes: A plurality of electrode flat portions are arranged in an array along row and column directions, one electrode flat portion is correspondingly arranged in one second repeating unit, and in the same repeating unit, the orthographic projection of the electrode flat portion on the substrate at least partially overlaps with the orthographic projections of two second active portions, two ninth active portions and two third active portions on the substrate.

29. The display panel according to claim 27, wherein: The second metal layer is a first electrode layer; Each first electrode located in the first sub-pixel row is correspondingly located in one of the second repeating units. In any second repeating unit, the orthographic projection of the first electrode located in the first sub-pixel row on the substrate covers the orthographic projections of the two second active portions and the two ninth active portions on the substrate, and at least partially overlaps with the orthographic projections of the two third active portions on the substrate.

30. The display panel according to claim 27, wherein: In any two adjacent second repeating units in the row direction, the data signal line and the first power line of the third pixel driving circuit in one repeating unit are mirror-symmetrical to the data signal line and the first power line of the fourth pixel driving circuit in another repeating unit, and the data signal line in one third pixel driving circuit and the data signal line in another repeating unit mirror-symmetrical to it are arranged adjacent to each other, and the first power line in one third pixel driving circuit and the first power line in another repeating unit mirror-symmetrical to it are respectively located on both sides of the two data signal lines; The orthographic projection of the first electrode of the second sub-pixel row on the base substrate is located on the orthographic projection of the first power line and the data signal line of two adjacent second repeating units in the row direction on the base substrate.

31. The display panel according to claim 27, wherein: The pixel driving circuit comprises a first transistor, a driving transistor, a fourth transistor and a seventh transistor, wherein a first electrode of the first transistor is connected to a first initialization signal terminal, and a second electrode is connected to a gate of the driving transistor; a first electrode of the fourth transistor is connected to a second electrode of the driving transistor, and a second electrode is connected to a data signal terminal; a first electrode of the seventh transistor is connected to a second initialization signal terminal, and a second electrode is connected to a first electrode of the light emitting device; The active layer further comprises: an eleventh active portion, used to form a second electrode of the first transistor; a twelfth active portion, used to form a first electrode of the first transistor; a fourteenth active portion, used to form a second electrode of the fourth transistor; A fifteenth active portion, used to form a first electrode of the seventh transistor; A seventeenth active portion, used for forming a first electrode of the fifth transistor; The display panel further includes: A first conductive layer is located between the active layer and the first electrode layer, and the first conductive layer includes: a first conductive block, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the first conductive block is used to form a gate of the driving transistor; A second conductive layer is located between the first conductive layer and the first electrode layer, and the second conductive layer includes: A first initialization signal line, the orthographic projection of which on the substrate extends along a row direction; A second initialization signal line, the orthographic projection of which on the base substrate extends along a row direction; A first source-drain metal layer is located between the second conductive layer and the first electrode layer, and the first source-drain metal layer includes: The first bridge portion extends along the column direction on the orthographic projection of the base substrate, one end of the first bridge portion is connected to the eleventh active portion through a via hole, and the other end is connected to the first A conductive block for connecting the second electrode of the first transistor to the gate of the driving transistor; a second bridge portion, the orthographic projection of the base substrate extending in the column direction, one end of the second bridge portion connected to the fifteenth active portion through a via hole, and the other end of the second bridge portion connected to the second initialization signal line through a via hole, so as to connect the first electrode of the seventh transistor to the second initialization signal line; a third bridge portion, extending in a column direction on an orthographic projection of the base substrate, one end of the third bridge portion being connected to the twelfth active portion through a via hole, and the other end of the third bridge portion being connected to the first initialization signal line through a via hole, so as to connect the first electrode of the first transistor to the first initialization signal line; A power adapter line, extending in a column direction on an orthographic projection of the base substrate, the power adapter line being connected to the seventeenth active portion through a via hole to connect to the first electrode of the fifth transistor; a data transfer portion, connected to the fourteenth active portion through a via hole, so as to be connected to the second electrode of the fourth transistor; A second source-drain metal layer is located between the first source-drain metal layer and the first electrode layer, and the second source-drain metal layer includes: A data signal line, the orthographic projection of the base substrate extending along the column direction, the data signal line connected to the data transfer portion through a via hole; A first power line, the orthographic projection of the base substrate extending along the column direction, the first power line connected to the power adapter line through a via hole; Among them, the two first bridge portions, the two second bridge portions, the two third bridge portions, the two power adapter lines, the two data adapter portions, the two data signal lines and the two first power lines in any second repeating unit are mirror-symmetrical.

32. The display panel according to claim 1, wherein: The pixel driving circuit includes a seventh transistor, a first electrode of the seventh transistor is connected to a second initialization signal terminal; the display panel includes a first display area and a second display area at least partially surrounding the first display area, the first display area has a greater light transmittance than the second display area, and the first display area includes a plurality of pixel rows; The active layer further comprises: A fifteenth active portion, used to form a first electrode of the seventh transistor; The display panel further includes: A second conductive layer is located between the active layer and the second metal layer, and the second conductive layer includes: A second initialization signal line, the orthographic projection of which on the base substrate extends along a row direction; A first source-drain metal layer is located between the second conductive layer and the second metal layer, and the first source-drain metal layer includes: a second bridge portion, the orthographic projection of the base substrate extending in the column direction, one end of the second bridge portion connected to the fifteenth active portion through a via hole, and the other end of the second bridge portion connected to the second initialization signal line through a via hole, so as to connect the first electrode of the seventh transistor to the second initialization signal line; The first connecting line is located in the second display area and extends along the column direction in the orthographic projection of the base substrate. The first connecting line connects the second bridge portions of two adjacent rows.

33. A display device, wherein: A display panel comprising any one of claims 1-32.

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