Capacitive pressure sensor, manufacturing method thereof, and electronic device

Abstract

An embodiment of the present disclosure provides a capacitive pressure sensor, a manufacturing method thereof, and an electronic device, the manufacturing method comprising: forming a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer on a first side of a substrate; forming a first electrode via and a second electrode via in the second electrode layer; removing a portion of the second dielectric layer exposed by the second electrode via to form a dielectric groove; forming a passivation layer on a side of the second electrode layer away from the substrate, the passivation layer having a passivation protrusion filling the dielectric groove and a first passivation opening, the first passivation opening being spatially connected to the first electrode via and constituting a release hole; performing an etching process from the second side of the substrate to form a first cavity in the substrate; and performing a dielectric etching process to form a second cavity, the second cavity being spatially connected to the release hole, a portion of the first electrode layer being located between the first cavity and the second cavity and serving as a diaphragm, and the passivation protrusion being located in the second cavity.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the fields of micro-electromechanical system sensors and semiconductor technology, and in particular to a capacitive pressure sensor, a manufacturing method thereof, and an electronic device. Background Art

[0002] Micro-electro-mechanical system (MEMS) capacitive pressure sensors are widely used in electronic devices such as microphones and e-cigarettes. They can convert the pressure applied to the diaphragm by sound waves or smoking into an electrical signal, thereby sensing the pressure through the output electrical signal.

[0003] Generally speaking, MEMS capacitive pressure sensors can be manufactured using semiconductor processing technology. However, the existing process is complex, costly, and has a long processing cycle. How to optimize the manufacturing process of MEMS capacitive pressure sensors and save costs is an important research topic in this field. Summary of the Invention

[0004] According to at least one embodiment of the present disclosure, a method for manufacturing a capacitive pressure sensor is provided, comprising: providing a substrate, the substrate having a first side and a second side opposite to each other in a first direction; sequentially forming a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer on the first side of the substrate; performing an electrode patterning process on the second electrode layer to form a first electrode via and a second electrode via in the second electrode layer that expose the second dielectric layer; removing a portion of the second dielectric layer exposed by the second electrode via to form a dielectric groove in the second dielectric layer; forming a passivation layer on a side of the second electrode layer away from the substrate, the passivation layer having a passivation protrusion that fills the dielectric groove and having a first passivation protrusion that fills the dielectric groove and has .... The invention relates to a method for manufacturing a passivation opening, wherein the first passivation opening is connected to the first electrode via space and together constitutes a release hole; performing an etching process on the substrate from the second side to form a first cavity in the substrate and expose the first dielectric portion of the first dielectric layer; and performing a dielectric etching process to remove the first dielectric portion and extend the first cavity to expose a portion of the surface of the first electrode layer, and remove the second dielectric portion of the second dielectric layer to form a second cavity, wherein the second cavity is connected to the release hole space and overlaps with the first cavity in the first direction, wherein a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm, and the passivation protrusion is located in the second cavity.

[0005] In the manufacturing method of a capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the passivation layer also includes a first passivation filling portion filled in the second electrode via, the first passivation filling portion is located on a side of the passivation protrusion away from the first electrode layer, and is surrounded by the second electrode layer in a second direction parallel to the main surface of the substrate.

[0006] In the method for manufacturing a capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the orthographic projections of the first electrode via and the second electrode via on the main surface of the first electrode layer are located within the orthographic projection of the second cavity on the main surface of the first electrode layer.

[0007] In the method for manufacturing a capacitive pressure sensor according to at least one embodiment of the present disclosure, the second cavity is defined by facing surfaces of the first and second electrode layers and an inner sidewall of the second dielectric layer.

[0008] In the manufacturing method of the capacitive pressure sensor provided according to at least one embodiment of the present disclosure, forming the passivation layer includes: forming a passivation material layer, the passivation material layer covering the surface of the second electrode layer away from the substrate, and filling the first electrode via, the second electrode via and the dielectric groove; and removing the portion of the passivation material layer located at and covering the first electrode via to form the first passivation opening and expose the first electrode via.

[0009] In the manufacturing method of a capacitive pressure sensor provided according to at least one embodiment of the present disclosure, forming the passivation layer also includes forming a second passivation opening and a third passivation opening, the second passivation opening extending through the passivation layer and exposing a portion of the surface of the second electrode layer, and the third passivation opening extending through the passivation layer, the second electrode layer and the second dielectric layer and exposing a portion of the surface of the first electrode layer.

[0010] In the manufacturing method of a capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the electrode patterning process also includes forming a third electrode via in the second electrode layer that exposes the second dielectric layer, and before forming the passivation layer, it also includes: removing the portion of the second dielectric layer exposed by the third electrode via to form a contact hole in the second dielectric layer; a portion of the passivation layer is formed in the third electrode via and the contact hole, and the third passivation opening is formed in the portion of the passivation layer.

[0011] The manufacturing method of a capacitive pressure sensor provided according to at least one embodiment of the present disclosure also includes: forming a first conductive pad in the third passivation opening, the first conductive pad being electrically connected to the first electrode layer; and forming a second conductive pad in the second passivation opening, the second conductive pad being electrically connected to the second electrode layer.

[0012] In the manufacturing method of a capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the electrode patterning process further forms a fourth electrode via in the second electrode layer, and the passivation layer further forms a second passivation filling portion, which fills the fourth electrode via and contacts the second dielectric layer.

[0013] In the method for manufacturing a capacitive pressure sensor according to at least one embodiment of the present disclosure, the dielectric etching process includes a wet etching process, and an etchant used in the wet etching process enters the area where the second dielectric portion is located through the release hole.

[0014] The method for manufacturing a capacitive pressure sensor provided according to at least one embodiment of the present disclosure further includes: performing a patterning process on the first electrode layer to form a via hole in the first electrode layer, and the via hole is connected to the first cavity and the second cavity space.

[0015] At least one embodiment of the present disclosure provides a capacitive pressure sensor, comprising: a substrate having a first side and a second side opposite to each other in a first direction; a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer, which are sequentially arranged on the substrate in the first direction; a first cavity, which extends from the second side of the substrate through the substrate and the first dielectric layer and exposes a portion of the surface of the first electrode layer; a second cavity, which is located on a side of the first electrode layer away from the first cavity and is defined by surfaces of the first electrode layer and the second electrode layer facing each other and an inner sidewall of the second dielectric layer, wherein a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm; and a passivation layer, which is arranged on a side of the second electrode layer away from the substrate and extends through the second electrode layer and into the second cavity.

[0016] In the capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the second electrode layer includes a first electrode via and a second electrode via, and the orthographic projections of the first electrode via and the second electrode via on the main surface of the first electrode layer are located within the orthographic projection of the second cavity on the main surface of the first electrode layer; the passivation layer includes a first passivation opening, and the first passivation opening and the first electrode via together constitute a release hole and are connected to the second cavity space; the second electrode via is partially filled with the passivation layer.

[0017] In the capacitive pressure sensor provided according to at least one embodiment of the present disclosure, the passivation layer includes: a first passivation filling portion, located in the second electrode via; and a passivation protrusion, located on a side of the first passivation filling portion close to the first electrode layer, and located in the second cavity, and protruding from the surface of the second electrode layer close to the diaphragm in the first direction toward the diaphragm.

[0018] At least one embodiment of the present disclosure provides an electronic device, comprising any of the above-mentioned capacitive pressure sensors, wherein the electronic device comprises a microphone or an electronic cigarette.

[0019] The capacitive pressure sensor and its manufacturing method provided according to at least one embodiment of the present disclosure can simplify the process, save costs, and can be beneficial to increasing the initial capacitance of the capacitive element and / or reducing the device size, thereby increasing the number of devices produced on a single chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0021] Figure 1 A schematic cross-sectional view shows a substrate provided in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0022] Figure 2 A schematic cross-sectional view illustrating forming a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer on a substrate in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0023] Figure 3 A schematic cross-sectional view illustrating a process of performing electrode patterning on a second electrode layer in a method of manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0024] Figure 4A schematic cross-sectional view illustrating forming a dielectric groove in a second dielectric layer in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0025] Figure 5 A schematic cross-sectional view illustrating forming a contact hole in a second dielectric layer in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0026] Figure 6 A schematic cross-sectional view illustrating forming a passivation material layer over a substrate in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0027] Figure 7 A schematic cross-sectional view illustrating a patterning process of a passivation material layer in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0028] Figure 8 A schematic cross-sectional view illustrating forming a passivation layer after patterning a passivation material layer in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0029] Figure 9 A schematic cross-sectional view illustrating forming a first conductive pad and a second conductive pad in a method of manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0030] Figure 10 A schematic cross-sectional view illustrating a process of removing a material layer on a second side of a substrate and performing a thinning process on the substrate in a method of manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0031] Figure 11 A schematic cross-sectional view illustrating forming a substrate opening from a second side of a substrate in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0032] Figure 12 A schematic cross-sectional view shows a capacitive pressure sensor including a first cavity and a second cavity formed after a dielectric etching process is performed in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0033] Figure 13 A schematic cross-sectional view shows a capacitive pressure sensor according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0036] An embodiment of the present disclosure provides a method for manufacturing a capacitive pressure sensor, comprising: providing a substrate, the substrate having a first side and a second side opposite to each other in a first direction; sequentially forming a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer on the first side of the substrate; performing an electrode patterning process on the second electrode layer to form a first electrode via and a second electrode via in the second electrode layer that expose the second dielectric layer; removing a portion of the second dielectric layer exposed by the second electrode via to form a dielectric groove in the second dielectric layer; forming a passivation layer on a side of the second electrode layer away from the substrate, the passivation layer having a passivation protrusion that fills the dielectric groove and having a first passivation opening , the first passivation opening is connected to the first electrode via space and together constitute a release hole; the substrate is etched from the second side to form a first cavity in the substrate and expose the first dielectric portion of the first dielectric layer; and a dielectric etching process is performed to remove the first dielectric portion and extend the first cavity to expose a portion of the surface of the first electrode layer, and remove the second dielectric portion of the second dielectric layer to form a second cavity, the second cavity is connected to the release hole space and overlaps with the first cavity in the first direction, wherein a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm, and the passivation protrusion is located in the second cavity.

[0037] In an embodiment of the present disclosure, a second electrode layer is first patterned, followed by forming a dielectric groove in the second dielectric layer. A passivation layer is formed on the side of the second electrode layer facing away from the substrate, with a passivation protrusion formed in the passivation layer to fill the dielectric groove. Subsequently, substrate and dielectric etching processes are performed to form the first and second cavities. This allows the passivation layer to extend from the side of the second electrode layer facing away from the substrate into the second cavity. In this way, the passivation layer serves as a support layer for the second electrode layer, while the passivation protrusion in the second cavity prevents contact between the diaphragm and the first electrode layer. This manufacturing method eliminates the need for passivation material on the substrate-facing side of the second electrode layer, simplifying the process and reducing costs. Furthermore, the distance between the first electrode layer (i.e., the diaphragm) and the second electrode layer is reduced, thereby increasing the initial capacitance of the capacitive element formed by the first and second electrode layers. Furthermore, since the reduced distance between the first and second electrode layers increases the initial capacitance, the horizontal dimensions of the sensor can be further reduced while maintaining electrical performance parameters, thereby increasing the number of devices produced from a single wafer.

[0038] Figures 1 to 12 Schematic cross-sectional views showing structures of various steps in a method for manufacturing a capacitive pressure sensor according to some embodiments of the present disclosure.

[0039] In some embodiments, a substrate is provided, the substrate having a first side and a second side opposite to each other in a first direction; a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer are sequentially formed on the first side of the substrate.

[0040] For example, reference Figure 1 , providing a substrate 100, which may be or include a semiconductor substrate; for example, the substrate 100 may include a semiconductor material such as silicon, for example, including single crystal silicon. In some embodiments, the substrate 100 may be a semiconductor wafer, for example, a silicon wafer. The substrate 100 has a first side S1 and a second side S2 opposite to each other in a first direction D1. In some embodiments, the substrate 100 may be an N-type substrate and may be doped with dopants such as phosphorus or arsenic, but the present disclosure is not limited thereto. In other embodiments, the substrate 100 may also be a P-type substrate and may be doped with dopants such as boron. In this document, the first direction D1 may be a direction substantially perpendicular to the main surface of the substrate 100 (for example, the horizontal surface shown in the figure), and the second direction D2 intersects with the first direction D1. For example, the second direction D2 may be substantially perpendicular to the first direction D1 and may be a direction substantially parallel to the main surface of the substrate.

[0041] refer to Figure 2, a first dielectric layer 101, a first electrode layer 102, a second dielectric layer 103, and a second electrode layer 104 are sequentially formed on a substrate 100. For example, the above material layers may be sequentially formed at least on the first side S1 of the substrate 100. In some examples, such as Figure 2 As shown, the above material layers may also be sequentially formed on the second side S2 of the substrate 100. In this document, "on" a component may include on any side of the component, and is not limited to being "above" as shown in the figures.

[0042] For example, the first dielectric layer 101 may include a dielectric material such as silicon oxide and may be formed on the substrate 100 through a thermal oxidation process. The first electrode layer 102 may include a doped semiconductor material, such as silicon, for example, amorphous silicon (α-Si), and the semiconductor material may be doped with phosphorus or arsenic, or may be doped with boron.

[0043] In some embodiments, a semiconductor material layer may be formed on a side of the first dielectric layer 101 away from the substrate 100 by a deposition process (e.g., a low-pressure deposition process), followed by a doping process (e.g., an ion implantation process) to implant dopants such as phosphorus into the semiconductor material layer, followed by an annealing process to form the first electrode layer 102. For example, the deposition process may be a low-pressure chemical vapor deposition (LPCVD) process.

[0044] The second dielectric layer 103 may comprise the same or similar dielectric material as the first dielectric layer 101. For example, the second dielectric layer 103 may comprise silicon oxide, tetraethyl orthosilicate (TEOS), or the like. For example, the second dielectric layer 103 may be formed on the side of the first electrode layer 102 facing away from the substrate 100 using a deposition process (e.g., LPCVD). For example, the second dielectric layer 103 may be a single layer structure; the thickness of the second dielectric layer 103 may be greater than that of the first dielectric layer 101. In some embodiments, the thickness of the second dielectric layer 103 may range from 4,000 angstroms to 18,000 angstroms (Å), for example, 10,000 Å.

[0045] In some embodiments, the second electrode layer 104 may include a semiconductor material such as silicon, for example, polysilicon, and the semiconductor material may be doped with phosphorus or arsenic, or may be doped with boron. For example, the second electrode layer 104 may include in-situ doped polysilicon (D-polysilicon) and may be formed by in-situ doping during a deposition process (e.g., a low-pressure deposition process).

[0046] like Figure 2As shown, the second dielectric layer 103 is directly formed between the first electrode layer 102 and the second electrode layer 104 , and is in direct contact with the first electrode layer 102 and the second electrode layer 104 .

[0047] In some embodiments, the second electrode layer is subjected to an electrode patterning process to form a first electrode via and a second electrode via in the second electrode layer that expose the second dielectric layer; then, the portion of the second dielectric layer exposed by the second electrode via is removed to form a dielectric groove in the second dielectric layer.

[0048] In some embodiments, the electrode patterning process further forms a third electrode via in the second electrode layer that exposes the second dielectric layer, and before subsequently forming the passivation layer, further comprises: removing the portion of the second dielectric layer exposed by the third electrode via to form a contact hole in the second dielectric layer. In some embodiments, the electrode patterning process further forms a fourth electrode via in the second electrode layer.

[0049] For example, reference Figure 2 and Figure 3 , an electrode patterning process is performed on the second electrode layer 104 to form a plurality of electrode vias in the second electrode layer 104 that expose the second dielectric layer 103. For example, the plurality of electrode vias may include one or more first electrode vias 11, one or more second electrode vias 12, a third electrode via 13, and a fourth electrode via 14. It should be understood that the number of electrode vias shown in the figure is for illustration only and the present disclosure is not limited thereto.

[0050] In some embodiments, the electrode patterning process may include photolithography and etching processes. For example, after forming the second electrode layer 104, a first patterned mask layer 105 may be formed on a side of the second electrode layer 104 away from the substrate 100. The first patterned mask layer 105 may include a patterned photoresist layer and may be formed by forming a photoresist layer on the second electrode layer 104 and then performing a photolithography process including exposure and development to pattern the photoresist layer. The first patterned mask layer 105 has a plurality of mask openings, and the pattern of the plurality of mask openings is consistent with the pattern of the plurality of electrode vias to be formed in the second electrode layer 104. Subsequently, the second electrode layer 104 is etched using the first patterned mask layer 105 as an etching mask to form the plurality of electrode vias. For example, the etching process may include a dry etching process.

[0051] refer to Figure 3 and Figure 4, the portion of the second dielectric layer 103 exposed by the second electrode via 12 is removed to form a dielectric recess 103r in the second dielectric layer 103. For example, after forming a plurality of electrode vias in the second electrode layer 104, the first patterned mask layer 105 is removed, and a second patterned mask layer 106 is formed on the second dielectric layer 103 and the second electrode layer 104. The second patterned mask layer 106 covers the second electrode layer 104 and fills the first electrode via 11, the third electrode via 13, and the fourth electrode via 14. It has a mask opening that is spatially connected to the second electrode via 12; for example, the pattern of the mask opening can be substantially the same as the pattern of the second electrode via 12. The second patterned mask layer 106 can include patterned photoresist and can be formed by a photolithography process. Next, an etching process (e.g., a dry etching process) is performed on the second dielectric layer 103 using the second patterned mask layer 106 as an etching mask to remove the portion of the second dielectric layer 103 exposed by the mask opening and the second electrode via 12. For example, the process of forming the dielectric groove 103r can be referred to as a first dielectric patterning process.

[0052] In some embodiments, during the etching process for forming the dielectric groove 103r, the thickness of the removed portion of the second dielectric layer 103 (i.e., the depth of the dielectric groove 103r) can be controlled by controlling the etching time, such that the depth of the dielectric groove 103r is less than the thickness of the second dielectric layer 103. That is, the dielectric groove 103r is recessed from the surface of the second dielectric layer 103 away from the substrate 100 toward the first electrode layer 102, but does not penetrate the second dielectric layer 103.

[0053] refer to Figure 4 and Figure 5 The portion of the second dielectric layer 103 exposed by the third electrode via 13 is removed to form a contact hole 103c in the second dielectric layer 103. For example, after forming the dielectric groove 103r, the second patterned mask layer 106 is removed, and a third patterned mask layer 107 is formed on the second dielectric layer 103 and the second electrode layer 104.

[0054] The third patterned mask layer 107 covers the second electrode layer 104 and fills the first electrode via 11, the second electrode via 12, the dielectric recess 103r, and the fourth electrode via 14. It also includes a mask opening that is spatially connected to the third electrode via 13. For example, the pattern of the mask opening can be substantially the same as the pattern of the third electrode via 13. The third patterned mask layer 107 can include patterned photoresist and be formed by a photolithography process. Next, an etching process (e.g., a dry etching process) is performed on the second dielectric layer 103 using the third patterned mask layer 107 as an etching mask to remove the portion of the second dielectric layer 103 exposed by the mask opening and the third electrode via 13, thereby forming a contact hole 103c and exposing a portion of the surface of the first electrode layer 102. That is, the contact hole 103c penetrates the second dielectric layer 103 to expose the first electrode layer 102. The process of forming the contact hole 103c can be referred to as a second dielectric patterning process.

[0055] In some embodiments, a passivation layer is formed on a side of the second electrode layer away from the substrate, the passivation layer having a passivation protrusion filling the dielectric groove and a first passivation opening, the first passivation opening being connected to the first electrode via space and together constituting a release hole.

[0056] In some embodiments, the passivation layer also includes a first passivation filling portion filled in the second electrode via, the first passivation filling portion is located on the side of the passivation protrusion away from the first electrode layer, and is surrounded by the second electrode layer in a second direction parallel to the main surface of the substrate.

[0057] In some embodiments, forming the passivation layer includes: forming a passivation material layer, the passivation material layer covering the surface of the second electrode layer away from the substrate, and filling the first electrode via, the second electrode via and the dielectric groove; and removing the portion of the passivation material layer located at and covering the first electrode via to form the first passivation opening and expose the first electrode via.

[0058] In some embodiments, forming the passivation layer further includes forming a second passivation opening and a third passivation opening, wherein the second passivation opening extends through the passivation layer and exposes a portion of the surface of the second electrode layer, and the third passivation opening extends through the passivation layer, the second electrode layer, and the second dielectric layer and exposes a portion of the surface of the first electrode layer. In some embodiments, a portion of the passivation layer is formed in the third electrode via and the contact hole, and the third passivation opening is formed in the portion of the passivation layer. In some embodiments, the passivation layer further includes a second passivation filling portion, which fills the fourth electrode via and contacts the second dielectric layer.

[0059] refer to Figure 8 For example, a passivation layer 108 is formed on the side of the second electrode layer 104 away from the substrate 100. The passivation layer 108 covers the surface of the second electrode layer 104 away from the substrate 100 and fills the dielectric groove and a portion of the electrode via. For example, the passivation layer 108 includes a passivation protrusion 108p that fills the dielectric groove 103r, a first passivation filling portion 108a that fills the second electrode via 12, and a second passivation filling portion 108b that fills the fourth electrode via 14. The passivation layer 108 also has a first passivation opening 21, a second passivation opening 22, and a third passivation opening 23.

[0060] The first passivation opening 21 is spatially connected to the first electrode via 11 and forms a release hole 31. The second passivation opening 22 extends through the passivation layer 108 and exposes a portion of the surface of the second electrode layer 104. The third passivation opening 23 extends through the passivation layer 108, the second electrode layer 104, and the second dielectric layer 103 and exposes a portion of the surface of the first electrode layer 102. For example, a portion of the passivation layer 108 is formed in the third electrode via 13 and the contact hole 103c, and the third passivation opening 23 is formed in the portion of the passivation layer 108. For example, the third passivation opening 23 is located within the third electrode via 13 and the contact hole 103c. That is, the orthographic projection of the third passivation opening 23 on the main surface of the substrate 100 is located within the orthographic projection of the third electrode via 13 and the contact hole 103c on the main surface of the substrate 100.

[0061] In some embodiments, the passivation layer 108 may be formed by forming a passivation material layer and performing a patterning process on the passivation material layer.

[0062] refer to Figure 5 and Figure 6 For example, after forming the contact hole 103c in the second dielectric layer 103, the third patterned mask layer 107 is removed, and then a passivation material layer 18 is formed over the first side of the substrate 100. The passivation material layer 18 covers the surface of the second electrode layer 104 on the side away from the substrate 100 and fills the first electrode via 11, the second electrode via 12, the third electrode via 13, and the fourth electrode via 14 in the second electrode layer 104, as well as the dielectric recess 103r and the contact hole 103c in the second dielectric layer 103. The passivation material layer 18 is made of a different material than the second dielectric layer 103 and the first dielectric layer 101. For example, the passivation material layer 18 may include a dielectric material such as silicon nitride and may be formed using a deposition process such as LPCVD.

[0063] refer to Figures 6 to 8Next, the portion of the passivation material layer 18 located in and covering the first electrode via 11 is removed to form a first passivation opening 21 and expose the first electrode via 11, so that the first passivation opening 21 and the first electrode via 11 are spatially connected to each other and together constitute a release hole 31. The portion of the passivation material layer 18 located on the side of the second electrode layer 104 away from the substrate is removed to form a second passivation opening 22 and expose a portion of the surface of the second electrode layer 104. The portion of the passivation material layer 18 located in the third electrode via 13 and / or the contact hole 103c is removed to form a third passivation opening 23. Removal of the above-mentioned portion of the passivation material layer 18 can be performed by a patterning process including photolithography and etching.

[0064] For example, reference Figure 6 and Figure 7 , a fourth patterned mask layer 109 may be formed on the passivation material layer to cover the passivation material layer, and the fourth patterned mask layer 109 has a mask opening that exposes the above-mentioned portion of the passivation material layer to be removed, that is, the pattern of the mask opening is consistent with the pattern of the multiple passivation openings to be formed; the fourth patterned mask layer 109 may include a patterned photoresist layer formed by a photolithography process; then, the passivation material layer is subjected to an etching process (for example, a dry etching process) using the fourth patterned mask layer 109 as an etching mask to remove the portion of the passivation material layer exposed by the mask opening, and form a passivation layer 108 with multiple passivation openings. In the etching process, the portion of the passivation layer 108 located in the second electrode via 12 and the dielectric groove 103r and the portion located in the fourth electrode via 14 are covered by the fourth patterned mask layer 109 and therefore will not be removed. For example, Figure 8 As shown, the portions of the passivation layer 108 located in the dielectric groove 103r, the second electrode via hole 12, and the fourth electrode via hole 14 constitute a passivation protrusion 108p, a first passivation filling portion 108a, and a second passivation filling portion 108b, respectively.

[0065] In some embodiments, since the second electrode layer 104 is Figure 3 The electrode has been patterned in the illustrated patterning process, so the above etching process removes the passivation material layer without removing the second electrode layer 104 .

[0066] In some embodiments, a first conductive pad is formed in the third passivation opening, the first conductive pad being electrically connected to the first electrode layer; and a second conductive pad is formed in the second passivation opening, the second conductive pad being electrically connected to the second electrode layer.

[0067] refer to Figure 8 and Figure 9For example, a first conductive pad 111 is formed in the third passivation opening 23 and electrically connected to the first electrode layer 102. A second conductive pad 112 is formed in the second passivation opening 22 and electrically connected to the second electrode layer 104. The first conductive pad 111 and the second conductive pad 112 may include a metal material such as chromium, gold, alloys thereof, or the like. For example, the multiple pads may be formed by evaporation and lift-off processes.

[0068] For example, after forming the passivation layer 108, a fifth patterned mask layer (not shown) may be formed on the passivation layer 108. The fifth patterned mask layer may include a patterned photoresist layer formed by a photolithography process. The fifth patterned mask layer covers the passivation layer 108 and has a first mask opening and a second mask opening. The first mask opening is spatially connected to the third passivation opening and exposes a portion of the surface of the first electrode layer. The second mask opening is spatially connected to the second passivation opening and exposes a portion of the surface of the second electrode layer. Next, a pad material layer is formed over the first side of the substrate by an evaporation process. The pad material layer is formed on a side of the fifth patterned mask layer facing away from the substrate and is formed in the third passivation opening and the second passivation opening. Thereafter, the fifth patterned mask layer and the pad material layer thereon may be removed by a lift-off process, leaving the pad material layer in the third passivation opening and the second passivation opening to form the first conductive pad and the second conductive pad, respectively.

[0069] In some embodiments, the substrate is then etched from the second side of the substrate to form a first cavity in the substrate and expose the first dielectric portion of the first dielectric layer; and a dielectric etching process is performed to remove the first dielectric portion and extend the first cavity to expose a portion of the surface of the first electrode layer, and to remove the second dielectric portion of the second dielectric layer and form a second cavity, wherein the second cavity is spatially connected to the release hole and overlaps with the first cavity in the first direction.

[0070] For example, reference Figure 9 and Figure 10 , remove the material layer located on the second side S2 of the substrate 100. It should be understood that Figures 3 to 9 The process steps shown are all performed on the relevant material layers on the first side S1 of the substrate 100. In some examples, the material layers on the second side S2 of the substrate 100 may be removed by a grinding process such as chemical mechanical polishing (CMP) or mechanical grinding.

[0071] In some embodiments, after removing the material layer on the second side S2 of the substrate 100, a thinning process may be performed on the substrate 100 to reduce the thickness of the substrate 100. The thinning process may include, for example, a grinding process such as CMP or mechanical grinding.

[0072] refer to Figure 10 and Figure 11 , an etching process is performed on the substrate 100 from the second side S2 of the substrate 100 to form a first cavity 120 in the substrate 100 and expose the first dielectric portion of the first dielectric layer 101 .

[0073] For example, a sixth patterned mask layer may be formed on the second side S2 of the substrate 100, wherein the sixth patterned mask layer may include a patterned photoresist layer formed by a photolithography process and has a mask opening corresponding to the pattern of the first cavity; then, the above-mentioned etching process is performed on the substrate 100 using the sixth patterned mask layer as an etching mask to remove the portion of the substrate 100 exposed by the mask opening and form the first cavity 120.

[0074] refer to Figure 11 and Figure 12 A dielectric etching process is then performed to form the first cavity 120 and the second cavity 220, thereby forming the capacitive pressure sensor 500. For example, the dielectric etching process removes the exposed first dielectric portion of the first dielectric layer 101, extending the first cavity 120 through the first dielectric layer 101 to expose a portion of the surface of the first electrode layer 102 on the side away from the second electrode layer. That is, the first cavity 120 includes a substrate opening formed in the substrate 100 and a dielectric opening formed in the first dielectric layer 101. The substrate opening and the dielectric opening are spatially connected to each other and together constitute the first cavity 120. The dielectric etching process also removes the second dielectric portion of the second dielectric layer 103 and forms the second cavity 220. The second cavity 220 is spatially connected to the release hole 31 and overlaps with the first cavity 120 in the first direction D1. The second cavity 220 exposes a portion of the surface of the first electrode layer 102 on the side close to the second electrode layer. A portion of the first electrode layer 102 is located between the first cavity 120 and the second cavity 220 and serves as a diaphragm. After forming the second cavity 220, the passivation protrusion 108p is located in the second cavity 220. Herein, a plurality of members overlapping in a certain direction means that orthographic projections of the plurality of members on a reference plane perpendicular to the direction overlap with each other.

[0075] In some embodiments, the dielectric etching process may include a wet etching process, and an etchant used in the wet etching process enters the region where the second dielectric portion is located through the release hole.

[0076] For example, the wet etching process may use an etchant such as a buffered oxide etchant (BOE) (a mixture of hydrofluoric acid and ammonium fluoride) to etch the first dielectric layer 101 and the second dielectric layer 103. For example, the etchant used in the wet etching process may enter the region where the second dielectric portion is located through the release hole 31 to remove the second dielectric portion and form the second cavity 220 in the region previously occupied by the second dielectric portion. For example, the etchant may contact and etch the first dielectric portion through the substrate opening.

[0077] The dielectric etching process can be isotropic etching. In some examples, in addition to removing the first dielectric portion of the first dielectric layer 101 exposed by the substrate opening, the dielectric etching process can also remove the portion of the first dielectric layer 101 located between the substrate 100 and the first electrode layer 102, thereby forming an undercut between the substrate 100 and the first electrode layer 102 at the side of the first dielectric layer 101.

[0078] For example, the dielectric etching process may have a smaller etching selectivity for the first dielectric layer 101 and the second dielectric layer 103, and a larger etching selectivity for the second dielectric layer 103 and the passivation layer 108. For example, the etching process does not substantially remove the passivation layer 108, and after forming the second cavity 220, the passivation protrusion 108p of the passivation layer 108 is suspended above the first electrode layer 102 and is located in the second cavity 220.

[0079] In some embodiments, Figures 1 to 12 The process steps shown are wafer-level processes. For example, the substrate is a semiconductor wafer and includes a plurality of die regions. The plurality of die regions may be separated from each other by dicing regions. Figures 1 to 12 The process steps in one die area of ​​the wafer are shown. It should be understood that the process steps and the structures formed in the other die areas are the same as those shown in the figure. After completing the above process steps, multiple semiconductor devices (i.e., capacitive pressure sensors 500) are formed in the multiple die areas of the wafer. Thereafter, a wafer dicing process can be performed along the dicing area to separate the semiconductor devices located in the multiple die areas and form multiple independent dies, as shown in FIG. Figure 12 The capacitive pressure sensor 500 is shown. The capacitive pressure sensor 500 is a MEMS capacitive pressure sensor.

[0080] An embodiment of the present disclosure provides a capacitive pressure sensor, comprising: a substrate having a first side and a second side opposite to each other in a first direction; a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer, which are sequentially arranged on the substrate in the first direction; a first cavity, which extends from the second side of the substrate through the substrate and the first dielectric layer and exposes a portion of the surface of the first electrode layer; a second cavity, which is located on a side of the first electrode layer away from the first cavity and is defined by the facing surfaces of the first electrode layer and the second electrode layer and the inner sidewall of the second dielectric layer, wherein a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm; and a passivation layer, which is arranged on a side of the second electrode layer away from the substrate and extends through the second electrode layer and into the second cavity.

[0081] In some embodiments, the second electrode layer includes a first electrode via and a second electrode via, and the orthographic projections of the first electrode via and the second electrode via on the main surface of the first electrode layer are located within the orthographic projection of the second cavity on the main surface of the first electrode layer; the passivation layer includes a first passivation opening, and the first passivation opening and the first electrode via together constitute a release hole and are connected to the second cavity space; the second electrode via is partially filled with the passivation layer.

[0082] In some embodiments, the passivation layer includes: a first passivation filling portion, located in the second electrode via; and a passivation protrusion, located on a side of the first passivation filling portion close to the first electrode layer, and located in the second cavity, and protruding from the surface of the second electrode layer close to the diaphragm toward the diaphragm in the first direction.

[0083] refer to Figure 12 For example, the capacitive pressure sensor 500 includes a substrate 100, a first dielectric layer 101, a first electrode layer 102, a second dielectric layer 103, a second electrode layer 104, a passivation layer 108, a first conductive pad 111, and a second conductive pad 112, and has a first cavity 120 and a second cavity 220. The substrate 100 has a first side S1 and a second side S2 that are opposite to each other in a first direction D1. The first cavity 120 extends from the second side S2 of the substrate 100 through the substrate 100 and the first dielectric layer 101, exposing a portion of the surface of the first electrode layer 102 that is remote from the second electrode layer. For example, the first cavity 120 is defined by the inner sidewalls of the substrate 100 and the first dielectric layer 101, as well as the surface of the first electrode layer 102 that is remote from the second electrode layer 104. The second cavity 220 is located on a side of the first electrode layer 102 away from the first cavity 120 and is defined by facing surfaces of the first electrode layer 102 and the second electrode layer 104 and an inner sidewall of the second dielectric layer 103 .

[0084] The first cavity 120 and the second cavity 220 overlap in the first direction D1, and also overlap with the first electrode layer 102 and the second electrode layer 104 in the first direction D1. A portion (e.g., the central portion) of the first electrode layer 102 is located between the first cavity 120 and the second cavity 220 and serves as a diaphragm. Other portions of the first electrode layer 102 are located between the first dielectric layer 101 and the second dielectric layer 103, between the first dielectric layer 101 and the passivation layer 108, and between the first dielectric layer 101 and the first conductive pad 111, such that the edge portion of the first electrode layer 102 is fixed between these material layers.

[0085] In some embodiments, the first electrode layer 102 can also be referred to as a lower plate, and the second electrode layer 104 can also be referred to as an upper plate. A portion (e.g., a central portion) of the second electrode layer 104 is located above the second cavity 220, i.e., on the side of the second cavity away from the first electrode layer. For example, the orthographic projection of this portion of the second electrode layer 104 on a reference plane parallel to the major surface of the substrate (e.g., the major surface of the first electrode layer) overlaps (e.g., coincides) with the orthographic projection of the second cavity on the reference plane and is offset from the orthographic projection of the second dielectric layer 103 on the reference plane. Other portions (e.g., edge portions) of the second electrode layer 104 are located on the side of the second dielectric layer 103 away from the first electrode layer, and the second conductive pads 112 are formed on these other portions of the second electrode layer.

[0086] In some embodiments, the passivation layer 108 is disposed on a side of the second electrode layer 104 that is distal from the substrate 100, with a portion of the passivation layer 108 extending through the second electrode layer 104 and into the second cavity 220. The passivation layer 108 covers the second electrode layer 104 and can serve as a support layer, thereby maintaining the second electrode layer 104 in a fixed position and substantially preventing vibration, i.e., positional change, during sensor operation. In some embodiments, the passivation layer 108 can have a sufficient thickness to support the second electrode layer 104. For example, the thickness of the passivation layer 108 can be set within a range of 4000 angstroms to 12000 angstroms (Å), such as 8000 Å.

[0087] The first conductive pad 111 and the second conductive pad 112 are respectively located in corresponding passivation openings of the passivation layer 108 and are electrically connected to the first electrode layer 102 and the second electrode layer 104 .

[0088] In some embodiments, the second electrode layer 104 includes a first electrode via 11 and a second electrode via 12. Both the first electrode via 11 and the second electrode via 12 are located above the second cavity 220, such as directly above the second cavity 220 as shown in the figure. For example, the orthographic projections of the first electrode via 11 and the second electrode via 12 on a reference plane parallel to the major surface of the substrate (e.g., the major surface of the first electrode layer 102) are located within the orthographic projection of the second cavity 220 on the reference plane.

[0089] In some embodiments, the first electrode via 11 and the first passivation opening 21 together constitute a release hole 31, and the release hole 31 is spatially connected to the second cavity 220. In some embodiments, the release hole can also be referred to as an acoustic hole or an air hole. In some embodiments, the second electrode via 12 is partially filled (e.g., completely filled) by the passivation layer and does not communicate with the second cavity 220.

[0090] For example, the passivation layer 108 may extend continuously from a side of the second electrode layer 104 remote from the substrate, through the second electrode layer 104, and into the second cavity 220. For example, the portion of the passivation layer 108 extending through the second electrode layer and into the second cavity includes a first passivation filling portion 108a and a passivation protrusion 108p. The first passivation filling portion 108a is located in the second electrode via 12 and may, for example, completely fill the second electrode via 12. For example, the first passivation filling portion 108a contacts the sidewalls of the second electrode layer 104 defining the second electrode via 12 and is surrounded by the second electrode layer 104 in a direction parallel to the main surface of the substrate (e.g., a horizontal direction including the second direction D2). The passivation protrusion 108p is located on a side of the first passivation filling portion 108a closer to the first electrode layer 102 and is located in the second cavity 220. The passivation protrusion 108 p protrudes from a surface of the second electrode layer 104 close to the diaphragm (ie, the bottom surface shown in the figure) toward the diaphragm (ie, the first electrode layer 102 ) in the first direction D1 .

[0091] The thickness of the passivation protrusion 108p in the first direction D1 is substantially equal to the distance between the bottom surface of the second electrode layer 104 and the bottom surface of the passivation protrusion 108p in the first direction D1, and is less than the thickness of the second dielectric layer 103 in the first direction D1. In other words, the thickness of the passivation protrusion 108p is less than the initial spacing between the first electrode layer 102 and the second electrode layer 104, thereby allowing the first electrode layer 102 to move in the first direction D1 and preventing the first electrode layer 102 from contacting the second electrode layer 104 when the first electrode layer 102 moves in the first direction.

[0092] In some embodiments, the passivation layer 108 covers and contacts the surface of the second electrode layer 104 facing away from the substrate (i.e., the top surface shown in the figure) and portions of the sidewalls of the second electrode layer 104. The surface of the second electrode layer 104 facing the substrate (i.e., the bottom surface shown in the figure) is exposed in the second cavity 220 or in contact with the second dielectric layer 103, but may not be in contact with the passivation layer or other passivation material. For example, an edge portion of the second electrode layer 104 is in direct contact with the second dielectric layer 103, and no other passivation material is disposed between the second electrode layer 104 and the second dielectric layer 103.

[0093] In the capacitive pressure sensor 500, the first electrode layer 102, the second electrode layer 104, the second dielectric layer 103 and the second cavity 220 constitute a capacitor element, wherein the first electrode layer 102 and the second electrode layer 104 serve as electrode plates of the capacitor element respectively, and the second dielectric layer 103 and the second cavity 220 constitute an inter-electrode dielectric. The first conductive pad 111 and the second conductive pad 112 serve as conductive terminals of the capacitor element and can be used to detect the capacitance value of the capacitor element. A portion of the first electrode layer 102 is located between the first cavity 120 and the second cavity 220 and serves as a diaphragm 102a. For example, the diaphragm 102a can be as follows in the initial state. Figure 12 As shown, the diaphragm 102a extends substantially along a horizontal direction including the second direction D2. At this time, there is an initial spacing between the diaphragm 102a and the second electrode layer 104 (i.e., substantially equal to the thickness of the second dielectric layer 103). Accordingly, the capacitive element has an initial capacitance corresponding to the initial spacing. The diaphragm 102a can vibrate (i.e., displace) when subjected to pressure. For example, the diaphragm 102a can displace in the first direction D1 when subjected to upward or downward pressure, thereby causing the spacing between the diaphragm 102a and the second electrode layer 104 in the first direction D1 to change, thereby changing the capacitance of the capacitive element. The change in capacitance can be detected by the first conductive pad 111 and the second conductive pad 112, and the pressure applied to the diaphragm can be sensed by the detected change in capacitance. The passivation protrusion 108p is located in the second cavity 220 to prevent the diaphragm 102a from contacting the second electrode layer 104 when its position changes.

[0094] It should be understood that according to the calculation formula of capacitance, the capacitance value of the capacitor element is proportional to the area facing the electrode plates and inversely proportional to the distance between the electrode plates. For example, when the diaphragm 102a is subjected to upward pressure, the diaphragm 102a moves toward the second electrode layer 104 (for example, bends). At this time, the distance between the diaphragm 102a and the second electrode layer 104 becomes smaller, and the capacitance value of the capacitor element becomes larger. When the diaphragm 102a is subjected to downward pressure, the diaphragm 102a moves away from the second electrode layer 104 (for example, bends). At this time, the distance between the diaphragm 102a and the second electrode layer 104 becomes larger, and the capacitance value of the capacitor element becomes smaller. In some embodiments, the magnitude of the pressure can be sensed by measuring the change in capacitance.

[0095] An embodiment of the present disclosure provides an electronic device, which may include the capacitive pressure sensor described above, wherein the electronic device may include a microphone (ie, a microphone) or an electronic cigarette.

[0096] For example, the capacitive pressure sensor 500 can be used in an electronic cigarette, and can sense the position change of the diaphragm 102a by sensing the capacitance change of the capacitor element through the first conductive pad 111 and the second conductive pad 112, thereby sensing the user's inhalation action (ie, smoking action).

[0097] For example, the first cavity 120 may be connected to the atmosphere, while the second cavity 220 and the release hole 31 may be connected to the inhalation channel of the electronic cigarette. When the user inhales (i.e., takes a puff), the air pressure in the second cavity 220 decreases, causing the air pressure in the first cavity 120 to be greater than that in the second cavity 220. This exerts upward pressure on the diaphragm 102a, causing it to move toward the second electrode layer 104. This reduces the distance between the diaphragm 102a and the second electrode layer 104, increasing the capacitance of the capacitive element. This change in capacitance can then be detected by the first and second conductive pads 111 and 112. Therefore, the user's puffing action can be sensed by detecting the change in capacitance. For example, the degree of the user's inhalation can also be determined by the degree of change in the detected capacitance value.

[0098] Similarly, the capacitive pressure sensor 500 can be used in a microphone (i.e., a microphone), and sound waves can enter the cavity through the sound hole (e.g., the release hole 31) and act on the diaphragm, thereby generating pressure on the diaphragm, causing the position of the diaphragm to change, and then causing the capacitance of the capacitive element to change, and the capacitance change can be detected by the first conductive pad and the second conductive pad.

[0099] In the above embodiment, the first electrode layer 102 is located between the first cavity 120 and the second cavity 220 and can isolate the first cavity 120 from the second cavity 220. However, the present disclosure is not limited thereto.

[0100] Figure 13 A schematic cross-sectional view shows a capacitive pressure sensor according to some other embodiments of the present disclosure.

[0101] In some other embodiments, the first electrode layer may further include one or more vias, and the one or more vias are connected to the first cavity and the second cavity space. For example, in the manufacturing method of the capacitive pressure sensor, the method further includes: performing a patterning process on the first electrode layer to form vias in the first electrode layer. For example, the patterning process of the first electrode layer may be performed in Figure 2 The steps shown are performed after forming the first electrode layer and before forming the second dielectric layer.

[0102] refer to Figure 13 For example, the first electrode layer 102 is provided with one or more vias 41; these one or more vias 41 penetrate the first electrode layer 102 and are spatially connected to the first cavity 120 and the second cavity 220. The one or more vias 41 may or may not overlap with the one or more release holes 31 in the first direction D1. It should be understood that the number of release holes 31 and vias 41 shown in the figures is for illustration only and is not intended to limit the present disclosure.

[0103] For example, in Figure 2 In the process steps shown, after forming the first electrode layer 102, the first electrode layer 102 is patterned to form one or more vias 41 in the first electrode layer 102. The patterning process may include photolithography and etching processes. The second dielectric layer 103 formed thereafter is filled in the vias 41, and the portion of the second dielectric layer 103 filled in the vias 41 is formed. Figures 11 to 12 The dielectric etching process is removed, so that the via hole 41 is exposed and communicated with the formed first cavity and second cavity space.

[0104] Figure 13 The other structural features, manufacturing methods, and operating principles of the capacitive pressure sensor are substantially the same or similar to those of the aforementioned embodiments and are not further described here. In some embodiments, one or more vias are provided in the first electrode layer to improve the sensitivity of an electronic device such as a microphone when the capacitive pressure sensor is applied to the microphone.

[0105] In the capacitive pressure sensor and its manufacturing method of various embodiments of the present disclosure, a passivation layer is provided on the side of the second electrode layer away from the substrate to provide support for the second electrode layer, and the passivation layer extends through the second electrode layer and extends into the second cavity to prevent the diaphragm from contacting the second electrode layer when the position changes; in this way, a passivation material layer may not be required on the side of the second electrode layer close to the substrate, that is, a passivation material layer (for example, a silicon nitride layer) may be omitted between the second electrode layer and the second cavity and between the second electrode layer and the second dielectric layer. In this way, the process can be simplified and the number of photolithography layers can be reduced (that is, the number of material layers that need to be patterned using a patterning process including photolithography is reduced), thereby reducing process costs. For example, in Figures 1 to 12 In the embodiment shown, the manufacturing method uses 6 photolithography processes. Compared with some manufacturing methods that require 8-10 photolithography processes, the manufacturing method of the embodiment of the present disclosure reduces process complexity and cost, and can shorten the processing cycle.

[0106] Furthermore, since the passivation material located on the side of the second electrode layer close to the substrate is omitted, the initial spacing between the first electrode layer and the second electrode layer can be reduced, thereby facilitating an increase in the initial capacitance of the capacitive element comprising the first electrode layer and the second electrode layer. Furthermore, while ensuring electrical performance parameters, the size of the die in a direction parallel to the main surface of the substrate can be reduced, thereby increasing the number of die produced per single wafer (i.e., a single wafer). In other words, the size of the die area can be reduced, thereby increasing the number of die (i.e., capacitive pressure sensors) formed from the same wafer, thereby also improving yield. For example, the capacitance of a capacitive element is proportional to the area facing the plates and inversely proportional to the distance between the plates. Therefore, while ensuring electrical performance parameters, since the distance between the first and second electrode layers is reduced, even if the horizontal size of the sensor is reduced (e.g., the area facing the plates is reduced), the capacitive element can still maintain expected electrical performance parameters.

[0107] There are a few points to note:

[0108] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design.

[0109] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0110] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a capacitive pressure sensor, characterized in that: include: providing a substrate having a first side and a second side opposite to each other in a first direction; forming a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer in sequence on the first side of the substrate; performing an electrode patterning process on the second electrode layer to form a first electrode via hole and a second electrode via hole in the second electrode layer that expose the second dielectric layer; removing a portion of the second dielectric layer exposed by the second electrode via hole to form a dielectric groove in the second dielectric layer, wherein the depth of the dielectric groove is less than the thickness of the second dielectric layer; A passivation layer is formed on a side of the second electrode layer away from the substrate, the passivation layer covers the second electrode layer and continuously extends from the side of the second electrode layer away from the substrate into the dielectric groove, and has a passivation protrusion filling the dielectric groove and a first passivation opening, the first passivation opening is spatially connected to the first electrode via hole, and together constitutes a release hole; performing an etching process on the substrate from the second side to form a first cavity in the substrate and expose a first dielectric portion of the first dielectric layer; as well as Performing a dielectric etching process to remove the first dielectric portion and extend the first cavity to expose a portion of the surface of the first electrode layer, and removing the second dielectric portion of the second dielectric layer to form a second cavity, wherein the second cavity is connected to the release hole space and overlaps with the first cavity in the first direction. After the first cavity and the second cavity are formed, a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm, a portion of the second electrode layer is suspended over the second cavity, and a surface of the portion of the second electrode layer close to the first electrode layer is exposed in the second cavity, a surface of the portion of the second electrode layer away from the first electrode layer is covered by the passivation layer, and the passivation protrusion of the passivation layer is located in the second cavity. The thickness of the passivation layer ranges from 4000 angstroms to 12000 angstroms.

2. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein: The passivation layer also includes a first passivation filling portion filled in the second electrode via, the first passivation filling portion is located on a side of the passivation protrusion away from the first electrode layer, and is surrounded by the second electrode layer in a second direction parallel to the main surface of the substrate.

3. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein: The orthographic projections of the first electrode via and the second electrode via on the main surface of the first electrode layer are located within the orthographic projection of the second cavity on the main surface of the first electrode layer.

4. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein: The second cavity is defined by surfaces of the first electrode layer and the second electrode layer facing each other and an inner sidewall of the second dielectric layer.

5. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein: Forming the passivation layer includes: forming a passivation material layer, the passivation material layer covering a surface of the second electrode layer away from the substrate and filling the first electrode via hole, the second electrode via hole, and the dielectric groove; and The portion of the passivation material layer located at and covering the first electrode via hole is removed to form the first passivation opening and expose the first electrode via hole.

6. The method for manufacturing a capacitive pressure sensor according to any one of claims 1 to 5, characterized in that: Forming the passivation layer also includes forming a second passivation opening and a third passivation opening, wherein the second passivation opening extends through the passivation layer and exposes a portion of the surface of the second electrode layer, and the third passivation opening extends through the passivation layer, the second electrode layer and the second dielectric layer and exposes a portion of the surface of the first electrode layer.

7. The method for manufacturing a capacitive pressure sensor according to claim 6, wherein: The electrode patterning process further includes forming a third electrode via hole in the second electrode layer to expose the second dielectric layer, and before forming the passivation layer, further includes: removing a portion of the second dielectric layer exposed by the third electrode via hole to form a contact hole in the second dielectric layer; Portions of the passivation layer are formed in the third electrode via hole and the contact hole, and the third passivation opening is formed in the portions of the passivation layer.

8. The method for manufacturing a capacitive pressure sensor according to claim 6, wherein: Also includes: forming a first conductive pad in the third passivation opening, wherein the first conductive pad is electrically connected to the first electrode layer; as well as A second conductive pad is formed in the second passivation opening, and the second conductive pad is electrically connected to the second electrode layer.

9. The method for manufacturing a capacitive pressure sensor according to any one of claims 1 to 5, characterized in that: The electrode patterning process further forms a fourth electrode via hole in the second electrode layer, and the passivation layer further forms a second passivation filling portion, which fills the fourth electrode via hole and contacts the second dielectric layer.

10. The method for manufacturing a capacitive pressure sensor according to any one of claims 1 to 5, characterized in that: The dielectric etching process includes a wet etching process, and an etchant used in the wet etching process enters the area where the second dielectric portion is located through the release hole.

11. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein: Also includes: A patterning process is performed on the first electrode layer to form a via hole in the first electrode layer, wherein the via hole is in communication with the first cavity and the second cavity.

12. A capacitive pressure sensor, characterized in that: include: a substrate having a first side and a second side opposite to each other in a first direction; A first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer are sequentially arranged on the substrate in the first direction; a first cavity extending from the second side of the substrate through the substrate and the first dielectric layer and exposing a portion of the surface of the first electrode layer; a second cavity located on a side of the first electrode layer away from the first cavity and defined by surfaces of the first electrode layer and the second electrode layer facing each other and an inner sidewall of the second dielectric layer, wherein a portion of the first electrode layer is located between the first cavity and the second cavity and serves as a diaphragm; as well as a passivation layer covering a surface of the second electrode layer on a side away from the substrate, and continuously extending from the side of the second electrode layer away from the substrate, through the second electrode layer, and extending into the second cavity, wherein a portion of the second electrode layer is suspended over the second cavity, and a surface of the portion of the second electrode layer on a side close to the first electrode layer is exposed in the second cavity, and the surface of the portion of the second electrode layer on a side away from the first electrode layer is covered by the passivation layer, wherein the thickness of the passivation layer is in a range of 4000 angstroms to 12000 angstroms, The passivation layer includes a passivation protrusion located in the second cavity, and a thickness of the passivation protrusion in the first direction is smaller than a thickness of the second dielectric layer in the first direction.

13. The capacitive pressure sensor according to claim 12, wherein: The second electrode layer includes a first electrode via and a second electrode via, wherein orthographic projections of the first electrode via and the second electrode via on the main surface of the first electrode layer are located within an orthographic projection of the second cavity on the main surface of the first electrode layer; The passivation layer includes a first passivation opening, wherein the first passivation opening and the first electrode via hole together constitute a release hole and are connected to the second cavity space; The second electrode via hole is partially filled with the passivation layer.

14. The capacitive pressure sensor according to claim 13, wherein: The passivation layer comprises: a first passivation filling portion, located in the second electrode via hole; and The passivation protrusion is located on a side of the first passivation filling portion close to the first electrode layer, and protrudes from a surface of the second electrode layer close to the diaphragm in the first direction toward the diaphragm.

15. An electronic device, characterized in that: The capacitive pressure sensor according to any one of claims 12 to 14, wherein the electronic device comprises a microphone or an electronic cigarette.

Images