A MEMS capacitive pressure sensor structure and its manufacturing method

Abstract

This invention discloses a MEMS capacitive pressure sensor structure and its manufacturing method, belonging to the field of pressure sensor technology. It employs a planar capacitor structure, where a doped layer is formed on a substrate to create the lower electrode of the capacitive pressure sensor. Multiple structural layers are deposited on this doped layer to form the upper electrode. A first insulating dielectric layer and a cavity are disposed between the upper and lower electrodes, from bottom to top. This invention features a simple structure and convenient fabrication. Furthermore, the entire fabrication process is performed on the front side of the substrate, a planar process, eliminating the need for front-back alignment and facilitating single-chip integration with CMOS technology.

Description

Technical Field

[0001] This invention relates to the field of pressure sensor technology, and in particular to a MEMS capacitive pressure sensor structure and its manufacturing method. Background Technology

[0002] Capacitive pressure sensors use MEMS technology to create a capacitor whose capacitance changes with applied pressure. The pressure is measured by detecting these minute changes in capacitance through signal processing circuitry. The advantages of capacitive pressure sensors include high sensitivity, lower power consumption, and lower temperature drift, thus attracting widespread attention in the industry.

[0003] Traditional capacitive pressure sensors are manufactured by etching silicon films on both sides of a silicon wafer, forming an electrode on each film. This silicon wafer is then soldered to another silicon wafer or glass plate with a different electrode, creating a sealed cavity. The capacitor's electrode is fabricated on the silicon film and the glass (or another silicon wafer). This method of manufacturing capacitive pressure sensors has the following problems: 1. The back-side etching process limits the structure; 2. Soldering the silicon wafer to the glass or another silicon wafer leads to thermal expansion mismatch, fatigue and creep of the solder layer, complex and difficult assembly methods, unstable soldering, and high costs; 3. Processing both sides of the silicon wafer requires double-sided alignment equipment, which is prone to alignment errors; 4. Poor compatibility with planar processing techniques makes integration difficult. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention employs a planar structure, forming one electrode of the capacitor by doping the substrate, and forming the other electrode by depositing two structural layers on the surface. The structure is simple and the processing is straightforward.

[0005] To achieve the above objectives, the present invention provides a MEMS capacitive pressure sensor structure, comprising: employing a planar capacitor structure, doping a substrate to obtain a doped layer to form a lower electrode of the capacitive pressure sensor, depositing multiple structural layers on the substrate to form an upper electrode of the capacitive pressure sensor, and further comprising a first insulating dielectric layer and a cavity between the upper electrode and the lower electrode from bottom to top.

[0006] Furthermore, the upper electrode plate includes at least a first structural layer and a second structural layer, wherein the first structural layer has a plurality of corrosion pores that are sealed by the dielectric layer or the second structural layer.

[0007] Furthermore, the etched holes are arranged in a matrix, and can be round, square, or polygonal.

[0008] Furthermore, the first and second structural layers are made of polycrystalline silicon.

[0009] Furthermore, the upper electrode plate serves as a movable electrode plate of the capacitor, used to sense changes in pressure, and the thickness of the structural layer is 0.1 μm to tens of μm.

[0010] Furthermore, a second insulating dielectric layer is provided on the upper electrode plate, and a contact hole is provided in the second insulating dielectric layer. One contact hole is connected to the second structural layer as the upper electrode, and the other contact hole is connected to the doped layer of the substrate as the lower electrode. A metal layer is deposited in the contact hole to form an electrical connection structure corresponding to the lower electrode and the upper electrode. A passivation layer is provided on the contact hole.

[0011] This invention also provides a method for fabricating a MEMS capacitive pressure sensor, based on the MEMS capacitive pressure sensor described above, comprising the following steps:

[0012] (1) A doped layer is formed on a substrate by ion implantation or diffusion, and then a first insulating layer is grown thereon;

[0013] (2) A sacrificial layer is deposited on the first insulating layer, and excess sacrificial layer is removed by photolithography etching process according to the design pattern. Then, a first structural layer is deposited on it. Then, an array of etched holes is formed on the first structural layer by photolithography etching process according to the design pattern, and the sacrificial layer is released. The released sacrificial layer portion forms a cavity.

[0014] (3) A dielectric layer is deposited on the first structural layer to seal the corrosion holes. The dielectric layer outside the corrosion holes is removed by photolithography etching process. Then, a second structural layer is deposited on it. The excess first and second structural layers are removed by photolithography etching process according to the design pattern.

[0015] Alternatively, the second structural layer can be grown directly while sealing the etched holes, and then the excess first and second structural layers can be removed by photolithography etching according to the design pattern.

[0016] (4) Deposit a second insulating layer on the second structural layer, and then etch contact holes according to the design pattern by photolithography. One hole is connected to the second structural layer as the upper electrode, and the other hole is connected to the doped layer of the substrate as the lower electrode. Then deposit a metal layer, and then remove the excess metal layer according to the design pattern by photolithography etching process to form the electrical connection structure corresponding to the lower electrode and the upper electrode.

[0017] (5) A passivation layer is deposited on the above structure, and then passivation holes are etched by photolithography according to the design pattern to expose the underlying metal layer and form a metal pad. At the same time, the corresponding part of the upper electrode plate should also be exposed.

[0018] Furthermore, if the substrate uses an N-type silicon wafer, the doping layer must be doped with P-type impurities; if the substrate uses a P-type silicon wafer, the doping layer must be doped with N-type impurities.

[0019] Furthermore, the first insulating layer, the second insulating layer, and the dielectric layer are all made of silicon oxide material in a single-layer structure or a composite layer structure made of silicon oxide and silicon nitride material.

[0020] The passivation layer is a single-layer structure made of silicon oxide and silicon nitride or a composite layer structure made of silicon oxide and silicon nitride.

[0021] The beneficial effects of this invention are:

[0022] 1. This invention features a simple structure. One electrode of the capacitor is formed by doping a substrate, and the other electrode is formed by depositing two structural layers on the surface. The structural layers are preferably made of polycrystalline silicon, which has similar mechanical properties to monocrystalline silicon but is easier to process. The simplicity of the structure and the ease of processing give this solution a cost advantage.

[0023] 2. The entire processing of this invention is carried out on the front side of the substrate, which is the so-called planar process processing. It does not require front and back alignment, and can be easily integrated with CMOS process for single chip integration. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the MEMS capacitive pressure sensor structure according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic flowchart illustrating the manufacturing method of a MEMS capacitive pressure sensor according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the corrosion hole array of a MEMS capacitive pressure sensor according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the structure formed by sealing corrosion holes using the second method in an embodiment of the present invention for a MEMS capacitive pressure sensor.

[0028] Wherein, 1—substrate, 2—doped region, 3—first insulating layer, 4—sacrificial layer, 5a—first structural layer, 5b—second structural layer, 6—dielectric layer, 7—second insulating layer, 8a—lower electrode, 8b—upper electrode, 9—passivation layer, 10—cavity. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings and preferred embodiments.

[0030] like Figure 1As shown, the present invention provides a MEMS capacitive pressure sensor structure. The capacitive pressure sensor adopts a planar capacitor structure. A doped layer (2) is formed on a substrate (1) to serve as the lower electrode of the capacitive pressure sensor. Multiple structural layers are deposited on the substrate to form the upper electrode of the capacitive pressure sensor. A first insulating dielectric layer (3) and a cavity (10) are provided between the upper electrode and the lower electrode from bottom to top. The upper electrode includes at least a first structural layer (5a) and a second structural layer (5b). The first structural layer (5a) has multiple etched holes that are closed by the dielectric layer (6) or the second structural layer (5b). A second insulating dielectric layer (7) is provided on the upper electrode. The second insulating dielectric layer (7) has contact holes. One hole is connected to the second structural layer (5b) as the upper electrode, and the other hole is connected to the doped layer (2) on the substrate as the lower electrode. A metal layer is deposited in the contact hole to form an electrical connection structure corresponding to the lower electrode (8b) and the upper electrode (8a). A passivation layer (9) is provided on the contact hole.

[0031] The etched holes are arranged in a matrix and can be round, square, or polygonal.

[0032] The first structural layer (5a) and the second structural layer (5b) are made of polycrystalline silicon.

[0033] The upper electrode plate serves as the movable electrode plate of the capacitor, used to sense changes in pressure. The thickness of the structural layer ranges from 0.1µm to tens of µm.

[0034] like Figure 2 As shown, the present invention also provides a method for fabricating a MEMS capacitive pressure sensor, which, based on the above-mentioned MEMS capacitive pressure sensor, includes the following steps:

[0035] S101. A doped layer is formed on the substrate (1) by ion implantation or diffusion, and then a first insulating layer is grown thereon.

[0036] The substrate (1) is a P-type silicon wafer. A doped layer (2) is formed on the front side by P+ ion implantation (or high phosphorus impurity diffusion). Then, it is treated at a high temperature, such as 1000 degrees Celsius, for a certain period of time to activate the impurities in the substrate. The resistivity of the doped layer should generally be less than 0.01 ohm / cm. The structure at this time is as follows: Figure 2 As shown in (a). If an N-type silicon wafer is used, it must be doped with a P-type impurity, such as boron impurity.

[0037] An insulating dielectric layer—the first insulating dielectric layer (3)—is grown on the front side of the above structure. This can be achieved through LPCVD or other processes. This insulating dielectric layer can take many forms, such as a single layer of silicon oxide, a composite layer of silicon oxide and silicon nitride, or a composite layer with more layers. One of the main functions of this insulating dielectric layer is to achieve electrical isolation between the two plates of the capacitor. Another function is to significantly improve the pressure resistance of the pressure sensor. For example, for a pressure sensor with a range of 100 kPa, if the pressure exceeds 500 kPa, the movable plate will move so much that it contacts the insulating dielectric layer of the substrate. However, due to the obstruction of the insulating dielectric layer, the movable plate cannot move further, thus it can withstand greater sudden pressure without causing structural damage. The structure at this time is as follows: Figure 2 As shown in (b).

[0038] S102. A sacrificial layer is deposited on the first insulating layer (3), and excess sacrificial layer is removed by photolithography etching process according to the design pattern. Then, a first structural layer (5a) is deposited on it. Then, an array of etched holes is formed on the first structural layer by photolithography etching process according to the design pattern, and the sacrificial layer is released. The released sacrificial layer is the cavity (10).

[0039] A sacrificial layer is deposited on the front side of the above structure. The height of this sacrificial layer determines the distance between the capacitor plates, which in turn determines the capacitance value. Specifically, this sacrificial layer can be silicon oxide or other materials that are easily removed by etching or etching, such as silicon oxide formed using PECVD. Then, the unwanted sacrificial layer is removed using photolithography etching. The resulting structure is as follows: Figure 2 As shown in (c), a first structural layer (5a) is deposited on the formed sacrificial layer. The preferred material for the first structural layer (5a) is polycrystalline silicon, which can be formed using an LPCVD process. Then, an array of etched holes is formed on this polycrystalline silicon layer using a photolithography etching process, as shown in the diagram. Figure 2 As shown in (d). The size of the corrosion pits must be appropriate. If the pits are too large, it will hinder the sealing of the subsequent holes; if the pits are too small, it will hinder the corrosion of the underlying sacrificial layer. Therefore, the size of the pits and the distance between them need to be carefully considered. The shape of the corrosion pits can be square, circular, or other geometric shapes. A top view of the resulting corrosion pit array is shown below. Figure 3 As shown. Next, the sacrificial layer beneath the structural layer needs to be removed. This can be done through wet etching with an etchant, gaseous hydrofluoric acid etching, or other etching processes. The resulting structure is shown below. Figure 2 As shown in (e).

[0040] S103. A dielectric layer (6) is deposited on the first structural layer (5a) to seal the etched holes. The dielectric layer outside the etched holes is then removed by photolithography etching. A second structural layer (5b) is then deposited on it. The excess first structural layer (5a) and second structural layer (5b) are then removed by photolithography etching according to the design pattern. Alternatively, the second structural layer (5b) can be grown directly while sealing the etched holes. The excess first structural layer (5a) and second structural layer (5b) can then be removed by photolithography etching according to the design pattern.

[0041] Next, the etched holes need to be sealed to form a closed cavity (10) as a reference pressure chamber on one side of the movable electrode plate (the pressure inside this cavity needs to be kept constant; generally, the pressure inside this cavity is very low, for example, below 10 kPa). One method is to seal the etched holes by depositing a dielectric layer (6). During the deposition process, a dielectric layer (6) will also grow on the hole wall. When the thickness of the dielectric layer (6) on the hole wall exceeds the radius of the hole, the hole is sealed. This dielectric layer (6) can be silicon oxide, silicon nitride, or a composite layer of silicon oxide and silicon nitride, or other dielectric materials. After the hole is sealed, the dielectric layer (6) outside the etched hole is removed by photolithography etching. The structure formed at this time is as follows: Figure 2 As shown in (f). Then, a second structural layer (5b) is deposited on top of the structure. The second structural layer (5b) is preferably polycrystalline silicon. These two structural layers form the upper electrode plate, resulting in the structure shown in (f). Figure 2 As shown in (g). The reason why a second structural layer (5b) still needs to be deposited is that the thickness of the first structural layer (5a) cannot reach the thickness required by the upper electrode to facilitate the etching of the underlying sacrificial layer.

[0042] Another method to seal the etched pits is to directly grow a second structural layer (5b), preferably polycrystalline silicon. For example, a second polycrystalline silicon layer can be epitaxially grown on an existing polycrystalline silicon layer. Similarly, when the thickness of the polycrystalline silicon grown on the pit wall exceeds the radius of the pit, the pit will be sealed. This method is simpler and more efficient than the first method because while growing the polycrystalline silicon to seal the etched pits, forming the second polycrystalline silicon layer simultaneously creates a complete movable electrode structure. The structure formed by this method is as follows: Figure 4 As shown.

[0043] S104. A second insulating layer (7) is deposited on the second structural layer (5b). Then, contact holes are etched by photolithography according to the design pattern. One hole is connected to the second structural layer as the upper electrode (8b), and the other hole is connected to the doped layer of the substrate as the lower electrode (8a). Then, a metal layer is deposited. Then, the excess metal layer is removed by photolithography etching according to the design pattern to form the electrical connection structure corresponding to the lower electrode and the upper electrode.

[0044] The unwanted portion of the polysilicon layer in the above structure is removed by photolithography etching, and then a second insulating dielectric layer (7) is deposited. This insulating dielectric layer is preferably made of silicon oxide. The resulting structure is as follows: Figure 2 As shown in (h), contact holes are etched into the above structure using photolithography, then a layer of conductive metal is deposited, and the metal in unwanted areas is removed using photolithography to form the required electrical connection structure, as shown in the diagram. Figure 2 As shown in (i), the upper electrode is connected to the polycrystalline silicon layer, and the lower electrode is connected to the doped layer of the substrate.

[0045] S105. Deposit a passivation layer (9) on the metal layer, and then etch passivation holes through photolithography etching process according to the design pattern to expose the underlying metal layer and form metal pads.

[0046] Finally, a passivation layer (9) is deposited on the above structure. The passivation layer (9) can be silicon oxide, silicon nitride, or a composite layer of silicon oxide and silicon nitride, as well as other insulating materials. Then, the required passivation holes are formed by photolithography etching to expose the underlying metal pads. The structure at this point is as follows: Figure 2 As shown in (j), the passivation layer on the capacitor structure was also removed simultaneously. This is because the thickness of the passivation layer is not negligible compared to the thickness of the polysilicon layer, and it will have a significant impact on the mechanical properties of the upper electrode. Therefore, it is necessary to remove the passivation layer on the upper electrode.

Claims

1. A method for fabricating a MEMS capacitive pressure sensor, characterized in that: The MEMS capacitive pressure sensor adopts a planar capacitor structure. A doped layer is formed on the substrate to create the lower electrode of the capacitive pressure sensor. Multiple structural layers are deposited on top of this doped layer to form the upper electrode. A first insulating dielectric layer and a cavity are disposed between the upper and lower electrodes from bottom to top. The upper electrode includes at least a first structural layer and a second structural layer. The first structural layer contains multiple etched holes sealed by the dielectric layer or the second structural layer. A second insulating dielectric layer is disposed on top of the upper electrode. Contact holes are provided in the second insulating dielectric layer; one hole connects to the second structural layer as the upper electrode, and the other connects to the doped layer on the substrate as the lower electrode. A metal layer is deposited in the contact holes to form the electrical connection structure corresponding to the lower and upper electrodes. A passivation layer is applied to the contact hole; The preparation method includes the following steps: (1) A doped layer is formed on a substrate by ion implantation or diffusion, and then a first insulating dielectric layer is grown thereon; (2) A sacrificial layer is deposited on the first insulating dielectric layer, and excess sacrificial layer is removed by photolithography etching process according to the design pattern. Then, a first structural layer is deposited on it, and an array of etched holes is formed on the first structural layer by photolithography etching process according to the design pattern. The sacrificial layer is released, and the released sacrificial layer part forms a cavity. (3) A dielectric layer is deposited on the first structural layer to seal the corrosion holes. The dielectric layer outside the corrosion holes is removed by photolithography etching process. Then, a second structural layer is deposited on it. The excess first and second structural layers are removed by photolithography etching process according to the design pattern. Alternatively, the second structural layer can be grown directly while sealing the etched holes, and then the excess first and second structural layers can be removed by photolithography etching according to the design pattern. (4) Deposit a second insulating dielectric layer on the second structural layer, and then etch contact holes by photolithography according to the design pattern. One hole is connected to the second structural layer as the upper electrode, and the other hole is connected to the doped layer of the substrate as the lower electrode. Then deposit a metal layer, and then remove the excess metal layer by photolithography according to the design pattern to form the electrical connection structure corresponding to the lower electrode and the upper electrode. (5) A passivation layer is deposited on the above structure, and then passivation holes are etched by photolithography according to the design pattern to expose the underlying metal layer and form a metal pad. At the same time, the corresponding part of the upper electrode plate should also be exposed.

2. The method for manufacturing a capacitive pressure sensor according to claim 1, characterized in that: If the substrate uses an N-type silicon wafer, the doping layer must be doped with P-type impurities; if the substrate uses a P-type silicon wafer, the doping layer must be doped with N-type impurities.

3. The method for manufacturing a capacitive pressure sensor according to claim 1, characterized in that: The first insulating dielectric layer, the second insulating dielectric layer, and the dielectric layer are all made of a single-layer structure of silicon oxide material or a composite layer structure of silicon oxide and silicon nitride material. The passivation layer is a single-layer structure made of silicon oxide and silicon nitride or a composite layer structure made of silicon oxide and silicon nitride.

4. The method for manufacturing a capacitive pressure sensor according to claim 1, characterized in that: The corrosion holes are arranged in a matrix and can be either circular or polygonal.

5. The method for manufacturing a capacitive pressure sensor according to claim 1, characterized in that: The first and second structural layers are made of polycrystalline silicon.

6. The method for manufacturing a capacitive pressure sensor according to claim 1, characterized in that: The upper electrode plate serves as the movable electrode plate of the capacitor, used to sense changes in pressure, and the thickness of the structural layer is 0.1 μm to tens of μm.

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