Inter-hierarchy metadata storage

Abstract

The invention relates to inter-hierarchy metadata storage. A controller associated with a memory system may manage metadata storage across a memory hierarchy within the memory system or across the memory system. The controller may transfer metadata between memory tiers based on whether an access count associated with the metadata satisfies a threshold. For example, if the access count satisfies a threshold count, the controller may transfer metadata from a first memory level to a second memory level. If the access count fails to meet the threshold count, the controller may transfer the metadata from the second memory level to the first memory level.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 639,716 filed by Roberts on April 18, 2024, entitled “INTER-TIER METADATA STORAGE,” and U.S. Provisional Patent Application No. 63 / 510,419 filed by Roberts on June 27, 2023, entitled “INTER-TIER METADATA STORAGE,” which are assigned to their assignees and are expressly incorporated herein by reference.

[0003] The technical field relates to inter-tier metadata storage. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells may be described according to volatile configurations or non-volatile configurations. Memory cells of non-volatile configurations may maintain a stored logic state for an extended period of time even in the absence of an external power source. Memory cells of volatile configurations may lose the stored state when disconnected from the external power source. Summary of the invention

[0006] A method is described. The method may include: using a controller associated with a memory system, accessing metadata stored in a first memory tier of the memory system based on a command to access data associated with the metadata; determining whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier; and transferring the metadata to a second memory tier of the memory system based on the number of accesses to the metadata satisfying the threshold number of accesses, wherein a first access latency associated with the first memory tier is different from a second access latency associated with the second memory tier.

[0007] An apparatus is described. The apparatus may include: a first memory tier associated with a first access latency; a second memory tier associated with a second access latency different from the first access latency; and a controller coupled to the first memory tier and the second memory tier, the controller configured to transfer metadata between the first memory tier and the second memory tier based on whether a number of accesses to the metadata satisfies a threshold number of accesses.

[0008] An apparatus is described. The apparatus may include: a controller associated with a memory system, the controller configured to cause the apparatus to: access metadata stored in a first memory tier of the memory system using the controller based on a command to access data associated with the metadata; determine whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier; and transfer the metadata to a second memory tier of the memory system based on the number of accesses to the metadata satisfying the threshold number of accesses, wherein a first access latency associated with the first memory tier is different from a second access latency associated with the second memory tier. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 An example of a system supporting inter-tier metadata storage according to examples disclosed herein is presented.

[0010] Figure 4 A block diagram of a memory system supporting inter-tier metadata storage according to examples disclosed herein is shown.

[0011] Figure 5 A flowchart illustrating a method of supporting inter-tier metadata storage according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0012] Some systems (e.g., Compute Express Link (CXL) systems, Peripheral Component Interconnect Express (PCIe), systems implementing the Gen-Z protocol, Open Coherent Accelerator Processor Interface (OpenCAPI) systems, Ethernet systems) can utilize metadata to support various operations of the system. For example, the system can utilize metadata to implement data pre-fetching, among other operations. Data pre-fetching can include learning from past data accesses of the memory system and predicting future data accesses of the memory system, and buffering (e.g., transferring, pre-fetching) the data to a low-latency memory (e.g., cache memory, volatile memory) before receiving an access request for the data, which can improve data access speed and system efficiency. Metadata can support data pre-fetching, for example, by indicating a history of one or more previous access sequences that can be replayed in advance, such as at the start of the previously observed sequence. Thus, metadata can be used to predict subsequent data accesses based on the observed sequence to support pre-fetching data based on the prediction.

[0013] In some instances, metadata may be managed and stored on-chip, such as at a host system associated with a memory system. However, in some cases, the amount of metadata may exceed the metadata storage capacity at the host system, and the host system may support off-chip metadata storage, such as storing the metadata at the memory system. In this way, the host system may access metadata from the memory system, but such access may result in a large amount of off-chip traffic and increased latency associated with communicating metadata between the memory system and the host system. Some systems may support pre-fetching metadata to a host system cache to reduce latency, but in some cases, the amount of pre-fetched metadata may exceed the cache storage available for metadata, resulting in a limited amount of metadata that can be pre-fetched to the host system cache and continuous access by the host system to the metadata at the memory system.

[0014] Additionally, storing a greater amount of metadata at the memory system may enable improved pre-fetch accuracy and longer latency hiding, for example, by enabling tracking and storage of additional access sequences. However, storing large amounts of metadata in lower latency memory may be expensive, and storing metadata in higher latency memory may increase metadata access latency, thereby reducing pre-fetch performance.

[0015] Techniques, systems, and devices are described herein for inter-tier metadata storage within a memory system to support increased metadata storage while reducing cost and metadata access latency, among other advantages. For example, a controller associated with a memory system (e.g., a controller included in the memory system, a controller coupled to the memory system, such as included in a switch for coupling the memory system with a host system) may manage metadata storage across one or more memory tiers (which may be referred to as memory tiers) within the memory system or across the memory system. For example, each memory tier may be associated with a corresponding (e.g., different) access latency and / or bandwidth (and other operating parameters), wherein a top (e.g., higher) memory tier may be characterized by lower latency and / or higher bandwidth, while a bottom (e.g., lower) tier may be characterized by higher latency and / or lower bandwidth. The controller may manage metadata such that some metadata that is relatively more frequently accessed may be stored in a higher memory tier, while metadata that is relatively less frequently accessed may be stored in a lower memory tier. Additionally or alternatively, metadata may be transferred (e.g., moved) between memory tiers as corresponding access rates (e.g., access counts, access frequencies) change. In this way, the controller may promote or demote stored metadata between tiers so that metadata associated with higher access counts may be readily available for access (e.g., accessed with reduced latency). Furthermore, by storing some metadata in lower tier, less expensive memory and transferring the metadata to higher, faster tier memory when accessed more frequently, a larger amount of metadata may be stored at a lower cost while supporting lower latency access and other advantages.

[0016] Additionally, in some instances of prefetching, the controller may access the metadata and transfer the metadata to a metadata cache contained in a memory system or a switch (e.g., if the metadata is not already stored in the metadata cache) based on a request to access data associated with the metadata. The controller may use the metadata in association with prefetching the additional data. Thus, in some instances, metadata communication may be contained between the memory hierarchy and the metadata cache, and in some cases, may not be communicated to the host system, thereby reducing latency associated with such communication. Additionally or alternatively, an adjustable hierarchy of metadata supported by the controller may reduce latency for metadata to be transferred to the metadata cache to support prefetching.

[0017] In reference Figures 1 to 3 Features of the present disclosure are described in the context of the systems and devices described herein. Figure 4 and 5 These and other features of the present disclosure are further illustrated and referenced by the device diagrams and flow diagrams associated with the described inter-tier metadata storage.

[0018] Figure 1 An example of a system 100 supporting inter-tier metadata storage according to examples disclosed herein is shown. The system 100 may include a host system 105, a memory system 110, and a plurality of channels 115 coupling the host system 105 with the memory system 110. The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system (e.g., memory system 110).

[0019] System 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory system 110 may be a component of system 100 that is operable to store data for one or more other components of system 100.

[0020] Portions of system 100 may be instances of host system 105. Host system 105 may be an instance of a processor (e.g., circuitry, processing circuitry, processing component) within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other instances. In some examples, host system 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host (e.g., host system 105).

[0021] The memory system 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by the system 100. In some examples, the memory system 110 may be configured to work with one or more different types of host devices. The signaling between the host system 105 and the memory system 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for communicating a signal, various form factors for physical packaging of the host system 105 and the memory system 110, clock signaling and synchronization between the host system 105 and the memory system 110, timing conventions, or other functions.

[0022] The memory system 110 is operable to store data for components of the host system 105. In some examples, the memory system 110 (e.g., operating as an auxiliary type device of the host system 105, operating as an independent type device of the host system 105) can respond to and execute commands provided by the host system 105 through the external memory controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0023] The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of the host system 105 may be coupled to each other using a bus 135.

[0024] The processor 125 is operable to provide functionality (e.g., control functionality) for the system 100 or the host system 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

[0025] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host system 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host system 105. BIOS component 130 may include instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0026] In some examples, system 100 or host system 105 may include various peripheral components. A peripheral component may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100 or host system 105. Examples may include one or more of a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. The peripheral component(s) may be other components that are understood by one of ordinary skill in the art to be peripherals.

[0027] In some examples, system 100 or host system 105 may include an I / O controller. The I / O controller may manage data communications between processor 125 and (several) peripheral components (e.g., input devices, output devices). The I / O controller may manage peripheral devices that are not integrated into or integrated with system 100 or host system 105. In some examples, the I / O controller may represent a physical connection (e.g., one or more ports) to an external peripheral component.

[0028] In some examples, the system 100 or the host system 105 may include an input component, an output component, or both. An input component may represent a device or signal external to the system 100 that can provide information (e.g., a signal, data) to the system 100 or its components. In some examples, an input component may include an interface (e.g., a user interface or an interface between other devices). In some examples, an input component may be a peripheral device that interfaces with the system 100 via one or more peripheral components or may be managed by an I / O controller. An output component may represent a device or signal external to the system 100 that is operable to receive an output from any of the system 100 or its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and others. In some examples, an output may be a peripheral device that interfaces with the system 100 via one or more peripheral components or may be managed by an I / O controller.

[0029] The memory system 110 may include a memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity (e.g., expected capacity, specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more storage bodies, one or more tiles, one or more sectors), each of which is operable to store one or more data bits. A memory system 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] The memory controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory system 110. The memory controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory system 110. The memory controller 155 may be operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some examples, the memory controller 155 may control the operation of the memory system 110 described herein in conjunction with a local memory controller 165 of a memory die 160.

[0031] In some examples, the memory system 110 can communicate information (e.g., data, commands, or both) with the host system 105. For example, the memory system 110 can receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory die 160 to the host system 105, among other types of information communications.

[0032] The local memory controller 165 (e.g., local to the memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the memory controller 155 (e.g., receive or transmit component data or commands or both). In some examples, the memory system 110 may not include a memory controller 155 and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components operable to support the described operations of the memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 is operable to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 100). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between components of the host system 105 and the memory system 110. In some examples, the external memory controller 120, or other components of the system 100 or the host system 105, or the functions thereof described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is described as being external to the memory system 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory system 110 (e.g., the memory controller 155, the local memory controller 165), or vice versa.

[0034] Components of the host system 105 may exchange information with the memory system 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory system 110. Each channel 115 may be an example of a transmission component medium that carries information between the host system 105 and the memory system 110. Each channel 115 may include one or more signal paths (e.g., transmission component media, conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to serve as part of a channel.

[0035] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be conveyed through the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be aligned for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be aligned for each clock cycle (e.g., on both a rising and falling edge of a clock signal).

[0036] In some examples, CA channel 186 is operable to communicate commands between host system 105 and memory system 110, the commands including control information (e.g., address information) associated with the commands. For example, a command carried by CA channel 186 may include a read command and an address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for communicating control information (e.g., commands or addresses).

[0037] In some examples, data channel 190 is operable to transfer information (e.g., data, control information) between host system 105 and memory system 110. For example, data channel 190 may transfer information to be written to memory system 110 (e.g., bidirectionally) or information to be read from memory system 110.

[0038] In some examples, metadata may be managed and stored at the host system. However, in some cases, the amount of metadata may exceed the metadata storage capacity of the host system 105, and the host system 105 may support off-chip metadata storage, such as storing the metadata at the memory system 110. As such, the host system 105 may access metadata from the memory system 110, but such access may result in a large amount of off-chip traffic and increased latency associated with communicating metadata between the memory system 110 and the host system 105. Some systems may support pre-fetching metadata to a cache of the host system 105 (e.g., to the processor 125, to the external memory controller 120) to reduce latency, but in some cases, the amount of pre-fetched metadata may exceed the cache storage available for metadata at the host system 105, resulting in a limited amount of metadata that can be pre-fetched to the cache of the host system 105 and continuous access of the metadata at the memory system 110 by the host system 105.

[0039] Additionally, storing a greater amount of metadata at the memory system 110 may enable improved prefetch accuracy and longer latency hiding, for example, by enabling tracking and storage of additional access sequences. However, storing large amounts of metadata in lower latency memory may be expensive, and storing metadata in higher latency memory may increase metadata access latency, thereby reducing prefetch performance.

[0040] Techniques, systems, and devices are described herein for inter-tier metadata storage within a memory system 110 to support increased metadata storage while reducing cost and metadata access latency, among other advantages. For example, a controller 195 associated with the memory system 110 may manage storage of metadata across memory tiers within the memory system 110 or across the memory system 110. For example, each memory tier (e.g., a different memory die 160, a different memory array 170) may be associated with a corresponding (e.g., different) access latency and / or bandwidth (and other operating parameters). The controller 195 may manage (e.g., control, facilitate) storage of metadata such that metadata that is more frequently accessed may be stored in a higher memory tier, while metadata that is relatively less frequently accessed may be stored in a lower memory tier. Additionally, metadata may be transferred (e.g., moved) between memory tiers as corresponding access rates (e.g., access counts, access frequencies) change. To support this adjustable metadata hierarchy, the controller 195 may track respective access counts (eg, respective numbers of accesses) of respective metadata and transfer metadata between memory tiers based on whether the respective access counts satisfy respective threshold access counts.

[0041] Additionally, in some instances of prefetching, the controller 195 may access the metadata and transfer the metadata to a metadata cache contained in a memory system or a switch (e.g., if the metadata is not already stored in the metadata cache) based on a request received from the host system 105 to access data associated with the metadata. The controller 195 may use the metadata in association with prefetching additional data (e.g., prefetching to the host system 105). Thus, metadata communication may be contained between the memory hierarchy and the metadata cache, and in some cases, may not be communicated to the host system 105, thereby reducing latency associated with such communication. Additionally, the adjustable hierarchical level of metadata supported by the controller 195 may reduce latency for metadata to be transferred to the metadata cache to support prefetching.

[0042] In some examples, controller 195 may be included in memory system 110, such as Figure 1 In some other examples, the controller 195 can be included in a switch, such as a switch configured to selectively couple the memory system 110 and the host system 105.

[0043] In addition to applicability in memory systems as described herein, the techniques for inter-tier metadata storage may be implemented generally to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices that support artificial intelligence applications and processes may be needed. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes, and may benefit from memory devices that are able to effectively and efficiently store relatively large amounts of data or access the stored data relatively quickly. Implementation of the techniques described herein may support artificial intelligence and / or machine learning techniques by supporting improved data pre-fetch accuracy, increased metadata storage while reducing cost and metadata access latency, and improving memory access speeds, among other advantages.

[0044] Figure 2 An example of a system 200 supporting inter-tier metadata storage according to an example disclosed herein is shown. The system 200 may include a reference Figure 1 For example, system 200 may include one or more hosts 210, which may be instances of host system 105, and may also include one or more memory systems 225 (e.g., memory modules), which may be instances of memory system 110, as described in reference to FIG. Figure 1 described.

[0045] The system 200 may also include a switch 205 and one or more switches 215. The switches 215 may be used to selectively couple the hosts 210 with the memory systems 225. For example, the switch 215-a may selectively couple the hosts 210-a and 210-b to the one or more memory systems 225, and the switch 215-b may selectively couple the hosts 210-c and 210-d to the one or more memory systems 225. In some examples, the switches 205 may facilitate (e.g., determine) coupling the hosts 210 with the memory systems 225 via the respective switches 215, such as by indicating to the respective switches 215 which host 210 is to be coupled with the respective memory systems 225. In some examples, the system 200 may exclude the switches 205, and the switches 215 may determine which memory system(s) 225 are coupled with the respective hosts 210. In some examples, switch 205 and one or more switches 215 may be respective instances of a CXL switch, a PCIe switch, a Gen-Z switch, an OpenCAPI switch, or an Ethernet switch, as well as other types of switches that support selectively coupling a host 210 (e.g., an on-chip processor) to a memory system 225 (e.g., off-chip storage).

[0046] The system 200 may include one or more memory systems 225. In some examples, each of the memory systems 225, the switch 205, or the switch 215 may include a respective controller (e.g., a pre-fetch controller) and a metadata cache. The controller may support (e.g., control, facilitate, perform) pre-fetching of data stored in each respective memory system of the memory systems 225 to one or more associated hosts 210 using metadata stored in the metadata cache. In some examples, the controller may learn from data accesses requested by the one or more hosts 210 (e.g., store metadata indicating data accesses) to predict future data accesses. Thus, before receiving a command from one of the hosts 210 to access future data, the controller may utilize metadata associated with the data to pre-fetch data associated with the future accesses to the one or more hosts 210, move data associated with the future accesses to a higher performance memory tier, or a combination thereof.

[0047] In some systems 200, metadata may be cached to the host 210, which may utilize the metadata to support prefetching. However, for a large extended system 200 (e.g., a system operable to store relatively large amounts of data), the host 210 may include insufficient storage for the controller to cache (e.g., prefetch) metadata for prefetching. That is, even if some cache capacity at the host 210 is sacrificed for metadata, metadata sufficient (e.g., desired) to support accurate prefetching may still exceed the available cache capacity of the host 210. Therefore, the controller may instead store the metadata in a larger capacity memory of the memory system 225, and access the metadata stored in the memory system 225 to cache (e.g., transfer) the metadata in the metadata cache to support prefetching by the controller. In this way, a large amount of metadata may be stored and utilized without transferring the metadata between the memory system 225 and the host 210, which may achieve improved prefetcher accuracy and system performance and longer latency hiding associated with prefetching.

[0048] Each memory system 225 may include one or more memory tiers (e.g., memory types). To support storage of large amounts of metadata, memory tiers may be utilized to partition and manage metadata placement within each memory system 225 (e.g., rather than on the host 210). For example, each memory tier may be used to store metadata or other data, and each may be characterized by latency, bandwidth, storage, cost, or a combination and characteristics thereof. For example, a memory system 225 may include one or more first tier memories 230, which may include the lowest latency and / or highest bandwidth (e.g., and highest cost) memory of the memory tier. A memory system 225 may include one or more third tier memories 240, which may be associated with the highest latency and / or lowest bandwidth (e.g., and lowest cost) memory of the memory tier. The memory system 225 may also include one or more second-tier memory 235, which may include higher latency and / or lower bandwidth (e.g., and lower cost) memory relative to the first-tier memory 230, and lower latency and / or higher bandwidth (e.g., and higher cost) memory relative to the third-tier memory 240. In some cases, the memory system 225 may include more or fewer tiers of memory than the tiers of memory 230, 235, and 240. The memory tiers of the memory system 225 may include various types of volatile memory, non-volatile memory, DRAM, NAND, or other types of memory, and may also be associated with different latencies, bandwidths, and associated costs. In some examples, each tier of the memory system 225 may be an instance of a memory die 160 or a memory array 170, as described with reference to FIG. Figure 1 discussed.

[0049] The system 200 may include one or more memory tier configurations 220. For example, the system 200 may include one or more memory tier configurations 220-a, one or more memory tier configurations 220-b, one or more memory tier configurations 220-c, or any combination thereof. The memory tier configuration 220-a may include a first tier memory 230, a second tier memory 235, and a third tier memory 240 included in separate memory systems of the memory system 225. That is, each memory system 225 in the memory tier configuration 220-a may include a single type of hierarchical memory (e.g., or some other tier memory) of the first tier memory 230, the second tier memory 235, and the third tier memory 240.

[0050] The system 200 may additionally or alternatively include a memory hierarchy configuration 220-b. The memory hierarchy configuration 220-b may include a first tier of memory 230, a second tier of memory 235, and a third tier of memory 240 distributed across memory systems 225 of the memory hierarchy configuration 220-b such that each memory system 225 may include a portion of various hierarchical memories. That is, each memory system 225 in the memory hierarchy configuration 220-b may include each type of hierarchical memory of the first tier of memory 230, the second tier of memory 235, and the third tier of memory 240.

[0051] The system 200 may additionally or alternatively include a memory hierarchy configuration 220-c. The memory hierarchy configuration 220-c may include a first tier memory 230, a second tier memory 235, and a third tier memory 240 included in various combinations across memory systems 225. That is, one or more memory systems 225 in the memory hierarchy configuration 220-c may include one of the first tier memory 230, the second tier memory 235, or the third tier memory 240 (e.g., a single type of hierarchical memory), while one or more memory systems 225 may include a combination of one or more of the first tier memory 230, the second tier memory 235, and the third tier memory 240. In other words, the memory hierarchy configuration 220-c may include a mix of the memory systems 225 included in the memory hierarchy configurations 220-a and 220-b. Each memory hierarchy configuration 220 included in the system 200 may be coupled with one or more switches 215. In some examples, memory systems 225 of different memory hierarchy configurations 220 may be coupled to each other.

[0052] In some examples, metadata may be stored in one or more of the first tier memory 230, the second tier memory 235, and the third tier memory 240 of the memory system 225 and may be managed by one or more controllers. For example, similar to how data may be stored in the hierarchical memory of the memory system 225, metadata may also be stored in the hierarchical memory of the memory system 225. In some examples, a controller of a respective memory system 225 including two or more tiers of memory may manage the stored metadata of the first tier memory 230, the second tier memory 235, the third tier memory 240, or a combination thereof. For example, the controller may rearrange previously stored metadata of the hierarchical memory so that the corresponding metadata with a higher number of accesses may be located in the first tier memory 230 (e.g., the fastest, highest bandwidth, highest cost memory), while the corresponding metadata with a lower number of accesses may be stored in the second tier memory 235 or the third tier memory 240. In some examples, the controller may be placed in one of the switches 215 or in the switch 205. In this case, the controller may manage metadata between one or more memory systems 225 of one or more memory tier configurations 220. For example, a controller located in switch 215-b may transfer metadata between memory tiers, which may include transferring metadata from one memory system 225 to another memory system 225.

[0053] Hierarchical and caching metadata (e.g., within the memory system 225) without transmitting to the host 210 may allow for the utilization of large amounts of memory that may be available in the memory system 225, which may improve pre-fetch accuracy and system performance, and enable hiding of longer latencies associated with accessing data from higher latency memories. For example, storing metadata within the memory system 225 may allow for a reduction in latency by enabling a pre-fetcher to recognize access patterns (e.g., access patterns that may have occurred many microseconds in the past). Additionally, distributing metadata across hierarchical memories may prevent the first tier memory 230 from being overloaded with metadata, which may improve performance and / or save costs of the system 200 by supporting a reduced amount of first tier memory 230. Furthermore, distributing metadata across hierarchical memories of the memory system 225 may allow for storage of large amounts of metadata, which may enable easier identification of access patterns, reduction in latency, improved pre-fetch accuracy, and other advantages.

[0054] Figure 3 An example of a system 300 supporting inter-tier metadata storage according to an example disclosed herein is shown. The system 300 may be a reference Figure 1 and 2 For example, system 300 may include one or more switches 310, which may be referenced to system 100 or system 200. Figure 2The system 300 may also include one or more memory systems 305 (eg, memory modules), which may be examples of the memory system 225 or the memory system 110, as described in reference to FIG. Figure 1 and 2 Each memory system 305 (eg, memory system 305-a, memory system 305-b, memory system 305-c) of system 300 may include one or more memory tiers 345, which may be reference tiers. Figure 1 and 2 1 , a first tier memory 230, a second tier memory 235, a third tier memory 240, or a memory die 160 is depicted. The memory system 305 may also include a controller 325, a metadata cache 330, a metadata map 335, one or more counters 355, and a memory controller 340. In some cases, the controller 325 may be an example of a prefetch controller (e.g., a prefetcher). In some examples, the data map 335 may include the counter 355. In other examples, the counter 355 may be included (e.g., maintained) elsewhere in the memory system 305. The memory system 305 may also include an interface 315, which may be an example of a CXL interface, a PCIe interface, an interface implementing the Gen-Z protocol, OpenCAPI, an Ethernet interface, or another interface.

[0055] The interface 315 may be coupled to one or more components of the associated memory system 305 and facilitate communication between the memory system 305 and devices external to the memory system 305 (e.g., switch 310, host 210). For example, an interface 315-a of a memory system 305-a may be coupled to a switch 310, a controller 325, and a memory controller 340. The interface 315-a may help facilitate the transfer of commands, data 360, and metadata 350 between the various components of the system 300. For example, the interface 315-a may help facilitate the communication of information (e.g., data 360, metadata 350) and commands between a switch 310 (e.g., controller 320 of the switch 310) and a controller 325, a memory controller 340, or both.

[0056] The memory system 305 may also include a controller 325 and a metadata cache 330. For example, the memory system 305-a may include a controller 325 that may distribute and manage metadata 350 (e.g., and data 360). Additionally, the memory system 305-a may include a metadata cache 330 that may store metadata 350 that is accessed (e.g., pre-fetched) by the controller 325. For example, the controller 325 may receive (e.g., snoop) an incoming command from the switch 310 (e.g., via the interface 315-a), and may access metadata 350 stored in the metadata cache 330 (e.g., previously pre-fetched metadata, metadata previously transferred to the metadata cache 330). Alternatively, if the metadata 350 is not contained in the metadata cache 330, the controller 325 may transfer the metadata 350 from the associated memory tier 345 to the metadata cache. The controller 325 may utilize a portion of the metadata 350 stored in the metadata cache 330 to pre-fetch future data 360 that may be requested by a host (e.g., the host 210). To pre-fetch the data 360, the controller 325 may access the data 360 associated with the stored metadata 350 via the memory controller 340 (e.g., or using a data mover component), which may help facilitate the communication of the data 360 via the interface 315-a. The controller 325 may manage the storage of the metadata 350 within the memory hierarchy 345 (e.g., via the memory controller 340 or the data mover component). For example, the controller 325 may move the metadata 350 between the memory hierarchies 345 (e.g., via the memory controller 340, via the data mover), move the corresponding metadata 350 to the metadata cache 330, or both.

[0057] If metadata 350 is moved between memory hierarchies 345, the controller 325 may update the metadata map 335 with the new location of the metadata 350 within the memory hierarchy 345. For example, the metadata map 335 may store a mapping indicating the location of the respective metadata 350 within the respective memory system 305. In some examples, the mapping may be a logical-to-physical (L2P) mapping of the respective metadata 350 and the physical location of the respective metadata 350 within the memory system 305-a (e.g., the respective memory hierarchy 345). In some examples, the metadata map 335 may be included in a reserved portion of memory within the memory system 305-a. In some examples, the metadata map 335 may be structured as a page table having multiple entries, each entry including a respective mapping of the respective metadata 350, a radix tree, a hash table, or some other structure. The controller 325 may access the metadata map 335 to support accessing the metadata 350 and transferring the metadata 350 to the metadata cache 330. For example, if the metadata cache 330 excludes (e.g., does not currently store) metadata 350 associated with the requested data 360, the controller 325 may access the metadata map 335 to determine the location of the metadata 350 (e.g., the physical address of the metadata 350 within a given memory hierarchy 345) and transfer the metadata 350 to the metadata cache 330.

[0058] In some examples, each entry of the metadata map 335 may be associated with (e.g., include) a counter 355. Each of the counters 355 may be associated with a respective metadata 350 (e.g., metadata 350-a, metadata 350-b) and may count accesses (e.g., by the controller 325, by the memory controller 340) to the associated metadata 350. For example, the counter 355-a of the metadata map 335 may count each access operation associated with the metadata 350-a (e.g., currently stored in the memory tier 345-a). In some cases, when the metadata 350-a may be located in the metadata cache 330, the counter 355-a may also count accesses to the metadata 350-a.

[0059] The controller 325 may be responsible for managing the counters 355 and their values. For example, the controller 325 may increment the value of the counter 355 each time the associated metadata 350 is accessed. In addition to incrementing the value of the counter 355 each time an access is made, the controller 325 may also decrement, reset, or divide the value of each counter 355 each time an access is made, periodically, or in response to a command from a host system or from a memory system 305-a via the switch 310.

[0060] In some examples, a prefetch policy associated with the system 300 may define a threshold number of access counts (e.g., associated with a value of the counter 355) for transferring metadata 350 between memory tiers 345. For example, there may be a first threshold number of accesses (e.g., a threshold access count) associated with moving metadata 350 between memory tier 345-a and memory tier 345-b, and a second threshold access count associated with moving metadata 350 between memory tier 345-b and memory tier 345-c, and so on. Thus, for N memory tiers 345 (e.g., within each memory system 305, across memory systems 305, such as if one or more memory systems 305 include a single memory tier 345), there may be N-1 thresholds.

[0061] Each memory system of the memory systems 305 may also include one or more memory tiers 345. For example, the memory system 305-a may include a memory tier 345-a, a memory tier 345-b, and a memory tier 345-c, which may be instances of the memory layers 230, 235, and 240, respectively. In some examples, the memory system 305 may include different configurations of the memory tiers 345 (e.g., as described in reference to FIG. 1 ). Figure 2 discussed).

[0062] The controller 325 may move metadata 350 stored in one or more memory tiers 345 between memory tiers 345. In some examples, the controller 325 may move metadata 350 stored in the memory tiers 345 between memory tiers 345 based on whether corresponding values ​​of counters 355 associated with the metadata 350 satisfy one or more threshold access counts. For example, the controller 325 may determine that the value of the counter 355-b associated with the access metadata 350-b may satisfy (e.g., meet or exceed) a threshold associated with moving metadata 350 between memory tiers 345-a and memory tiers 345-b. In response to the access count of the counter 355-b satisfying this threshold, the controller 325 may transfer the metadata 350-b from the memory tier 345-b to the memory tier 345-a (e.g., via the memory controller 340).

[0063] By promoting metadata 350-b to a memory tier 345 (e.g., memory tier 345-a) associated with higher bandwidth and / or lower latency, the controller 325 may enable easier access to frequently accessed metadata 350 (e.g., metadata 350-b), which may enable improved access speeds and system efficiency, among other advantages. In some other examples, the controller 325 may access metadata 350-a stored in memory tier 345-a, and may determine that a value of a counter 355-a associated with accessing metadata 350-a may fail to meet (e.g., be less than, less than, or equal to) a threshold associated with moving metadata 350 between memory tier 345-a and memory tier 345-b. In this manner, the controller 325 may transfer metadata 350-a from memory tier 345-a to memory tier 345-b. By relegating metadata 350-a to a memory tier (e.g., memory tier 345-b) that includes lower bandwidth and higher latency, the controller 325 can free up fast, expensive memory for storing frequently accessed metadata 350. In this way, the controller 325 can attempt to distribute metadata 350 to balance the latency of loading (e.g., transferring) metadata to the metadata cache 330 with the capacity consumed in the expensive higher tier memory.

[0064] In some examples, the controller 325 may promote or demote the metadata 350 one memory tier 345 at a time. For example, the controller 325 may not promote the metadata 350 directly between the memory tier 345-c and the memory tier 345-a. In some examples, the controller 325 may demote the metadata 350 to more than one memory tier 345 at a time. For example, if the counter 355 associated with the metadata 350 is reset, the controller 325 may demote the metadata 350 to one or more memory tiers 345 (e.g., to the lowest memory tier 345, such as the memory tier 345-c).

[0065] In some examples, the controller 325 may include or be coupled with a data mover to facilitate migration of metadata between memory tiers 345. For example, the data mover may be an instance of a standard IP block that may include one or more data copy engines. In some examples, the data copy engine of the data mover may enable concurrent copying (e.g., transfer) of data 360 or metadata 350 between memory tiers 345, between components of the memory system 305-a, between memory systems 305, between switches 310 and memory systems, or a combination thereof.

[0066] In some examples, a host system (e.g., host 210) may transmit an access command, and the controller 325 may initiate a pre-fetch strategy. For example, the host system may determine that the host system's cache may not store the desired data 360 (e.g., data 360-a), and may send an access command to the controller 325 via the interface 315-a (e.g., via the switch 310) to access the data 360-a. Based on (e.g., in response to) the access command, the controller 325 may invoke the pre-fetch strategy. That is, the controller 325 may access the metadata cache 330 to determine whether metadata 350 associated with the received command (e.g., associated with the data 360-a requested by the command) is stored in the metadata cache 330. For example, metadata 350-b may be metadata associated with data 360-a that enables the controller 325 to pre-fetch additional data (e.g., data 360-b) based on the accessed data 360-a. In the event that metadata 350-b is stored within metadata cache 330, controller 325 may utilize the stored metadata 350-b to pre-fetch additional data (e.g., data 360-b) to a cache of a host system or memory system 305-a, or transfer (e.g., promote) additional data 360 to a higher memory tier 345 (e.g., transfer data 360-b from memory tier 345-b to memory tier 345-a) so that the additional data 360 may be accessed with reduced latency. In some examples, controller 325 may also increment a counter 355 associated with metadata 350-b.

[0067] If the metadata 350 is not stored within the metadata cache 330, the controller 325 may move (e.g., pre-fetch) at least a portion of the metadata 350 to the metadata cache 330. Here, the controller 325 may access the metadata map 335. For example, in response to determining that the metadata cache 330 does not store the metadata 350-b associated with the received command, the controller 325 may access the metadata map 335 to determine the location of the metadata 350-b within the memory hierarchy 345. For example, the controller 325 may access the metadata map 335 to determine the location of the metadata 350-b in the memory hierarchy 345-b via a corresponding mapping of the metadata map 335.

[0068] The controller 325 may (e.g., via the memory controller 340) access the desired metadata 350-b using the mapping accessed in the metadata mapping 335 and transfer the metadata 350-b to the metadata cache 330. That is, the controller 325 may transmit an address associated with the accessed mapping (e.g., associated with the memory tier 345-b) to the memory controller 340, and the memory controller 340 may retrieve the metadata 350-b. The controller 325 may cache the accessed metadata 350-b in the metadata cache 330, and may increment the value of the counter 355-b associated with the metadata 350-b to reflect the access. The controller 325 may use the metadata 350-b to pre-fetch additional data 360 (e.g., data 360-b) to a cache of the host system or the memory system 305-a, or transfer (e.g., promote) the additional data 360 to a higher memory tier 345 (e.g., memory tier 345-a).

[0069] In some examples, the controller 325 may initiate promotion of the metadata 350-b based on accessing the metadata 350-b (e.g., in the memory tier 345-b, in the metadata cache 330). For example, the controller 325 may determine that the updated value of the counter 355-b satisfies a threshold access count associated with moving metadata 350 between the memory tier 345-a and the memory tier 345-b (e.g., indicated by a prefetch policy). The controller 325 may then promote (e.g., move up one tier, transfer) the metadata 350-b from the memory tier 345-b to the memory tier 345-a via the memory controller 340 or the data mover component. This promotion may enable the controller 325 to access the metadata 350-b and transfer it to the metadata cache 330 more quickly in the future relative to if the metadata 350-b remained in the memory tier 345-b.

[0070] In some examples, the controller 325 may degrade the metadata 350, for example, based on adjusting the values ​​of one or more counters 355. For example, the host system may transmit a command to the controller 325 that instructs the controller 325 to reset the corresponding values ​​of the one or more counters 355 (e.g., to zero), divide the corresponding values ​​of the one or more counters 355 (e.g., by 2 and other divisors), or decrement the corresponding values ​​of the one or more counters 355 (e.g., by 1 or a value greater than 1). In some examples, the command may indicate a range of metadata 350 (e.g., a logical address associated with the metadata 350 or data 360) for which the corresponding counter 355 is to adjust its value. Alternatively, the controller 325 may be configured to periodically reset, divide, or decrement the corresponding values ​​of the one or more counters 355. Due to the adjustment of the values ​​of the one or more counters 355, the corresponding metadata 350 may be degraded by the controller 325. For example, after adjusting the value of the counter 355-a associated with the metadata 350-a, the controller 325 may determine that the adjusted value of the counter 355-a fails to meet the threshold access count associated with moving the metadata 350 between the memory tier 345-a and the memory tier 345-b. As such, the controller 325 may demote (e.g., move down one tier, transfer) the metadata 350-a from the memory tier 345-a to the memory tier 345-b to free up the memory tier 345-a for the metadata 350 associated with the higher access count. In some examples, the controller 325 may check the value of the counter 355 for demoting in response to the adjusted value. In some examples, the controller 325 may check the value of the counter 355 after a corresponding subsequent access to the corresponding metadata 350.

[0071] In some examples, the controller 320 (e.g., prefetcher, data mover) of the switch 310 can facilitate the hierarchical level of metadata 350, such as between the memory systems 305 or within a given memory system 305. That is, the operations of the controller 325 can be implemented by the controller 320 to support the hierarchical level of metadata 350. For example, the controller 320 can move (e.g., promote, demote, transfer) metadata 350 between the memory system 305-a, the memory system 305-b, the memory system 305-c, or a combination thereof. For example, the controller 320 can receive a command (e.g., from a host system) to access data 360 stored in one of the memory systems 305. The controller 320 may access metadata 350 associated with the data 360 (e.g., located in a memory tier 345 of the memory system 305-b), and may move the metadata 350 to a memory tier 345 of the memory system 305-a, e.g., based on a threshold access count associated with transferring the metadata 350 between the memory tiers 345. The controller 320 may also support destaging of the metadata 350 between the memory tiers 345 of the respective memory systems 305, in accordance with the techniques described herein.

[0072] In some examples, the switch 310 (e.g., the controller 320) may forward addresses for other memory systems 305 to the memory system 305-a that performs the hierarchical prefetch function. For example, if the memory system 305-a supports hierarchical metadata storage, the controller 320 may transmit a command to the memory system 305-a to access the metadata 350 stored in the memory system 305-b. The controller 325 may access the metadata 350 stored in the memory system 305-b so that the metadata 350 may then be hierarchical within the memory hierarchy 345 of the memory system 305-a.

[0073] Utilizing the managed memory hierarchy 345 within one or more memory systems 305 may enable improved prefetch accuracy, more efficient use of higher latency memory, reduced overhead, and the ability to store large amounts of metadata, among other advantages.

[0074] Figure 4 A block diagram 400 is shown of a system 420 supporting inter-tier metadata storage according to an example disclosed herein. The system 420 may be a reference Figures 1 to 34. The system 420 or its various components may be examples of means for performing various aspects of inter-tier metadata storage described herein. For example, the system 420 may include an access component 425, a threshold component 430, a transmission component 435, a receiver component 440, a mapping component 445, a counter component 450, a memory component 455, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0075] The access component 425 may be configured or otherwise support means for accessing metadata stored in a first memory tier of the memory system based on a command to access data associated with the metadata using a controller associated with the memory system. The threshold component 430 may be configured or otherwise support means for determining whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier. The transfer component 435 may be configured or otherwise support means for transferring the metadata to a second memory tier of the memory system based on the number of accesses to the metadata satisfying the threshold number of accesses, wherein a first access latency associated with the first memory tier is different from a second access latency associated with the second memory tier.

[0076] In some examples, receiver component 440 may be configured or otherwise support means for receiving a command to access data. In some examples, mapping component 445 may be configured or otherwise support means for accessing a metadata map indicating a location of metadata within a memory system based on excluding metadata from a metadata cache of the memory system, wherein accessing metadata stored in a first memory tier of the memory system is based on accessing the metadata map.

[0077] In some examples, mapping component 445 may be configured or otherwise support means for updating the metadata map to indicate a second location of the metadata within the second memory tier based on transferring the metadata to the second memory tier.

[0078] In some examples, to support accessing metadata, access component 425 can be configured or otherwise support means for reading metadata to a metadata cache according to a prefetch policy associated with the controller, wherein the threshold access number is defined by the prefetch policy.

[0079] In some examples, the counter component 450 may be configured or otherwise support means for adjusting a value of a counter that tracks a number of accesses to metadata based on accessing the metadata, wherein the metadata is transferred to the second memory tier based on the value of the counter satisfying a threshold number of accesses.

[0080] In some examples, a respective counter is maintained for each entry of the metadata map that indicates a respective location of respective metadata within the memory system.

[0081] In some examples, access component 425 may be configured as or otherwise support means for accessing second metadata stored in a first memory tier of a second memory system based on a command to access second data associated with the second metadata using a controller associated with the memory system.

[0082] In some examples, threshold component 430 may be configured as or otherwise support means for determining that a second number of accesses to second metadata stored in the first memory tier fails to satisfy a second threshold number of accesses. In some examples, transfer component 435 may be configured as or otherwise support means for transferring the second metadata to a third memory tier of the memory system based on the second number of accesses to the second metadata failing to satisfy the second threshold number of accesses.

[0083] In some examples, the counter component 450 may be configured or otherwise support means for adjusting a value of a counter that tracks a number of accesses to metadata. In some examples, the transfer component 435 may be configured or otherwise support means for transferring metadata from a first memory tier to a second memory tier or a third memory tier of the memory system based on the adjusted value of the counter failing to satisfy a threshold number of accesses or a second threshold number of accesses.

[0084] In some examples, receiver component 440 can be configured or otherwise support means for receiving a second command to adjust the counter value from the host system, wherein the value of the counter is adjusted based on the second command.

[0085] In some examples, the value of the counter is periodically adjusted.

[0086] In some examples, the value of the counter is adjusted by resetting the value of the counter, dividing the value of the counter by a second value, or decrementing the counter by a third value.

[0087] In some instances, the controller is included in a switch associated with the memory system. In some instances, the controller is included in the memory system.

[0088] In some examples, the prefetch policy defines a plurality of threshold access quantities associated with transferring respective metadata between a plurality of memory tiers of the memory system. In some examples, the threshold access quantities are defined by the prefetch policy associated with transferring metadata between a first memory tier and a second memory tier.

[0089] In some examples, the second memory tier is associated with lower access latency than the first memory tier, higher bandwidth than the first memory tier, or a combination thereof.

[0090] In some examples, the first memory tier includes a first type of non-volatile memory associated with a first access latency or a first type of volatile memory associated with a second access latency. In some examples, the second memory tier includes a second type of non-volatile memory associated with a third access latency that is less than the first access latency or the second access latency, or a second type of volatile memory associated with a fourth access latency that is less than the first access latency or the second access latency.

[0091] Figure 5 A flowchart illustrating a method 500 for supporting inter-tier metadata storage according to an example disclosed herein is shown. The operations of the method 500 may be implemented by the system or components thereof described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4 The system described herein may be executed by a system (e.g., a memory system, a system including a memory system). In some examples, the system may execute a set of instructions to control the functional elements of the device to perform the described functions. In addition, or alternatively, the system may use dedicated hardware to perform aspects of the described functions.

[0092] At 505, the method may include, using a controller associated with a memory system, accessing metadata based on a command to access data associated with metadata stored in a first memory level of the memory system. Operation 505 may be performed according to examples disclosed herein. In some examples, the system may include controller 320 or 325, which may access metadata (e.g., metadata 350-b) based on a command to access data associated with metadata stored in a first memory level (e.g., memory level 345-b) of a memory system (e.g., memory system 305-a). In some examples, aspects of operation 505 may be performed as described in reference to Figure 4 The described access component 425 is executed.

[0093] At 510, the method may include determining whether the number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier. Operation 510 may be performed according to examples disclosed herein. In some examples, the memory system may include a controller 320 or 325, which may determine whether the number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier. In some examples, aspects of operation 510 may be performed as described in reference to Figure 4 The threshold component 430 described above is performed.

[0094] At 515, the method may include transferring the metadata to a second memory tier of the memory system based on a number of accesses to the metadata satisfying a threshold access number, wherein a first access latency associated with the first memory tier is different from a second access latency associated with the second memory tier. Operation 515 may be performed according to examples disclosed herein. In some examples, the memory system may include a controller 320 or 325, a data mover, a memory controller 340, or a combination thereof, which may transfer metadata (e.g., metadata 350-b) from a first memory tier (e.g., memory tier 345-b) of a memory system (e.g., memory system 305-a) to a second memory tier (e.g., memory tier 345-a) (e.g., facilitate the transfer) based on the number of accesses to the metadata satisfying a threshold access number. In some examples, aspects of operation 515 may be performed as described in reference to Figure 4 The described transfer component 435 is performed.

[0095] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0096] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: using a controller associated with a memory system, accessing metadata based on a command to access data associated with metadata stored in a first memory tier of the memory system; determining whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier; and transmitting the metadata to a second memory tier of the memory system based on the number of accesses to the metadata satisfying the threshold number of accesses, wherein a first access latency associated with the first memory tier is different from a second access latency associated with the second memory tier.

[0097] Aspect 2: A method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a command to access data and accessing a metadata map indicating a location of metadata within a memory system based on excluding metadata from a metadata cache of the memory system, wherein accessing metadata stored in a first memory level of the memory system is based on accessing the metadata map.

[0098] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: updating a metadata map based on transferring metadata to a second memory level to indicate a second location of the metadata within the second memory level.

[0099] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 2 to 3, wherein accessing metadata includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: reading metadata to a metadata cache according to a prefetch policy associated with a controller, wherein a threshold access number is defined by the prefetch policy.

[0100] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for adjusting the value of a counter that tracks the number of accesses to metadata based on accessing the metadata, wherein the metadata is transferred to a second memory level based on the value of the counter satisfying a threshold number of accesses.

[0101] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of Aspect 5, wherein a respective counter is maintained for each entry of the metadata map indicating a respective location of the respective metadata within the memory system.

[0102] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: using a controller associated with the memory system, accessing second metadata stored in a first memory level of a second memory system based on a command to access second data associated with the second metadata.

[0103] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that a second access quantity of second metadata stored in a first memory level fails to satisfy a second threshold access quantity, and based on the second access quantity of the second metadata failing to satisfy the second threshold access quantity, transmitting the second metadata to a third memory level of the memory system.

[0104] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for adjusting the value of a counter that tracks the number of accesses to metadata, and transferring metadata from a first memory level to a second memory level or a third memory level of a memory system based on the adjusted value of the counter failing to meet a threshold access number or a second threshold access number.

[0105] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to Aspect 9, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: receiving a second command to adjust the counter value from the host system, wherein the value of the counter is adjusted based on the second command.

[0106] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 9 to 10, wherein the value of the counter is adjusted periodically.

[0107] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 9 to 11, wherein the value of the counter is adjusted by resetting the value of the counter, dividing the value of the counter by a second value, or decrementing the counter by a third value.

[0108] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 1 to 12, wherein the controller is included in a switch associated with the memory system, or the controller is included in the memory system.

[0109] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 1 to 13, wherein a prefetch policy defines multiple threshold access numbers associated with transferring corresponding metadata between multiple memory levels of a memory system, and the threshold access numbers are defined by the prefetch policy associated with transferring metadata between a first memory level and a second memory level.

[0110] Aspect 15: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 1 to 14, wherein the second memory level is associated with lower access latency than the first memory level, higher bandwidth than the first memory level, or a combination thereof.

[0111] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to any of Aspects 1 to 15, wherein a first memory tier includes a first type of non-volatile memory associated with a first access delay or a first type of volatile memory associated with a second access delay, and a second memory tier includes a second type of non-volatile memory associated with a third access delay less than the first access delay or the second access delay or a second type of volatile memory associated with a fourth access delay less than the first access delay or the second access delay.

[0112] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0113] A device is described. The following provides an overview of aspects of the device as described herein:

[0114] Aspect 17: A device comprising: a first memory level associated with a first access latency; a second memory level associated with a second access latency different from the first access latency; and a controller coupled to the first memory level and the second memory level, the controller being configured to transfer metadata between the first memory level and the second memory level based on whether a number of accesses to the metadata satisfies a threshold access number.

[0115] Aspect 18: A device according to Aspect 17, further comprising: a metadata map configured to store an indication of a location of metadata within the device, wherein the controller is configured to update the indication of the metadata map to indicate a second location of the metadata within the device based on transferring metadata between the first memory level and the second memory level.

[0116] Aspect 19: An apparatus according to any one of Aspects 17 to 18, further comprising: a metadata cache coupled to a controller, wherein the controller is configured to transfer metadata to the metadata cache based on a command to access data associated with the metadata, and wherein the amount of access to the metadata is adjusted based on the command.

[0117] Aspect 20: An apparatus according to any one of Aspects 17 to 19, further comprising: one or more counters configured to track corresponding access numbers of corresponding metadata, wherein the controller is configured to transfer metadata between the first memory level and the second memory level based on whether the value of the counter configured to track the access number of the metadata satisfies a threshold access number.

[0118] Aspect 21: An apparatus according to Aspect 20, wherein the controller is configured to adjust the corresponding value of one or more of the one or more counters periodically or based on a command from a host system.

[0119] Aspect 22: An apparatus according to any one of Aspects 17 to 21, further comprising: a plurality of memory levels, comprising a first memory level and a second memory level, each memory level being associated with a corresponding access latency, a corresponding bandwidth, or a combination thereof, wherein a controller is configured to transmit corresponding metadata between corresponding memory levels based on whether a corresponding access quantity of the corresponding metadata satisfies a corresponding threshold access quantity.

[0120] Aspect 23: A device according to any one of Aspects 17 to 22, wherein the first memory level and the second memory level are included in a memory system of the device, and wherein: the controller is included in a switch associated with the memory system, or the controller is included in the memory system.

[0121] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0122] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connected, coupled) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive path between components that are in electronic communication (e.g., conductive contact, connected, coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0123] The term "coupled" (e.g., "electrically coupled") may refer to a condition that changes from an open circuit relationship between components (where signals are currently unable to be transmitted between the components (e.g., via a conductive path)) to a closed circuit relationship between the components (where signals are able to be transmitted between the components (e.g., via a conductive path). When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components through conductive paths that previously did not allow signal flow.

[0124] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0125] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0126] The switching components (e.g., transistors) discussed herein may represent field effect transistors (FETs) and may include three-terminal components including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by doped (e.g., lightly doped) semiconductor regions or channels. If the channel is n-type (e.g., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated." A transistor may be “turned off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0127] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0128] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description may apply to any of the similar components with the same first reference label, regardless of the second reference label.

[0129] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0130] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed with a processor designed to perform the functions described herein, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0131] As used herein, "or", as used in the claims, as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0132] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code in the form of instructions or data structures and any other non-transitory media that can be accessed by a computer or processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0133] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: accessing the metadata, using a controller associated with a memory system, based on a command to access data associated with the metadata stored in a first memory tier of the memory system; determining whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier; and The metadata is communicated to a second memory tier of the memory system based on the number of accesses of the metadata satisfying the threshold access number, wherein the first memory tier is associated with a first access latency different than a second access latency associated with the second memory tier.

2. The method according to claim 1, further comprising: receiving the command to access the data; and A metadata map indicating a location of the metadata within the memory system is accessed based on excluding the metadata from a metadata cache of the memory system, wherein accessing the metadata stored in the first memory tier of the memory system is based on accessing the metadata map.

3. The method according to claim 2, further comprising: The metadata map is updated based on transferring the metadata to the second memory tier to indicate a second location of the metadata within the second memory tier.

4. The method of claim 2, wherein accessing the metadata comprises: The metadata is read to the metadata cache according to a prefetch policy associated with the controller, wherein the threshold number of accesses is defined by the prefetch policy.

5. The method according to claim 1, further comprising: Based on accessing the metadata, a value of a counter that tracks the number of accesses to the metadata is adjusted, wherein based on the value of the counter satisfying the threshold number of accesses, the metadata is transferred to the second memory tier.

6. The method of claim 5, wherein a respective counter is maintained for each entry of a metadata map indicating a respective location of respective metadata within the memory system.

7. The method according to claim 1, further comprising: Using the controller associated with the memory system, second metadata stored in a first memory tier of a second memory system is accessed based on a command to access second data associated with the second metadata.

8. The method according to claim 1, further comprising: determining that a second number of accesses to second metadata stored in the first memory tier fails to satisfy a second threshold number of accesses; and Based on the second number of accesses to the second metadata failing to satisfy the second threshold number of accesses, the metadata is transferred to a third memory tier of the memory system.

9. The method according to claim 1, further comprising: adjusting a value of a counter that tracks the number of accesses to the metadata; and The metadata is transferred from the first memory tier to the second memory tier or a third memory tier of the memory system based on the adjustment value of the counter failing to satisfy the threshold access number or a second threshold access number.

10. The method of claim 9, wherein the value of the counter is adjusted by resetting the value of the counter, dividing the value of the counter by a second value, or decrementing the counter by a third value.

11. The method according to claim 1, wherein: A prefetch policy defines a plurality of threshold access quantities associated with transferring respective metadata between a plurality of memory tiers of the memory system, and The threshold number of accesses is defined by the prefetch policy associated with transferring metadata between the first memory tier and the second memory tier.

12. The method of claim 1, wherein: The first memory hierarchy includes a first type of non-volatile memory associated with a first access latency or a first type of volatile memory associated with a second access latency, and The second memory tier includes a second type of non-volatile memory associated with a third access latency less than the first access latency or the second access latency, or a second type of volatile memory associated with a fourth access latency less than the first access latency or the second access latency.

13. An apparatus comprising: a first memory hierarchy associated with a first access latency; a second memory hierarchy associated with a second access latency different than the first access latency; and A controller is coupled to the first memory tier and the second memory tier, the controller being configured to transfer metadata between the first memory tier and the second memory tier based on whether a number of accesses to the metadata satisfies a threshold number of accesses.

14. The apparatus of claim 13, further comprising: A metadata map configured to store an indication of a location of the metadata within the device, wherein the controller is configured to update the indication of the metadata map to indicate a second location of the metadata within the device based on transferring the metadata between the first memory tier and the second memory tier.

15. The apparatus of claim 13, further comprising: A metadata cache is coupled to the controller, wherein the controller is configured to transfer the metadata to the metadata cache based on a command to access data associated with the metadata, and wherein the amount of accesses of the metadata is adjusted based on the command.

16. The apparatus of claim 13, further comprising: One or more counters configured to track respective access numbers of respective metadata, wherein the controller is configured to transfer the metadata between the first memory tier and the second memory tier based on whether a value of the counter configured to track the access number of the metadata satisfies the threshold access number.

17. The apparatus of claim 16, wherein the controller is configured to adjust respective values ​​of one or more of the one or more counters periodically or based on a command from a host system.

18. The apparatus of claim 13, further comprising: a plurality of memory tiers including the first memory tier and the second memory tier, each memory tier being associated with a respective access latency, a respective bandwidth, or a combination thereof, Wherein the controller is configured to transfer respective metadata between respective memory tiers based on whether respective access quantities of the respective metadata satisfy respective threshold access quantities.

19. The apparatus of claim 13, wherein the first memory tier and the second memory tier are included in a memory system of the apparatus, and wherein: The controller is included in a switch associated with the memory system, or The controller is included in the memory system.

20. An apparatus comprising: a controller associated with the memory system, the controller being configured to cause the device to: accessing, using the controller, the metadata based on a command to access data associated with the metadata stored in a first memory tier of the memory system; determining whether a number of accesses to the metadata satisfies a threshold number of accesses based on accessing the metadata stored in the first memory tier; and The metadata is communicated to a second memory tier of the memory system based on the number of accesses of the metadata satisfying the threshold access number, wherein the first memory tier is associated with a first access latency different than a second access latency associated with the second memory tier.

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