Address management method and system of Nand flash controller
By distinguishing command types and introducing preset flags in the NAND FLASH controller, random sampling and address set maintenance strategies are adopted, the problem of insufficient flexibility in address management under the suspend function is solved, and efficient use of addresses and system performance is achieved.
Patent Information
- Application Number
- CN202411326902.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-27
AI Technical Summary
The existing NAND FLASH controllers lack flexibility in address management during the suspend function process, resulting in waste of address space and inefficient utilization, limiting the scalability and performance of the system.
By distinguishing different types of commands and introducing preset flags, random sampling and address collection maintenance strategies are adopted to ensure that the choices of write, erase and read addresses are different in the suspend state, and flexible allocation and efficient utilization of addresses are achieved.
It improves the flexibility and efficiency of address processing, enhances data consistency and security, optimizes resource utilization, and improves the scalability and maintainability of the system.
Smart Images
Figure CN119200993A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solid state hard disks, and in particular to an address management method and system for a Nand flash controller. Background Art
[0002] In SSD (Solid State Drive), the verification of NAND FLASH controller is a key process, which ensures the stability and performance of SSD. The suspend function of NAND Flash is an aspect that needs special attention in this verification process. NAND FLASH requires that during the suspend process, the address of the program or erase operation cannot be the same as the address of the read operation that is processed first. In the process of verifying the stimulus, the address must be specially processed to meet this requirement. In the existing verification scenario, the existing NAND address is divided into two parts to meet this requirement. If the suspend function is not enabled, the first part of the address will be used; if the suspend function is enabled, the address of the read operation can only be selected from the second part. Although this implementation method meets this requirement, it reduces the flexibility of verification and greatly reduces randomness.
[0003] The existing address allocation method has some potential disadvantages. It will cause a certain degree of address space waste. If the suspend operation is not very frequent, the address space allocated for the suspend operation may be idle most of the time, resulting in address space waste. Similarly, if the address space for non-suspend operations is not sufficient to meet the demand during peak hours, and the address space dedicated to the suspend operation is not fully utilized, it will also lead to inefficient use of the overall address space. The division of address space is too fixed, which may also limit the scalability of the system. Summary of the invention
[0004] The purpose of the embodiments of the present invention is to provide an address management method and system for a Nand flash controller, which are used to completely or at least partially solve the technical problems existing in the above-mentioned prior art.
[0005] In order to achieve the above object, an embodiment of the present invention provides an address management method of a Nand flash controller, comprising:
[0006] Determine the command type of the input command;
[0007] For each type of command, determine whether it contains a preset flag. If it does not contain a preset flag, take out the addresses in the address set corresponding to each type of command in order. If it contains a preset flag, select the address for each command type according to the preset address selection method corresponding to it.
[0008] Optionally, before determining the command type of the input command, the address management method of the Nand flash controller further includes:
[0009] A continuous integer range set is used as a data source, and a random sampling method is adopted to select multiple non-repeating integers from the continuous integer range set to obtain a random sample;
[0010] The random samples are sorted to generate a writable address set, a readable address set and an erasable address set, respectively, where the address consists of a block address and a wl address.
[0011] Optionally, the command type of the input command includes a write command, a read command, and an erase command;
[0012] The preset flag is characterized as a suspend flag.
[0013] Optionally, for each type of command, it is determined whether it contains a preset flag. If it does not contain the preset flag, the addresses in the address set corresponding to each type of command are sequentially taken out. If it contains the preset flag, for each command type, an address is selected according to a preset address selection method corresponding to it, including:
[0014] For a write command, if it contains a suspend flag, an address is sequentially selected from a preset set of writable addresses, marked as the address of the current write operation (wr_addr), and saved. If the write command does not contain a suspend flag, an address is sequentially selected from a preset set of writable addresses.
[0015] Optionally, for each type of command, it is determined whether it contains a preset flag. If it does not contain the preset flag, the addresses in the address set corresponding to each type of command are sequentially taken out. If it contains the preset flag, for each command type, an address is selected according to a preset address selection method corresponding to it, including:
[0016] For the erase command, if it contains a suspend flag, an address is selected sequentially from the erasable address set, marked as the address of the current erase operation (erase_addr), and saved, and the address of the erase operation is added to the end of the writable address set so that it can be reused as the target of a write operation when needed. If it does not contain a suspend flag, addresses are taken out sequentially from the erasable address set and the erase operation is performed.
[0017] Optionally, for each type of command, it is determined whether it contains a preset flag. If it does not contain the preset flag, the addresses in the address set corresponding to each type of command are sequentially taken out. If it contains the preset flag, for each command type, an address is selected according to a preset address selection method corresponding to it, including:
[0018] For a read command, if the suspend flag is included, an address is first pre-fetched as a temporary address rd_addr_tmp1 for the read operation to quickly respond to the read request. At the same time, the next address is sequentially taken from the readable address set and saved as another temporary address rd_addr_tmp2 for subsequent operations or address comparisons.
[0019] According to the last write or erase type command, take out the saved wr_addr address or erase_addr address and enter the address comparison stage;
[0020] Compare the fetched address with the current or prefetched rd_addr_tmp1 or rd_addr_tmp2 read address and select the address based on the comparison result;
[0021] If the suspend flag is not included, the addresses are read sequentially from the readable addresses and output directly.
[0022] Optionally, the fetched address is compared with the current or pre-fetched rd_addr_tmp1 or rd_addr_tmp2 read address, and the address is selected based on the comparison result, including:
[0023] If the wr_addr address or erase_addr address is the same as the current or pre-fetched rd_addr_tmp1, another temporary address rd_addr_tmp2 is selected as the actual data read address and rd_addr_tmp1 is saved;
[0024] If the wr_addr address or the erase_addr address is different from the current or pre-fetched rd_addr_tmp1, rd_addr_tmp1 is used as the read address; wherein, in preparation for the next address comparison, the value of rd_addr_tmp2 is assigned to rd_addr_tmp1, so that in subsequent operations, rd_addr_tmp1 is regarded as the latest potential read address, and rd_addr_tmp2 is used to store the next address to be compared.
[0025] On the other hand, the present invention also provides an address management system for a Nand flash controller, comprising:
[0026] A determination unit, used for determining a command type of an input command;
[0027] The selection unit is used to determine whether each type of command contains a preset flag. If it does not contain the preset flag, the address in the address set corresponding to each type of command is taken out in order. If it contains the preset flag, the address is selected for each command type according to the preset address selection method corresponding to it.
[0028] On the other hand, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned Nand flash controller address management method when executing the program.
[0029] On the other hand, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned Nand flash controller address management method.
[0030] Through the above technical solution, by distinguishing different types of commands and introducing mechanisms such as preset flags, a maintenance strategy for pre-fetched addresses and address sets is adopted to achieve the function of writing or erasing addresses that are different from read addresses when the suspend operation is turned on, and all available address ranges can be traversed to ensure the comprehensiveness and randomness of the test coverage.
[0031] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0033] Figure 1 It is a flow chart of an implementation of an address management method of a Nand flash controller provided by an embodiment of the present invention;
[0034] Figure 2 It is a flow chart of a process for generating a set of writable, readable and erasable addresses provided by an embodiment of the present invention;
[0035] Figure 3 is a flow chart of a sending address command phase provided by an embodiment of the present invention;
[0036] Figure 4 is a flow chart of an address comparison phase provided by an embodiment of the present invention;
[0037] Figure 5The invention is a schematic diagram of the structure of an address management system of a Nand flash controller provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0038] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0039] See also Figure 1 As shown, it is a flowchart of an implementation method of an address management method of a Nand flash controller provided by an embodiment of the present invention, comprising the following execution steps:
[0040] Step 100: Determine the command type of the input command.
[0041] Specifically, before executing step 100, the following steps are further executed:
[0042] S1: A continuous integer range set is used as a data source, and a random sampling method is adopted to select multiple non-repeating integers from the continuous integer range set to obtain a random sample.
[0043] S2: Sort the random samples to generate a writable address set, a readable address set and an erasable address set, respectively, where the address consists of a block address and a wl address.
[0044] In some embodiments, see Figure 2 As shown, a flow chart of the generation process of a writable, readable and erasable address set provided by an embodiment of the present invention includes: generating three sets in the preparation stage, namely a writable address set, a readable address set and an erasable address set, and the address consists of a 16-bit block address and a 16-bit wl address. The specific steps are shown in the figure below, and a continuous integer range [a, b] is clearly defined as a potential data source, where a is the starting point of the sequence and b is the end point of the sequence. This step establishes the boundary conditions for data operations. Next, an efficient random algorithm is used to unbiasedly select n non-repeating integers from the range [a, b]. This process has a high degree of randomness to ensure that the probability of each element being selected is equal. After obtaining the random sample, a sorting algorithm is used to sort the sample to generate a sequential set.
[0045] It should be noted that the command types of the input commands include a write command, a read command, and an erase command; and the preset flag is represented by a suspend flag.
[0046] In SSD (Solid State Drive), the verification of NAND FLASH controller is a key process, which ensures the stability and performance of SSD. The suspend function of NAND Flash is an aspect that needs special attention in this verification process. The suspend function mainly refers to the system or controller's ability to temporarily interrupt the programming (Program) or erasing (Erase) operation of NAND Flash in order to give priority to other higher priority operations, such as read (Read) operations. The suspend function can reduce long waiting time and improve the response speed and processing efficiency of SSD. During the verification process, it is necessary to ensure that the suspend function can achieve this purpose correctly. It is related to the performance, stability and data consistency of SSD. Through rigorous testing and evaluation, it can be ensured that the suspend function of NAND controller meets the design requirements and provide users with high-quality storage solutions.
[0047] Step 101: for each type of command, determine whether it contains a preset flag. If it does not contain the preset flag, then take out the addresses in the address set corresponding to each type of command in order. If it contains the preset flag, then for each command type, select the address according to the preset address selection method corresponding to it.
[0048] Specifically, when executing step 101, there are three situations according to the command type:
[0049] Case 1: For a write command, if it contains a suspend flag, select an address sequentially from the preset set of writable addresses, mark it as the address of the current write operation (wr_addr), and save this address. If the write command does not contain a suspend flag, select an address sequentially from the preset set of writable addresses.
[0050] When a write command contains the suspend flag, an address is sequentially selected from a preset set of writable addresses as the address of the current write operation (wr_addr), and this address is specially saved. This allows the system to suspend the current write operation at a certain point in time, and when it resumes later, it can continue the write operation from the address where it was last suspended, instead of starting from the beginning or randomly selecting an address. This is very useful for application scenarios that require precise control of the order or location of data writing. By introducing the suspend flag in the write command, the system gains greater flexibility and control. It can suspend and resume write operations as needed, which is particularly important in applications that process large amounts of data or require fine control of the data writing process. When the system encounters an error or needs to temporarily interrupt the write operation to handle other urgent tasks, the suspend flag allows the system to safely suspend the current write operation and continue from the point where it was last suspended after the problem is resolved. This helps reduce the risk of data loss or corruption and improves the overall stability and reliability of the system. In some cases, the system's write operation performance can be optimized by using the suspend flag reasonably. For example, when system resources are tight, non-urgent write operations can be temporarily suspended to free up resources for other more critical tasks. When resources become available, these write operations are resumed. For end users or developers, the suspend flag provides a more intuitive and flexible way to control the behavior of write operations. They can enable or disable the suspend function as needed to adapt to different application scenarios and requirements.
[0051] Case 2: For the erase command, if the suspend flag is contained, an address is sequentially selected from the erasable address set, marked as the address of the current erase operation (erase_addr), and saved, and the address of the erase operation is added to the end of the writable address set so that it can be reused as the target of the write operation when needed. If the suspend flag is not contained, the addresses are sequentially taken out from the erasable address set and the erase operation is performed.
[0052] When processing an erase command, the erased address is added to the end of the writable address set, realizing address reuse. This innovation not only improves the utilization of storage resources, but also reduces the performance bottleneck caused by address waste.
[0053] Case 3: For the read command, if the suspend flag is contained, an address is first pre-fetched as the temporary address rd_addr_tmp1 of the read operation, which is used to quickly respond to the read request. At the same time, the next address is taken out from the readable address set in sequence and saved as another temporary address rd_addr_tmp2 for subsequent operations or address comparisons; according to the previous write or erase type command, the saved wr_addr address or erase_addr address is taken out to enter the address comparison stage; the taken address is compared with the current or pre-fetched rd_addr_tmp1 or rd_addr_tmp2 read address, and the address is selected according to the comparison result; if the suspend flag is not contained, the address is read from the readable address in sequence and output directly.
[0054] In the read command processing, the strategy of pre-fetching addresses (rd_addr_tmp1) and sequentially fetching addresses (rd_addr_tmp2) is adopted, and combined with the subsequent address comparison mechanism, the response speed and accuracy of the read operation are improved. This innovative mechanism helps to optimize data flow control and reduce the delay caused by address allocation and comparison.
[0055] Specifically, the fetched address is compared with the current or pre-fetched rd_addr_tmp1 or rd_addr_tmp2 read address, and the address is selected according to the comparison result, including the following steps:
[0056] SA: If the wr_addr address or the erase_addr address is the same as the current or pre-fetched rd_addr_tmp1, another temporary address rd_addr_tmp2 is selected as the actual data read address and rd_addr_tmp1 is saved.
[0057] In this way, read, write, or erase operations on the same address at or almost the same time are avoided, which may cause data corruption or inconsistency. By selecting another address (rd_addr_tmp2) for reading, data integrity and consistency can be ensured. This strategy helps improve the overall stability of the system by avoiding potential data conflicts. It reduces errors and anomalies caused by data read and write conflicts, reducing the risk of system crashes or data loss. In some cases, if the system attempts to perform read, write, or erase operations on the same address at the same time, it may need to spend extra time and resources to handle these conflicts. By selecting different addresses for reading, the system can perform these operations more efficiently, thereby improving overall performance. When the system detects an address conflict, it needs to perform complex error handling logic to determine how to continue the operation safely. By avoiding address conflicts, the system can simplify the error handling process, reduce potential sources of errors, and reduce the complexity of error handling. In a multi-tasking or multi-threaded environment, the system may need to handle multiple read, write, or erase requests at the same time. By selecting different addresses for different operations, the system can better support concurrent operations, ensuring that each operation is processed promptly and correctly.
[0058] SB: If the wr_addr address or the erase_addr address is different from the current or prefetched rd_addr_tmp1, rd_addr_tmp1 is used as the read address; wherein, in preparation for the next address comparison, the value of rd_addr_tmp2 is assigned to rd_addr_tmp1 so that in subsequent operations, rd_addr_tmp1 is regarded as the latest potential read address, and rd_addr_tmp2 is used to store the next address to be compared.
[0059] By continuously assigning the value of rd_addr_tmp2 to rd_addr_tmp1, the system implements an efficient address rotation mechanism. This ensures that rd_addr_tmp1 always contains the next potential read address, while rd_addr_tmp2 is used to store the next address to be evaluated. This mechanism simplifies the complexity of address management and improves the efficiency of address updates. Since rd_addr_tmp1 and rd_addr_tmp2 are used as consecutive potential read addresses, the system can more easily avoid address conflicts. When wr_addr or erase_addr does not match rd_addr_tmp1, the system knows that rd_addr_tmp2 (i.e., the next potential read address) is also unlikely to conflict with these addresses because it is evaluated after rd_addr_tmp1. By ensuring that rd_addr_tmp1 always contains the next address to be read, the system can respond to read requests faster. When data needs to be read, the system can immediately start reading from the address pointed to by rd_addr_tmp1 without additional lookup or calculation time. Using two temporary address variables (rd_addr_tmp1 and rd_addr_tmp2) to manage the state of the read address makes the state management of the system simpler and clearer. Each variable has a clear responsibility (one for the current read and the other for the next read), which helps reduce errors and confusion.
[0060] See also Figure 3As shown, it is a flowchart of the address command sending stage provided by an embodiment of the present invention, including judging the input command, for the write command: first check whether the command has a suspend flag. If it has a suspend flag, it means that this is a write operation that needs to be suspended and retain the state. At this time, an address will be selected sequentially from the preset writable address set, marked as the address of the current write operation (wr_addr), and saved for use in subsequent address comparison or state recovery. If the write command is not configured with a suspend flag, only one address will be selected sequentially from the writable address set, but this usually does not involve special storage or comparison of the address. For the erase command: similar to the write command, first check whether the erase command has a suspend flag. If it has, an address will be selected sequentially from the erasable address set, marked as the address of the current erase operation (erase_addr), and saved. In addition, in order to maintain the flexibility and responsiveness of the address set, the system will also add this erase address to the end of the writable address set so that it can be reused as the target of the write operation when needed. If the erase command is not configured with the suspend flag, the system only takes out the addresses from the erasable address set in sequence and performs the erase operation without performing additional address storage or set update. Since the erase command does not require the wl address but only the block address, the erase operation only outputs the block address. For the read command: The processing of the read command is relatively straightforward, but address management is also required. If the suspend flag is included, the system first pre-fetches an address as a temporary address (rd_addr_tmp1) for the read operation to quickly respond to the read request. At the same time, the system also sequentially takes out the next address from the readable address set and saves it as another temporary address (rd_addr_tmp2) for subsequent operations or address comparison. This pre-fetch mechanism helps optimize read performance and reduce the delay introduced by address allocation. Next, the system needs to take out the previously saved address (wr_addr or erase_addr) according to the type of the previous command (write or erase) to enter the address comparison stage and compare the fetched address with the current or pre-fetched read address (such as rd_addr_tmp1 or rd_addr_tmp2). The result of the comparison will determine how the system selects the output address; if there is no suspend flag, the address is read directly from the readable address in sequence and output directly.
[0061] See also Figure 4As shown, a flowchart of an address comparison phase provided by an embodiment of the present invention, if wr_addr / erase_addr is the same as rd_addr_tmp1, this means that the operation (whether it is a write operation or an erase operation) matches the address previously prepared to be read. In this case, another temporary read address rd_addr_tmp2 will be selected as the actual data read address, and rd_addr_tmp1 will continue to be saved. On the contrary, if wr_addr / erase_addr is different from rd_addr_tmp1, it indicates that the current operation does not involve the data area pointed to by rd_addr_tmp1. Therefore, rd_addr_tmp1 can be safely used directly as the read address to meet possible data read requests. At the same time, in order to prepare for the next address comparison, the value of rd_addr_tmp2 will be assigned to rd_addr_tmp1. In this way, in subsequent operations, rd_addr_tmp1 represents the latest potential read address, and rd_addr_tmp2 can be used to store the next address to be compared.
[0062] The beneficial effects of this application are embodied in the following aspects:
[0063] 1. Improve the flexibility and efficiency of address processing: By distinguishing different types of commands (write, erase, read) and introducing control mechanisms such as the suspend flag, the system can handle command address operation requests more flexibly. At the same time, the maintenance strategy of pre-fetching addresses and address sets helps to reduce the time of address allocation and improve the efficiency of address processing.
[0064] 2. Enhanced data consistency and security: In write and erase commands, by saving the address of the suspend command (wr_addr or erase_addr), the system can restore the state of these addresses when needed, thereby ensuring data consistency and integrity. In addition, the strategy of adding the erase address to the end of the writable address set also helps prevent data overwriting and improve data security.
[0065] 3. Optimize resource utilization: By dynamically managing the set of writable, erasable, and readable addresses, the system can use storage resources more efficiently. For example, adding addresses to the end of the writable address set after an erase command allows these addresses to be reused as write addresses when needed, thus avoiding waste of resources.
[0066] 4. Improve system scalability and maintainability: Through modular design and clear logical flow, the solution makes the system easier to expand and maintain. For example, new command types or control flags can be easily added without major modifications to the entire system. At the same time, clear address management and comparison logic also help reduce the occurrence of errors and failures.
[0067] See also Figure 5 As shown, it is a structural diagram of an address management system of a Nand flash controller provided by an embodiment of the present invention, including:
[0068] A determination unit 50, configured to determine a command type of an input command;
[0069] The selection unit 51 is used to determine whether each type of command contains a preset flag. If it does not contain the preset flag, the address in the address set corresponding to each type of command is taken out in order. If it contains the preset flag, the address is selected for each command type according to the preset address selection method corresponding to it.
[0070] On the other hand, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the address management method of the Nand flash controller described in any one of the above embodiments are implemented.
[0071] On the other hand, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the address management method of the Nand flash controller described in any of the above embodiments are implemented.
[0072] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0073] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0074] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0075] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0076] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0077] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.
[0078] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.
[0079] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0080] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.
Claims
1. A Nand flash controller address management method, characterized in that: include: Determine the command type of the input command; For each type of command, determine whether it contains a preset flag. If it does not contain a preset flag, take out the addresses in the address set corresponding to each type of command in order. If it contains a preset flag, select the address for each command type according to the preset address selection method corresponding to it.
2. The address management method of the Nand flash controller according to claim 1, characterized in that: Before determining the command type of the input command, the address management method of the Nand flash controller further includes: A continuous integer range set is used as a data source, and a random sampling method is adopted to select multiple non-repeating integers from the continuous integer range set to obtain a random sample; The random samples are sorted to generate a writable address set, a readable address set and an erasable address set, respectively, where the address consists of a block address and a wl address.
3. The address management method of Nand flash controller according to claim 1, characterized in that: The command types of input commands include write command, read command and erase command; The preset flag is characterized as a suspend flag.
4. The address management method of Nand flash controller according to claim 3, characterized in that: For each type of command, determine whether it contains a preset flag. If it does not contain a preset flag, then take out the address in the address set corresponding to each type of command in order. If it contains a preset flag, then for each command type, select an address according to the preset address selection method corresponding to it, including: For a write command, if it contains a suspend flag, an address is sequentially selected from a preset set of writable addresses, marked as the address of the current write operation (wr_addr), and saved. If the write command does not contain a suspend flag, an address is sequentially selected from a preset set of writable addresses.
5. The address management method of Nand flash controller according to claim 3, characterized in that: For each type of command, determine whether it contains a preset flag. If it does not contain a preset flag, then take out the address in the address set corresponding to each type of command in order. If it contains a preset flag, then for each command type, select an address according to the preset address selection method corresponding to it, including: For the erase command, if it contains a suspend flag, an address is selected sequentially from the erasable address set, marked as the address of the current erase operation (erase_addr), and saved, and the address of the erase operation is added to the end of the writable address set so that it can be reused as the target of a write operation when needed. If it does not contain a suspend flag, addresses are taken out sequentially from the erasable address set and the erase operation is performed.
6. The address management method of Nand flash controller according to claim 3, characterized in that: For each type of command, determine whether it contains a preset flag. If it does not contain a preset flag, then take out the address in the address set corresponding to each type of command in order. If it contains a preset flag, then for each command type, select an address according to the preset address selection method corresponding to it, including: For a read command, if the suspend flag is included, an address is first pre-fetched as a temporary address rd_addr_tmp1 for the read operation to quickly respond to the read request. At the same time, the next address is sequentially taken from the readable address set and saved as another temporary address rd_addr_tmp2 for subsequent operations or address comparisons. According to the last write or erase type command, take out the saved wr_addr address or erase_addr address and enter the address comparison stage; Compare the fetched address with the current or prefetched rd_addr_tmp1 or rd_addr_tmp2 read address and select the address based on the comparison result; If the suspend flag is not included, the addresses are read sequentially from the readable addresses and output directly.
7. The address management method of Nand flash controller according to claim 6, characterized in that: Compare the fetched address with the current or prefetched rd_addr_tmp1 or rd_addr_tmp2 read address and select an address based on the comparison result, including: If the wr_addr address or erase_addr address is the same as the current or pre-fetched rd_addr_tmp1, another temporary address rd_addr_tmp2 is selected as the actual data read address and rd_addr_tmp1 is saved; If the wr_addr address or the erase_addr address is different from the current or pre-fetched rd_addr_tmp1, rd_addr_tmp1 is used as the read address; wherein, in preparation for the next address comparison, the value of rd_addr_tmp2 is assigned to rd_addr_tmp1, so that in subsequent operations, rd_addr_tmp1 is regarded as the latest potential read address, and rd_addr_tmp2 is used to store the next address to be compared.
8. An address management system for a Nand flash controller, characterized in that: include: A determination unit, used for determining a command type of an input command; The selection unit is used to determine whether each type of command contains a preset flag. If it does not contain the preset flag, the address in the address set corresponding to each type of command is taken out in order. If it contains the preset flag, the address is selected for each command type according to the preset address selection method corresponding to it.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the address management method of the Nand flash controller as described in any one of claims 1 to 7 are implemented.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the address management method of the Nand flash controller as described in any one of claims 1 to 7 are implemented.