Information processing method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention discloses an information processing method and device, equipment, a storage medium and a program product, and at least relates to the field of artificial intelligence. The memory access times and the system power consumption are reduced, and the parallelism degree of data processing is increased. The method comprises the following steps: acquiring first to-be-processed information comprising kernel vector information and multiple pieces of feature map vector information with adjacent time sequences; splicing the multiple pieces of feature map vector information to obtain target feature map vector information; in each clock cycle, determining an information processing result of the corresponding clock cycle based on each core element and a feature element at a target position in target feature map vector information, the target position including an element position the same as the core element and a position having a difference of K sliding step lengths from the element position of the core element, the difference between the first sliding window and the second sliding window between every two adjacent clock periods is N sliding step lengths; and determining a target processing result based on the information processing results of the at least two clock cycles.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of artificial intelligence technology, and specifically to an information processing method, apparatus, device, storage medium, and program product. Background Art

[0002] Vector processing capability is a core indicator of artificial intelligence (AI) processors. The better the vector processing capability, the higher the processing performance of the AI ​​processor. High-performance vector processing capability is mainly reflected in the following two aspects: one is the parallelism of data processing. The higher the parallelism of data processing, the faster the AI ​​processor processes data; the second is the complexity of vector instructions. Adapting different instructions can cover a wider range of application scenarios and improve data processing efficiency.

[0003] The parallelism of data processing is easily limited by the bit width of the system's data bus. In order to solve the problem of limited parallelism, the traditional solution is usually to increase the bit width of the data bus in the system so that multiple vector data can be processed in parallel. Moreover, in the process of processing each vector data channel, the vector data needs to be read from the vector memory (VWME) and written to the VMEM after the calculation is completed. However, the traditional method of increasing the parallelism of data processing by increasing the bit width of the data bus not only brings a large overhead to the implementation of the back-end chip, but also makes the layout and wiring of the back-end chip difficult; and each processing of a vector data channel requires reading and writing the vector data from the VMEM, which increases the access power consumption of the VMEM, thereby increasing the system power consumption. Summary of the invention

[0004] The embodiments of the present application provide a method, apparatus, device, storage medium and program product for information processing, which can not only reduce the number of frequent memory accesses during the processing process and reduce system power consumption, but also greatly increase the parallelism of data processing.

[0005] In the first aspect, an embodiment of the present application provides a method for information processing. The method includes: obtaining first information to be processed, the first information to be processed includes kernel vector information and multiple time-series adjacent feature graph vector information, the kernel vector information includes at least two kernel elements, and each feature graph vector information includes at least two feature elements; performing splicing processing on multiple feature graph vector information to obtain target feature graph vector information; in each clock cycle of at least two clock cycles, based on each kernel element and the feature element at the target position in the target feature graph vector information, determining the information processing result of the corresponding clock cycle, wherein the target position includes the same element position as the kernel element and the position that differs from the element position of the kernel element by K sliding steps, and the first sliding window and the second sliding window between each two adjacent clock cycles differ by N sliding steps, the first sliding window includes the kernel element, the second sliding window includes the feature element, K is a positive integer, N≥2, and N is an integer; determining the target processing result based on the information processing results of at least two clock cycles, and the target processing result is used to filter the first information to be processed.

[0006] In a second aspect, an embodiment of the present application provides an information processing device. The information processing device includes an acquisition unit and a processing unit. Exemplarily, the information processing device also includes a sending unit. The acquisition unit is used to acquire first information to be processed, the first information to be processed includes kernel vector information and multiple time-series adjacent feature map vector information, the kernel vector information includes at least two kernel elements, and each feature map vector information includes at least two feature elements. The processing unit is used to splice multiple feature map vector information to obtain target feature map vector information. The processing unit is used to determine the information processing result of the corresponding clock cycle in each clock cycle of at least two clock cycles based on each kernel element and the feature element at the target position in the target feature map vector information, wherein the target position includes the same element position as the kernel element and the position that differs from the element position of the kernel element by K sliding steps, and the first sliding window and the second sliding window between each two adjacent clock cycles differ by N sliding steps, the first sliding window includes the kernel element, and the second sliding window includes the feature element, K is a positive integer, N≥2, and N is an integer. The processing unit is used to determine a target processing result based on information processing results of at least two clock cycles, and the target processing result is used to filter the first information to be processed.

[0007] In some optional implementations, the processing unit is used to: perform at least two multiplication and addition operations on each core element in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain an information processing result of the first clock cycle. The first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of core elements and the number of clock cycles.

[0008] In some other optional implementations, the processing unit is used to: perform multiplication and addition operations on each first core element in the first sliding window in the first clock cycle, respectively, with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and perform multiplication and addition operations on the second characteristic element at the corresponding position in the third sliding window, to obtain the information processing result of the first clock cycle. Wherein, the element position of the first core element is the same as the element position of the first characteristic element, the second sliding window differs from the third sliding window by K sliding steps, the first core element is an element of at least two core elements, and the first characteristic element and the second characteristic element are both characteristic elements in the target feature graph vector information.

[0009] In some other optional embodiments, the processing unit is further used to, before obtaining the information processing result of the first clock cycle, copy each first characteristic element and each second characteristic element when performing multiplication and addition operations in the first clock cycle to obtain a characteristic element sequence; copy each first core element when performing multiplication and addition operations in the first clock cycle to obtain a core element sequence, and the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence. The processing unit is used to perform multiplication and addition operations on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the information processing result of the first clock cycle.

[0010] In other optional embodiments, the processing unit is also used to: before performing multiplication and addition operations on each first core element in the first sliding window in the first clock cycle and the second feature element at the corresponding position in the third sliding window, slide the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to K sliding steps to obtain a third sliding window; determine the second feature element from the third sliding window.

[0011] In some other optional implementations, the processing unit is further used to: perform at least two multiplication and addition operations on each core element in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle, and after obtaining the information processing result of the first clock cycle, slide the first sliding window and the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to N sliding steps, respectively, to obtain the first sliding window and the second sliding window of the second clock cycle, and the first clock cycle is adjacent to the second clock cycle; perform at least two multiplication and addition operations on each core element in the first sliding window in the second clock cycle and the feature element at the target position in the second sliding window in the second clock cycle, and obtain the information processing result of the second clock cycle. The processing unit is used to sum the information processing result in the first clock cycle and the information processing result in the second clock cycle to obtain the target processing result.

[0012] In other optional embodiments, the processing unit is used to: in a first clock cycle, perform multiplication and addition operations on each first core element in the core element sequence with the characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle; and obtain an information processing result of the first clock cycle based on the carry result and the sum result.

[0013] In some other optional implementations, the processing unit is further configured to: after obtaining the carry result and the sum result of the first clock cycle, store the carry result in the carry register, and store the sum result in the sum register.

[0014] In other optional embodiments, the processing unit is also used to: before determining the target processing result based on the information processing results of at least two clock cycles, detect the processing timing time when the corresponding information processing result is determined within the target clock cycle, the target processing cycle is the last clock cycle of the at least two clock cycles; and load the second information to be processed in parallel within the processing timing time, the second information to be processed being adjacent to the first information to be processed in timing.

[0015] In some other optional implementations, the sending unit is used to send a data read request, the data read request includes a first access address and a second access address, the first access address is the storage address of the core vector information, and the second access address is the storage address of each feature map vector information. The acquiring unit is used to receive a data response message corresponding to the data read request, the data response message includes the core vector information and a plurality of time-sequentially adjacent feature map vector information, the core vector information is acquired based on the first access address, and each feature map vector information is acquired based on the second access address.

[0016] In a third aspect, an embodiment of the present application provides an information processing device. The information processing device includes a data loading unit, a sliding window multiplication and addition unit, and a data writing unit. The data loading unit is used to obtain first information to be processed, the first information to be processed includes kernel vector information and multiple time-series adjacent feature map vector information, the kernel vector information includes at least two kernel elements, and each feature map vector information includes at least two feature elements; the multiple feature map vector information are spliced ​​to obtain target feature map vector information; the sliding window multiplication and addition unit is used to determine the information processing result corresponding to the clock cycle in each of the at least two clock cycles, based on each kernel element and the feature element at the target position in the target feature map vector information, wherein the target position includes the same element position as the kernel element and the position that differs from the element position of the kernel element by K sliding steps, and the first sliding window and the second sliding window between each two adjacent clock cycles differ by N sliding steps, the first sliding window includes the kernel element, the second sliding window includes the feature element, K is a positive integer, N≥2, and N is an integer. The data writing unit is used to determine a target processing result based on the information processing results of the at least two clock cycles, and the target processing result is used to perform filtering processing on the first information to be processed.

[0017] In some optional implementations, the sliding window multiplication and addition unit is used to perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle. The first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of the core elements and the number of cycles of the clock cycle.

[0018] In some other optional implementations, the sliding window multiplication and addition unit is used to perform multiplication and addition operations on each first core element in the first sliding window in the first clock cycle, respectively, with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and with the second characteristic element at the corresponding position in the third sliding window, to obtain the information processing result of the first clock cycle. The element position of the first core element is the same as the element position of the first characteristic element, the second sliding window differs from the third sliding window by K sliding steps, the first core element is an element of the at least two core elements, and the first characteristic element and the second characteristic element are both characteristic elements in the target feature graph vector information.

[0019] In some other optional embodiments, the information processing device further includes a broadcast unit. The broadcast unit is used to copy each of the first characteristic elements and each of the second characteristic elements when the multiplication and addition operation is performed in the first clock cycle to obtain a characteristic element sequence; copy each of the first core elements when the multiplication and addition operation is performed in the first clock cycle to obtain a core element sequence, and the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence. The sliding window multiplication and addition unit is used to perform the multiplication and addition operation on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the information processing result of the first clock cycle.

[0020] In other optional embodiments, the information processing device also includes a sliding operation unit; the sliding operation unit is used to: before performing the multiplication and addition operation on each first core element in the first sliding window in the first clock cycle and the second feature element at the corresponding position in the third sliding window, slide the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to the K sliding steps to obtain the third sliding window; determine the second feature element from the third sliding window.

[0021] In some other optional embodiments, the information processing device further includes a sliding operation unit. The sliding operation unit is used to perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle, and then slide the first sliding window and the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to the N sliding steps to obtain the first sliding window and the second sliding window of the second clock cycle, and the first clock cycle is adjacent to the second clock cycle. The sliding window multiplication and addition unit is used to perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the second clock cycle and the feature element at the target position in the second sliding window in the second clock cycle to obtain the information processing result of the second clock cycle. The data writing unit is used to sum the information processing result in the first clock cycle and the information processing result in the second clock cycle to obtain the target processing result.

[0022] In other optional embodiments, the sliding window multiplication and addition unit is used to: in the first clock cycle, perform multiplication and addition operations on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the carry result and the sum result of the first clock cycle; and obtain the information processing result of the first clock cycle based on the carry result and the sum result.

[0023] In some other optional implementations, the sliding window multiplication and addition unit is further used to: after obtaining the carry result and the sum result of the first clock cycle, store the carry result in a carry register, and store the sum result in a sum register.

[0024] In other optional embodiments, the data loading unit is also used to: before determining the target processing result based on the information processing results of the at least two clock cycles, detect the processing timing time when the corresponding information processing result is determined within the target clock cycle, and the target processing cycle is the last clock cycle of the at least two clock cycles; and load the second information to be processed in parallel within the processing timing time, and the second information to be processed is adjacent to the first information to be processed in timing.

[0025] In a fourth aspect, an embodiment of the present application provides a chip, which at least includes the information processing device mentioned in the implementation of the third aspect.

[0026] The fifth aspect of the embodiment of the present application provides an information processing device, including: a memory, an input / output (I / O) interface and a memory. The memory is used to store program instructions. The processor is used to execute the program instructions in the memory to perform the information processing method corresponding to the implementation method of the first aspect above.

[0027] A sixth aspect of an embodiment of the present application provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer is enabled to execute a method corresponding to the implementation method of the first aspect above.

[0028] The seventh aspect of the embodiments of the present application provides a computer program product comprising instructions, which, when executed on a computer or a processor, enables the computer or the processor to execute the method corresponding to the implementation method of the first aspect.

[0029] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0030] In an embodiment of the present application, since the first information to be processed includes core vector information and multiple time-series adjacent feature graph vector information, after obtaining the first information to be processed, multiple feature graph vector information is spliced ​​to obtain target feature graph vector information. The vector information mentioned includes at least two core elements, and each feature graph vector information includes at least two feature elements. Subsequently, in each clock cycle of at least two clock cycles, the information processing result of the corresponding clock cycle is determined based on each core element and the feature element at the target position in the target feature graph vector information. It should be understood that the target position mentioned includes the same element position as the core element, and the position that differs from the element position of the core element by K sliding steps. In addition, the first sliding window and the second sliding window between every two adjacent clock cycles differ by N sliding steps, the first sliding window includes the core element mentioned above, and the second sliding window includes the feature element mentioned above. In this way, the target processing result is determined based on the information processing results within at least two clock cycles, and the target processing result is used to filter the first information to be processed. Through the above-mentioned method, for the core vector information and multiple time-series adjacent feature map vector information, in the process of information processing, it is possible to slide with N sliding steps between every two adjacent clock cycles, so as to achieve the effect of multiplexing the core vector information and multiple time-series adjacent feature map vector information, reduce the number of frequent memory accesses during the processing process, and reduce system power consumption. In addition, in the process of determining the information processing result of each clock cycle, not only is it considered to perform multiplication and addition operations based on each core element and the characteristic element in the target feature map vector information at the same element position, but it is also considered to perform multiplication and addition operations based on the characteristic element at the element position where each core element differs from the core element by K sliding steps to determine the information processing result of the corresponding clock cycle. In other words, the present application can consider performing multiple multiplication and addition operations on the elements in the core vector information and the feature map vector information in the same clock cycle from the perspective of the sliding step, thereby greatly increasing the parallelism of data processing and reducing the overhead required in subsequent chip development and layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the structure of data processing in a traditional solution is shown;

[0033] Figure 2A schematic diagram of a processing framework for information processing provided by an embodiment of the present application is shown;

[0034] Figure 3 A flow chart showing the information processing method provided by an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the processing flow of the multiplication and addition operation provided in an embodiment of the present application is shown;

[0036] Figure 5 Another processing flow diagram of the multiplication and addition operation provided by an embodiment of the present application is shown;

[0037] Figure 6 A schematic diagram showing the operating timing of information processing provided by an embodiment of the present application;

[0038] Figure 7 A schematic diagram of an embodiment of an information processing device provided in an embodiment of the present application is shown;

[0039] Figure 8 A schematic diagram of the hardware structure of an information processing device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The embodiments of the present application provide a method, apparatus, device, storage medium and program product for information processing, which can not only reduce the number of frequent memory accesses during the processing process and reduce system power consumption, but also greatly increase the parallelism of data processing.

[0041] It is understandable that in the specific implementation of this application, related data such as user information is involved. When the above embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the implementation of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] With the research and progress of artificial intelligence (AI) technology, AI technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, driverless cars, autonomous driving, drones, robots, smart medical care, smart customer service, etc. It is believed that with the development of technology, AI technology will be applied in more fields and play an increasingly important role.

[0045] Artificial intelligence is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making. Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level technology and software-level technology. The basic technology of artificial intelligence generally includes technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, and mechatronics. Artificial intelligence software technology mainly includes computer vision technology, speech technology, natural language processing technology, and machine learning / deep learning. Vector processing capability is the core indicator of AI processors. The better the vector processing capability, the higher the processing performance of the AI ​​processor. High-performance vector processing capability mainly includes the parallelism of data processing. However, the bit width of the system's data bus easily limits the parallelism of data processing.

[0046] In order to solve the parallelism problem, the traditional solution is usually to increase the bit width of the data bus in the system so that multi-channel vector data can be processed in parallel. Figure 1 FIG. 1 shows a schematic diagram of the structure of data processing in a traditional solution. Figure 1 As shown in the figure, assuming that the bus width of the system is 512 bits, each function unit (FU) can process 16 bits of data. At this time, up to 32 function units (such as FU0 to FU31) can be deployed to realize parallel processing of data. If you want to continue to increase the parallel processing of data, you can only increase the bus width to facilitate the deployment of more function units to complete the parallel processing of data. However, this method is easy to bring large overhead to the implementation of the back-end chip and cause difficulties in the layout and wiring of the back-end chip.

[0047] In addition, from Figure 1 It can also be seen that in the process of each FU processing vector data, each FU needs to read the vector data from VMEM, and after the calculation is completed, the output results of these 32 FUs are spliced ​​and written into VMEM. However, in the process of processing vector data, each FU needs to read and write vector data from VMEM, which easily increases the access power consumption of VMEM, thereby increasing the system power consumption.

[0048] Therefore, in order to solve the above-mentioned technical problems, an information processing method is provided in the embodiments of the present application. The information processing method can be applied to scenarios such as data parallel processing in the AI ​​field, and the specific application scenarios are not limited in the embodiments of the present application. For example, Figure 2 A schematic diagram of a processing framework for information processing provided by an embodiment of the present application is shown. Figure 2 As shown, at least a system bus and an information processing device are included. Among them, the information processing device at least includes a data loading unit (load unit, LDU), a sliding window multiplication and addition unit, a sliding window operation unit, a broadcast unit, and a data writing unit (store unit, STU. For example, taking the bus width of 512 bits as an example, at least 32 sliding window multiplication and addition units may be included in the embodiment of the present application, such as sliding window multiplication and addition unit [0] to sliding window multiplication and addition unit

[31] , etc., which are not limited in the specific embodiment of the present application. In some examples, the information processing device may also include a read control unit (load unit control, LDU_CTRL), a register, etc.

[0049] like Figure 2As shown, in the process where the information processing device needs to process data in parallel, the first information to be processed can be obtained from the system bus by the data loading unit in the form of a data read request. The first information to be processed includes kernel (kernel, KN) vector information and multiple time-series adjacent feature map (featuremap, FM) vector information. Exemplarily, the data loading unit sends a data read request to the system bus. After the system bus obtains the data read request, it feeds back the kernel vector information and the feature map vector information to the data loading unit by feeding back a data response message. In this way, after receiving the data response message fed back by the system bus, the data loading unit can obtain the kernel vector information and also obtain multiple time-series adjacent feature map vector information. For example, multiple time-series adjacent feature map vector information includes but is not limited to FM0, FM1, FM2, etc. As an exemplary description, FM0 can be adjacent to FM1 in time sequence, and FM1 can also be adjacent to FM2 in time sequence, which is not limited in the specific embodiments of the present application.

[0050] In addition, after splicing multiple feature map vector information, the target feature map vector information is obtained. In each clock cycle, the sliding window multiplication and addition unit determines the information processing result of the corresponding clock cycle based on each core element and the feature element at the target position in the target feature map vector information. In this way, the target processing result is determined by the data writing unit based on the information processing results of at least two clock cycles, thereby realizing filtering and other processing on the first information to be processed.

[0051] like Figure 2 As shown, taking any two adjacent clock cycles as an example, after obtaining the core vector information and multiple time-series adjacent feature map vector information through the data loading unit, in the first clock cycle, the second sliding window in the first clock cycle can be firstly slid according to K sliding steps by the sliding operation unit to determine the third sliding window in the first clock cycle. The first sliding window mentioned is used to limit the core elements when performing multiplication and addition operations. The second sliding window and the third sliding window mentioned are both used to limit the feature elements when performing multiplication and addition operations, and the difference is that the second sliding window and the third sliding window differ by K sliding steps. In this way, the core elements in the first sliding window are copied through the broadcast unit; similarly, the feature elements in the second sliding window and the third sliding window are copied based on the broadcast unit. After copying the core elements and the feature elements, the sliding window multiplication and addition unit [0] is used to perform at least two multiplication and addition operations on each core element and the feature element at the target position to determine the information processing result of the first clock cycle.

[0052] In this way, after obtaining the information processing result of the first clock cycle, the first sliding window and the second sliding window of the first clock cycle are slid according to N (N≥2, and N is an integer) sliding steps by the sliding operation unit, so as to determine the first sliding window and the second sliding window of the second clock cycle adjacent to the first clock cycle. In this way, the information processing result of the second clock cycle is determined by the sliding operation unit based on the same multiplication and addition operation mode in the first clock cycle. So as to determine the target processing result based on the information processing result of the first clock cycle and the information processing result of the second clock cycle.

[0053] As an exemplary description, Figure 2 As shown, for a bus width of 512 bits, 32 sliding window multiplication and addition units (e.g., sliding window multiplication and addition unit [0] to sliding window multiplication and addition unit

[31] ) can be used for processing, so that each sliding window multiplication and addition unit can complete at least two groups of multiplication and addition operations. For example, in the sliding window multiplication and addition unit [0], a carry save adder (CAS) can be used to process the partial product generated when performing multiplication operations between elements to obtain a carry result and a sum result, and then 4 data are input through 4-2CAS for carry save addition to output two data, and then the adder (adder) is used to complete the addition operation between the carry result and the sum result to obtain the final result. In the above manner, at least two groups of multiplication and addition operations are completed in the same sliding window multiplication and addition unit, so that the parallelism of data processing is 64. Compared with the traditional parallel processing scheme, the scheme provided by the present application greatly improves the parallel processing efficiency on the basis of the unchanged bus width.

[0054] It should be noted that the target position mentioned above includes the element position that is the same as the core element, and the position that differs from the element position of the core element by K sliding steps, where K is a positive integer. Figure 2 The process of how to perform multiplication and addition operations is described in the following section. Figure 4 Please understand the contents shown in the figure, and will not go into details here.

[0055] In some examples, after obtaining the kernel vector information and the feature vector information, the kernel vector information and the feature vector information may also be stored in corresponding registers. Figure 2 The registers mentioned in the description may include a feature map register and a core data register, which are mainly used to cache the acquired feature map vector data and core vector data. The described read control unit is mainly used to control the sending timing of the overall data read request, as well as the opening timing of the feature map register and the core data register.

[0056] In addition, the information processing devices mentioned include but are not limited to terminal devices, servers, question-answering robots, etc. Among them, terminal devices may include but are not limited to smart phones, desktop computers, laptops, tablet computers, smart speakers, vehicle-mounted devices, smart watches, wearable smart devices, intelligent voice interaction devices, smart home appliances, aircraft, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks (context delivery networks, CDN), and big data and artificial intelligence platforms and other basic cloud computing services, etc. This application does not make specific restrictions.

[0057] A method for information processing provided by an embodiment of the present application is introduced below with reference to the accompanying drawings. Figure 3 A flow chart of the information processing method provided by the embodiment of the present application is shown. Figure 3 As shown, the information processing method may include the following steps:

[0058] 301. Obtain first information to be processed, where the first information to be processed includes kernel vector information and multiple time-series adjacent feature graph vector information, where the kernel vector information includes at least two kernel elements, and each feature graph vector information includes at least two feature elements.

[0059] In this example, the first information to be processed mentioned includes kernel vector information and multiple time-series adjacent feature map vector information. Figure 2The data reading unit mentioned in the first sends a data reading request to the system bus. The data reading request carries a first access address and a second access address, the first access address is the storage address of the core vector information, and the second access address is the storage address of the feature map vector information. That is to say, the storage location of the core vector information can be known through the first access address, and the storage location of each feature map vector information can be known through the second access address. In this way, after the system bus obtains the data reading request, it can forward the data reading request to the corresponding cache unit according to the first access address and the second access address after demapping the data reading request to obtain the first access address and the second access address. At this time, the memory such as VEME can read the relevant core vector information according to the first access address, and read the relevant feature map vector information according to the second access address. Subsequently, the memory maps the core vector information and multiple feature map vector information into a data response message, and then feeds back the data response message to the information processing device through the data reading unit, so that the information processing device obtains the data response message, thereby demapping and obtaining the core vector information and multiple time-series adjacent feature map vector information.

[0060] The kernel vector information can be understood as the vector parameters of the convolution kernel. In the kernel vector information, at least two kernel elements are included, and each kernel element can reflect the weight of the corresponding convolution kernel. For example, assuming that the kernel vector information includes 6 valid parameters and is represented by a one-dimensional vector, the kernel vector information can be expressed as KN=[0,1,2,3,4,5,...], etc., which is not limited in the specific embodiments of this application.

[0061] In addition, multiple time-adjacent feature map vector information can be understood as being adjacent in the acquisition timing of the corresponding feature map vector information. Each feature map vector information includes at least two feature elements. For example, multiple time-adjacent feature map vector information may include time-adjacent feature maps (feature map, FM) 0 and FM1, etc., which are not limited in the specific embodiments of the present application. Taking FM0 and FM1 as examples, FM0 can be represented by a one-dimensional vector, such as FM0 = [0, 1, 2, 3, 4, 5, 6, 7], FM1 = [0, 1, 2, 3, 4, 5, 6, 7], etc., which are not limited in the specific embodiments of the present application.

[0062] It should be noted that the above-described kernel vector information KN is [0, 1, 2, 3, 4, 5, ...], FM0 is [0, 1, 2, 3, 4, 5, 6, 7], and FM1 is [0, 1, 2, 3, 4, 5, 6, 7], which is only an exemplary description. In practical applications, vectors of other dimensions can also be used for representation, which is not limited in the specific embodiments of the present application.

[0063] 302. Concatenate multiple feature map vector information to obtain target feature map vector information.

[0064] In this example, after obtaining multiple time-series adjacent feature graph vector information, the multiple feature graph vector information can also be spliced ​​to obtain the target feature graph vector information. Figure 2 The data loading unit shown splices the feature graph vector information with a later timing sequence onto the tail of the feature graph vector information with a previous timing sequence, etc., which is not specifically limited in the embodiments of the present application.

[0065] For example, taking FM0 and FM1 as multiple temporally adjacent feature map vector information, if FM0 = [0, 1, 2, 3, 4, 5, 6, 7], FM1 = [0, 1, 2, 3, 4, 5, 6, 7], FM1 can be concatenated at the end of FM0 to obtain the corresponding target feature map vector information. For example, the target feature map vector information can be expressed as FM = {0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7}.

[0066] It should be noted that the multiple time-series adjacent feature graph vector information mentioned above is only illustrated by taking FM0 and FM1 as examples. In practical applications, other feature graph vector information may also be included, such as FM2, FM3, etc., which is not limited in the embodiments of the present application. In addition, the target feature graph vector information FM mentioned above is {0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7}, which is only a schematic illustration. In practical applications, it can also be obtained by splicing other feature graph vector information, which is not limited in the present application.

[0067] 302. In each clock cycle of at least two clock cycles, based on each core element and the characteristic element at the target position in the target feature map vector information, determine the information processing result of the corresponding clock cycle, wherein the target position includes the same element position as the core element and the position that differs from the element position of the core element by K sliding steps, and the first sliding window and the second sliding window between every two adjacent clock cycles differ by N sliding steps, the first sliding window includes the core element, and the second sliding window includes the characteristic element, K is a positive integer, N ≥ 2, and N is an integer.

[0068] In this example, for the same batch of core vector information and feature map vector information, elements at different positions can be processed in different clock cycles. That is, for each clock cycle, the information processing result of the corresponding clock cycle can be determined based on each core element and the feature element at the target position in the target feature map vector information.

[0069] The target position mentioned includes both the element position that is the same as the core element and the position that is K sliding steps away from the element position of the core element. In other words, for the processing process within each clock cycle, the core vector information and the feature map vector information can be reused by sliding processing, so that the core vector information and the feature map vector information can be processed in parallel at least twice within the same clock cycle.

[0070] In addition, the first sliding window and the second sliding window between every two adjacent clock cycles differ by N sliding steps. The first sliding window can limit the core elements when performing the multiplication and addition operation, and the second sliding window is used to limit the characteristic elements when performing the multiplication and addition operation. That is to say, it is understood that in the first clock cycle, each core element in the first sliding window in the first clock cycle and the characteristic element at the target position in the second sliding window in the first clock cycle are multiplied and added. After obtaining the information processing result of the first clock cycle, the first sliding window and the second sliding window of the first clock cycle are both slid according to N (N≥2, and N is an integer) sliding steps, so as to determine the first sliding window and the second sliding window of the adjacent second clock cycle. In this way, in the second clock cycle, the multiplication and addition operation between the core element and the characteristic element in the second clock cycle is implemented based on the same processing method, thereby determining the information processing result of the second clock cycle.

[0071] Regarding how to determine the processing process of the information processing results of all clock cycles, the first clock cycle and the second clock cycle are used as examples in the embodiment of the present application for explanation. It should be understood that the first clock cycle and the second clock cycle are two adjacent clock cycles. The processing process of the information processing results of the first clock cycle can be specifically understood by referring to the following method, namely:

[0072] In the first clock cycle, at least two multiplication and addition operations are performed on each core element in the first sliding window in the first clock cycle and the characteristic element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle. As an illustrative description, in the process of performing at least two multiplication and addition operations, taking at least two multiplication and addition operations as an example, each first core element in the first sliding window in the first clock cycle can be respectively multiplied and added with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and multiplied and added with the second characteristic element at the corresponding position in the third sliding window, so as to obtain the information processing result of the first clock cycle.

[0073] In this example, the first clock cycle is any one of at least two clock cycles. The size of the first sliding window can be obtained based on the number of core elements and the number of clock cycles. For example, if the number of core elements in the core vector information is 6, and the first information to be processed needs to be processed through 3 clock cycles, then the size of the first sliding window can be determined to be 2 core elements. That is to say, it is understood that in each clock cycle, 2 core elements can be processed in parallel.

[0074] In addition, the size of the second sliding window is the same as the vector dimension of the feature map vector information. The third sliding window differs from the second sliding window by K sliding steps. In addition, the multiplication and addition operation mentioned can be understood as performing a product process on the elements at the corresponding positions and then performing an accumulation process. The first core element described is an element of at least two core elements, and the first characteristic element and the second characteristic element are characteristic elements in the target feature map vector information. In addition, the element position of the first core element needs to be the same as the element position of the first characteristic element to ensure that point-to-point product processing is achieved during the multiplication and addition operation.

[0075] In addition, the third sliding window differs from the second sliding window by K sliding steps. That is, the element position of the second characteristic element in the third sliding window differs from the element position of the first core element in the first sliding window by K sliding steps. As an exemplary description, before performing the multiplication and addition operation on each first core element in the first sliding window and the second characteristic element at the corresponding position in the third sliding window, the following method can be used: Figure 2 The sliding operation unit described in the slide operation unit slides the first sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector according to K sliding steps to determine the third sliding window. Subsequently, the second feature element can be determined and obtained through the third sliding window. In this way, after completing the multiplication and addition operation between the first core element in the first sliding window and the first feature element in the second sliding window in the same clock cycle, the second sliding window is slid according to K sliding steps to complete the multiplication and addition operation between the second feature element in the third sliding window and the first core element in the first sliding window in parallel.

[0076] In some other optional examples, after determining the information processing result of the first clock cycle, the information processing result of the second clock cycle adjacent to the first clock cycle may also be determined. Figure 2The sliding operation unit described in the embodiment slides the first sliding window and the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to N sliding steps, so as to obtain the first sliding window and the second sliding window of the second clock cycle. Then, at least two multiplication and addition operations are performed on each core element in the first sliding window in the second clock cycle and the feature element at the target position in the second sliding window in the second clock cycle to obtain the information processing result of the second clock cycle.

[0077] It should be noted that in the second clock cycle, the process of performing at least two multiplication and addition operations on each core element in the first sliding window and the characteristic element at the target position in the second sliding window in the second clock cycle can be specifically understood with reference to the multiplication and addition operations in the aforementioned first clock cycle, and will not be elaborated here.

[0078] For example, taking the target feature map vector information FM = {0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7} constructed by the kernel vector information KN = [0,1,2,3,4,5,6,7] and the feature map vector information FM0 = [0,1,2,3,4,5,6,7] and FM1 = [0,1,2,3,4,5,6,7], Figure 4 A schematic diagram of the processing flow of the multiplication and addition operation provided in an embodiment of the present application is shown.

[0079] like Figure 4 As shown, a schematic process of a multiplication and addition operation of three clock cycles is shown. For the first clock cycle, the size of the first sliding window is 6 / 3=2 elements, specifically including the first kernel elements KN[0] and KN[1].

[0080] In addition, the size of the second sliding window in the first clock cycle can be the vector dimension of FM0 (i.e., 8), and can specifically include the first feature elements FM0[0] to FM0[7]. At this time, the multiplication and addition operations between KN[0], KN[1] and the target feature map vector information FM are completed in the first clock cycle. For example, the first core element in the first sliding window is multiplied and added with the first feature element in the second sliding window, such as KN[0]×FM0[0]+KN[1]×FM0[1].

[0081] Then, taking the sliding step K=1 as an example, after the second sliding window is slid according to K=1, the obtained third sliding window may include feature elements FM0[1] to FM0[7], and FM1[0]. At this time, the first core element in the first sliding window and the second feature element in the third sliding window may be multiplied and added, for example, KN[0]×FM0[1]+KN[1]×FM0[2]. Similarly, as the second sliding window continuously moves according to the sliding step K, the multiplication and addition operation between the first core elements KN[0] and KN[1] in the first sliding window and the target feature map vector information FM is completed in the first clock cycle, thereby obtaining the information processing result of the first clock cycle.

[0082] In addition, from Figure 4 It can be seen that after the processing flow of the multiplication and addition operation in the first clock cycle is completed, the first sliding window and the second sliding window in the first clock cycle are also slid according to N sliding steps, so as to obtain the first sliding window and the second sliding window of the second clock cycle. For example, the first sliding window of the second clock cycle includes the first core elements KN[2] and KN[3], and the second sliding window of the second clock cycle may include the first characteristic elements FM0[2] to FM0[7], and FM1[0] to FM1[1]. Similarly, for the second sliding window in the second clock cycle, it is also slid according to K (for example, K=1) sliding steps, so that the third sliding window in the second clock cycle can be obtained, for example, including the second characteristic elements FM0[3] to FM0[7], and FM1[0] to FM1[2]. Subsequently, according to the multiplication and addition operations performed in the above-mentioned first clock cycle, at least two multiplication and addition operations are performed on each core element in the first sliding window in the second clock cycle and the characteristic element at the target position in the second sliding window in the second clock cycle to obtain the information processing result of the second clock cycle, which is not limited to the specific embodiments of the present application.

[0083] In addition, for Figure 4 The multiplication and addition operation in the third clock cycle shown in the figure can be specifically understood by referring to the processing flow of the multiplication and addition operation in the first clock cycle and the second clock cycle mentioned above, and will not be described in detail here.

[0084] In some other optional examples, the specific process of performing the multiplication and addition operation in each clock cycle, taking the first clock cycle as an example, can also be understood in the following manner, that is:

[0085] Before performing multiplication and addition operations on the core element and the characteristic element based on the sliding window multiplication and addition unit to obtain the information processing content of the first clock cycle, first perform the following steps: Figure 2The broadcast unit shown in the figure copies each first characteristic element and each second characteristic element when performing multiplication and addition operations in the first clock cycle to obtain a characteristic element sequence. Similarly, each first core element when performing multiplication and addition operations in the first clock cycle is also copied by the broadcast unit to obtain a core element sequence. The number of first core elements in the core element sequence mentioned is the same as the number of characteristic elements in the characteristic element sequence. Finally, in the process of determining the information processing result of the first clock cycle, it can be obtained by Figure 2 The sliding window multiplication-addition unit shown performs a multiplication-addition operation on each first core element in the core element sequence and a characteristic element in the characteristic element sequence at the same position to obtain an information processing result of the first clock cycle.

[0086] For example, Figure 5 Another processing flow diagram of the multiplication and addition operation provided by the embodiment of the present application is shown. Figure 5 As shown, for Figure 4 The first core elements involved in performing multiplication and addition operations in the first clock cycle described in the main include KN[0] and KN[1]; the first characteristic elements mainly include FM0[0] to FM[7]; the second characteristic elements mainly include FM0[1] to FM[7], and FM1[0].

[0087] At this time, the first characteristic element and the second characteristic element when performing the multiplication and addition operation are copied to obtain a characteristic element sequence, for example, A1 = {FM0[0], FM0[1], FM0[1], FM0[2], FM0[2], FM0[3], FM0[3], FM0[4], FM0[4], FM0[5], FM0[5], FM0[6], FM0[6], FM0[7], FM0[7], FM1[0]} = {0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,0}. Similarly, the first kernel element when performing the multiplication and addition operation is copied, and the kernel element sequence obtained is B1 = {KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1], KN[0], KN[1]} = {0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1}. At this time, we only need to perform point-to-point multiplication and addition operations on the first core element and the characteristic element at the same position to obtain the information processing result within the first clock cycle, that is, R1=A1×B1=KN[0]×FM0[0]+KN[1]×FM0[1]+....+KN[0]×FM0[7]+KN[1]×FM1[0].

[0088] It should be noted that the specific process of the multiplication and addition operations performed in other clock cycles such as the second clock cycle and the third clock cycle can also be understood by referring to the specific execution process of the first clock cycle, and will not be repeated here.

[0089] In some other optional examples, in the first clock cycle, each first core element in the core element sequence is multiplied and added with the characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle. Then, the carry result and the sum result are summed to obtain the information processing result of the first clock cycle. Exemplarily, after obtaining the carry result and the sum result, the carry result can also be stored in a carry register, and the sum result can also be stored in a sum register. The described carry register, sum register, etc. may specifically include but are not limited to a shift register, a general register, a special register, or a control register, etc., which are not limited in the specific embodiments of the present application.

[0090] 304. Determine a target processing result based on the information processing results of at least two clock cycles, where the target processing result is used to perform filtering processing on the first information to be processed.

[0091] Since the final target information processing result is integrated from the information processing results of multiple clock cycles, after calculating the information processing result of the first clock cycle, it is also necessary to calculate the information processing results of the remaining clock cycles. Exemplarily, the processing process of the information processing results of other clock cycles can also be understood by referring to the process of the information processing results of the first clock cycle. In this way, after calculating the information processing results of each clock cycle of at least two clock cycles, the target processing result can be determined based on the information processing results of each clock cycle. For example, by Figure 2 The data writing unit shown performs summation processing on the information processing results of the at least two clock cycles to calculate and obtain the target processing result.

[0092] It should be noted that the above description is only based on the first clock cycle and the second clock cycle. In practical applications, the number of clock cycles can be determined based on the number of core elements, as long as the number of core elements in each clock cycle is not less than 2. Specifically, only 2 are used as an example for description in the embodiment of the present application.

[0093] In some other optional examples, before executing the above step 304, the processing timing time when the corresponding information processing result is determined within the target clock cycle can also be detected. The target processing cycle mentioned is the last clock cycle of at least two clock cycles. In this way, after the processing timing time is detected, the second information to be processed is loaded in parallel within the processing timing time. It should be noted that the second information to be processed is adjacent to the first information to be processed in terms of timing.

[0094] For example, Figure 6 A schematic diagram showing the operating timing of information processing provided by an embodiment of the present application is shown. Figure 6 As shown, taking the first information to be processed and the adjacent second information to be processed as an example, after completing the above steps 301 to 303 on the first information to be processed and determining the information processing result of each clock cycle, the following can be performed: Figure 2 The data loading unit shown loads the second information to be processed in parallel in the last clock cycle, that is, loads the next batch of core vector information and multiple feature map vector information adjacent in time sequence in parallel, and then performs the same processing operation as the first information to be processed. Through the above method, full load operation can be achieved under the control of precise information operation timing, thereby improving processing performance.

[0095] Through the above-mentioned method, for the core vector information and multiple time-series adjacent feature map vector information, in the process of information processing, it is possible to slide with N sliding steps between every two adjacent clock cycles, so as to achieve the effect of multiplexing the core vector information and multiple time-series adjacent feature map vector information, reduce the number of frequent memory accesses during the processing process, and reduce system power consumption. In addition, in the process of determining the information processing result of each clock cycle, not only is it considered to perform multiplication and addition operations based on each core element and the characteristic element in the target feature map vector information at the same element position, but it is also considered to perform multiplication and addition operations based on the characteristic element at the element position where each core element differs from the core element by K sliding steps to determine the information processing result of the corresponding clock cycle. In other words, the present application can consider performing multiple multiplication and addition operations on the elements in the core vector information and the feature map vector information in the same clock cycle from the perspective of the sliding step, thereby greatly increasing the parallelism of data processing and reducing the overhead required in subsequent chip development and layout.

[0096] The above mainly introduces the scheme provided by the embodiment of the present application from the perspective of the method. It can be understood that in order to realize the above functions, the hardware structure and / or software module corresponding to the execution of each function are included. Those skilled in the art should easily realize that, in combination with the modules and algorithm steps of each example described in the embodiment disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0097] The embodiment of the present application can divide the functional modules of the device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0098] The information processing device in the embodiment of the present application is described in detail below. Figure 7 FIG. 1 is a schematic diagram of an embodiment of an information processing device provided in an embodiment of the present application. Figure 7 As shown, the information processing device may include a data loading unit 701, a sliding window multiplication and addition unit 702, and a data writing unit 703. Exemplarily, the information processing device also includes a broadcasting unit 704 and a sliding operation unit 705.

[0099] The data loading unit 701 is used to obtain the first information to be processed, the first information to be processed includes kernel vector information and multiple time-series adjacent feature map vector information, the kernel vector information includes at least two kernel elements, and each feature map vector information includes at least two feature elements; the multiple feature map vector information are spliced ​​to obtain the target feature map vector information; the sliding window multiplication and addition unit 702 is used to determine the information processing result of the corresponding clock cycle in each clock cycle of at least two clock cycles based on each kernel element and the feature element at the target position in the target feature map vector information, wherein the target position includes the element position that is the same as the kernel element and the position that differs from the element position of the kernel element by K sliding steps, the first sliding window and the second sliding window between each two adjacent clock cycles differ by N sliding steps, the first sliding window includes the kernel element, the second sliding window includes the feature element, K is a positive integer, N≥2, and N is an integer. The data writing unit 703 is used to determine the target processing result based on the information processing results of at least two clock cycles, and the target processing result is used to filter the first information to be processed.

[0100] In some optional implementations, the sliding window multiplication and addition unit 702 is used to perform at least two multiplication and addition operations on each core element in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle. The first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of core elements and the number of clock cycles.

[0101] In some other optional implementations, the sliding window multiplication and addition unit 702 is used to perform multiplication and addition operations on each first core element in the first sliding window in the first clock cycle, respectively, with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and with the second characteristic element at the corresponding position in the third sliding window, to obtain the information processing result of the first clock cycle. Wherein, the element position of the first core element is the same as the element position of the first characteristic element, the second sliding window and the third sliding window differ by K sliding steps, the first core element is an element of at least two core elements, and the first characteristic element and the second characteristic element are both characteristic elements in the target feature map vector information.

[0102] In some other optional implementations, the information processing device further includes a broadcast unit 704. The broadcast unit 704 is used to copy each first characteristic element and each second characteristic element when performing a multiplication and addition operation in the first clock cycle to obtain a characteristic element sequence; copy each first core element when performing a multiplication and addition operation in the first clock cycle to obtain a core element sequence, and the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence. The sliding window multiplication and addition unit 702 is used to perform a multiplication and addition operation on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the information processing result of the first clock cycle.

[0103] In other optional embodiments, the information processing device also includes a sliding operation unit 705; the sliding operation unit 705 is used to: before performing a multiplication and addition operation on each first core element in the first sliding window in the first clock cycle and the second feature element at the corresponding position in the third sliding window, slide the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to K sliding steps to obtain a third sliding window; determine the second feature element from the third sliding window.

[0104] In some other optional embodiments, the information processing device further includes a sliding operation unit 705. The sliding operation unit 705 is used to perform at least two multiplication and addition operations on each core element in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle, and then slide the first sliding window and the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to N sliding steps, respectively, to obtain the first sliding window and the second sliding window of the second clock cycle, and the first clock cycle is adjacent to the second clock cycle. The sliding window multiplication and addition unit 702 is used to perform at least two multiplication and addition operations on each core element in the first sliding window in the second clock cycle and the feature element at the target position in the second sliding window in the second clock cycle to obtain the information processing result of the second clock cycle. The data writing unit 703 is used to sum the information processing result in the first clock cycle and the information processing result in the second clock cycle to obtain the target processing result.

[0105] In other optional embodiments, the sliding window multiplication and addition unit 702 is used to: in a first clock cycle, perform multiplication and addition operations on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle; and obtain an information processing result of the first clock cycle based on the carry result and the sum result.

[0106] In some other optional implementations, the sliding window multiplication and addition unit 702 is further used to: after obtaining the carry result and the sum result of the first clock cycle, store the carry result in the carry register, and store the sum result in the sum register.

[0107] In other optional embodiments, the data loading unit 701 is also used to: before determining the target processing result based on the information processing results of at least two clock cycles, detect the processing timing time when the corresponding information processing result is determined within the target clock cycle, the target processing cycle is the last clock cycle of the at least two clock cycles; and load the second information to be processed in parallel within the processing timing time, the second information to be processed being adjacent to the first information to be processed in timing.

[0108] The above describes the information processing device in the embodiment of the present application from the perspective of functional entity, and the following describes the information processing device in the embodiment of the present application from the perspective of hardware processing. Figure 8 801, a communication line 807, a memory 803, and at least one communication interface 804.

[0109] The processor 801 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more integrated circuits for controlling the execution of the program of the present application.

[0110] The communication link 807 may include a pathway to transmit information between the above-mentioned components.

[0111] The communication interface 804 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0112] The memory 803 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, and the memory may exist independently and be connected to the processor via a communication line 807. The memory may also be integrated with the processor.

[0113] The memory 803 is used to store computer-executable instructions for executing the solution of the present application, and the execution is controlled by the processor 801. The processor 801 is used to execute the computer-executable instructions stored in the memory 803, thereby implementing the information processing method provided by the above embodiment of the present application. Specifically, the processor 801 can be used to execute the computer-readable instructions in the memory 902 to perform the following operations:

[0114] Multiple feature map vector information are spliced ​​to obtain target feature map vector information; in each clock cycle of at least two clock cycles, based on each core element and the feature element at the target position in the target feature map vector information, the information processing result of the corresponding clock cycle is determined, wherein the target position includes the element position that is the same as the core element and the position that differs from the element position of the core element by K sliding steps, the first sliding window and the second sliding window between every two adjacent clock cycles differ by N sliding steps, the first sliding window includes the core element, and the second sliding window includes the feature element, K is a positive integer, N≥2, and N is an integer.

[0115] In some examples, the processor 801 is specifically configured to perform the following operations:

[0116] Perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature elements at the target position in the second sliding window in the first clock cycle to obtain an information processing result of the first clock cycle, the first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of the core elements and the number of cycles of the clock cycle.

[0117] In some other examples, the processor 801 is specifically configured to perform the following operations:

[0118] Performing multiplication and addition operations on each first core element in the first sliding window in the first clock cycle with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and performing the multiplication and addition operations on the second characteristic element at the corresponding position in the third sliding window, respectively, to obtain an information processing result of the first clock cycle;

[0119] Among them, the element position of the first core element is the same as the element position of the first feature element, the second sliding window differs from the third sliding window by K sliding steps, the first core element is an element among the at least two core elements, and the first feature element and the second feature element are both feature elements in the target feature graph vector information.

[0120] In some other examples, the processor 801 is further configured to perform the following operations:

[0121] Before performing multiplication and addition operations on each first core element in the first sliding window in the first clock cycle with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and performing the multiplication and addition operations on the second characteristic element at the corresponding position in the third sliding window to obtain the information processing result of the first clock cycle, each of the first characteristic elements and each of the second characteristic elements when the multiplication and addition operations are performed in the first clock cycle are copied to obtain a characteristic element sequence; each of the first core elements when the multiplication and addition operations are performed in the first clock cycle are copied to obtain a core element sequence, and the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence;

[0122] The processor 801 is specifically configured to perform the following operations:

[0123] The multiplication and addition operation is performed on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain an information processing result of the first clock cycle.

[0124] In some other examples, the processor 801 is further configured to perform the following operations:

[0125] Before performing the multiplication and addition operation on each first core element in the first sliding window in the first clock cycle and the second characteristic element at the corresponding position in the third sliding window, the second sliding window in the first clock cycle is slid along the element position of the last characteristic element in the target feature map vector information according to the K sliding steps to obtain the third sliding window; and the second characteristic element is determined from the third sliding window.

[0126] In some other examples, the processor 801 is further configured to perform the following operations:

[0127] After performing at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle, the first sliding window and the second sliding window in the first clock cycle are respectively subjected to sliding processing along the element position of the last feature element in the target feature map vector information according to the N sliding steps to obtain the first sliding window and the second sliding window of the second clock cycle,

[0128] The first clock cycle is adjacent to the second clock cycle;

[0129] Perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the second clock cycle and the characteristic element at the target position in the second sliding window in the second clock cycle to obtain an information processing result of the second clock cycle;

[0130] The information processing result in the first clock cycle and the information processing result in the second clock cycle are summed to obtain a target processing result.

[0131] In some other examples, the processor 801 is specifically configured to perform the following operations:

[0132] In the first clock cycle, performing a multiplication and addition operation on each first core element in the core element sequence and a characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle;

[0133] An information processing result of the first clock cycle is obtained based on the carry result and the sum result.

[0134] In some other examples, the processor 801 is specifically configured to perform the following operations:

[0135] Before determining a target processing result based on the information processing results of the at least two clock cycles, detecting a processing timing time when determining a corresponding information processing result within a target clock cycle, the target processing cycle being a last clock cycle of the at least two clock cycles;

[0136] The second information to be processed is loaded in parallel within the processing timing time, and the second information to be processed is adjacent to the first information to be processed in time sequence.

[0137] Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0138] In a specific implementation, as an embodiment, the information processing device may include multiple processors, such as Figure 8 801 and processor 802 in the embodiment of the present invention. Each of these processors may be a single-CPU processor or a multi-CPU processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0139] In a specific implementation, as an embodiment, the information processing device may further include an output device 805 and an input device 806. The output device 805 communicates with the processor 801 and may display information in a variety of ways. The input device 806 communicates with the processor 801 and may obtain the first information to be processed in a variety of ways, the first information to be processed including kernel vector information and multiple time-series adjacent feature map vector information. For example, the input device 806 may be a mouse, a touch screen device, or a sensor device.

[0140] The above-mentioned information processing device can be a general device or a special device. In a specific implementation, the information processing device can be a server, a terminal, etc. or a Figure 8 The embodiment of the present application does not limit the type of the information processing device.

[0141] Need to explain, Figure 8 The processor 801 in the information processing device can call the computer execution instructions stored in the memory 803 to make the information processing device execute the following Figure 3 The method in the corresponding method embodiment.

[0142] Specifically, Figure 7 The functions / implementation process of the sliding window multiplication and addition unit 702, the broadcasting unit 704, and the sliding operation unit 705 can be Figure 8 The processor 801 in the embodiment calls the computer execution instructions stored in the memory 803 to implement. Figure 7 The functions / implementation processes of the data loading unit 701 and the data writing unit 703 can be Figure 8 It is implemented by the communication interface 804 in.

[0143] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any information processing method recorded in the above method embodiments.

[0144] An embodiment of the present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any information processing method recorded in the above method embodiments.

[0145] The present application also provides a chip in an embodiment, which has the function of executing the above Figure 3 The data processing functions shown and the chip include the above Figures 7 and 8 The data processing equipment shown.

[0146] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0147] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0151] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., and other media that can store program codes.

[0152] The above embodiments may be implemented in whole or in part through software, hardware, firmware or any combination thereof. When implemented by software, they may be implemented in whole or in part in the form of a computer program product.

[0153] The computer program product includes one or more computer instructions. When loading and executing the computer execution instruction on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instruction can be stored in a computer-readable storage medium, or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction can be transmitted from a website site, a computer, a server or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server, a data center, etc. that includes one or more available media integration. Available media can be magnetic media, (for example, floppy disk, hard disk, tape), optical media (for example, DVD), or semiconductor media (such as SSD)) and the like.

[0154] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of information processing, characterized in that: include: Acquire first information to be processed, the first information to be processed comprising kernel vector information and a plurality of time-sequentially adjacent feature graph vector information, the kernel vector information comprising at least two kernel elements, and each of the feature graph vector information comprising at least two feature elements; Performing splicing processing on the plurality of feature map vector information to obtain target feature map vector information; In each of the at least two clock cycles, based on each of the core elements and the characteristic element at the target position in the target feature map vector information, determine the information processing result corresponding to the clock cycle, wherein the target position includes the same element position as the core element and a position that differs from the element position of the core element by K sliding steps, and a first sliding window and a second sliding window between every two adjacent clock cycles differ by N sliding steps, the first sliding window includes the core element, and the second sliding window includes the characteristic element, K is a positive integer, N≥2, and N is an integer; A target processing result is determined based on the information processing results of the at least two clock cycles, and the target processing result is used to perform filtering processing on the first information to be processed.

2. The method according to claim 1, characterized in that The step of determining, in each of the at least two clock cycles, an information processing result corresponding to the clock cycle based on each of the core elements and the feature element at the target position in the target feature map vector information, comprises: Perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature elements at the target position in the second sliding window in the first clock cycle to obtain an information processing result of the first clock cycle, the first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of the core elements and the number of cycles of the clock cycle.

3. The method according to claim 2, characterized in that The performing at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the characteristic element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle includes: Performing multiplication and addition operations on each first core element in the first sliding window in the first clock cycle with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and performing the multiplication and addition operations on the second characteristic element at the corresponding position in the third sliding window, respectively, to obtain an information processing result of the first clock cycle; Among them, the element position of the first core element is the same as the element position of the first feature element, the second sliding window differs from the third sliding window by K sliding steps, the first core element is an element among the at least two core elements, and the first feature element and the second feature element are both feature elements in the target feature graph vector information.

4. The method according to claim 3, characterized in that Before performing multiplication and addition operations on each first core element in the first sliding window in the first clock cycle with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and performing the multiplication and addition operations on the first characteristic element at the corresponding position in the third sliding window to obtain the information processing result of the first clock cycle, the method further includes: Copy each of the first characteristic elements and each of the second characteristic elements when the multiplication and addition operation is performed in the first clock cycle to obtain a characteristic element sequence; Copying each of the first core elements when the multiplication and addition operation is performed in the first clock cycle to obtain a core element sequence, wherein the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence; The step of performing a multiplication-addition operation on each first core element in the first sliding window in the first clock cycle with a first characteristic element at a corresponding position in the second sliding window in the first clock cycle, and performing the multiplication-addition operation on each first core element in the first sliding window in the first clock cycle with a second characteristic element at a corresponding position in the third sliding window, to obtain an information processing result of the first clock cycle includes: The multiplication and addition operation is performed on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain an information processing result of the first clock cycle.

5. The method according to any one of claims 3 to 4, characterized in that Before performing the multiplication and addition operation on each first core element in the first sliding window in the first clock cycle and the second characteristic element at the corresponding position in the third sliding window, the method further includes: Sliding the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to the K sliding steps to obtain the third sliding window; A second feature element is determined from the third sliding window.

6. The method according to any one of claims 2 to 4, characterized in that After performing at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the characteristic element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle, the method further includes: The first sliding window and the second sliding window in the first clock cycle are respectively subjected to sliding processing along the element position of the last feature element in the target feature map vector information according to the N sliding steps to obtain the first sliding window and the second sliding window of the second clock cycle, The first clock cycle is adjacent to the second clock cycle; Perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the second clock cycle and the characteristic element at the target position in the second sliding window in the second clock cycle to obtain an information processing result of the second clock cycle; Determining a target processing result based on the information processing results of the at least two clock cycles includes: The information processing result in the first clock cycle and the information processing result in the second clock cycle are summed to obtain a target processing result.

7. The method according to claim 4, characterized in that The method further comprises: performing the multiplication and addition operation on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the information processing result of the first clock cycle, including: In the first clock cycle, performing a multiplication and addition operation on each first core element in the core element sequence and a characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle; An information processing result of the first clock cycle is obtained based on the carry result and the sum result.

8. The method according to claim 7, characterized in that After obtaining the carry result and the sum result of the first clock cycle, the method further includes: The carry result is stored in a carry register, and the sum result is stored in a sum register.

9. The method according to any one of claims 1 to 4, characterized in that Before determining the target processing result based on the information processing results of the at least two clock cycles, the method further includes: detecting a processing timing time when determining a corresponding information processing result within a target clock cycle, wherein the target processing cycle is a last clock cycle of the at least two clock cycles; The second information to be processed is loaded in parallel within the processing timing time, and the second information to be processed is adjacent to the first information to be processed in time sequence.

10. The method according to any one of claims 1 to 4, characterized in that The obtaining of first information to be processed includes: Sending a data read request, the data read request including a first access address and a second access address, the first access address being a storage address of the core vector information, and the second access address being a storage address of each of the feature map vector information; Receive a data response message corresponding to the data read request, the data response message including the core vector information and a plurality of sequentially adjacent feature graph vector information, the core vector information being obtained based on the first access address, and each of the feature graph vector information being obtained based on the second access address.

11. An information processing device, characterized in that: include: Data loading unit, sliding window multiplication and addition unit, data writing unit; The data loading unit is used to obtain first information to be processed, wherein the first information to be processed includes kernel vector information and a plurality of time-sequentially adjacent feature graph vector information, wherein the kernel vector information includes at least two kernel elements, and each of the feature graph vector information includes at least two feature elements; The data loading unit is used to perform splicing processing on the plurality of feature map vector information to obtain target feature map vector information; The sliding window multiplication and addition unit is used to determine, in each of the at least two clock cycles, an information processing result corresponding to the clock cycle based on each of the core elements and the characteristic element at the target position in the target feature map vector information, wherein the target position includes an element position that is the same as the core element and a position that differs from the element position of the core element by K sliding steps, and a first sliding window and a second sliding window between every two adjacent clock cycles differ by N sliding steps, the first sliding window includes the core element, and the second sliding window includes the characteristic element, K is a positive integer, N≥2, and N is an integer; The data writing unit is used to determine a target processing result based on the information processing results of the at least two clock cycles, and the target processing result is used to perform filtering processing on the first information to be processed.

12. The device according to claim 11, characterized in that The sliding window multiplication and addition unit is used to perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the characteristic element at the target position in the second sliding window in the first clock cycle to obtain an information processing result of the first clock cycle; The first clock cycle is any one of the at least two clock cycles, the size of the second sliding window is the same as the vector dimension of the feature map vector information, and the size of the first sliding window is obtained based on the number of core elements and the number of cycles of the clock cycle.

13. The device according to claim 12, characterized in that The sliding window multiplication and addition unit is used to perform multiplication and addition operations on each first core element in the first sliding window in the first clock cycle with the first characteristic element at the corresponding position in the second sliding window in the first clock cycle, and perform the multiplication and addition operations on the second characteristic element at the corresponding position in the third sliding window, so as to obtain the information processing result of the first clock cycle; Among them, the element position of the first core element is the same as the element position of the first feature element, the second sliding window differs from the third sliding window by K sliding steps, the first core element is an element among the at least two core elements, and the first feature element and the second feature element are both feature elements in the target feature graph vector information.

14. The device according to claim 13, characterized in that The information processing device further includes a broadcast unit; the broadcast unit is used to: Copy each of the first characteristic elements and each of the second characteristic elements when the multiplication and addition operation is performed in the first clock cycle to obtain a characteristic element sequence; Copying each of the first core elements when the multiplication and addition operation is performed in the first clock cycle to obtain a core element sequence, wherein the number of first core elements in the core element sequence is the same as the number of characteristic elements in the characteristic element sequence; The sliding window multiplication and addition unit is used to perform the multiplication and addition operation on each first core element in the core element sequence and the characteristic element in the characteristic element sequence at the same position to obtain the information processing result of the first clock cycle.

15. The device according to any one of claims 13 to 14, characterized in that The information processing device further includes a sliding operation unit; the sliding operation unit is used to: Before performing the multiplication and addition operation on each first core element in the first sliding window in the first clock cycle and the second feature element at the corresponding position in the third sliding window, the second sliding window in the first clock cycle is slid along the element position of the last feature element in the target feature map vector information according to the K sliding steps to obtain the third sliding window; A second feature element is determined from the third sliding window.

16. The device according to any one of claims 12 to 14, characterized in that The information processing device further includes a sliding operation unit; The sliding operation unit is used for performing at least two multiplication and addition operations on each of the core elements in the first sliding window in the first clock cycle and the feature element at the target position in the second sliding window in the first clock cycle to obtain the information processing result of the first clock cycle, and then sliding the first sliding window and the second sliding window in the first clock cycle along the element position of the last feature element in the target feature map vector information according to the N sliding steps to obtain the first sliding window and the second sliding window of the second clock cycle, wherein the first clock cycle is adjacent to the second clock cycle; The sliding window multiplication and addition unit is used to perform at least two multiplication and addition operations on each of the core elements in the first sliding window in the second clock cycle and the characteristic element at the target position in the second sliding window in the second clock cycle to obtain an information processing result of the second clock cycle; The data writing unit is used to sum the information processing result in the first clock cycle and the information processing result in the second clock cycle to obtain a target processing result.

17. The device according to claim 14, characterized in that The sliding window multiplication and addition unit is used for: In the first clock cycle, performing a multiplication and addition operation on each first core element in the core element sequence and a characteristic element in the characteristic element sequence at the same position to obtain a carry result and a sum result of the first clock cycle; An information processing result of the first clock cycle is obtained based on the carry result and the sum result.

18. The device according to claim 17, characterized in that The sliding window multiplication and addition unit is further used for: after obtaining the carry result and the sum result of the first clock cycle, storing the carry result in the carry register, and storing the sum result in the sum register.

19. The device according to any one of claims 11 to 14, characterized in that The data loading unit is further used for: Before determining a target processing result based on the information processing results of the at least two clock cycles, detecting a processing timing time when determining a corresponding information processing result within a target clock cycle, the target processing cycle being a last clock cycle of the at least two clock cycles; The second information to be processed is loaded in parallel within the processing timing time, and the second information to be processed is adjacent to the first information to be processed in time sequence.

20. A chip, characterized in that: The information processing device comprises the information processing device as claimed in any one of claims 11 to 19.

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