Packet data transmission system and method for GPGPU (General Purpose Graphics Processing Unit) cluster

Abstract

The invention discloses a packet data transmission system and method oriented to a GPGPU cluster, and relates to the technical field of data transmission. For small packet data transmission of a GPGPU cluster, a loading storage module combines identification information of a target GPGPU with memory access address information and memory access data information into a transmission instruction, the transmission instruction is sent to a data compression protocol module through a crossbar, all memory access data in a memory space of the target GPGPU are integrated and packaged through the data compression protocol module, a small packet data set is formed, and the small packet data set is stored in a storage module. The method comprises the following steps: a GPGPU node sends a packet data to a PCIe transmission adaptation optimization module, the PCIe transmission adaptation optimization module gathers the packet data to form a data transmission entry, constructs a transaction layer data packet TLP conforming to PCIe according to the data transmission entry, and sends the packaged data packet to a corresponding target GPGPU node, a PCIe receiving decoding splitting module of the target GPGPU node decodes to obtain data transmission entry information, and the target GPGPU node sends the data transmission entry information to the PCIe transmission adaptation optimization module. And executing a specific memory access operation according to the data transmission entry information.

Description

Technical Field

[0001] The invention discloses a small packet data transmission system and method for a GPGPU cluster, and relates to the technical field of data transmission. Background Art

[0002] Integrating a large number of GPGPUs together to form a GPGPU cluster builds a computing environment with parallel processing capabilities, expands the scale of computing resources, improves data parallel computing capabilities, and ensures efficient data throughput.

[0003] Currently, PCI Express (PCIe) technology is the main technical means to achieve this goal. PCIe, as a widely adopted serial I / O connection standard, provides a reliable interface for high-speed data transmission between peripheral devices such as CPU and GPU in computer hardware and the host system.

[0004] PCIe data transmission adopts a data packet-based encapsulation and transmission mechanism, and its architecture consists of multiple layers, including the application layer, transaction layer, data link layer, and physical layer. The application layer is designed according to user needs, while the transaction layer, data link layer, and physical layer follow the PCIe standard specifications.

[0005] In the PCIe transmission process, in order to ensure the accuracy and reliability of data transmission, a wealth of control information is introduced, including target address information, transmission attributes, checksums, etc. Although these control signals are crucial to maintaining data integrity, in some cases, they may have an adverse effect on data transmission efficiency. Specifically, when the amount of data transmitted is large, the proportion of control signals is relatively small, and the impact on transmission efficiency is limited; however, in small data transmission scenarios, the overhead of control signals may become higher, and there may even be a situation where the number of symbols in the control signal exceeds the actual amount of data transmitted.

[0006] Therefore, when a GPGPU cluster performs complex parallel computing tasks involving the transmission of a large amount of small data, it is easy to reduce the effective bandwidth utilization of the link, and may also block network resources and affect the progress of other transmission tasks. Summary of the invention

[0007] The present invention provides a small packet data transmission system and method for a GPGPU cluster, which solves the problems of low link effective bandwidth utilization, low data transmission efficiency, etc. in the process of small data volume data transmission of the existing GPGPU cluster.

[0008] The specific scheme proposed by the present invention is:

[0009] The present invention provides a small packet data transmission system for a GPGPU cluster, which comprises a loading and storage module, a data compression protocol module, a PCIe transmission adaptation and optimization module, and a PCIe receiving, decoding and splitting module.

[0010] The load storage module receives the instruction sent by the source GPGPU core, parses the instruction information, obtains the memory access address information and the memory access data information, and determines whether the destination GPGPU is a local GPGPU. If so, the memory access data information is sent to the local L2 cache through the crossbar switch. Otherwise, the identification information of the destination GPGPU is extracted from the instruction, and the identification information is combined with the memory access address information and the memory access data information into a transmission instruction, which is sent to the data compression protocol module through the crossbar.

[0011] The data compression protocol module allocates and maintains memory space for each GPGPU, and sends the identification information, memory access address information, and memory access data information of the destination GPGPU in the transmission instruction to the memory space corresponding to the destination GPGPU.

[0012] The memory address information in each memory space is sorted in ascending order of value.

[0013] According to the data transmission mechanism based on the network congestion degree or the data transmission mechanism based on the memory space capacity, all the memory access data of the destination GPGPU memory space are integrated and packaged to form a small packet data set, which is sent to the PCIe transmission adaptation optimization module.

[0014] The PCIe transmission adaptation optimization module uses the smallest memory access address in the packet data set as the base address, calculates the address offset between each memory access address and the base address, reorganizes and packages the packet data set based on the encoding format of the base address and the address offset, forms a data transmission entry, constructs a transaction layer data packet TLP that complies with the PCIe according to the data transmission entry, encapsulates the transaction layer data packet TLP at the data link layer and the physical layer, and sends the encapsulated data packet to the corresponding GPGPU node.

[0015] The PCIe receiving decoding and splitting module of the GPGPU node decodes the received data packet, restores it to a transaction layer data packet TLP, continues decoding to obtain data transmission entry information, and performs specific memory access operations according to the data transmission entry information.

[0016] Furthermore, when the data compression protocol module of the small packet data transmission system for the GPGPU cluster detects that multiple transmission instructions point to the same memory access address of the same destination GPGPU, the latest write data is selected according to the timestamp to overwrite the memory space of the destination GPGPU, and for read operations, multiple transmission instructions are merged into a single transmission instruction to ensure data consistency.

[0017] Furthermore, the data transmission mechanism based on memory space capacity of the packet data transmission system for GPGPU clusters includes:

[0018] When a target GPGPU memory space reaches the capacity threshold, the data compression protocol module automatically triggers the data transmission mechanism based on the memory space capacity, integrates and packages all the memory access data of the target GPGPU memory space to form a small packet data set.

[0019] Furthermore, the data transmission mechanism based on network congestion degree for a packet data transmission system for a GPGPU cluster includes:

[0020] The data compression protocol module decides whether to transmit a small packet data set in the memory space based on the network congestion information in the GPGPU cluster. If there are vacant physical links in the GPGPU cluster and the memory space of all destination GPGPUs has not reached the capacity threshold, the data transmission mechanism based on the network congestion level is triggered, the idle link with the best current network status is identified and selected, the corresponding destination GPGPU is determined, and all memory access data in the destination GPGPU memory space is integrated and packaged to form a small packet data set.

[0021] Furthermore, the PCIe transmission adaptation optimization module of the small packet data transmission system for the GPGPU cluster reserves the address offset starting from the base address. If there is no continuous memory access address, the burst data burst is 1; if there is a continuous memory access address, the address offset between the first memory access address in the continuous memory access address and the base address is reserved, and the number of continuous memory access addresses is used as the burst data burst. The data transmission entry includes the address offset, burst data, memory access data length and the memory access data corresponding to all memory access addresses.

[0022] Furthermore, when the PCIe transmission adaptation optimization module of the small packet data transmission system for the GPGPU cluster constructs a transaction layer data packet TLP according to the data transmission entries, the Header field, Data field and ECRC field of the transaction layer data packet TLP are filled, wherein the address parameter Addr of the Header field is filled with the base address data of the data set, and the length parameter Length of the Header field is filled with the cumulative length of the accessed data; all data transmission entries in the transaction layer data packet TLP are filled into the Data field; and the ECRC field information is filled by default for verifying the transaction layer data packet TLP.

[0023] The present invention also provides a GPGPU cluster-oriented small packet data transmission method, and utilizes the GPGPU cluster-oriented small packet data transmission system to perform small packet data transmission on the GPGPU cluster.

[0024] The present invention also provides a computer-readable medium, on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the small packet data transmission method for a GPGPU cluster.

[0025] The benefits of the present invention are:

[0026] The present invention aims at the efficiency problem existing in the transmission process of small data volume of GPGPU cluster, focuses on optimizing the transmission efficiency of small data packets, and solves the problem of low transmission efficiency of small data volume in the prior art.

[0027] The data compression protocol module of the present invention allocates and maintains exclusive memory space for each target GPGPU, effectively preprocesses and caches the transmitted data, and optimizes the data transmission process. At the same time, the module designs and develops address sorting protocols and data overlay protocols, optimizes data storage mode and data transmission locality, and reduces the redundancy of address information.

[0028] The data transmission mechanism of the present invention is based on the memory space capacity, which ensures the consistency of the effective data load during the transmission process; another data transmission mechanism of the present invention is based on the network congestion level, which intelligently decides the timing and target of data transmission, thereby improving the data transmission efficiency of the physical link.

[0029] The PCIe adaptation optimization module of the present invention optimizes the adaptability of the data transmission architecture of PCIe, takes the constructed small packet data set as the basic data for PCIe transmission, and makes customized modifications to the construction logic of the transaction layer data packet (TLP) to adapt to the characteristics of the small packet data set. And by utilizing an efficient data packaging strategy, a unique encoding format is designed to reorganize and package the data, which not only improves the density and efficiency of data transmission, but also improves the effective bandwidth utilization of the link by reducing the ratio of control signals to data signals.

[0030] The present invention is carried out without changing the GPGPU software engineering code and PCIe transmission logic, ensuring the compatibility and easy deployment of the solution, so that the present invention can be seamlessly integrated into the existing GPGPU cluster and PCIe transmission system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of module interaction when the system of the present invention is applied.

[0032] Figure 2 This is a schematic diagram of editing data transmission entries in the PCIe transmission adaptation optimization module. DETAILED DESCRIPTION

[0033] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0034] Example 1

[0035] The present invention provides a small packet data transmission system for a GPGPU cluster, which comprises a loading and storing module, a data compression protocol module, a PCIe transmission adaptation and optimization module, and a PCIe receiving decoding and splitting module. The loading and storing module is a Load-Store Unit (LSU) module.

[0036] The load storage module receives the instruction sent by the source GPGPU core, parses the instruction information, obtains the memory access address information and the memory access data information, and determines whether the destination GPGPU is a local GPGPU. If so, the memory access data information is sent to the local L2 cache through the crossbar switch. Otherwise, it involves cross-GPGPU cluster communication. The identification information GPGPU_id of the destination GPGPU is extracted from the instruction, and the identification information GPGPU_id is combined with the memory access address information and the memory access data information into a transmission instruction, which is sent to the data compression protocol module through the crossbar.

[0037] The data compression protocol module allocates and maintains memory space for each GPGPU, and effectively pre-processes and caches the transmitted data, thereby optimizing the data transmission process.

[0038] Specifically, the data compression protocol module receives the GPGPU cluster data communication request from the LSU module, obtains the identification information GPGPU_id, memory access address information trans_addr and memory access data information trans_data of the destination GPGPU in the transmission instruction, and sends the GPGPU identification information GPGPU_id, memory access address information trans_addr and memory access data information trans_data to the memory space corresponding to the destination GPGPU.

[0039] The data compression protocol module sorts the memory access address information in each memory space in ascending order of numerical values. This sorting not only optimizes the data storage mode and improves the locality of subsequent destination GPGPU memory access, but also enhances the effect of the subsequent data compression stage by reducing the redundancy of address information.

[0040] When multiple transfer instructions are detected pointing to the same memory access address of the same destination GPGPU, the latest write data will be selected for overwriting based on the timestamp. This process can solve the write conflict problem on the same memory access address of the destination GPGPU. The read operation is merged into a single instruction to ensure data consistency.

[0041] The data compression protocol module integrates and packages all memory access data of the destination GPGPU memory space according to the data transmission mechanism based on the network congestion level or the data transmission mechanism based on the memory space capacity, forms a small packet data set, and sends it to the PCIe transmission adaptation optimization module.

[0042] The data transmission mechanism based on the memory space capacity includes:

[0043] When the memory space of a certain destination GPGPU reaches the capacity threshold, the data compression protocol module automatically triggers the data transmission mechanism based on the memory space capacity, integrates and packages all the memory access data of the destination GPGPU memory space, and forms a small packet data set. By setting a fixed memory space capacity for each destination GPGPU in the data compression protocol module, and the data transmission mechanism based on the memory space capacity, the consistency of the effective data load during the "source GPGPU-destination GPGPU" transmission process is ensured. And for the transmission of small data packets, the same memory space as the transmission of large data can cache dozens of groups of small packet data, and then these small packet data can be combined into a larger data set for one-time transmission, thereby significantly improving the efficiency of small data transmission. At the same time, the data transmission mechanism based on the memory space capacity allows the capacity of the memory space to be flexibly adjusted to meet the data transmission needs of GPGPU clusters of different scales and different data characteristics, further enhancing the data transmission performance of the entire GPGPU cluster.

[0044] Data transmission mechanism based on network congestion level, including:

[0045] The data compression protocol module decides whether to transmit a small packet data set in the memory space based on the network congestion information in the GPGPU cluster. If the physical links in the GPGPU cluster are idle and the memory spaces of all destination GPGPUs have not reached the capacity threshold, the data transmission mechanism based on the network congestion level is triggered, the idle link with the best current network status is identified and selected, the corresponding destination GPGPU is determined, and all memory access data of the destination GPGPU memory space is integrated and packaged to form a small packet data set. If the data compression protocol module identifies that multiple destination GPGPUs are in a state of low network congestion, the mechanism can select the destination GPGPU with the largest amount of stored data as the transmission object according to the preset optimization criteria, and integrate and package the memory access data of the memory space to form a data set.

[0046] The data set is adapted through the PCIe transmission adaptation optimization module and transmitted to the destination GPGPU through the PCIe physical layer.

[0047] The PCIe transmission adaptation optimization module uses the smallest memory access address in the packet data set as the base address, calculates the address offset between each memory access address and the base address, reorganizes and packages the packet data set based on the encoding format of the base address and the address offset, forms a data transmission entry, constructs a transaction layer data packet TLP that complies with the PCIe according to the data transmission entry, encapsulates the transaction layer data packet TLP at the data link layer and the physical layer, and sends the encapsulated data packet to the corresponding GPGPU node.

[0048] The PCIe receiving decoding and splitting module of the GPGPU node decodes the received data packet, restores it to a transaction layer data packet TLP, continues decoding to obtain data transmission entry information, and performs specific memory access operations according to the data transmission entry information.

[0049] Example 2

[0050] Based on Example 1, when the PCIe transmission adaptation optimization module forms a data transmission entry, the PCIe transmission adaptation optimization module reserves the address offset starting from the base address. If there is no continuous memory access address, the burst data burst is 1; if there is a continuous memory access address, the address offset between the first memory access address in the continuous memory access address and the base address is reserved, and the number of continuous memory access addresses is used as the burst data burst. The data transmission entry includes the address offset, burst data, memory access data length, and memory access data corresponding to all memory access addresses.

[0051] For example, the data set transmitted by the data compression protocol module contains six groups of address data: 00001, 00002, 00003, 00005, 00007, 00008. The PCIe transmission adaptation optimization module selects the minimum address 00001 as the base address, and calculates the address offsets relative to the base address as 0, 1, 2, 4, 6, and 7 respectively. On this basis, it is recognized that the first three address offsets are continuous, so the offset 0 is retained, and the corresponding burst value is accumulated to 3. For the last two consecutive address offsets, the module retains the offset 6 and accumulates the corresponding burst value to 2. Finally, the PCIe transmission adaptation optimization module converts the received data set into three data transmission entries, as follows:

[0052] (1) The first entry has offset = 0, burst = 3, and length is the cumulative data length of access data 1, 2, and 3. The data field contains these three sets of access data.

[0053] (2) The second entry has offset=4, burst=1, and length is the data length of the single access data 4. The data field contains this set of access data.

[0054] (3) The third entry has offset=6, burst=2, and its length is the cumulative data length of the accessed data 5 and 6. The data field contains these two sets of accessed data.

[0055] The PCIe transmission adaptation optimization module packages the completed data transmission items and constructs a transaction layer data packet TLP that complies with the PCIe hierarchical architecture specification according to the PCIe data format requirements. This process involves the accurate filling of the three main components of TLP: Header, Data, and ECRC:

[0056] (1) TLP Header field: The Header field carries key information in the data transmission process. The Header field is assigned parameters including transmission type (Type), byte enable (Byte Enable), address (Addr), length (Length), tag (Tag), requester ID (Requester ID) and completer ID (Completion ID). In order to ensure compatibility with the PCIe transmission system, the PCIe transmission adaptation optimization module makes adaptive changes to the address (Addr) and length (Length) information. The address information is selected from the base address data of the data set, while the length information selects the cumulative length of the overall data transmission.

[0057] (2) Data field: The Data field is the part of the TLP used to store the actual transmission data. In the present invention, the multiple groups of data transmission items that have been packaged are continuously filled into the Data field according to their order in the data set. This sequential filling strategy ensures the continuity of data and the efficiency of transmission.

[0058] (3) ECRC field: As an optional part of TLP, the ECRC field is designed to provide additional integrity check for data packets. In the present invention, the ECRC field is retained and maintained at its default setting to ensure the reliability and error detection capability of data transmission.

[0059] After constructing the transaction layer data packet TLP in the PCIe multi-layer structure, the data packet is further encapsulated in the data link layer and physical layer in accordance with the PCIe data transmission mode, ensuring that the data packet can carry the information of the target GPGPU in accordance with the predetermined transmission protocol and be accurately sent to the corresponding GPGPU node.

[0060] The encapsulated data packet is sent to the corresponding destination GPGPU node. The PCIe receiving decoding and splitting module of the destination GPGPU node first performs PCIe hierarchical splitting, gradually decodes the received physical layer data packet, decomposes it into data link layer data packets, and finally restores it to transaction layer data packet TLP, continues decoding to obtain data transmission entry information, and performs specific memory access operations according to the data transmission entry information.

[0061] The system of the present invention optimizes the adaptability of the data transmission architecture of PCIe. In the transaction layer of PCIe, the constructed small packet data set is used as the basic data for PCIe transmission, and the construction logic of TLP (Transaction Layer Packet) is customized to adapt to the characteristics of the small packet data set. The overall implementation process of the scheme of the present invention is carried out without changing the GPGPU software engineering code and PCIe transmission logic, ensuring the compatibility and easy deployment of the scheme.

[0062] During the implementation of the scheme of the present invention, by optimizing the encapsulation and serialization process of the data packet, the efficient transmission of multiple groups of small packet data sets is achieved, the control signal overhead in the transmission of small data volumes is effectively reduced, the ratio of control signals to data signals in a single transmission is reduced, the effective bandwidth utilization of the link is improved, the occupancy of network resources is reduced, and thus the overall communication efficiency of the GPGPU cluster is improved.

[0063] Example 3

[0064] The present invention also provides a GPGPU cluster-oriented small packet data transmission method, and utilizes the GPGPU cluster-oriented small packet data transmission system to perform small packet data transmission on the GPGPU cluster.

[0065] The execution process of the above method and other contents are based on the same concept as the embodiment of the system of the present invention. For specific contents, please refer to the description in the embodiment of the system of the present invention, and no further description is given here.

[0066] Likewise, the method of the present invention is beneficial in that:

[0067] Aiming at the efficiency problem of GPGPU cluster in the process of transmitting small data volumes, we focus on optimizing the transmission efficiency of small data packets, and solve the problem of low transmission efficiency of small data volumes in existing technologies.

[0068] The method of the present invention uses a data compression protocol module to allocate and maintain exclusive memory space for each target GPGPU, effectively preprocesses and caches the transmitted data, and optimizes the data transmission process. At the same time, the module designs and develops an address sorting protocol and a data overlay protocol, optimizes the data storage mode and data transmission locality, and reduces the redundancy of address information.

[0069] The method of the present invention has a data transmission mechanism based on the memory space capacity, which ensures the consistency of the effective data load during the transmission process; the method of the present invention has another data transmission mechanism based on the network congestion level, which intelligently decides the timing and target of data transmission, thereby improving the data transmission efficiency of the physical link.

[0070] The method of the present invention applies a PCIe adaptation optimization module: the adaptability of the data transmission architecture of PCIe is optimized, the constructed small packet data set is used as the basic data for PCIe transmission, and the construction logic of the transaction layer data packet (TLP) is customized to adapt to the characteristics of the small packet data set. And by using an efficient data packaging strategy, a unique encoding format is designed to reorganize and package the data, which not only improves the density and efficiency of data transmission, but also improves the effective bandwidth utilization of the link by reducing the ratio of control signals to data signals.

[0071] The method of the present invention is performed without changing the GPGPU software engineering code and PCIe transmission logic, ensuring the compatibility and easy deployment of the solution, so that the present invention can be seamlessly integrated into the existing GPGPU cluster and PCIe transmission system.

[0072] It should be noted that not all steps and modules in the above method flow and each system structure are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or some components in multiple independent devices may be implemented together.

[0073] Example 4

[0074] The present invention also provides a computer-readable medium, on which a computer instruction is stored, and when the computer instruction is executed by a processor, the processor executes the packet data transmission method for a GPGPU cluster. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code that implements the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

[0075] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0076] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0077] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling an operating system operating on the computer to complete part or all of the actual operations based on instructions from the program code.

[0078] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or written to a memory provided in an expansion unit connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or the expansion unit is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0079] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A small packet data transmission system for GPGPU clusters, characterized by Small packet data transmission for GPGPU clusters, including loading and storage modules, data compression protocol modules, PCIe transmission adaptation and optimization modules, and PCIe receiving, decoding and splitting modules. The load storage module receives the instruction sent by the source GPGPU core, parses the instruction information, obtains the memory access address information and the memory access data information, and determines whether the destination GPGPU is a local GPGPU. If so, the memory access data information is sent to the local L2 cache through the crossbar switch. Otherwise, the identification information of the destination GPGPU is extracted from the instruction, and the identification information is combined with the memory access address information and the memory access data information into a transmission instruction, which is sent to the data compression protocol module through the crossbar. The data compression protocol module allocates and maintains memory space for each GPGPU, and sends the identification information, memory access address information, and memory access data information of the destination GPGPU in the transmission instruction to the memory space corresponding to the destination GPGPU. The memory address information in each memory space is sorted in ascending order of value. According to the data transmission mechanism based on the network congestion degree or the data transmission mechanism based on the memory space capacity, all the memory access data of the destination GPGPU memory space are integrated and packaged to form a small packet data set, which is sent to the PCIe transmission adaptation optimization module. The PCIe transmission adaptation optimization module uses the smallest memory access address in the packet data set as the base address, calculates the address offset between each memory access address and the base address, reorganizes and packages the packet data set based on the encoding format of the base address and the address offset, forms a data transmission entry, constructs a transaction layer data packet TLP that complies with the PCIe according to the data transmission entry, performs data link layer encapsulation and physical layer encapsulation on the transaction layer data packet TLP, and sends the encapsulated data packet to the corresponding destination GPGPU node. The PCIe receiving decoding and splitting module of the destination GPGPU node decodes the received data packet, restores it to a transaction layer data packet TLP, continues decoding to obtain data transmission entry information, and performs specific memory access operations according to the data transmission entry information.

2. According to the GPGPU cluster-oriented packet data transmission system of claim 1, it is characterized in that the data When the compression protocol module detects that multiple transfer instructions point to the same memory access address of the same destination GPGPU, it selects the latest write data according to the timestamp to overwrite the memory space of the destination GPGPU. For read operations, multiple transfer instructions are merged into a single transfer instruction to ensure data consistency.

3. The packet data transmission system for GPGPU cluster according to claim 1 is characterized in that Data transmission mechanism based on memory space capacity, including: When a target GPGPU memory space reaches the capacity threshold, the data compression protocol module automatically triggers the data transmission mechanism based on the memory space capacity, integrates and packages all the memory access data of the target GPGPU memory space to form a small packet data set.

4. The packet data transmission system for GPGPU cluster according to claim 1 is characterized in that Data transmission mechanism based on network congestion level, including: The data compression protocol module decides whether to transmit a small packet data set in the memory space based on the network congestion information in the GPGPU cluster. If there are vacant physical links in the GPGPU cluster and the memory space of all destination GPGPUs has not reached the capacity threshold, the data transmission mechanism based on the network congestion level is triggered, the idle link with the best current network status is identified and selected, the corresponding destination GPGPU is determined, and all memory access data in the destination GPGPU memory space is integrated and packaged to form a small packet data set.

5. The packet data transmission system for GPGPU cluster according to claim 1 is characterized in that The PCIe transmission adaptation optimization module reserves the address offset starting from the base address. If there is no continuous memory access address, the burst data burst is 1; if there is a continuous memory access address, the address offset between the first memory access address and the base address in the continuous memory access address is reserved, and the number of continuous memory access addresses is used as the burst data burst. The data transmission entry includes the address offset, burst data, memory access data length, and the memory access data corresponding to all memory access addresses.

6. The packet data transmission system for GPGPU cluster according to claim 1 is characterized in that When the PCIe transmission adaptation optimization module constructs a transaction layer data packet TLP according to the data transmission entries, the Header field, Data field and ECRC field of the transaction layer data packet TLP are filled, wherein the address parameter Addr of the Header field is filled with the base address data of the data set, and the length parameter Length of the Header field is filled with the cumulative length of the accessed data; all data transmission entries in the transaction layer data packet TLP are filled into the Data field; and the ECRC field information is filled by default for verifying the transaction layer data packet TLP.

7. A small packet data transmission method for a GPGPU cluster, characterized by: The small packet data transmission system for GPGPU cluster as described in any one of claims 1 to 7 is used to perform small packet data transmission for GPGPU cluster.

8. A computer readable medium, characterized in that The computer-readable medium stores computer instructions, and when the computer instructions are executed by the processor, the processor executes the packet data transmission method for a GPGPU cluster as described in claim 7.

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