A digital-analog hybrid verification method for clock chips

Abstract

The present invention provides a digital-analog hybrid verification method for a clock chip, comprising: building a test top layer based on the analog circuit top layer of the clock chip, and extracting an analog Verilog circuit model; using the analog circuit to complete module-level simulation, and obtaining nonlinear parameters and jitter clock parameters; inserting the nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and building a digital-analog hybrid simulation environment in conjunction with a digital RTL / digital netlist; applying a test stimulus in the digital-analog hybrid simulation environment to lock a phase-locked loop, and periodically collecting data to calculate jitter indicators, and completing the digital-analog hybrid simulation verification of the clock chip. The present invention can make the simulation closer to the real scene, the simulation result is more reliable, and the simulation speed is faster by introducing nonlinear TDC, DTC, DCO models and jitter clock models in the digital-analog hybrid verification of the clock chip.

Description

Technical Field

[0001] The invention relates to the field of chip verification, and in particular to a digital-analog hybrid verification method for a clock chip. Background Art

[0002] Clock chips based on digital phase-locked loops, time-to-digital converters (TDC) and digital-to-time converters (DTC) are usually used in digital phase-locked loop (DPLL) frequency synthesizers as phase detectors. TDC and DTC are used for strict time measurement or phase shifting. However, TDC and DTC implementations will have certain nonlinearities. Each level of delay in the TDC based on the delay architecture will be different, thus affecting the nonlinearity of TDC. Currently, clock chip simulation based on digital phase-locked loops is based on linear TDC and DTC models for mixed analog-digital simulation, such as Figure 1 The nonlinear curve and linear curve shown cannot truly reflect the nonlinear characteristics of simulated TDC and DTC, and there is a certain deviation between the simulated performance and the actual performance.

[0003] In the clock chip of the digital phase-locked loop, the digitally controlled oscillator DCO (Digitally controlled oscillator) uses the input digital code as control to adjust the frequency and phase of its output signal. The typical architecture of the current DCO is based on a capacitor-inductor (LC) resonant network, where L and C are the total inductance and total capacitance in the resonant circuit respectively. The LC resonant network outputs a frequency Therefore, the method of realizing digital control of the output frequency includes digitally controlling the capacitor C, or digitally controlling the inductor L, or controlling both at the same time. In today's integrated circuit technology, the on-chip capacitor has a smaller area and a higher Q value than the on-chip inductor, so a practical solution is to use a digital control signal to control the total capacitance value in the loop while keeping the inductor unchanged, so the output frequency of the LC resonant network , where N is the number of digitally controlled capacitors that are enabled. is the kth enabled effective capacitance value. The DCO oscillator cannot be completely linear and has certain nonlinear characteristics. The current mainstream simulation uses the DCO linear model for simulation, such as Figure 2 The nonlinear curve and linear curve shown cannot reflect the nonlinear characteristics of DCO, and there is a certain deviation between the simulation performance and the actual performance.

[0004] In the clock chip, the signal quality of the system reference clock has a great impact on the performance of the digital phase-locked loop. If the reference clock performance is poor, the performance of the digital phase-locked loop will be poor. The ideal reference clock currently used in the clock chip simulation based on the digital phase-locked loop cannot reflect the frequency deviation and phase jitter of the reference clock in real situations. Figure 3 As shown in the figure, the ideal clock is the same in each cycle T, while the jitter clock is different in each cycle (T0, T1, T2). The performance of the ideal reference clock will be biased and cannot truly reflect the performance of the clock chip. Summary of the invention

[0005] The present invention provides a digital-analog hybrid verification method for a clock chip. The present invention obtains nonlinear parameters of TDC, DTC and DCO and adds them into a modeling process through pre-simulation and post-simulation of an analog module, so as to solve the problem that linear TDC, DTC and DCO models are used in digital-analog hybrid simulation, which cannot reflect the real nonlinear characteristics of TDC, DTC and DCO, and that ideal clocks are used, which cannot truly reflect the real jitter clock characteristics, resulting in a certain deviation between simulation results and real results.

[0006] The first aspect of the present invention provides a digital-analog hybrid verification method for a clock chip, which is applied in pre-simulation and includes:

[0007] Build the test top layer based on the analog circuit top layer of the clock chip and extract the analog Verilog circuit model;

[0008] Use analog circuits to complete module-level pre-simulation and obtain nonlinear parameters and jitter clock parameters;

[0009] Insert nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and build a mixed-analog pre-simulation environment with digital RTL;

[0010] In the pre-simulation environment of digital-analog hybrid, the test stimulus is applied to lock the phase-locked loop, and the data is periodically collected to calculate the jitter index, thus completing the pre-simulation verification of the clock chip.

[0011] As a preferred solution, the nonlinear parameter acquisition process includes:

[0012] Complete module-level DTC pre-simulation through analog circuits to obtain its control word and delay nonlinear parameters;

[0013] Complete module-level TDC pre-simulation through analog circuits to obtain nonlinear parameters of the delay architecture TDC;

[0014] The module-level DCO pre-simulation is completed through analog circuits to obtain its capacitor and inductor nonlinear parameters, phase modulation noise jitter parameters, and frequency modulation noise jitter parameters.

[0015] As a preferred solution, the jitter clock parameter acquisition process includes:

[0016] The phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are obtained based on the crystal and crystal oscillator jitter indicators measured in the laboratory.

[0017] As a preferred solution, when applying test stimulus to lock the phase-locked loop, the typical frequency point frequency of the clock operation, the upper and lower boundary operating frequencies, and random frequency point use cases within the working range are generated according to the chip specification configuration, and the generated use cases are configured separately to verify the phase-locked loop lock.

[0018] As a preferred solution, the periodic data acquisition and calculation of jitter index to complete the pre-simulation verification of the clock chip includes:

[0019] After the phase-locked loop is locked, the DCO frequency is periodically sampled, and the cycle-to-cycle root mean square jitter value and the mean jitter of 12KHz-20MHz are calculated. The simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

[0020] The second aspect of the present invention provides a digital-analog hybrid verification method for a clock chip, which is applied in post-simulation and includes:

[0021] Build the test top layer based on the analog circuit top layer of the clock chip and extract the analog Verilog circuit model;

[0022] Use analog circuits to complete module-level post-simulation and obtain nonlinear parameters and jitter clock parameters;

[0023] Insert nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and build a mixed digital-analog simulation environment with the digital netlist;

[0024] In the mixed-analog post-simulation environment, test excitation is applied to lock the phase-locked loop, and data is periodically collected to calculate the jitter index, completing the mixed-analog post-simulation verification of the clock chip.

[0025] As a preferred solution, the nonlinear parameter acquisition process includes:

[0026] Complete module-level DTC post-simulation through analog circuits to obtain the delay values ​​corresponding to all control words at each process corner;

[0027] Complete module-level TDC post-simulation through analog circuits to obtain different delays at each level of each process corner;

[0028] The module-level DCO post-simulation is completed through analog circuits to obtain the nonlinear parameters of capacitors and inductors, phase modulation noise jitter parameters, and frequency modulation noise jitter parameters of each process corner; among them, the process corners include TT, FF, and SS.

[0029] As a preferred solution, the jitter clock parameter acquisition process includes:

[0030] The phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are obtained based on the crystal and crystal oscillator jitter indicators measured in the laboratory.

[0031] As a preferred solution, when applying test stimulus to lock the phase-locked loop, the typical frequency point frequency of the clock operation, the upper and lower boundary operating frequencies, and random frequency point use cases within the working range are generated according to the chip specification configuration, and the generated use cases are configured separately to verify the phase-locked loop lock.

[0032] As a preferred solution, the periodic data acquisition and calculation of jitter index, and the completion of the digital-analog hybrid simulation verification of the clock chip, specifically include:

[0033] After the phase-locked loop is locked, the DCO frequency is periodically sampled, and the cycle-to-cycle root mean square jitter value and the mean jitter of 12KHz-20MHz are calculated. The simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

[0034] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: by introducing nonlinear TDC, DTC, DCO models and jitter clock models in the mixed digital-analog verification of the clock chip, the present invention can make the simulation closer to the real scene, the simulation result is more reliable, and the simulation speed is faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the comparison between the linear parameter curve of the traditional linear TDC / DTC model and the actual nonlinear curve.

[0036] Figure 2 Schematic diagram comparing the linear parameter curve of the traditional linear DCO model and the actual nonlinear curve.

[0037] Figure 3 This is a schematic diagram comparing the ideal clock and the actual jitter clock.

[0038] Figure 4 This is a flow chart of the digital-analog hybrid verification method for the clock chip proposed by the present invention.

[0039] Figure 5 This is a pre-simulation verification flow chart in one embodiment of the present invention.

[0040] Figure 6 Corresponding graph of nonlinear parameters obtained for DTC.

[0041] Figure 7Schematic diagrams of two common delay architectures of TDC: vernier delay line TDC and flash memory (single delay line) TDC.

[0042] Figure 8 This is a post-simulation verification flow chart in one embodiment of the present invention. DETAILED DESCRIPTION

[0043] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0044] In the mixed-analog simulation verification of clock chips, the traditional solution uses linear TDC, DTC, DCO models and ideal clocks for simulation verification, which cannot reflect the nonlinear characteristics of TDC, DTC, DCO and clock jitter characteristics. Based on this, in order to make the simulation model truly reflect the system performance and the simulation results closer to the actual results, please refer to Figure 4 The embodiment of the present invention proposes a digital-analog hybrid verification method for a clock chip, and the specific steps are as follows:

[0045] (1) Build the test top layer based on the analog circuit top layer of the clock chip and extract the analog Verilog circuit model;

[0046] (2) Use analog circuits to complete module-level simulation and obtain nonlinear parameters and jitter clock parameters;

[0047] (3) Insert nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and build a digital-analog hybrid simulation environment in conjunction with the digital RTL / digital netlist;

[0048] (4) Apply test stimulus in a mixed-analog simulation environment to lock the phase-locked loop, and periodically collect data to calculate the jitter index to complete the mixed-analog simulation verification of the clock chip.

[0049] In the above digital-analog mixed verification process, by adding nonlinear parameters and jitter clock parameters, the simulation results can be made more reliable and the simulation speed can be faster.

[0050] During the entire design process of the clock chip, its verification process usually includes two parts: pre-simulation and post-simulation. Among them, pre-simulation is mainly the link of simulating and verifying the function and performance of the circuit during the design process, focusing on the functionality, timing and power consumption of the circuit to ensure the correctness and feasibility of the design. Pre-simulation is usually performed before physical layout, so it is also called static timing analysis or netlist-level simulation. Post-simulation refers to the link of simulating the actual performance of the chip after the physical layout of the chip. It mainly focuses on the actual performance of the chip under specific processes and layouts, including timing, power consumption, temperature, etc. Post-simulation can simulate the behavior of the chip under actual working conditions and provide a basis for chip optimization and debugging. There are differences between pre-simulation and post-simulation in the following aspects:

[0051] ① Simulation object: Pre-simulation focuses on the design and performance of the circuit, without considering the impact of physical factors such as process and layout on chip performance. Post-simulation focuses on the actual performance of the chip, including the impact of physical factors on chip performance.

[0052] ②Simulation accuracy: Pre-simulation usually uses netlist-level simulation, which only considers the logical relationship and signal transmission of the circuit, and does not consider physical details. Post-simulation considers the impact of physical factors such as process and layout on chip performance, so the simulation accuracy is higher.

[0053] ③Simulation speed: Since the pre-simulation only considers the logical relationship and signal transmission of the circuit, the simulation speed is usually faster. The post-simulation needs to consider the impact of physical factors on chip performance, so the simulation speed is relatively slow.

[0054] ④ Debugging purpose: Pre-simulation is mainly used to verify the correctness and feasibility of circuit design, as well as to find potential problems and errors. Post-simulation is mainly used to optimize chip performance, including adjusting process parameters, optimizing layout, etc.

[0055] The digital-analog hybrid verification method for a clock chip proposed in the present invention is applicable to both pre-simulation and post-simulation processes. It can be used in pre-simulation for rapid iteration, and in post-simulation for more accurate simulation results while also improving iteration speed.

[0056] Example 1

[0057] Please refer to Figure 5 This embodiment proposes a digital-analog hybrid verification method for a clock chip, which is mainly used in pre-simulation verification of the chip. The specific steps are as follows:

[0058] Step 101: Build a test top layer based on the analog circuit top layer of the clock chip, and extract the analog Verilog circuit model.

[0059] Since the clock chip needs to verify the analog circuit and the digital circuit, but due to the different design platforms, mixed verification cannot be performed directly. Therefore, in this embodiment, the analog circuit is converted into an analog Verilog circuit model to complete the mixed test of the analog circuit and the digital circuit under Verilog.

[0060] Step 102: Use analog circuits to complete module-level pre-simulation to obtain nonlinear parameters and jitter clock parameters.

[0061] Pre-simulation mainly verifies whether the circuit behavior is consistent with the design concept and ensures that the circuit function meets the specification requirements. Pre-simulation does not involve specific device delay and connection delay information, and mainly focuses on the correctness of the logic function. In this embodiment, the module-level pre-simulation is performed by simulating the circuit to obtain the corresponding parameters, so as to introduce the nonlinear TDC, DTC, DCO model and jitter clock model into the simulation process.

[0062] Specifically, for DTC, this embodiment completes module-level DTC pre-simulation through analog circuits to obtain its control words and nonlinear parameters of delay, including the delay values ​​corresponding to all control words of DTC. Please refer to Figure 6 For TDC, this embodiment completes module-level TDC pre-simulation through analog circuits to obtain nonlinear parameters of the delay architecture TDC, where: Figure 7 This is a typical delay architecture TDC. Each stage includes multiple delay units. In actual circuits, the delays of each delay unit are not the same. Therefore, it is necessary to obtain the different delays in each stage. ..... , ..... , ...... For DCO, this embodiment completes module-level DCO pre-simulation through analog circuits to obtain its capacitor and inductor nonlinear parameters, phase noise jitter parameters, and frequency noise jitter parameters. Among them, the capacitor and inductor nonlinear parameters include the inductance value L and the capacitance value of different gears, that is, each enabled effective capacitance value .

[0063] As for the reference clock, the phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are mainly obtained based on the crystal and crystal oscillator jitter indicators measured in the laboratory.

[0064] Step 103: Insert the nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete the nonlinear modeling, and build a digital-analog hybrid pre-simulation environment in conjunction with the digital RTL (register-transfer level).

[0065] After obtaining the nonlinear parameters and jitter clock parameters, they are inserted into the extracted Verilog circuit model to complete the nonlinear modeling, thus completing the modeling of the simulation part.

[0066] Based on the Verilog circuit model of nonlinear modeling, in this embodiment, digital RTL is used to complete the construction of a digital-analog mixed pre-simulation environment, and the pre-simulation verification of the clock chip can be achieved through the simulation environment.

[0067] Step 104 , applying a test stimulus in a pre-simulation environment to lock the phase-locked loop, and periodically collecting data to calculate the jitter index, thereby completing the pre-simulation verification of the clock chip.

[0068] In the simulation environment, a test stimulus is applied to lock the phase-locked loop. When the phase-locked loop is locked, the DCO frequency is periodically sampled, and the jitter index is calculated based on the periodically sampled frequency data. Whether the simulation verification has passed is determined by judging whether the jitter index meets expectations.

[0069] In practical applications, it is necessary to configure different locking frequencies to control the phase-locked loop to lock, and to judge the jitter index at different locking frequencies to complete the verification. In this embodiment, the typical frequency point frequency, upper and lower boundary working frequencies, and random frequency point use cases within the working range of the generated clock are configured according to the chip specifications, and these use cases are configured to verify the phase-locked loop lock.

[0070] Furthermore, after the DCO frequency is periodically collected, the cycle-to-cycle jitter RMS value and the mean jitter of 12KHz-20MHz are calculated, and the simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

[0071] Introducing nonlinear parameters during pre-simulation can allow for rapid iteration of pre-simulation and improve verification efficiency.

[0072] Example 2

[0073] Please refer to Figure 8 This embodiment proposes a digital-analog hybrid verification method for a clock chip, which is mainly used in post-simulation verification of the clock chip, including:

[0074] Step 201: Build a test top layer based on the analog circuit top layer of the clock chip, and extract the analog Verilog circuit model.

[0075] The same as the pre-simulation process of Example 1, since the clock chip needs to verify the analog circuit and the digital circuit, but due to the different design platforms, mixed verification cannot be performed directly. This embodiment also converts the analog circuit into an analog Verilog circuit model, and completes the mixed test of the analog circuit and the digital circuit under Verilog.

[0076] Step 202: Use analog circuits to complete module-level simulation to obtain nonlinear parameters and jitter clock parameters.

[0077] Post-simulation needs to consider actual device delay and line delay, including parasitic resistance, capacitance, interconnection delay and other factors, taking into account actual physical parameters, which is closer to the operation of real devices. Therefore, in this embodiment, module-level post-simulation is performed by simulating the circuit to obtain nonlinear parameters of the process corner, so as to introduce nonlinear parameters into the simulation process.

[0078] Specifically, for DTC, the module-level DTC post-simulation is completed through the analog circuit to obtain the delay values ​​corresponding to all control words of each process corner. For details, please refer to Figure 6 For TDC, the module-level TDC post-simulation is completed through analog circuits to obtain the different delays of each process corner at each level. ..... , ..... , ...... , please refer to Figure 7 For DCO, the module-level DCO post-simulation is completed through the analog circuit to obtain the nonlinear parameters of capacitance and inductance at each process angle, phase noise jitter parameters, and frequency noise jitter parameters; among them, the nonlinear parameters of capacitance and inductance include the inductance value L and the capacitance value of different gears, that is, each enabled effective capacitance value .

[0079] In integrated circuit design, process corners refer to a series of extreme values ​​that the electrical characteristics of transistors may reach under a specific manufacturing process. These extreme values ​​usually include the fastest, slowest, and typical device performance. Process corners are crucial to circuit design because they represent the performance fluctuations that actual chips may exhibit under different process conditions. The main types of process corners include: TT (Typical Typical): NMOS and PMOS are both in typical conditions, usually used for preliminary circuit design and simulation; FF (Fast Fast): NMOS and PMOS are both in the fastest condition, when the device switches at the fastest speed; SS (Slow Slow): NMOS and PMOS are both in the slowest condition, when the device switches at the slowest speed; FS (Fast Slow): NMOS is in the fastest condition, while PMOS is in the slowest condition, or vice versa FS (Slow Fast); SF (SlowFast): NMOS is in the slowest condition, while PMOS is in the fastest condition, or vice versa SF (Fast Slow).

[0080] In this embodiment, the control words and nonlinear parameters of delay under the three process angles of TT, FF and SS are mainly obtained. In other embodiments, the control words and nonlinear parameters of delay under other process angles can also be obtained.

[0081] Furthermore, similar to the pre-simulation of Example 1, in the post-simulation process, the phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are obtained according to the crystal and crystal oscillator jitter indicators measured in the laboratory, so as to reflect the frequency deviation and phase jitter of the reference clock under real conditions.

[0082] Step 203: insert the nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete the nonlinear modeling, and build a mixed digital-analog simulation environment with the digital netlist.

[0083] Different from the pre-simulation, after the nonlinear modeling of the Verilog circuit model is completed using nonlinear parameters and jitter clock parameters, a mixed digital-analog post-simulation environment is built in conjunction with the digital netlist.

[0084] Step 204: Apply test stimulus in the digital-analog hybrid simulation environment to lock the phase-locked loop, and periodically collect data to calculate the jitter index, thereby completing the digital-analog hybrid simulation verification of the clock chip.

[0085] Finally, in the post-simulation environment, test excitation is applied to lock the phase-locked loop. When locked, the DCO frequency is periodically sampled, and the jitter index is calculated based on the periodically sampled frequency data. Whether the simulation verification passes is determined by judging whether the jitter index meets expectations.

[0086] Similar to the pre-simulation process, in the post-simulation process, it is also necessary to configure different locking frequencies to control the phase-locked loop locking, and to judge the jitter index at different locking frequencies to complete the verification.

[0087] According to the chip specification configuration, the typical frequency point frequency, upper and lower boundary operating frequency, and random frequency point use cases within the working range of the generated clock are configured, and these use cases are configured separately to make the phase-locked loop locked for verification.

[0088] Furthermore, after the DCO frequency is periodically collected, the cycle-to-cycle jitter RMS value and the mean jitter of 12KHz-20MHz are calculated, and the simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

[0089] Through the clock chip digital-analog hybrid simulation verification method proposed in this embodiment, nonlinear parameters are used in the simulation process, which are closer to real parameters, making the simulation more accurate and the iteration speed faster.

[0090] In practical applications, the clock chip digital-analog mixed verification method proposed in the present invention can be applied alone to the pre-simulation process, or can be applied alone to the post-simulation process, or can be applied to the entire pre- and post-simulation verification process.

[0091] An embodiment of the present invention further proposes a system, including a memory and a processor, wherein the memory stores a computer program corresponding to the digital-analog hybrid verification method for a clock chip as described above, which can be loaded and executed by the processor.

[0092] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program includes a program code for executing the method shown in the flowchart.

[0093] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0094] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0095] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0096] As another aspect, the present application further provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the digital-analog hybrid verification method for a clock chip described in the above embodiment.

[0097] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the digital-analog hybrid verification method of the clock chip described in the above embodiment.

[0098] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0099] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation method of the present application.

[0100] For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific situations; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0101] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A digital-analog hybrid verification method for a clock chip, characterized in that: Applied in pre-simulation, including: Build the test top layer based on the analog circuit top layer of the clock chip and extract the analog Verilog circuit model; Using analog circuits to complete module-level pre-simulation, nonlinear parameters and jitter clock parameters are obtained; the nonlinear parameters include nonlinear parameters of DTC control words and delays, nonlinear parameters of different delays at each level of the delay architecture TDC, and nonlinear parameters of DCO capacitors and inductors, phase modulation noise jitter parameters, and frequency modulation noise jitter parameters; the jitter clock parameters include phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock; Insert nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and build a mixed-analog pre-simulation environment with digital RTL; In the pre-simulation environment of digital-analog hybrid, the test stimulus is applied to lock the phase-locked loop, and the data is periodically collected to calculate the jitter index, thus completing the pre-simulation verification of the clock chip.

2. The digital-analog hybrid verification method for a clock chip according to claim 1, characterized in that: The nonlinear parameter acquisition process includes: Complete module-level DTC pre-simulation through analog circuits to obtain its control word and delay nonlinear parameters; Complete module-level TDC pre-simulation through analog circuits to obtain nonlinear parameters of the delay architecture TDC; The module-level DCO pre-simulation is completed through analog circuits to obtain its capacitor and inductor nonlinear parameters, phase modulation noise jitter parameters, and frequency modulation noise jitter parameters.

3. The digital-analog hybrid verification method for a clock chip according to claim 1 or 2, characterized in that: The jitter clock parameter acquisition process includes: The phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are obtained based on the crystal and crystal oscillator jitter indicators measured in the laboratory.

4. The digital-analog hybrid verification method for a clock chip according to claim 1, characterized in that: When the test stimulus is applied to lock the phase-locked loop, the typical frequency point frequency of the clock operation, the upper and lower boundary operating frequencies, and random frequency point use cases within the working range are generated according to the chip specification configuration, and the generated use cases are configured separately to verify the phase-locked loop locking.

5. The digital-analog hybrid verification method for a clock chip according to claim 1, characterized in that: The periodic data collection calculates the jitter index and completes the pre-simulation verification of the clock chip before the digital-analog hybrid, specifically including: After the phase-locked loop is locked, the DCO frequency is periodically sampled, and the cycle-to-cycle root mean square jitter value and the mean jitter of 12KHz-20MHz are calculated. The simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

6. A digital-analog hybrid verification method for a clock chip, characterized in that: Applied in post-simulation, including: Build the test top layer based on the analog circuit top layer of the clock chip and extract the analog Verilog circuit model; The module-level post-simulation is completed by using an analog circuit to obtain nonlinear parameters and jitter clock parameters; the nonlinear parameters include delay values ​​corresponding to all control words of each process corner of DTC, different delays of each level of each process corner of TDC, nonlinear parameters of capacitance and inductance of each process corner of DCO, phase modulation noise jitter parameters and frequency modulation noise jitter parameters, wherein the process corners include TT, FF, and SS; the jitter clock parameters include phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock; Insert nonlinear parameters and jitter clock parameters into the Verilog circuit model to complete nonlinear modeling, and build a mixed digital-analog simulation environment with the digital netlist; In the mixed-analog post-simulation environment, test excitation is applied to lock the phase-locked loop, and data is periodically collected to calculate the jitter index, completing the mixed-analog post-simulation verification of the clock chip.

7. The digital-analog hybrid verification method for a clock chip according to claim 6, characterized in that: The nonlinear parameter acquisition process includes: Complete module-level DTC post-simulation through analog circuits to obtain the delay values ​​corresponding to all control words at each process corner; Complete module-level TDC post-simulation through analog circuits to obtain different delays at each level of each process corner; The module-level DCO post-simulation is completed through analog circuits to obtain the nonlinear parameters of capacitors and inductors, phase modulation noise jitter parameters, and frequency modulation noise jitter parameters of each process corner; among them, the process corners include TT, FF, and SS.

8. The digital-analog hybrid verification method for a clock chip according to claim 6 or 7, characterized in that: The jitter clock parameter acquisition process includes: The phase modulation noise jitter parameters and frequency modulation noise jitter parameters of the reference clock are obtained based on the crystal and crystal oscillator jitter indicators measured in the laboratory.

9. The digital-analog hybrid verification method for a clock chip according to claim 6, characterized in that: When the test stimulus is applied to lock the phase-locked loop, the typical frequency point frequency of the clock operation, the upper and lower boundary operating frequencies, and random frequency point use cases within the working range are generated according to the chip specification configuration, and the generated use cases are configured separately to verify the phase-locked loop locking.

10. The digital-analog hybrid verification method for a clock chip according to claim 6, characterized in that: The periodic data acquisition calculates the jitter index and completes the digital-analog hybrid simulation verification of the clock chip, specifically including: After the phase-locked loop is locked, the DCO frequency is periodically sampled, and the cycle-to-cycle root mean square jitter value and the mean jitter of 12KHz-20MHz are calculated. The simulation verification is completed by judging whether the jitter value is consistent with the design expectation.

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