A DNN computing engine
By designing a DNN computing engine, the problems of insufficient flexibility and versatility in multi-core DNN accelerator systems are solved, achieving higher computing throughput and bandwidth utilization flexibility, and improving the performance of multi-core DNN accelerator systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2024-10-14
- Publication Date
- 2026-05-29
AI Technical Summary
Existing single-core DNN accelerator systems lack flexibility and versatility, making it difficult to achieve performance improvements in multi-core DNN accelerator systems. Furthermore, their bandwidth allocation and task scheduling strategies are not flexible enough.
A DNN computation engine is designed, including a compiler, an input feature cache block, an input feature rearrangement module, a weight cache block, and a computation array. DNN computation engines of different scales are implemented through engine parameterization, supporting the scalability and flexibility of multi-core DNN accelerator systems.
It improves the computational throughput and bandwidth utilization flexibility of multi-core DNN accelerator systems, making it suitable as a single computing engine for multi-core DNN accelerator systems, and achieving higher computational performance and task scheduling flexibility.
Smart Images
Figure CN119204129B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of deep learning technology, and more specifically, to a DNN computing engine. Background Technology
[0002] With the rapid development of artificial intelligence technology, deep neural networks (DNNs) have become key tools for solving many complex problems such as image recognition, speech recognition, and natural language processing. However, as the complexity of task scenarios increases dramatically, single-core DNN accelerator systems are struggling to meet the computational performance requirements of these scenarios. Multi-core DNN accelerator systems, which employ multiple single-core DNN accelerators, offer higher performance and have therefore received extensive research attention.
[0003] However, current single-core DNN accelerators are primarily focused on hardware designs for specific DNN networks, resulting in limited flexibility and scalability. When used in multi-core DNN accelerator systems, they fail to achieve performance proportional to the number of accelerators. Furthermore, the specialized design of single-core DNN accelerators makes it difficult to deploy more flexible bandwidth allocation and task scheduling strategies in such multi-core DNN accelerator systems, hindering significant performance improvements from multi-core implementation. Summary of the Invention
[0004] To overcome the shortcomings of the existing multi-core DNN accelerators in terms of flexibility and versatility, this invention provides a DNN computing engine.
[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:
[0006] Firstly, a DNN computation engine includes:
[0007] The compiler is used to obtain engine parameters, which include data precision, input channel expansion coefficients, and output channel expansion coefficients.
[0008] An input feature buffer block is used to read and cache the original input feature map to be convolved in the DNN network; wherein, the number of the input feature buffer blocks is determined according to the input channel unrolling coefficient;
[0009] The input feature reordering module is used to reorder the original input feature map based on im2col and output the reordered feature map to transform the convolution operation into matrix-vector multiplication.
[0010] A first selector is used for mode switching; wherein, when the computing engine is working in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine is working in a non-first-layer computing mode, the first selector selects the original input feature map as the output.
[0011] A weight buffer block is used to read and cache the convolutional layer parameters of the DNN network; wherein, the number of weight buffer blocks is determined according to the output channel unrolling coefficient, and the data bit width of the weight buffer block is determined according to the input channel unrolling coefficient and the data precision;
[0012] The computation array includes multiple parallel computation channels for reading the output of the first selector and the convolutional layer parameters to perform convolutional layer computations and obtain an output feature map; wherein the number of computation channels is determined according to the output channel unrolling coefficient.
[0013] Secondly, a multi-core DNN accelerator system includes several DNN computing engines as described in the first aspect.
[0014] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:
[0015] This invention discloses an accelerator hardware system architecture suitable for DNN networks, comprising multiple input feature buffer blocks, multiple weight buffer blocks, an input feature rearrangement module, a first selector for mode switching, and a computing array. Furthermore, based on engine parameters introduced by the compiler, DNN computing engines of different scales can be generated according to different application scenarios, such as bandwidth constraints / computational resource constraints. It has good scalability and high computational throughput, and is more flexible in bandwidth usage and task scheduling, making it more suitable as a single computing engine in a multi-core DNN accelerator system. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of the computing engine described in the embodiments of this application;
[0017] Figure 2 This is a flowchart illustrating the non-first-layer computing mode described in the embodiments of this application;
[0018] Figure 3 This is a flowchart illustrating the first-layer computing mode described in the embodiments of this application;
[0019] Figure 4 This is a schematic diagram of the input feature rearrangement module described in the embodiments of this application;
[0020] Figure 5 This is a schematic diagram illustrating the computation and data transmission granularity of the computing engine described in the embodiments of this application. Detailed Implementation
[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the description of embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to those processes, methods, products, or apparatuses. The term "determine" broadly covers a wide variety of actions, including acquiring, calculating, processing, deriving, investigating, searching (e.g., searching in a table, database, or other data structure), probing, and similar actions; it may also include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and similar actions; it may also include generating, creating, establishing, and similar actions; and parsing, selecting, choosing, and similar actions, etc. Definitions of other terms will be given in the following description.
[0022] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.
[0023] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent.
[0024] To better illustrate this embodiment, some parts in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions;
[0025] It will be understood by those skilled in the art that certain well-known structures and their descriptions may be omitted in the accompanying drawings.
[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0027] This embodiment provides a DNN computing engine, as shown in Figure 1, including:
[0028] The compiler is used to obtain engine parameters, which include data precision, input channel expansion coefficients, and output channel expansion coefficients.
[0029] An input feature buffer block is used to read and cache the original input feature map to be convolved in the DNN network; wherein, the number of the input feature buffer blocks is determined according to the input channel unrolling coefficient;
[0030] The input feature reordering module is used to reorder the original input feature map based on im2col and output the reordered feature map to transform the convolution operation into matrix-vector multiplication.
[0031] A first selector is used for mode switching; wherein, when the computing engine is working in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine is working in a non-first-layer computing mode, the first selector selects the original input feature map as the output.
[0032] A weight buffer block is used to read and cache the convolutional layer parameters of the DNN network; wherein, the number of weight buffer blocks is determined according to the output channel unrolling coefficient, and the data bit width of the weight buffer block is determined according to the input channel unrolling coefficient and the data precision;
[0033] The computation array includes multiple parallel computation channels for reading the output of the first selector and the convolutional layer parameters to perform convolutional layer computations and obtain an output feature map; wherein the number of computation channels is determined according to the output channel unrolling coefficient.
[0034] It is important to emphasize that the computing engine described in this embodiment is highly parameterized. The expansion coefficients of the input and output channels in the computing array, the number and data width of the input feature buffer blocks, the number and data width of the weight buffer blocks, the computational precision, and the system frequency can all be parameterized. These parameters can generate DNN computing engines of different scales according to different application scenarios, such as bandwidth constraints / computational resource constraints, making it more versatile.
[0035] It should be understood that the switching between different computing modes can be achieved by changing the control signal of the first selector.
[0036] It should be noted that in the first-layer computation mode, the original input feature map undergoes data rearrangement through the input feature rearrangement module, which transforms the convolution operation into matrix-vector multiplication, converting data with a lower number of channels into high-channel vector data and improving computational utilization. In non-first-layer computation modes, a direct convolution mapping computation strategy is adopted.
[0037] In some specific implementations, a non-first-layer computation mode is used to implement 2x2 convolution, with 2 output channels for the convolution and 2 input channels for the original input feature map. The DNN computation engine has 2 expansion coefficients for both its input and output channels. The DNN computation engine has 2 computation channels, and these 2 channels share the input feature map data. (See also...) Figure 2In the first computation cycle (see Figure 2(a)), the computation array receives the feature values of the original input feature map in the direction of the input channel, i.e., the I0 and J0 elements in the input feature map in Figure 2. For the weight values (i.e., the parameters of the convolution kernel matrix), different computation channels receive the weight values of different output channels. Specifically, for the first computation channel in Figure 2(a), it receives the weight values corresponding to the first output channel of the weight block, i.e., W0 and X0, while the second computation channel receives the weight values corresponding to the second output channel of the weight block, i.e., Y0 and Z0. At the same time, the result of the first cycle is stored in a register (identified by D). In the second cycle (see Figure 2(b)), the input feature map and weight block values are switched. The computation array receives the corresponding input channel values of the second element of the convolution kernel in the original input feature map, i.e., I1 and J1. The result of this cycle is accumulated with the result of the previous cycle and stored in a register, i.e., the output static data stream strategy is adopted. In the last cycle (see Figure 2(d)), all elements of the convolution kernel are traversed, and the computation array outputs the final values O and P.
[0038] It is important to emphasize that since the number of input channels in the first layer of a DNN network is typically 3, while the input channel expansion coefficients of a DNN computation engine are typically multiples of 32, the effective utilization of computational resources is very low. This embodiment therefore designs a first-layer computation mode suitable for the first layer computation of a DNN network. Referring to Figure 3, assume the convolutional layer performs a 2x2 convolution (stride 1), the number of convolutional output channels is 2, the number of input channels in the original input feature map is 2, the input channel expansion coefficients of the computation engine are 4, and the output channel expansion coefficients are 2. Since the input channel expansion coefficients of the DNN computation engine are greater than the number of input channels in the convolutional layer, adopting a non-first-layer computation mode for the DNN computation engine would result in half of the computational units in the computation array being ineffective. In the first-layer computation mode, the convolution operation is transformed into matrix multiplication by reordering the input feature map and the convolutional kernel matrix, converting the originally low-channel data into high-channel vector data, as shown in the middle sub-figure of Figure 3. In the first-layer computation mode, matrix multiplication is essentially performed. The number of columns in the rearranged input feature matrix is the kernel size multiplied by the number of input channels (i.e., 2×2×2=8). In this example, the DNN computation engine has 4 input channel expansion coefficients and 2 output channel expansion coefficients. Therefore, the multiplication and addition results of I0, J0, I1, J1 with W0, X0, W1, X1 and Y0, Z0, Y1, Z1 are calculated first and stored in a register, as shown in Figure 3(a). Then, the multiplication and addition results of I3, J3, I4, J4 with W2, X2, W3, X3 and Y2, Z2, Y3, Z3 are calculated and added to the results in Figure 3(a), thus calculating O0 and P0. The calculation process of O0-O3 and P1-P3 requires repeating this step, the difference being that the feature input part of the computation array corresponds to different rows of the rearranged input feature matrix.
[0039] It is important to note that in a DNN hardware accelerator, the original input feature map is an external input, i.e., non-fixed data, while the values of the convolution kernel matrix are parameters obtained by pre-training the DNN hardware accelerator and do not change during operation. Therefore, the rearrangement of the convolution kernel matrix can be achieved during the training of the DNN accelerator without the need for reordering the convolution kernel matrix on the hardware.
[0040] In some specific implementations, the computing engine can be implemented based on FPGA (Field Programmable Gate Array).
[0041] In some specific implementations, the input feature cache block and weight cache block are implemented based on SRAM (Static Random-Access Memory).
[0042] In some preferred embodiments, the input feature rearrangement module includes a second selector, a third selector, a fourth selector, a data preparation buffer, and a data buffer; referring to Figure 4 (it should be noted that, for ease of understanding, the several fourth selectors connected to the computing array are not shown in Figure 4), wherein,
[0043] The second selector is used to read the original input feature map from the input feature cache block and write it to the data preparation cache based on a ping-pong operation; and,
[0044] Each of the data preparation caches stores the original input feature map. Before all input channels Each piece of data is then pieced together to form a... × The matrix, This ensures that the rate of input feature rearrangement does not affect the computation rate of the computation array; and,
[0045] The data buffer receives the concatenated matrix from the data preparation buffer via the third selector, and its storage capacity is [missing information]. × , before A data buffer forms a read window, and the data within the read window is connected to the computation array through several fourth selectors to provide data for matrix multiplication; and, whenever the data buffer completes the computation of a pixel, all buffers within the data buffer are moved forward. Each data; whenever there is free space in the data cache. × When the data space is of a certain size, the data in the data preparation buffer is written into the data buffer; wherein, Indicates the height of the convolution kernel; Indicates the width of the convolution kernel; This represents the number of input feature map channels related to the original input feature map; This represents the expansion coefficient of the input channel; This represents the convolution stride.
[0046] In some specific implementations, two data preparation buffers are used to implement the ping-pong operation.
[0047] In some alternative embodiments, the computation engine uses convolutional layers as the scheduling granularity, the behavior of the output feature map as the computation granularity, and the original input feature map as the computation granularity. Behavioral data transmission granularity; pipelined processing is used between computation and data transmission.
[0048] It should be noted that the computing engine uses the DNN layer as the scheduling granularity. Based on the relevant information of the DNN layer, the execution time can be accurately predicted, thereby deploying a more flexible upper-layer task scheduling algorithm.
[0049] Furthermore, the computation engine computes at the behavior granularity of the convolutional layer (i.e., at the behavior granularity of the output feature map), and the corresponding off-chip memory access granularity is also at the behavior unit, enabling the computation and memory access stages to be piped, while improving the flexibility of bandwidth scheduling.
[0050] Figure 5 illustrates the computation and memory access granularity of the computation engine. In Figure 5(a), the original input feature map of the computed convolutional layer is shown, with N rows and multiple input channels, and the corresponding convolutional kernel size is... The step size is 1. Figure 5(b) shows the data transmission and computation process of the DNN computing engine. Based on the bandwidth allocated to the DNN computing engine, it can be divided into two categories:
[0051] 1. If the data transmission time is less than the calculation time, it is denoted as... ;
[0052] 2. If the calculation time is less than the transmission time, it is denoted as... .
[0053] Before the DNN computation engine runs, the convolutional kernel matrix corresponding to the convolutional layer needs to be read into the weight cache block within the DNN computation engine. Simultaneously, the first three rows of all input channels of the original input feature map need to be read into the input feature cache block within the DNN computation engine (denoted as M-1). After reading, the DNN computation engine can begin calculating the first row of the output feature map (denoted as C-1). During the calculation process, the next row of the original input feature map can be read in advance (denoted as M-2). Since the fourth row of the original input feature map has been read in advance, after the first three rows of the original input feature map are calculated, the calculation of the next row of the output feature map can begin directly. Therefore, by using the rows of the feature map for computation and memory access granularity, the computation and transmission stages overlap, significantly reducing the execution time of the DNN layer.
[0054] Furthermore, the calculation of the output features is defined. Figure 1 Time of travel The time of transmitting the original input feature map s rows When they are equal, that is The computing engine is allocated bandwidth of critical bandwidth. ;
[0055] When the computing engine is allocated bandwidth Above the critical bandwidth At that time, the latency of the computing engine To read the convolutional layer parameters and the original input feature map during initialization. The time consumed by the line and the calculation of the output feature map The sum of the time consumed by each line is expressed as follows:
[0056]
[0057] And, when the computing engine is allocated bandwidth Not higher than the critical bandwidth At that time, the latency of the computing engine The sum of the time for transmitting all the convolutional layer parameters and all rows of the original input feature map, and the time for calculating the last row of the output feature map, is expressed as follows:
[0058]
[0059] In the formula, This indicates the number of output feature map channels related to the output feature map; This represents the height of the original input feature map; This represents the width of the original input feature map; Indicates the data bit width.
[0060] Furthermore, the calculation of the output features Figure 1 Time of travel The expression is:
[0061]
[0062] And, the time for transmitting the original input feature map s rows. The expression is:
[0063]
[0064] In the formula, This represents the expansion coefficient of the output channel.
[0065] It should be noted that the computing engine employs pipelining between computation and data transmission, thus reducing the time required to compute one line. With transmission input feature map Time of travel They overlap. For convolutional layers of different sizes, their execution time varies depending on the time required to compute one row. With transmission input feature map Time of travel The larger value in the equation determines the outcome, i.e., the one that requires a longer time.
[0066] The designed DNN computation engine has a latency when computing convolutional layers. This can be represented as a piecewise function with the allocated bandwidth as the variable. The latency can be calculated based on the DNN computation engine design parameters, the calculated convolutional layer parameters, and the currently allocated bandwidth. As shown below:
[0067]
[0068] When the bandwidth allocated by the DNN computing engine is higher than the critical bandwidth During this time, the transmission needs to wait for the computation to complete, so the overall latency is the time required to read the convolution kernel matrix and input feature map during initialization. Time consumed by the line (in) (Identifier), and calculated output feature map Time consumed by the line (in) (Identification);
[0069] When the bandwidth allocated to the DNN computing engine is lower than the critical bandwidth At this time, the computation needs to wait for the transmission to finish, so the overall latency is the time required to transmit the weights of the entire convolutional layer and all rows of the input feature map (in words). (Identifier), and the time for calculating the last row of the output feature map. .
[0070] In some preferred embodiments, the computing array implements a static data stream output strategy based on registers and accumulation units at the output result, eliminating the need to access on-chip memory. Intermediate output results are reused at the register level (i.e., the output of the adder tree is accumulated with the previous output result), reducing memory access frequency. It should be understood that this computing architecture has high computational throughput and significantly reduces bandwidth utilization through the static data stream output strategy.
[0071] In some preferred embodiments, the computation channel consists of a multiplication array and an adder tree; wherein the multiplication array includes a plurality of multipliers and the adder tree includes a plurality of adders, which are responsible for adding the results of multiple multiplications.
[0072] In some alternative embodiments, the engine parameters also include speed levels; registers are inserted between each level in the adder tree according to the speed levels.
[0073] It should be noted that the speed levels map to different system frequency requirements. Register insertion is based on the principle of meeting speed level requirements, enabling the system to reach the required frequency with minimal register usage.
[0074] In some alternative embodiments, within the multiplication array of any of the computation channels, the first operand of all the multipliers is connected to the output of the first selector, and the second operand is connected to the convolutional layer parameters of the corresponding output channel in the weight buffer block.
[0075] In some specific implementations, the output channel expansion coefficient is 2. Therefore, the generated parallel computing architecture (i.e., computing array) has two computing channels, each consisting of a multiplication array and an adder tree. Taking the first computing channel as an example, the first operand of all multipliers in its multiplication array is connected to the output of the selector, and the second operand is connected to the weight corresponding to the first output channel in the weight buffer block. For the second computing channel, the first operand of all multipliers in the multiplication array shares the output of the selector, but the second operand corresponds to the weight of the second output channel in the weight buffer block.
[0076] This embodiment also provides a multi-core DNN accelerator system, including several DNN computing engines as described in the above embodiments.
[0077] In some specific implementations, several DNN computing engines can share a single compiler.
[0078] This embodiment also provides a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set. The at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor, causing the processor to perform some or all of the steps of the method provided in this application embodiment, including but not limited to first-level computing mode and non-first-level computing mode.
[0079] By way of example, the processor may be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.
[0080] In some examples, a computer program product is provided, which can be implemented by hardware, software, or a combination thereof. As a non-limiting example, the computer program product can be embodied in the storage medium, or it can be embodied in a software product, such as an SDK (Software Development Kit).
[0081] As a non-limiting example, a computer program product is provided, comprising a computer program or computer-executable instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer program or computer-executable instructions from the computer-readable storage medium, and executes the computer-executable instructions, causing the electronic device to perform some or all of the steps of the method described in the embodiments of this application.
[0082] In some examples, a computer program is provided, including computer-readable code, wherein, when the computer-readable code is run in a computer device, a processor in the computer device performs some or all of the steps for implementing the method.
[0083] The same or similar labels correspond to the same or similar parts;
[0084] The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this application.
[0085] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.
[0086] In different specific implementations, the methods or systems described in this application can be implemented in software, hardware, or a combination thereof. Furthermore, the order of the method steps can be changed, and various elements can be added, reordered, combined, omitted, or modified.
[0087] Obviously, the above embodiments of this application are merely examples for clearly illustrating this application, and are not intended to limit the implementation of this application, nor are they intended to limit this application. For those skilled in the art, other variations or modifications can be made based on the above description. The separate structural / functional modules or units can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part. The structure and function of the separate components can be implemented as a combined structure or component. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of the claims of this application.
Claims
1. A DNN computing engine, characterized in that, include: The compiler is used to obtain engine parameters, which include data precision, input channel expansion coefficients, and output channel expansion coefficients. An input feature buffer block is used to read and cache the original input feature map to be convolved in the DNN network; wherein, the number of the input feature buffer blocks is determined according to the input channel unrolling coefficient; The input feature reordering module is used to reorder the original input feature map based on im2col and output the reordered feature map to transform the convolution operation into matrix-vector multiplication. A first selector is used for mode switching; wherein, when the computing engine is working in the first-layer computing mode, the reordered feature map is selected as the output; when the computing engine is working in a non-first-layer computing mode, the first selector selects the original input feature map as the output. A weight buffer block is used to read and cache the convolutional layer parameters of the DNN network; wherein, the number of weight buffer blocks is determined according to the output channel unrolling coefficient, and the data bit width of the weight buffer block is determined according to the input channel unrolling coefficient and the data precision; The computation array comprises multiple parallel computation channels for reading the output of the first selector and the convolutional layer parameters to perform convolutional layer computations and obtain an output feature map; wherein, the number of computation channels is determined according to the output channel unrolling coefficients; The input feature rearrangement module includes a second selector, a third selector, a fourth selector, a data preparation buffer, and a data buffer; wherein, The second selector is used to read the original input feature map from the input feature cache block and write it to the data preparation cache based on a ping-pong operation; and, Each of the data preparation caches stores the original input feature map. Before all input channels Each piece of data is then pieced together into one. × The matrix, This ensures that the rate of input feature rearrangement does not affect the computation rate of the computation array; and, The data buffer receives the concatenated matrix from the data preparation buffer via the third selector, and its storage capacity is [missing information]. × , before A data buffer forms a read window, and the data within the read window is connected to the computation array through several fourth selectors to provide data for matrix multiplication; and, whenever the data buffer completes the computation of a pixel, all buffers within the data buffer are moved forward. Each data; whenever there is free space in the data cache. × When the data space is of a certain size, the data in the data preparation buffer is written into the data buffer; wherein, Indicates the height of the convolution kernel; Indicates the width of the convolution kernel; This represents the number of input feature map channels related to the original input feature map; This represents the expansion coefficient of the input channel; Indicates the convolution stride; The computation channel consists of a multiplication array and an adder tree; wherein the multiplication array includes several multipliers and the adder tree includes several adders, which are responsible for adding the results of multiple multiplications.
2. The DNN computing engine according to claim 1, characterized in that, The computation engine uses convolutional layers as the scheduling granularity, the output feature map as the computation granularity, and the original input feature map as the computation granularity. Behavioral data transmission granularity; pipelined processing is used between computation and data transmission.
3. A DNN computing engine according to claim 2, characterized in that: Define the time to compute one row of the output feature map. The time of transmitting the original input feature map s rows When they are equal, that is The computing engine is allocated bandwidth of critical bandwidth. ; When the computing engine is allocated bandwidth Above the critical bandwidth At that time, the latency of the computing engine To read the convolutional layer parameters and the original input feature map during initialization. The time consumed by the line and the calculation of the output feature map The sum of the time consumed by each line is expressed as follows: And, when the computing engine is allocated bandwidth Not higher than the critical bandwidth At that time, the latency of the computing engine The sum of the time for transmitting all the convolutional layer parameters and all rows of the original input feature map, and the time for calculating the last row of the output feature map, is expressed as follows: In the formula, This indicates the number of output feature map channels related to the output feature map; This represents the height of the original input feature map; This represents the width of the original input feature map; Indicates the data bit width.
4. A DNN computing engine according to claim 3, characterized in that, The time required to calculate one row of the output feature map. The expression is: And, the time for transmitting the original input feature map s rows. The expression is: In the formula, This represents the expansion coefficient of the output channel.
5. A DNN computing engine according to claim 1, characterized in that, The computing array implements a static data stream output strategy based on registers and accumulation units at the output result location, without needing to access on-chip memory, and reuses intermediate output results at the register level.
6. A DNN computing engine according to claim 1, characterized in that, The engine parameters also include speed levels; registers are inserted between each level in the adder tree according to the speed levels.
7. A DNN computing engine according to claim 6, characterized in that, Within the multiplication array of any of the computation channels, the first operand of all the multipliers is connected to the output of the first selector, and the second operand is connected to the convolutional layer parameters of the corresponding output channel in the weight buffer block.
8. A multi-core DNN accelerator system, characterized in that, It includes several DNN computing engines as described in any one of claims 1-7.