A quantum logic gate, a method for preparing a quadratic function quantum state, and a related device

Abstract

The application discloses a quantum logic gate, a quadratic function quantum state preparation method and related devices, and the quadratic function quantum state preparation method comprises the following steps: determining quantum bits for preparing a quadratic function quantum state; constructing a target quantum circuit, the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the quantum bits, each action time sequence comprises a first quantum logic gate, each first quantum logic gate acts on three quantum bits, and the first quantum logic gate acts on the lowest bit quantum bit and the adjacent quantum bit; and running the target quantum circuit to prepare the quadratic function quantum state. Compared with the prior art, the quadratic function quantum state preparation method provided by the application only needs O (n) layers or O (logn) layers, and can effectively compress the running time of a quantum computer.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum logic gate, a method for preparing a quadratic function quantum state, and related devices. Background Technology

[0002] Quantum computing is a novel computing paradigm that manipulates quantum information units to perform calculations according to the laws of quantum mechanics. Unlike classical computing, quantum computing follows the laws of quantum mechanics and is a new computing paradigm that can break through the limitations of classical computing power. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because of their ability to process mathematical problems more efficiently than ordinary computers; for example, they can accelerate the time to crack RSA keys from hundreds of years to hours.

[0003] Since the quadratic function is the first nontrivial polynomial function, its efficient preparation can play an important role and significance in the subsequent preparation of polynomials. The quadratic function can effectively approximate a large class of quantum states, thereby completing some efficient generation schemes for other functions. How to efficiently prepare the quantum state of the quadratic function in quantum computing has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a quantum logic gate, a method for preparing quadratic function quantum states, and related devices to solve the technical problems in the prior art. It enables the efficient preparation of quadratic function quantum states in quantum computing.

[0005] In a first aspect, the present invention provides a quantum logic gate, including a CX gate acting on a preset qubit and a controlled RY gate, wherein the timing of the controlled RY gate is located between the timings of the two CX gates, the target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate.

[0006] In a quantum logic gate as described above, preferably, the preset qubits include a first qubit, a second qubit, and a third qubit; the CX gate includes a first CX gate, a second CX gate, a third CX gate, and a fourth CX gate; the controlled RY gate includes a first controlled RY gate and a second controlled RY gate; the activation timing of the first controlled RY gate is between the activation timings of the first CX gate and the second CX gate; the activation timing of the second controlled RY gate is between the activation timings of the third CX gate and the fourth CX gate; and the activation timing of the third CX gate is after the activation timing of the second CX gate, wherein:

[0007] The target bits of both the first CX gate and the second CX gate are the first qubits, and the control bits of both the first CX gate and the second CX gate are the second qubits.

[0008] The target bits of the third CX gate and the fourth CX gate are both the first qubit, and the control bits of the third CX gate and the fourth CX gate are both the third qubit;

[0009] The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit;

[0010] The target bit of the second controlled RY gate is the third qubit, and the control bits of the second controlled RY gate are the first qubit and the second qubit.

[0011] In the quantum logic gate described above, preferably, the parameter values ​​of the first controlled RY gate are expressed as follows: The parameter values ​​of the second controlled RY gate are expressed as follows:

[0012] In a quantum logic gate as described above, preferably, the preset qubits include a first qubit and a second qubit, the CX gate includes a first CX gate and a second CX gate, the controlled RY gate includes a first controlled RY gate, and the activation timing of the first controlled RY gate is located between the activation timing of the first CX gate and the second CX gate, wherein:

[0013] The target bits of both the first CX gate and the second CX gate are the first qubits, and the control bits of both the first CX gate and the second CX gate are the second qubits.

[0014] The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit.

[0015] In the quantum logic gate described above, preferably, the parameter values ​​of the first controlled RY gate are expressed as follows:

[0016] Secondly, the present invention provides a method for preparing a quadratic function quantum state, the method comprising:

[0017] Determine the qubits used to prepare the quadratic function quantum state;

[0018] Construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on qubits, wherein:

[0019] The first quantum logic gate is the aforementioned quantum logic gate. Each action sequence includes one first quantum logic gate. Each first quantum logic gate acts on three qubits, ordered from the most significant qubit to the least significant qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the qubit number acted by the first quantum logic gate in the next action sequence is reduced by one compared to the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the least significant qubit.

[0020] The second quantum logic gate is the aforementioned quantum logic gate. The timing of the second quantum logic gate is after the timing of the first quantum logic gates. The first quantum logic gates act on the least significant qubit and the adjacent qubits.

[0021] The target quantum circuit is run to prepare the quadratic function quantum state.

[0022] In the quadratic function quantum state preparation method described above, preferably, the target quantum circuit further includes an H-gate acting on all qubits, wherein the H-gate is located after the multi-layer action timing of the first quantum logic gate and the second quantum logic gate on the qubits.

[0023] Thirdly, the present invention provides a device for preparing a quadratic function quantum state, the device comprising:

[0024] The acquisition module is used to determine the qubits used to prepare the quadratic function quantum state;

[0025] A target quantum circuit construction module is used to construct a target quantum circuit. The target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on qubits. Each action sequence includes one first quantum logic gate, and each first quantum logic gate acts on three qubits, ordered from the most significant qubit to the least significant qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the qubit number acted by the first quantum logic gate in the later action sequence is reduced by one compared to the previous action sequence, until the first quantum logic gate acts on the least significant qubit. The action sequence of the second quantum logic gate is located after the action sequences of multiple first quantum logic gates, and the first quantum logic gate acts on the least significant qubit and its adjacent qubits.

[0026] The execution module is used to run the target quantum circuit to prepare the quadratic function quantum state.

[0027] Fourthly, the present invention provides a storage medium storing a computer program, wherein the computer program is configured to implement the aforementioned method when run.

[0028] Fifthly, the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to implement the aforementioned method.

[0029] Compared with existing technologies, the quadratic function quantum state preparation method provided by this invention only requires O(n) or O(logn) layers of circuit depth, which can effectively compress the running time of quantum computers. Attached Figure Description

[0030] Figure 1 This is a network block diagram of a quantum circuit construction system provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of the structure of the first quantum logic gate provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of the second quantum logic gate provided in an embodiment of the present invention;

[0033] Figure 4 This is a flowchart of a method for preparing a quadratic function quantum state according to an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of a target quantum circuit provided in an embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of a quadratic function quantum state preparation device provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the structure of a deentangled quantum logic gate provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of the structure of a de-entangled quantum circuit provided in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of another target quantum circuit provided in an embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram of another de-entangled quantum circuit provided in an embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram of another target quantum circuit provided in an embodiment of the present invention. Detailed Implementation

[0041] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0042] [Structure of a quantum circuit construction system]

[0043] Figure 1 This is a network block diagram of a quantum circuit construction system provided in an embodiment of this application. The quantum circuit construction system may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0044] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit construction system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0045] Server 120 and client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0046] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) may be used to implement a quantum algorithm compiled according to the quantum circuit construction method provided in the embodiments of this application.

[0047] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0049] The aforementioned classical processing system 160 and quantum processing system 170 can be integrated into a single device or distributed across two different devices. For example, the first device, including the classical processing system 160, runs a classical computer operating system that provides quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum applications using the quantum application development tools and services on the second device and send the quantum program to the second device, including the quantum processing system 170, via the network services. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0050] In the classic silicon-based processing system 160, the units of the classic processor 161 are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of these computing units in a silicon chip is sufficient; currently, a classic processor contains tens of thousands of computing units. The sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0051] Unlike the logic units in the classical processing system 160, the basic computational unit of the quantum processor 171 in the quantum processing system 170 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logic function combinations to achieve computational effects.

[0052] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit's use) is crucial to improving the computational performance of quantum computers and requires specialized design. The aforementioned design considerations for qubits are technical issues that ordinary computing devices do not need to address.

[0053] [Structure of quantum logic gates and methods for preparing quadratic function quantum states]

[0054] The quadratic function is the first nontrivial polynomial function, and its efficient preparation can play an important role and significance in subsequent polynomial preparation. The embodiments provided in this invention aim to achieve... Efficient preparation of the state.

[0055] x 2 The walsh-transformed form is as follows (unnormalized).

[0056]

[0057] Now consider the form of the function after the Walsh transformation:

[0058]

[0059] We can then integrate these two parts to solve the problem. The final result can be expressed in the following form:

[0060]

[0061] make

[0062] in

[0063] Then we can deduce that:

[0064]

[0065] For an initial input state: |0> n-d |1> d What needs to be built is

[0066] Similar to SCSPP n,k The definition of a matrix is ​​as follows:

[0067] SCSPP n,k |0> k+1 =|0> k+1

[0068] SCSPP n,k |0>k-d |0>|1> d =|0> k-d SCSP n,d |0>|1> d

[0069] SCSPP n,k |1> k+1 =|1> k+1

[0070] in

[0071] Assume the input is:

[0072] |0> n-d |1> d via SCSPP n,k After the matrix is ​​applied, its quantum state becomes:

[0073]

[0074] At this point, U is applied to the first n-1 qubits. n-1 Therefore, we can obtain the following equation:

[0075]

[0076] Therefore, SCSPP was used. n,k The matrix can then be synthesized into U using a recursive method. n The door was then prepared.

[0077] The following is an example of SCSPP. n,k The matrix preparation method, since it involves a quadratic function, means that the input has at most two |1> states. (SCSPP) n,k A matrix is ​​a quantum logic gate, which includes a CX gate and a controlled RY gate acting on a preset number of qubits. The number of preset qubits is 2 or 3, and at most 3. The timing of the controlled RY gate is between the timing of the two CX gates. The target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate.

[0078] SCSPP n,k The matrix can be a first quantum logic gate operating on three qubits, or a second quantum logic gate operating on two qubits, where:

[0079] When SCSPP n,kWhen a matrix is ​​a first quantum logic gate operating on three qubits, the predefined qubits include a first qubit, a second qubit, and a third qubit. Each qubit within the quantum circuit needs to be uniquely identified; therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the quantum circuit are numbered sequentially from the most significant bit to the least significant bit. For example, referring to... Figure 2 As shown, the quantum circuit used to construct the first quantum logic gate has 3 qubits. The 3 qubits are numbered sequentially from 1 to 3 from the highest bit to the lowest bit. The first qubit is located at the bottom of the diagram and is also the highest bit. The third qubit is located at the top of the diagram and is also the lowest bit.

[0080] The CX gates include a first CX gate, a second CX gate, a third CX gate, and a fourth CX gate. The controlled RY gates include a first controlled RY gate and a second controlled RY gate. The activation timing of the first controlled RY gate is between the activation timings of the first and second CX gates. The activation timing of the second controlled RY gate is between the activation timings of the third and fourth CX gates. The activation timing of the third CX gate is after the activation timing of the second CX gate.

[0081] The target bits of the first and second CX gates are both first qubits, the control bits of the first and second CX gates are both second qubits, the target bits of the third and fourth CX gates are both first qubits, and the control bits of the third and fourth CX gates are both third qubits.

[0082] The target bit of the first controlled RY gate is the second qubit, the control bit of the first controlled RY gate is the first qubit, the target bit of the second controlled RY gate is the third qubit, and the control bit of the second controlled RY gate is the first qubit and the second qubit.

[0083] In one feasible implementation, the parameter value of the first controlled RY gate is expressed as: The parameter values ​​of the second controlled RY gate are expressed as follows: The parameter values ​​of the first and second controlled RY gates represent the proportion of the RY gate's segmentation of the |0> state, which is... The corresponding value.

[0084] When SCSPP n,k When a matrix is ​​a first quantum logic gate operating on three qubits, referencing Figure 3As shown, the preset qubits include a first qubit and a second qubit, the CX gates include a first CX gate and a second CX gate, and the controlled RY gates include a first controlled RY gate. The activation timing of the first controlled RY gate is between the activation timing of the first CX gate and the second CX gate, wherein:

[0085] The target bit of both the first CX gate and the second CX gate is the first qubit, and the control bit of both the first CX gate and the second CX gate is the second qubit. The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit.

[0086] In one feasible implementation, the parameter value of the first controlled RY gate is expressed as: The parameter value of the first controlled RY gate represents the ratio of the RY gate segmentation, that is... The corresponding value.

[0087] Reference Figure 4 as well as Figure 5 As shown, this invention provides a method for preparing a quadratic function quantum state, the method comprising:

[0088] Step S101: Determine the qubits to be used to prepare the quadratic function quantum state.

[0089] The number of qubits corresponding to a quadratic function quantum state can be predetermined, depending on the number of qubits supported by the quantum device. Generally, it is less than or equal to the number of qubits supported. When the number of qubits supported by the quantum device is relatively large, the number of qubits required for preparation can be selected as appropriate.

[0090] Step S102: Construct the target quantum circuit, which has a first quantum logic gate and a second quantum logic gate acting on the qubits, wherein:

[0091] Each qubit within the target quantum circuit needs to be uniquely identified. Therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the target quantum circuit are numbered sequentially from the most significant bit to the least significant bit. In each action sequence, the qubits are renumbered. The next action sequence ignores the first qubit in the previous action sequence and the qubits that were ignored in the previous action sequence. For example, the most significant qubit in the first action sequence is the first qubit, while in the second action sequence, the most significant qubit is ignored and the second most significant qubit is taken as the first qubit. In the third action sequence, the most significant and the second most significant qubits are ignored and the third most significant qubit is taken as the first qubit, and so on.

[0092] It should be noted that the target quantum circuit for preparing the quadratic function quantum state includes a first quantum logic gate located at n-2 different activation times and a second quantum logic gate located after the first quantum logic gate. Here, n is the number of qubits in the target quantum circuit for preparing the quadratic function quantum state. Each first quantum logic gate acts on three sequentially arranged qubits, and n-2 first quantum logic gates act on n qubits sequentially. The target quantum circuit passing through a first quantum logic gate reduces the number of qubits representing the quadratic function quantum state at the output of the target quantum circuit at that activation time by one compared to the number of qubits representing the quadratic function quantum state at the input. Therefore, passing through n-2 first quantum logic gates allows the quadratic function quantum state to be represented using only 2 qubits, effectively reducing the qubit resources required for preparing the quadratic function quantum state and saving classical hardware resources for quantum computing simulation or quantum hardware resources for actual quantum computing.

[0093] Specifically, each action sequence includes a first quantum logic gate, and each first quantum logic gate acts on three qubits, ordered from the most significant qubit to the least significant qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the first quantum logic gate of the next action sequence acts on qubits with a qubit number one less than the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the least significant qubit.

[0094] That is, starting from the highest-order qubit, the qubits are numbered 1, 2, ..., n. In the initial activation sequence, qubits 1, 2, and 3 are all activated by the first quantum logic gate, acting as the first, second, and third qubits within that gate, respectively. In the second activation sequence, another first quantum logic gate is activated. Since the qubit number activated by the first quantum logic gate in the later activation sequence is one less than that in the earlier sequence, the first quantum logic gate activates qubits 2, 3, and 4 in the second activation sequence. Qubits 3 and 4 are respectively used as the first, second, and third qubits within the first quantum logic gate. In the third action sequence, a first quantum logic gate is also used. Since the qubit number used by the first quantum logic gate in the later action sequence is one less than the qubit number used by the first quantum logic gate in the previous action sequence, in the third action sequence, the first quantum logic gate acts on qubits 3, 4, and 5. Qubits 3, 4, and 5 are respectively used as the first, second, and third qubits within the first quantum logic gate, and so on, until the first quantum logic gate acts on the least significant qubit.

[0095] Based on the aforementioned first quantum logic gate, the first quantum logic gate includes a first CX gate, a second CX gate, a third CX gate, a fourth CX gate, a first controlled RY gate, and a second controlled RY gate. Within the execution timing of the first quantum logic gate, the execution timing of the first controlled RY gate is between the execution timings of the first CX gate and the second CX gate; the execution timing of the second controlled RY gate is between the execution timings of the third CX gate and the fourth CX gate; and the execution timing of the third CX gate is after the execution timing of the second CX gate. Wherein:

[0096] The target bits of the first CX gate and the second CX gate are both the first qubit, and the control bits of the first CX gate and the second CX gate are both the second qubit; the target bits of the third CX gate and the fourth CX gate are both the first qubit, and the control bits of the third CX gate and the fourth CX gate are both the third qubit; the target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit; the target bit of the second controlled RY gate is the third qubit, and the control bits of the second controlled RY gate are the first qubit and the second qubit.

[0097] After all the first quantum logic gates have been applied, a second quantum logic gate is applied to the least significant qubit and its adjacent qubits. The second quantum logic gate includes a first CX gate, a second CX gate, and a first controlled RY gate. During the application sequence of the second quantum logic gate, the application sequence of the first controlled RY gate is between the application sequences of the first CX gate and the second CX gate. Specifically, the second least significant qubit and the least significant qubit serve as the first and second qubits in the second quantum logic gate, respectively. The target qubits of both the first and second CX gates are the second least significant qubits, and the control qubits of both the first and second CX gates are the least significant qubits. The target qubit of the first controlled RY gate is the least significant qubit, and the control qubit of the first controlled RY gate is the second least significant qubit.

[0098] The target quantum circuit also includes H gates that act on all qubits, wherein the H gates are located after the multi-level action timing of the first and second quantum logic gates on the qubits.

[0099] Step S103: Run the target quantum circuit to prepare a quadratic function quantum state. In the specific preparation process, first obtain the target quantum circuit, then run the quantum operations corresponding to the target quantum circuit on the quantum chip to prepare the quadratic function quantum state.

[0100] Based on the quadratic function quantum state preparation method provided in the above embodiments, the circuit depth only needs to be O(n) layers, which can effectively compress the running time of quantum computers.

[0101] Device for preparing quadratic function quantum states

[0102] See Figure 6 As shown, the quadratic function quantum state preparation device includes:

[0103] The acquisition module is used to determine the qubits used to prepare the quadratic function quantum state;

[0104] The target quantum circuit construction module is used to construct the target quantum circuit. The target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the qubits. Each action sequence includes one first quantum logic gate, and each first quantum logic gate acts on three qubits, ordered from the most significant qubit to the least significant qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the first quantum logic gate of the later action sequence acts on qubits with a number one lower than the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the least significant qubit. The action sequence of the second quantum logic gate is located after the action sequence of multiple first quantum logic gates. The first quantum logic gate acts on the least significant qubit and its adjacent qubits.

[0105] The execution module is used to run the target quantum circuit to prepare a quadratic function quantum state.

[0106] The operating module is a quantum system capable of running quantum circuits. For example, a quantum hardware system including a quantum processor and a quantum measurement and control system with communication connection is a system. The quantum processor refers to a quantum chip, and the quantum measurement and control system is used to provide analog signals to implement the quantum logic gates in the quantum circuit. The analog signals act on the quantum chip to realize the operation of the quantum circuit.

[0107] [Structure of storage media]

[0108] This invention also provides a storage medium storing a computer program, wherein the computer program is configured to implement the steps in any of the above method embodiments when running.

[0109] Specifically, in this embodiment, the storage medium can be configured to store a computer program for implementing the following steps:

[0110] Step S101: Determine the qubits to be used to prepare the quadratic function quantum state.

[0111] Step S102: Construct the target quantum circuit, which has a first quantum logic gate and a second quantum logic gate acting on the qubits. Each action sequence includes a first quantum logic gate, and each first quantum logic gate acts on three qubits, ordered from the highest-order qubit to the lowest-order qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the first quantum logic gate of the later action sequence acts on qubits with an order number one lower than the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest-order qubit. The action sequence of the second quantum logic gate is located after the action sequences of multiple first quantum logic gates, and the first quantum logic gate acts on the lowest-order qubit and the adjacent qubits.

[0112] Step S103: Run the target quantum circuit to prepare a quadratic function quantum state.

[0113] Structure of electronic devices

[0114] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to implement the steps in any of the above method embodiments.

[0115] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0116] Specifically, in this embodiment, the processor described above can be configured to implement the following steps via a computer program:

[0117] Step S101: Determine the qubits to be used to prepare the quadratic function quantum state.

[0118] Step S102: Construct the target quantum circuit, which has a first quantum logic gate and a second quantum logic gate acting on the qubits. Each action sequence includes a first quantum logic gate, and each first quantum logic gate acts on three qubits, ordered from the highest-order qubit to the lowest-order qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the first quantum logic gate of the later action sequence acts on qubits with an order number one lower than the first quantum logic gate of the previous action sequence, until the first quantum logic gate acts on the lowest-order qubit. The action sequence of the second quantum logic gate is located after the action sequences of multiple first quantum logic gates, and the first quantum logic gate acts on the lowest-order qubit and the adjacent qubits.

[0119] Step S103: Run the target quantum circuit to prepare a quadratic function quantum state.

[0120] [Methods for Constructing Unentangled Quantum Logic Gates]

[0121] In the embodiments provided by the present invention, a de-entangled quantum logic gate is also provided. This entangled quantum logic gate is used to realize controlled rotation operation between two entangled qubits, and the quantum states of the two qubits are switched between the |01> state and the |10> state.

[0122] Its constructed unentangled quantum logic gate reference Figure 7 As shown, the construction method includes:

[0123] S201: Determine two qubits and obtain the first H gate, the parametric RY gate, and the second H gate that are sequentially applied to each qubit; wherein, the angle parameters of the parametric RY gates of the two qubits are opposites, and the absolute value of the angle parameters of the parametric RY gates is jointly determined by the quantum state amplitude value of each qubit.

[0124] S202: A first controlled rotation gate is constructed at both the first and second evolution timings on the two qubits. Preferably, the first controlled rotation gate is a controlled Z gate, and the control bits of the two first controlled rotation gates are on the same qubit. The first evolution timing is the timing between the first H gate and the parametric RY gate, and the second evolution timing is the timing between the parametric RY gate and the second H gate.

[0125] [Methods for preparing quadratic function quantum states at shallower circuit depths]

[0126] Suppose that the initial state of a certain unentangled quantum circuit is the quadratic function quantum state to be prepared; then, by unentanglementing the quadratic function quantum state, a quantum circuit that evolves the target quantum state to the state can be obtained. The above steps are a classical process that can be implemented using a quantum simulator.

[0127] Furthermore, the inverse circuit of the above-mentioned unentangled quantum circuit can be constructed to obtain the target quantum circuit. The target quantum circuit is then run and applied to the initial state |0> n This allows for the fabrication of quadratic function quantum states on real quantum chips by placing them on qubits of the quadratic state.

[0128] In one feasible implementation, the present invention provides a method for preparing a quadratic function quantum state, comprising the following steps:

[0129] Step S301: Determine the qubits to be used to prepare the quadratic function quantum state.

[0130] Step S302: Multiple unentangled quantum logic gates are applied to a qubit whose initial state is a quadratic function quantum state, resulting in a unentangled quantum circuit. The unentangled quantum circuit is used to evolve the quadratic function quantum state into |0> n The unentangled quantum logic gates are constructed using the aforementioned method, wherein the interaction relationship between the unentangled quantum logic gates and qubits in the later layer of the interaction sequence is determined by the interaction relationship between the unentangled quantum logic gates and qubits in the previous layer of the interaction sequence.

[0131] In a de-entangled quantum circuit, each de-entangled quantum logic gate acts on two preset qubits. These two qubits can be two adjacent qubits or two qubits at positions separated by a gap, depending on the circuit configuration. No limitation is made here. Along the action sequence, multiple de-entangled quantum logic gates are distributed in multiple layers. Each layer of de-entangled quantum logic gates includes at least one de-entangled quantum logic gate, and the de-entangled quantum logic gates in the same layer all act on the same action sequence.

[0132] In deentangled quantum circuits, deentangled quantum logic gates play a role in deentangled two qubits. After the deentangled quantum circuit passes through two qubits, the deentanglement of these two qubits is completed. After each layer of deentangled quantum logic gates, some qubits in the target quantum state become mutually deentangled until all layers have passed, resulting in an approximate |0> n state.

[0133] Step S303: Determine the inverse circuit of the deentangled quantum circuit as the target quantum circuit. The target quantum circuit has a target quantum logic gate, which is determined based on the deentangled quantum logic gate. Specifically, the interaction relationship between the target quantum logic gate and the qubit in the previous layer's interaction timing is determined by the interaction relationship between the target quantum logic gate and the qubit in the next layer's interaction timing.

[0134] The number of target quantum logic gates in a target quantum circuit is the same as the number of unentangled quantum logic gates in a deentangled quantum circuit, while the execution timing of multiple target quantum logic gates is the opposite of that of multiple deentangled quantum logic gates.

[0135] The target quantum circuit is obtained by reverse engineering the de-entangled quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset qubits. These two qubits can be two adjacent qubits or two qubits at spaced positions. The pairwise qubits can be freely set. At the same time, the maximum parallel executable quantum gate pair must be satisfied to efficiently complete the de-entanglement. Along the action sequence, the multiple target quantum logic gates are distributed in multiple layers. Each layer of target quantum logic gates includes at least one target quantum logic gate. Target quantum logic gates in the same layer of target quantum logic gates all act on the same action sequence.

[0136] In the target quantum circuit, the target quantum logic gate functions to generate a predetermined entangled state between two qubits, with the initial state being |0> n After each layer of target quantum logic gate, some of the qubits in the state become entangled with each other until, after all the action sequences, a quadratic function quantum state is obtained.

[0137] Step S204: Run the target quantum circuit to prepare a quadratic function quantum state. In the specific preparation process, first obtain the target quantum circuit, and then run the quantum operation corresponding to the target quantum circuit on the quantum chip to prepare the quadratic function quantum state.

[0138] Based on the quadratic function quantum state preparation method provided in the above embodiments, the circuit depth only needs to be O(logn) layers, thereby realizing the qubit logarithmic preparation scheme of quadratic function quantum states, which can effectively compress the running time of quantum computers.

[0139] Furthermore, the specific method for determining the interaction relationship between the deentangled quantum logic gate and the qubit in the later layer's interaction timing from the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer's interaction timing is as follows:

[0140] Each qubit within a deentangled quantum circuit needs to be uniquely identified; therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the deentangled quantum circuit are numbered sequentially from the least significant bit to the most significant bit. For example, referring to... Figure 8 As shown, the unentangled quantum circuit has 8 qubits, which are numbered sequentially from 1 to 8. Qubit 1 is located at the top of the diagram, which is also the lowest qubit, and qubit 8 is located at the bottom of the diagram, which is also the highest qubit.

[0141] In each layer of the interaction sequence, the qubits are regrouped to form several qubit pairs. Each qubit pair includes a first qubit and a second qubit, with the first qubit being in a lower position than the second qubit. In each layer of the interaction sequence, each qubit pair is subjected to a deentangled quantum logic gate.

[0142] In the first layer of operation, the qubits are grouped sequentially from the least significant bit to the most significant bit, with each pair of qubits forming a qubit pair. These two qubits can be two adjacent qubits or two qubits at positions separated by a gap. Preferably, each pair of two adjacent qubits forms a qubit pair. Each qubit pair is subjected to a deentanglement quantum logic gate, thereby deentanglement of the two qubits. After the deentanglement quantum logic gate is applied to the two qubits, the deentanglement of the two qubits is completed, and the first or second qubit is evolved into the |0> state.

[0143] In other layers of the interaction sequence, several qubits are regrouped according to the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer of the interaction sequence to form a qubit set. The qubits in the qubit set come from the first or second qubit in each qubit pair in the previous layer of the interaction sequence that has not evolved to the |0> state. The qubits in the qubit set are grouped sequentially from the least significant bit to the most significant bit, and every two qubits form a qubit pair. These two qubits can be two qubits in adjacent positions or two qubits in positions that are separated by a gap. Preferably, every two adjacent qubits form a qubit pair, and each qubit pair is subjected to a deentangled quantum logic gate.

[0144] After each layer of deentangled quantum logic gates, some qubits in the target quantum state become unentangled with each other, until after all the interaction sequences, the initial approximate state |0> is obtained. n state.

[0145] The deentanglement quantum circuit provided by this invention can directly deentangle the first layer. The number of qubits, half the number of qubits remaining after the second layer of deentanglement. By continuing in this way, all entanglement can eventually be completed, and the depth of the line only needs to be O(logn) layers.

[0146] In one feasible implementation, refer to Figure 8 As shown, an example of a deentangled quantum circuit with 8 qubits will be used for illustration:

[0147] In the first layer of the interaction sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6] and [7,8]. Each qubit pair is subjected to an unentangled quantum logic gate, which limits the second qubit in the qubit pair to evolve into an approximate |0> state. That is, qubits 2, 4, 6 and 7 are in an approximate |0> state after being interacted.

[0148] After the first layer of interaction, the amplitude is approximately present in qubits 1, 3, 5, and 7. At this point, in the second layer of interaction, the remaining qubits are regrouped. This time, there are two qubit pairs, [1,3] and [5,7]. Each qubit pair is subjected to a deentanglement quantum logic gate, which limits the second qubit in the qubit pair to evolve into an approximate |0> state. That is, after qubits 3 and 7 are interacted, they are in an approximate |0> state.

[0149] After the second layer of interaction, the amplitude exists only on qubits 1 and 5. At this point, in the third layer of interaction, it is only necessary to apply the deentanglement quantum logic gate on qubits 1 and 5 to completely collapse the quantum states on qubits 1 and 5 into the |0> state.

[0150] For n qubits, let's first assume they are powers of 2, that is, n = 2. m Where m is a positive integer, in the first layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2 m -1,2 m ].

[0151] If the second qubit in a constrained qubit pair evolves into an approximate |0> state, then after the first layer of interaction timing, the remaining qubits with amplitude are qubits 1, 3, up to 2. m -1 qubit, in the second layer of the timing sequence, these remaining qubits are regrouped to obtain the following qubit pairs: [1,3],[5,7]......[2 m -3,2 m -1].

[0152] In this way, until the last layer, only two qubits remain to be grouped, requiring a total of m = logn layers of pairing.

[0153] When considering n qubits that are not exponents of 2, the highest-order qubit is not grouped during the first layer of operation. It is only during the second layer of operation that the highest-order qubit is included in the grouping.

[0154] The following example uses 7 qubits:

[0155] Reference Figure 10 As shown, in the first layer of the interaction sequence, there are three qubit pairs: [1,2], [3,4], [5,6], and the remaining qubit number 7 is not grouped.

[0156] In the second layer of the timing sequence, qubit 7 is included in the grouping range, and the qubit pair is two: [1,3], [5,7].

[0157] In the third layer of the interaction sequence, the qubit pair is [1,5].

[0158] In the embodiments provided by this invention, the specific method for determining the interaction relationship between the target quantum logic gate and the qubit in the previous layer's interaction timing sequence of the target quantum circuit from the interaction relationship between the target quantum logic gate and the qubit in the next layer's interaction timing sequence is as follows:

[0159] In each layer of the interaction sequence, the qubits are regrouped to form several qubit pairs. Different qubit pairs contain different qubits. Each qubit pair includes a first qubit and a second qubit. The first qubit is in a lower position than the second qubit. In each layer of the interaction sequence, each qubit pair is interacted with a target quantum logic gate.

[0160] In the final layer of the interaction sequence, the qubits from the least significant bit to the most significant bit are grouped sequentially, with each pair of adjacent qubits forming a qubit pair. In the final layer of the interaction sequence, each pair of adjacent qubits is interacted with a target quantum logic gate. Since the target quantum circuit is derived by reverse engineering from the deentangled quantum circuit, the qubit pairs interacted by the target quantum logic gate in the final layer of the interaction sequence are the same as the qubit pairs interacted by the deentangled quantum logic gate in the first layer of the interaction sequence of the deentangled quantum circuit.

[0161] In other layers of interaction, several qubits are regrouped according to the interaction relationship between the target quantum logic gate and the qubits in the next layer of interaction, forming a qubit set. Within each qubit set, the qubits are grouped sequentially from the least significant bit to the most significant bit, forming qubit pairs. This can be derived from deentangled quantum circuits. For example, in the penultimate layer of interaction, the qubit pair interacting with the target quantum logic gate is the same as the qubit pair interacting with the deentangled quantum logic gate in the second layer of interaction of the deentangled quantum circuit. This process is repeated to obtain the qubit pairs for all interaction times of the target quantum circuit.

[0162] After each layer of target quantum logic gate, some of the qubits in the initial state become entangled with each other until, after all the action sequences, a quadratic function quantum state is obtained.

[0163] In one feasible implementation, refer to Figure 9 As shown, an example of a target quantum circuit with 8 qubits will be used for illustration:

[0164] In the final layer of the timing sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6] and [7,8], and each qubit pair is acted upon by a target quantum logic gate.

[0165] In the penultimate layer of the interaction sequence, there are two qubit pairs, [1,3] and [5,7], and each qubit pair is interacted with a conjugate transpose of a unitary matrix (the target quantum logic gate).

[0166] In the first layer of the interaction sequence, the target quantum logic gate is applied to qubits 1 and 5.

[0167] For n qubits, let's first assume they are powers of 2, that is, n = 2. m Where m is a positive integer, in the last layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2 m -1,2 m ].

[0168] In the penultimate engagement sequence, the qubits are rearranged to obtain the following qubit pairs: [1,3],[5,6]......[2 m -3,2 m -1].

[0169] By analogy with the first layer of timing, only two qubits remain to be grouped, requiring a total of m = logn layers of pairing.

[0170] When considering n qubits that are not exponents of 2, the highest-order qubits are not grouped in the last layer of the operational sequence.

[0171] The following example uses 7 qubits:

[0172] Reference Figure 11 As shown, in the last layer of the timing sequence, there are three qubit pairs: [1,2], [3,4], [5,6], and the remaining qubit number 7 is not grouped.

[0173] In the penultimate layer of the timing sequence, qubit 7 is included in the grouping range, and the qubit pair is two: [1,3], [5,7].

[0174] In the first layer of the interaction sequence, the qubit pair is [1,5].

[0175] The quantum state preparation method provided in the above embodiments requires only O(logn) layers of circuit depth, thereby enabling the logarithmic preparation scheme of quadratic function quantum states and effectively compressing the running time of quantum computers.

[0176] Furthermore, the deentangled quantum circuit also includes a second controlled rotation gate acting after each deentangled quantum gate. The control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate. Preferably, the second controlled rotation gate is a controlled X gate. Figure 7 For example, the control bits of the first controlled rotating gate are qubits 1, 3, 5, and 7, and the target bits are qubits 2, 4, 6, and 8. The control bits of the second controlled rotating gate are qubits 2, 4, 6, and 8, and the target bits are qubits 1, 3, 5, and 7.

[0177] In the embodiments provided by this invention, the quantum state to be prepared is first considered to be: When n is even, we can apply unentangled quantum logic gates to it pairwise from left to right, and it will actually become the following quantum state:

[0178]

[0179] Then, the controlled X gate is controlled from left to right, and can be written in the following form:

[0180]

[0181] For ease of understanding, the following shows the cases corresponding to 6 bits.

[0182] At 6 bits,

[0183] By applying unentangled quantum logic gates on bits [1,2], [3,4], and [5,6], it becomes

[0184] First, assume the input quantum state is on an even number of qubits. However, if the basis of the quantum state corresponding to the last bit is 1, then it needs to be multiplied by a coefficient 'a'. Consider the corresponding parallel circuit, and consider the quantum state as follows:

[0185]

[0186] The quantum state after passing through m parallel deentangled quantum logic gates is:

[0187]

[0188] For example:

[0189] Applying a deentangled quantum logic gate to bits [1,2],[3,4],[5,6] and then applying a controlled CX gate transforms the result into...

[0190] The form on the right side of the above equation This corresponds perfectly to the input of this form, except that m may be odd and only the basis of quantum states on odd-numbered bits is considered.

[0191] If the number of qubits to be processed is odd, then first apply the deentanglement quantum logic gate and the controlled X gate to the last qubit. At this point, the quantum state changes from...

[0192]

[0193] It became:

[0194]

[0195] in The form of the first n-1 bits is the same as the form of the first n bits after transformation. If n is odd, it can be transformed into an even number using this method, thus completing the parallel deentanglement of the quantum logic gate. Using this method, the final quantum state obtained is a one-hot quantum state. One-hot quantum states can be logarithmically deep encoded, so we have completed the corresponding special 2-hot encoding. After passing through the H gate, it can be restored to a quadratic function.

[0196] In reality, a one-hot transformation encoding of the term is still required. Here, a logarithmic linear function is used to simultaneously perform LCU combined 2-hot encoding and one-hot encoding, thus completing the corresponding logarithmic depth preparation process. Since the LCU consists of two parts, its success probability is above 0.5.

[0197] Those skilled in the art will know that Figure 8-11 Some individual gates in the formula can be merged, but in order to fully demonstrate the derivation process of the formula, the merging is not completed here.

[0198] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A quantum logic gate, characterized in that: This includes a CX gate acting on a preset qubit and a controlled RY gate. The timing of the controlled RY gate's operation is between the timings of the two CX gates. The target bit of the controlled RY gate is the control bit of the CX gate, and the control bit of the controlled RY gate is the target bit of the CX gate, wherein: The preset qubits include a first qubit, a second qubit, and a third qubit. The CX gates include a first CX gate, a second CX gate, a third CX gate, and a fourth CX gate. The controlled RY gates include a first controlled RY gate and a second controlled RY gate. The activation timing of the first controlled RY gate is between the activation timings of the first CX gate and the second CX gate. The activation timing of the second controlled RY gate is between the activation timings of the third CX gate and the fourth CX gate. The activation timing of the third CX gate is after the activation timing of the second CX gate. The target bits of both the first CX gate and the second CX gate are the first qubits, and the control bits of both the first CX gate and the second CX gate are the second qubits. The target bits of the third CX gate and the fourth CX gate are both the first qubit, and the control bits of the third CX gate and the fourth CX gate are both the third qubit; The target bit of the first controlled RY gate is the second qubit, and the control bit of the first controlled RY gate is the first qubit; The target bit of the second controlled RY gate is the third qubit, and the control bits of the second controlled RY gate are the first qubit and the second qubit.

2. The quantum logic gate according to claim 1, characterized in that, The parameter values ​​of the first controlled RY gate are expressed as follows: The parameter values ​​of the second controlled RY gate are expressed as follows: .

3. A method for preparing a quadratic function quantum state, characterized in that, The method includes: Determine the qubits used to prepare the quadratic function quantum state; Construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on qubits, wherein: The first quantum logic gate is the quantum logic gate as described in claim 1. Each action sequence includes one first quantum logic gate. Each first quantum logic gate acts on three qubits, ordered from the highest-order qubit to the lowest-order qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the qubit number acted by the first quantum logic gate in the next action sequence is reduced by one compared to the qubit number acted by the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order qubit. The second quantum logic gate includes a CX gate and a controlled RY gate acting on a preset qubit, wherein: the preset qubit includes a first qubit and a second qubit; the CX gate includes a first CX gate and a second CX gate; the controlled RY gate includes a first controlled RY gate; the timing of the first controlled RY gate is between the timing of the first CX gate and the second CX gate; the target qubit of both the first CX gate and the second CX gate is the first qubit; the control qubit of both the first CX gate and the second CX gate is the second qubit; the target qubit of the first controlled RY gate is the second qubit; and the control qubit of the first controlled RY gate is the first qubit. The second quantum logic gate operates after the first quantum logic gates, and the first quantum logic gate operates on the least significant qubit and adjacent qubits. The target quantum circuit is run to prepare the quadratic function quantum state.

4. The method for preparing a quadratic function quantum state according to claim 3, characterized in that: The target quantum circuit also includes an H-gate acting on all qubits, wherein the H-gate is located after the multi-layer action timing of the first quantum logic gate and the second quantum logic gate on the qubits.

5. A device for preparing a quadratic function quantum state, characterized in that, The device includes: The acquisition module is used to determine the qubits used to prepare the quadratic function quantum state; A target quantum circuit construction module is used to construct a target quantum circuit, wherein the target quantum circuit has a first quantum logic gate and a second quantum logic gate acting on the qubits, wherein: The first quantum logic gate is the quantum logic gate as described in claim 1. Each action sequence includes one first quantum logic gate. Each first quantum logic gate acts on three qubits, ordered from the highest-order qubit to the lowest-order qubit. In the initial action sequence, the first quantum logic gate acts on the first three qubits. Along the action sequence, the qubit number acted by the first quantum logic gate in the next action sequence is reduced by one compared to the qubit number acted by the first quantum logic gate in the previous action sequence, until the first quantum logic gate acts on the lowest-order qubit. The second quantum logic gate includes a CX gate and a controlled RY gate acting on a preset qubit, wherein: the preset qubit includes a first qubit and a second qubit; the CX gate includes a first CX gate and a second CX gate; the controlled RY gate includes a first controlled RY gate; the timing of the first controlled RY gate is between the timing of the first CX gate and the second CX gate; the target qubit of both the first CX gate and the second CX gate is the first qubit; the control qubit of both the first CX gate and the second CX gate is the second qubit; the target qubit of the first controlled RY gate is the second qubit; and the control qubit of the first controlled RY gate is the first qubit. The second quantum logic gate operates after the first quantum logic gates, and the first quantum logic gate operates on the least significant qubit and adjacent qubits. The execution module is used to run the target quantum circuit to prepare the quadratic function quantum state.

6. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to implement the method of any one of claims 3 to 4 when it is run.

7. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to implement the method of any one of claims 3 to 4.

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