Pixel driving circuit, display panel and display device

Abstract

The present application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit includes a data writing subcircuit, a first capacitor and a driving subcircuit. The data writing subcircuit is configured to control the connection or disconnection of the data signal terminal with the first node. It includes a first transistor and a second transistor. The first electrodes of the first transistor and the second transistor are both connected to the data signal terminal, and the second electrodes are both connected to the first node. The control electrode of the first transistor is connected to the high refresh scan signal terminal, and the control electrode of the second transistor is connected to the first scan signal terminal. The data writing subcircuit is configured so that when the pixel is in high refresh mode, in the data writing phase, the first transistor is turned on and the second transistor is turned on at the same time. One end of the first capacitor is connected to the first node, and the other end is connected to the second node. The driving subcircuit is connected to the second node, the third node and the fourth node, and is configured to control the connection or disconnection of the third node and the fourth node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) has advantages such as vivid colors, higher refresh rates, higher contrast, and lower power consumption, making it gradually replacing LCD (Liquid Crystal Display) in the small and medium-sized market. However, AMOLED (Active Matrix Organic Light Emitting Diode) has a more complex pixel drive circuit than LCD, which makes the AMOLED TFT (Thin Film Transistor) process more complex. Therefore, the design of AMOLED pixel drive circuit is particularly important. Summary of the Invention

[0003] The purpose of the present application is to provide a pixel driving circuit, a display panel and a display device with excellent data signal writing capability.

[0004] The present application discloses a pixel driving circuit, which includes:

[0005] a data writing subcircuit connected to the data signal terminal and the first node, and configured to control the connection or disconnection between the data signal terminal and the first node; the data writing subcircuit includes a first transistor and a second transistor; the first electrodes of the first transistor and the second transistor are both connected to the data signal terminal, and the second electrodes are both connected to the first node; the control electrode of the first transistor is connected to the high refresh scan signal terminal, and the control electrode of the second transistor is connected to the first scan signal terminal;

[0006] The data writing sub-circuit is configured such that when the pixel is in the high refresh mode, during the data writing phase, the high refresh scan signal terminal controls the first transistor to be turned on, and the first scan signal terminal controls the second transistor to be turned on;

[0007] a first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node;

[0008] The driving subcircuit is connected to the second node, the third node and the fourth node, and is configured to control the connection or disconnection of the third node and the fourth node, wherein the third node is connected to the light-emitting unit and the fourth node is connected to the first power signal terminal.

[0009] Optionally, the data writing sub-circuit is further configured such that when the pixel is in the low refresh mode, during the data writing phase, the high refresh scan signal terminal controls the first transistor to be disconnected, and the first scan signal terminal controls the second transistor to be turned on.

[0010] Optionally, the pixel driving circuit further includes:

[0011] a compensation sub-circuit, connected to the second node and the third node, and configured to compensate for the data signal;

[0012] The compensation sub-circuit includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode is connected to the second node, and a control electrode is connected to the second scan signal terminal;

[0013] The fourth transistor is a metal oxide thin film transistor.

[0014] Optionally, the compensation sub-circuit further includes a tenth transistor;

[0015] The first electrode of the tenth transistor is connected to the second electrode of the fourth transistor, the second electrode is connected to the second node, and the control electrode is connected to the second gate signal terminal; or the first electrode of the tenth transistor is connected to the third node, the second electrode is connected to the first electrode of the fourth transistor, and the control electrode is connected to the second gate signal terminal;

[0016] The tenth transistor is a low-temperature polysilicon transistor.

[0017] Optionally, the driving sub-circuit includes a third transistor and a ninth transistor;

[0018] The first electrode of the third transistor is connected to the fourth node, the second electrode is connected to the third node, and the control electrode is connected to the second electrode of the ninth transistor;

[0019] The first electrode of the ninth transistor is connected to the second node, and the control electrode is connected to the fourth scan signal terminal; the ninth transistor is a metal oxide thin film transistor.

[0020] Optionally, the driving sub-circuit further includes a fifteenth transistor;

[0021] The first electrode of the fifteenth transistor is connected to the second electrode of the ninth transistor, the second electrode is connected to the control electrode of the third transistor, and the control electrode is connected to the fourth gate signal terminal; or the first electrode of the fifteenth transistor is connected to the second node, the second electrode is connected to the first electrode of the ninth transistor, and the control electrode is connected to the fourth gate signal terminal;

[0022] The fifteenth transistor is a low-temperature polysilicon transistor.

[0023] Optionally, the pixel driving circuit further includes a first light emitting control subcircuit;

[0024] The first light emitting control subcircuit includes a sixth transistor and an eleventh transistor, wherein one of the sixth transistor and the eleventh transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0025] The first electrode of the sixth transistor is connected to the second electrode of the eleventh transistor, the second electrode is connected to the fourth node, and the control electrode is connected to the first light emitting control signal terminal;

[0026] The first electrode of the eleventh transistor is connected to the first power signal terminal, and the control electrode is connected to the first gate control signal terminal.

[0027] Optionally, the pixel driving circuit further includes a second light emitting control subcircuit;

[0028] The second light emitting control subcircuit includes a fifth transistor and a twelfth transistor, one of the fifth transistor and the twelfth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0029] The first electrode of the fifth transistor is connected to the second electrode of the twelfth transistor, the second electrode is connected to the light-emitting unit, and the control electrode is connected to the second light-emitting control signal terminal;

[0030] The first electrode of the twelfth transistor is connected to the third node, and the control electrode is connected to the second gate control signal terminal.

[0031] Optionally, the pixel driving circuit further includes a first reset subcircuit;

[0032] The first reset sub-circuit includes an eighth transistor and a thirteenth transistor, one of the eighth transistor and the thirteenth transistor is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0033] The first electrode of the eighth transistor is connected to the second electrode of the thirteenth transistor, the second electrode is connected to the light emitting unit, and the control electrode is connected to the third scan signal terminal;

[0034] The first electrode of the thirteenth transistor is connected to the second reset signal terminal, and the control electrode is connected to the third gate signal terminal.

[0035] Optionally, the pixel driving circuit further includes a second reset subcircuit;

[0036] The second reset sub-circuit includes a seventh transistor and a fourteenth transistor, one of the seventh transistor and the fourteenth transistor is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0037] The first electrode of the seventh transistor is connected to the first reset signal terminal, the second electrode is connected to the first electrode of the fourteenth transistor, and the control electrode is connected to the third scan signal terminal;

[0038] The second electrode of the fourteenth transistor is connected to the first node, and the control electrode is connected to the third gate signal terminal.

[0039] Optionally, the pixel driving circuit further includes a pre-charging sub-circuit;

[0040] The pre-charging sub-circuit is connected to the data signal terminal, the data writing sub-circuit is connected to the data signal terminal through a wire, and the pre-charging sub-circuit is configured to pre-charge the line between the data signal terminal and the data writing sub-circuit.

[0041] Optionally, the pixel driving circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein the first light-emitting control subcircuit is connected between the first power signal terminal and the fourth node and is connected to the first light-emitting control signal terminal; the second light-emitting control subcircuit is connected between the third node and the fourth node and is connected to the second light-emitting control signal terminal;

[0042] The pre-charge sub-circuit includes a seventeenth transistor;

[0043] The first electrode of the seventeenth transistor is connected to the pre-charge signal terminal, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to: control the seventeenth transistor to be turned on before the data writing stage.

[0044] Optionally, the pre-charge sub-circuit further includes a sixteenth transistor;

[0045] The first electrode of the sixteenth transistor is connected to the second electrode of the seventeenth transistor, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the control signal terminal.

[0046] Optionally, the control signal terminal is configured to: control the sixteenth transistor to be turned on when the pixel is in a high refresh mode, and control the sixteenth transistor to be turned off when the pixel is in a low refresh mode.

[0047] The present application also provides a display panel, which includes the above-mentioned pixel driving circuit.

[0048] Optionally, the display panel includes a plurality of pixel driving circuits, a plurality of first light-emitting control signal lines, and a plurality of second light-emitting control signal lines, the plurality of pixel driving circuits are arranged in a plurality of rows, the first light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same first light-emitting control signal line, and the second light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same second light-emitting control signal line;

[0049] When the pre-charging sub-circuit includes the seventeenth transistor, in the pixel driving circuit, the control electrode of the seventeenth transistor is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal of the upper n rows of pixel driving circuits, where n is an integer greater than 0.

[0050] The present application also provides a display device, which includes the above-mentioned display panel.

[0051] Compared with the related art, the data writing subcircuit of the present application includes a first transistor and a second transistor arranged in parallel. When the pixel is in high refresh mode, the first transistor and the second transistor are turned on at the same time during the data writing stage to improve the writing capability of the data signal.

[0052] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0054] Figure 1 FIG. 1 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0055] Figure 2 FIG. 1 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0056] Figure 3 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0057] Figure 4 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0058] Figure 5 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0059] Figure 6In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0060] Figure 7 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0061] Figure 8 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0062] Figure 9 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0063] Figure 10 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0064] Figure 11 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0065] Figure 12 In one embodiment Figure 4 The timing diagram of the pixel driving circuit shown is shown.

[0066] Figure 13 FIG. 1 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0067] Figure 14 In one embodiment, multiple Figure 13 The specific connection circuit diagram of the pixel driving circuit is shown.

[0068] Figure 15 In one embodiment, multiple Figure 13 The specific connection circuit diagram of the pixel driving circuit is shown. DETAILED DESCRIPTION

[0069] Here, the technical solutions in the embodiments (or "implementations") of the present application will be clearly and completely described in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0070] The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and should not be understood as indicating or implying relative importance.

[0071] The present application provides a pixel driving circuit for a display panel. Figures 1 to 3 As shown, the pixel driving circuit includes a data writing sub-circuit 10 , a first capacitor C1 and a driving sub-circuit 20 .

[0072] The data write subcircuit 10 is connected to the data signal terminal DATA and the first node N1 and is configured to control the connection or disconnection between the data signal terminal DATA and the first node N1. The data write subcircuit 10 includes a first transistor T1 and a second transistor T2. The first electrodes of the first transistor T1 and the second transistor T2 are both connected to the data signal terminal DATA, and the second electrodes are both connected to the first node N1. The control electrode of the first transistor T1 is connected to the high refresh scan signal terminal SC-HR, and the control electrode of the second transistor T2 is connected to the first scan signal terminal SC1.

[0073] The data writing sub-circuit DATA is configured such that, when the display panel is in high refresh mode, during the data writing phase, the high refresh scan signal terminal SC-HR controls the first transistor T1 to be conductive, and the first scan signal terminal SC1 controls the second transistor T2 to be conductive. The display panel can have a high refresh mode and a low refresh mode, and the number of images displayed per second by the display panel in the high refresh mode is greater than the number of images displayed per second in the low refresh mode.

[0074] One end of the first capacitor C1 is connected to the first node N1 , and the other end of the first capacitor C1 is connected to the second node N2 .

[0075] The driver sub-circuit 20 is connected to the second node N2, the third node N3, and the fourth node N4. The driver sub-circuit 20 is configured to control the connection or disconnection between the third node N3 and the fourth node N4. The third node N3 is connected to the light-emitting unit 90, and the fourth node N4 is connected to the first power signal terminal VDD.

[0076] The data writing sub-circuit of the present application includes a first transistor and a second transistor arranged in parallel. When the pixel is in high refresh mode, the first transistor and the second transistor are turned on at the same time during the data writing stage to increase the conduction current between the data signal terminal DATA and the first node N1, thereby improving the writing ability of the data signal data.

[0077] The following will describe in detail the various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0078] like Figure 3As shown, the signal terminals connected to the pixel circuit provided in the present application also include a first power signal terminal VDD, a second power signal terminal VSS, a first scan signal terminal SC1, a second scan signal terminal SC2, a third scan signal terminal SC3 and a fourth scan signal terminal SC4, a second gate signal terminal VC2, a third gate signal terminal VC3 and a fourth gate signal terminal VC4, a first light-emitting control signal terminal EM1, a second light-emitting control signal terminal EM2, a first gate control signal terminal VC-M1 and a second gate control signal terminal VC-M2, a first reset signal terminal VINIT1, a second reset signal terminal VINIT2, a control signal terminal CONTROL and a pre-charge signal terminal VRE-CHARGE.

[0079] The first power signal terminal VDD and the second power signal terminal VSS are respectively configured to provide a first power signal vdd and a second power signal vss to the pixel circuit. The first scan signal terminal SC1, the second scan signal terminal SC2, the third scan signal terminal SC3, and the fourth scan signal terminal SC4 are respectively configured to provide a first scan signal sc1, a second scan signal sc2, a third scan signal sc3, and a fourth scan signal sc4 to the pixel circuit. The second gate signal terminal VC2, the third gate signal terminal VC3, and the fourth gate signal terminal VC4 are respectively configured to provide a second gate signal vc2, a third gate signal vc3, and a fourth gate signal vc4 to the pixel circuit. The second gate signal vc2, the third gate signal vc3, and the fourth gate signal vc4 are respectively in phase with the second scan signal sc2, the third scan signal sc3, and the fourth scan signal sc4. The high refresh scan signal terminal SC-HR is configured to output a high refresh scan signal sc-hr. The first emission control signal terminal EM1 and the second emission control signal terminal EM2 are respectively configured to provide a first emission control signal em1 and a second emission control signal em2 to the pixel circuit. The first gate control signal terminal VC-M1 and the second gate control signal terminal VC-M2 are respectively configured to provide a first gate control signal vc-m1 and a second gate control signal vc-m2 to the pixel circuit, wherein the first gate control signal vc-m1 and the second gate control signal vc-m2 are respectively opposite in phase to the first emission control signal em1 and the second emission control signal em2. The first reset signal terminal VINIT1 and the second reset signal terminal VINIT2 are respectively configured to provide a first reset signal vinit1 and a second reset signal vinit2 to the pixel circuit. The data signal terminal DATA is configured to output a data signal data. The control signal terminal CONTROL is configured to provide a control signal control to the pixel circuit. The pre-charge signal terminal VRE-CHARGE is configured to provide a pre-charge signal vre-charge to the pixel circuit.

[0080] Unless otherwise specified, the transistors used in this application may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0081] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0083] like Figure 1 As shown, in an optional embodiment, the pixel driving circuit includes a data writing sub-circuit 10 , a first capacitor C1 and a driving sub-circuit 20 .

[0084] The data writing sub-circuit 10 is connected to the first scan signal terminal SC1, the data signal terminal DATA and the first node N1. The data writing sub-circuit 10 is configured to control whether the data signal data is written into the first node N1 under the control of the first scan signal sc1.

[0085] The first node N1 is coupled to the second node N2 via the first capacitor C1 , so that the potential of the second node N2 is adjusted by the potential change of the first node N1 .

[0086] The driving sub-circuit 20 is connected to the second node N2, the third node N3, and the fourth node N4. The driving sub-circuit 20 is configured to control the conduction of the third node N3 and the fourth node N4 under the control of the second node N2. The fourth node N4 is connected to the first power signal terminal VDD, and the third node N3 is connected to the light-emitting unit 90.

[0087] like Figure 2 As shown, in an optional embodiment, the pixel driving circuit further includes a compensation subcircuit 30 and / or a first light-emitting control subcircuit 40 and / or a second light-emitting control subcircuit 50 and / or a first reset subcircuit 60 and / or a second reset subcircuit 70.

[0088] The compensation sub-circuit 30 is connected to the second scan signal terminal SC2, the second node N2 and the third node N3. The compensation sub-circuit 30 is configured to control the connection between the second node N2 and the third node N3 under the control of the second scan signal sc2.

[0089] The first light-emission control subcircuit 40 is disposed between the driver subcircuit 20 and the first power supply signal terminal VDD. Specifically, the first light-emission control subcircuit 40 is connected to the first power supply signal terminal VDD, the first light-emission control signal terminal EM1, and the fourth node N4. The first light-emission control subcircuit 40 is configured to control whether the first power supply signal VDD is written to the fourth node N4 under the control of the first light-emission control signal EM1.

[0090] The second light-emission control subcircuit 50 is disposed between the driving subcircuit 20 and the light-emitting unit 90. Specifically, the second light-emission control subcircuit 50 is connected to the second light-emission control signal terminal EM2, the third node N3, and the fifth node N5. The fifth node N5 is connected to the light-emitting unit 90. The second light-emission control subcircuit 50 is configured to control the connection between the fifth node N5 and the third node N3 under the control of the second light-emission control signal em2.

[0091] The first reset sub-circuit 60 is connected to the second reset signal terminal VINIT2, the third scan signal terminal SC3 and the fifth node N5. The first reset sub-circuit 60 is configured to control whether the second reset signal vinit2 is written into the fifth node N5 under the control of the third scan signal sc3.

[0092] The second reset sub-circuit 70 is connected to the first reset signal terminal VINIT1, the third scan signal terminal SC3 and the first node N1. The second reset sub-circuit 70 is configured to control whether the first reset signal vinit1 is written into the first node N1 under the control of the third scan signal sc3.

[0093] like Figure 3 As shown, in an optional embodiment, the data writing sub-circuit 10 includes a first transistor T1 and a second transistor T2. The first electrodes of the first transistor T1 and the second transistor T2 are both connected to the data signal terminal DATA, the second electrodes of the first transistor T1 and the second transistor T2 are both connected to the first node N1, the control electrode of the first transistor T1 is connected to the high refresh scan signal terminal SC-HR, and the control electrode of the second transistor T2 is connected to the first scan signal terminal SC1. The first transistor T1 and the second transistor T2 can both be low-temperature polysilicon transistors.

[0094] The driving sub-circuit 20 includes a third transistor T3. A first electrode of the third transistor T3 is connected to the fourth node N4, a second electrode of the third transistor T3 is connected to the third node N3, and a control electrode of the third transistor T3 is connected to the second node N2. The third transistor T3 may be a low-temperature polysilicon transistor.

[0095] The compensation sub-circuit 30 includes a fourth transistor T4. A first electrode of the fourth transistor T4 is connected to the third node N3, a second electrode of the fourth transistor T4 is connected to the second node N2, and a control electrode of the fourth transistor T4 is connected to the second scan signal terminal SC2. The fourth transistor T4 may be a metal oxide thin film transistor, specifically, an IGZO (Indium Gallium Zinc Oxide) transistor. When the refresh rate of the display panel is low, the fourth transistor T4 is an IGZO transistor. Its lower leakage current can make the potential of the second node N2 more stable, thereby making the signal at the control electrode of the third transistor T3 more stable, thereby achieving better optical performance.

[0096] The first light emission control subcircuit 40 includes a sixth transistor T6. A first electrode of the sixth transistor T6 is connected to the first power supply signal terminal VDD, a second electrode of the sixth transistor T6 is connected to the fourth node N4, and a control electrode of the sixth transistor T6 is connected to the first light emission control signal terminal EM1. The sixth transistor T6 may be a low-temperature polysilicon transistor.

[0097] The second light-emission control subcircuit 50 includes a fifth transistor T5. A first electrode of the fifth transistor T5 is connected to the third node N3, a second electrode of the fifth transistor T5 is connected to the light-emitting unit 90, and a control electrode of the fifth transistor T5 is connected to the second light-emission control signal terminal EM2. The fifth transistor T5 may be a low-temperature polysilicon transistor.

[0098] The first reset sub-circuit 60 includes an eighth transistor T8. A first electrode of the eighth transistor T8 is connected to the second reset signal terminal VINIT2, a second electrode of the eighth transistor T8 is connected to the fifth node N5, and a control electrode of the eighth transistor T8 is connected to the third scan signal terminal SC3. The eighth transistor T8 may be a low-temperature polysilicon transistor.

[0099] The second reset sub-circuit 70 includes a seventh transistor T7. A first electrode of the seventh transistor T7 is connected to the first reset signal terminal VINIT1, a second electrode of the seventh transistor T7 is connected to the first node N1, and a control electrode of the seventh transistor T7 is connected to the third scan signal terminal SC3. The seventh transistor T7 may be a low-temperature polysilicon transistor.

[0100] like Figure 4 As shown, Figure 4 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 4The driver subcircuit 20 of the illustrated circuit also includes a ninth transistor T9. The ninth transistor T9 is disposed between the control electrode of the third transistor T3 and the second node N2. Specifically, a first electrode of the ninth transistor T9 is connected to the second node N2, a second electrode of the ninth transistor T9 is connected to the control electrode of the third transistor T3, and the control electrode of the ninth transistor T9 is connected to the fourth scan signal terminal SC4. The ninth transistor T9 may be a metal oxide thin film transistor, specifically, an IGZO transistor. When the refresh rate of the pixel is low, the ninth transistor T9 is an IGZO transistor. Its lower leakage current can make the signal transmitted from the second node N2 to the control electrode of the third transistor T3 more stable, thereby achieving better optical performance.

[0101] like Figure 5 As shown, Figure 5 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 4 Compared with the circuit shown, Figure 5 The driver sub-circuit 20 of the illustrated circuit also includes a fifteenth transistor T15. A first electrode of the fifteenth transistor T15 is connected to the second electrode of the ninth transistor T9, a second electrode of the fifteenth transistor T15 is connected to the control electrode of the third transistor T3, and the control electrode of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. Alternatively, a first electrode of the fifteenth transistor T15 is connected to the second node N2, a second electrode of the fifteenth transistor T15 is connected to the first electrode of the ninth transistor T9, and the control electrode of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. The fifteenth transistor T15 may be a low-temperature polysilicon transistor. Because the ninth transistor T9 and the fifteenth transistor T15 are connected in series, and the ninth transistor T9 is a low-temperature polysilicon transistor, and the fifteenth transistor T15 is an IGZO transistor, leakage current from the second node N2 can be effectively prevented from affecting the control electrode of the third transistor T3.

[0102] like Figure 6 As shown, Figure 6 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 6The compensation sub-circuit 30 of the illustrated circuit also includes a tenth transistor T10. A first electrode of the tenth transistor T10 is connected to the second electrode of the fourth transistor T4, a second electrode of the tenth transistor T10 is connected to the second node N2, and a control electrode of the tenth transistor T10 is connected to the second gate signal terminal VC2. Alternatively, a first electrode of the tenth transistor T10 is connected to the third node N3, a second electrode of the tenth transistor T10 is connected to the first electrode of the fourth transistor T4, and a control electrode of the tenth transistor T10 is connected to the second gate signal terminal VC2. The tenth transistor is a low-temperature polysilicon transistor. Because the tenth transistor T10 is connected in series with the fourth transistor T4, and because the tenth transistor T10 is a low-temperature polysilicon transistor and the fourth transistor T4 is an IGZO transistor, leakage current from the third node N3 can be effectively prevented from affecting the second node N2.

[0103] like Figure 7 As shown, Figure 7 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 7 The first light-emitting control subcircuit 40 of the illustrated circuit also includes an eleventh transistor T11. A first electrode of the eleventh transistor T11 is connected to the first power supply signal terminal VDD, a second electrode of the eleventh transistor T11 is connected to the first electrode of the sixth transistor T6, and a control electrode of the eleventh transistor T11 is connected to the first gate control signal terminal VC-M1. One of the sixth transistor T6 and the eleventh transistor T11 is a low-temperature polysilicon transistor, and the other is a metal oxide thin-film transistor. In this embodiment, the sixth transistor T6 is a low-temperature polysilicon transistor, and the eleventh transistor T11 is an IGZO transistor, which effectively prevents leakage current from the first power supply signal terminal VDD from affecting the fourth node N4.

[0104] like Figure 8 As shown, Figure 8 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 8 The second light-emission control subcircuit 50 of the illustrated circuit also includes a twelfth transistor T12. A first electrode of the twelfth transistor T12 is connected to the third node N3, a second electrode of the twelfth transistor T12 is connected to the first electrode of the fifth transistor T5, and a control electrode of the twelfth transistor T12 is connected to the second gate control signal terminal VC-M2. One of the fifth transistor T5 and the twelfth transistor T12 is a low-temperature polysilicon transistor, and the other is a metal oxide thin-film transistor. In this embodiment, the fifth transistor T5 is a low-temperature polysilicon transistor, and the twelfth transistor T12 is an IGZO transistor, which effectively prevents leakage current from the third node N3 from affecting the fifth node N5.

[0105] like Figure 9 As shown, Figure 9 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 9 The first reset sub-circuit 60 of the illustrated circuit further includes a thirteenth transistor T13. A first electrode of the thirteenth transistor T13 is connected to the second reset signal terminal VINIT2, a second electrode of the thirteenth transistor T13 is connected to the first electrode of the eighth transistor T8, and a control electrode of the thirteenth transistor T13 is connected to the third gate signal terminal VC3. One of the eighth transistor T8 and the thirteenth transistor T13 is a low-temperature polysilicon transistor, and the other is a metal oxide thin-film transistor. In this embodiment, the eighth transistor T8 is a low-temperature polysilicon transistor, and the thirteenth transistor T13 is an IGZO transistor, which effectively prevents leakage current from the second reset signal terminal VINIT2 from affecting the fifth node N5.

[0106] like Figure 10 As shown, Figure 10 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 10 The second reset sub-circuit 70 of the illustrated circuit also includes a fourteenth transistor T14. A first electrode of the fourteenth transistor T14 is connected to the second electrode of the seventh transistor T7, a second electrode of the fourteenth transistor T14 is connected to the first node N1, and a control electrode of the fourteenth transistor T14 is connected to the third gate signal terminal VC3. One of the seventh transistor T7 and the fourteenth transistor T14 is a low-temperature polysilicon transistor, and the other is a metal oxide thin-film transistor. In this embodiment, the seventh transistor T7 is a low-temperature polysilicon transistor, and the fourteenth transistor T14 is an IGZO transistor, which effectively prevents leakage current from the first reset signal terminal VINIT1 from affecting the first node N1.

[0107] like Figure 11 As shown, Figure 11 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 11 The driving subcircuit 20 of the circuit shown further includes a ninth transistor T9 and a fifteenth transistor T15, the compensation subcircuit 30 further includes a tenth transistor T10, the first light-emitting control subcircuit 40 further includes an eleventh transistor T11, the second light-emitting control subcircuit 50 further includes a twelfth transistor T12, the first reset subcircuit 60 further includes a thirteenth transistor T13, and the second reset subcircuit 70 further includes a fourteenth transistor T14. The connection methods and types of the above transistors are similar to those of FIG. Figures 4 to 10 The embodiment shown is the same and will not be described in detail here. Of course, in some optional embodiments, the pixel circuit can be Figures 4 to 10 Combinations of the embodiments shown, for example, pixel circuits may be configured Figure 5The ninth transistor T9 and the fifteenth transistor T15 are shown as Figure 10 The fourteenth transistor T14 shown may also be set Figure 6 The tenth transistor T10 and Figure 7 The eleventh transistor T11 is shown, and so on.

[0108] like Figure 12 As shown, Figure 12 In one embodiment Figure 4 The timing diagram of the circuit diagram shown. The driving period of a frame includes an initialization period S1, a compensation period S2, a data writing period S3, and a light-emitting period S4. The data writing sub-circuit 10 is configured so that when the display panel is in high refresh mode, during the S3 phase, the high refresh scan signal terminal SC-HR controls the first transistor T1 to turn on; when the display panel is in low refresh mode, during the S3 phase, the high refresh scan signal terminal SC-HR controls the first transistor to turn off.

[0109] like Figure 12 As shown, during period S1, the first scan signal sc1 is high, the second scan signal sc2 is low, the third scan signal sc3 is low, the fourth scan signal sc4 is low, and the first emission control signal em1 is high. The first emission control signal em1 transitions to a high level. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off. The seventh transistor T7 and the eighth transistor T8 are turned on. The first reset signal vinit1 resets the first node N1 and the second node N2, and the second reset signal vinit2 resets the fifth node N5.

[0110] like Figure 12 As shown, during period S2, the second scan signal sc2 transitions to a high level, the fourth scan signal sc4 transitions to a high level, and the first emission control signal em1 transitions to a low level. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 transition to an on state. The first power supply signal vdd begins charging the second node N2 until the second node N2 reaches a potential of ELVDD+Vth, where ELVDD is the potential of the first power supply signal vdd and Vth is the threshold voltage of the third transistor T3.

[0111] like Figure 12As shown, during period S3, the first scan signal sc1 transitions to a low potential, the second scan signal sc2 transitions to a low potential, the third scan signal sc3 transitions to a high potential, and the first emission control signal em1 transitions to a high potential. The first transistor T1 and the second transistor T2 transition to an on state, while the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the sixth transistor T6 transition to an off state. The data signal data is written to the first node N1 and then to the second node N2 via the first capacitor C1. The potential of the second node N2 transitions to Vdata + ELVDD + Vth. In this way, when the third transistor T3 is driven, it can offset both the effects of the ELVDD voltage drop and the effects of Vth.

[0112] like Figure 12 As shown, during period S4, the first scanning signal sc1 transitions to a high level, the first emission control signal em1 transitions to a low level, and the second emission control signal em2 transitions to a low level. The first transistor T1 and the second transistor T2 transition to an off state, while the fifth transistor T5 and the sixth transistor T6 transition to an on state. The third transistor T3 transitions to a conductive state under the control of the potential of the second node N2. The first power supply signal vdd is connected to the light-emitting unit 90 via the sixth transistor T6, the third transistor T3, and the fifth transistor T5, thereby driving the light-emitting unit 90 to emit light.

[0113] Afterwards, the pixel circuit repeats the above driving sequence to control the light-emitting unit 90 to emit light.

[0114] For pixel circuits in other embodiments of the present application, the light emitting unit 90 may also be driven to emit light according to the above-mentioned timing logic. Figure 11 The pixel circuit shown in FIG. 1 can also be operated in the same manner as the pixel circuit shown in FIG. 2 , because the added transistor and the driving terminal do not affect the conduction of the original circuit. Figure 12 The timing diagram shown is used to realize the driving.

[0115] like Figure 13 As shown, in an optional embodiment, the pixel driving circuit further includes a pre-charging sub-circuit 80. The pre-charging sub-circuit 80 is connected to the data signal terminal DATA, and the data writing sub-circuit 10 is connected to the data signal terminal DATA via a wire. The pre-charging sub-circuit 80 is configured to pre-charge the line between the data signal terminal DATA and the data writing sub-circuit 10.

[0116] like Figure 14As shown, the pre-charge sub-circuit 80 further includes a seventeenth transistor T17. The first electrode of the seventeenth transistor T17 is connected to the pre-charge signal terminal VRE-CHARGE, the second electrode of the seventeenth transistor T17 is connected to the data signal terminal DATA and the wire between the data writing sub-circuit 10, and the control electrode of the seventeenth transistor T17 is connected to the first light-emitting control signal terminal EM1 or the second light-emitting control signal terminal EM2. The seventeenth transistor T17 can be a metal oxide thin film transistor, specifically, the seventeenth transistor T17 can be an IGZO transistor. According to Figure 12 As can be seen from the timing sequence shown, the seventeenth transistor T17 is turned on before the S3 period, ie, the data writing period, so that the precharge signal terminal VRE-CHARGE precharges the wire between the data signal terminal DATA and the data writing sub-circuit 10 .

[0117] like Figure 14 As shown, optionally, the pre-charge sub-circuit 80 also includes a sixteenth transistor T16. The first electrode of the sixteenth transistor T16 is connected to the second electrode of the seventeenth transistor T17, the second electrode of the sixteenth transistor T16 is connected to the data signal terminal DATA and the wire between the data write sub-circuit 10, and the control electrode of the sixteenth transistor T16 is connected to the control signal terminal CONTRIL. The control signal terminal CONTRIL is configured to control the sixteenth transistor T16 to be turned on when the pixel is in high refresh mode, and to control the sixteenth transistor T16 to be turned off when the pixel is in low refresh mode. In this way, the writing ability of the data signal data can be improved when the pixel is in high refresh mode, and power consumption can be saved when the pixel is in low refresh mode. The sixteenth transistor T16 is a low-temperature polysilicon transistor, and because the seventeenth transistor T17 is a metal oxide thin film transistor, the leakage current of the pre-charge signal terminal VRE-CHARGE can be effectively prevented from affecting the wire between the data signal terminal DATA and the data write sub-circuit 10.

[0118] The present application also provides a display panel including the above-mentioned pixel driving circuit. The display panel also includes a plurality of sub-pixels, each of which corresponds to a pixel driving circuit, and each pixel driving circuit is electrically connected to a corresponding sub-pixel to drive the corresponding sub-pixel.

[0119] The display panel includes a plurality of pixel driving circuits, a plurality of first light-emission control signal lines, and a plurality of second light-emission control signal lines. The plurality of pixel driving circuits are arranged in a plurality of rows, wherein a first light-emission control signal terminal EM1 of a row of pixel driving circuits is connected to the same first light-emission control signal line, and a second light-emission control signal terminal EM2 of a row of pixel driving circuits is connected to the same second light-emission control signal line.

[0120] like Figure 15As shown, when the pre-charging sub-circuit 80 includes the seventeenth transistor T17, in the pixel driving circuit, the control electrode of the seventeenth transistor T17 is connected to the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the pixel driving circuit in the upper n rows, where n is an integer greater than 0. Thus, when the light-emitting control signal provided to the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the pixel driving circuit in the upper n rows is at a high potential, the seventeenth transistor T17 is turned on, effectively ensuring that the pre-charging signal terminal VRE-CHARGE pre-charges the wire between the data signal terminal DATA and the data writing sub-circuit 10 before data is written into the pixel circuit.

[0121] The present application also provides a display device, which includes the above-mentioned display panel.

[0122] In one embodiment, the display device further includes a driver and a power supply circuit, wherein the driver is configured to provide a driving signal for driving the sub-pixels to emit light, and the power supply circuit is configured to supply power to the display substrate.

[0123] In one embodiment, the display device further includes a housing, and the display panel is disposed in the housing.

[0124] The display device provided in the embodiments of the present application may be, for example, a mobile phone, a tablet computer, a television, a laptop computer, an in-vehicle device, or any other device with a display function.

[0125] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the scope of protection of this application.

Claims

1. A pixel driving circuit, characterized in that: For display panels; The pixel driving circuit includes: a data writing subcircuit connected to the data signal terminal and the first node, and configured to control the connection or disconnection between the data signal terminal and the first node; the data writing subcircuit includes a first transistor and a second transistor; the first electrodes of the first transistor and the second transistor are both connected to the data signal terminal, and the second electrodes are both connected to the first node; the control electrode of the first transistor is connected to the high refresh scan signal terminal, and the control electrode of the second transistor is connected to the first scan signal terminal; The data writing sub-circuit is configured such that: when the display panel is in a high refresh mode, during a data writing phase, the high refresh scan signal terminal controls the first transistor to be turned on, and the first scan signal terminal controls the second transistor to be turned on; a first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node; a driving subcircuit connected to the second node, a third node, and a fourth node, and configured to control connection or disconnection between the third node and the fourth node, wherein the third node is connected to the light-emitting unit, and the fourth node is connected to the first power signal terminal; The driving sub-circuit includes a third transistor and a ninth transistor; the first electrode of the third transistor is connected to the fourth node, the second electrode is connected to the third node, and the control electrode is connected to the second electrode of the ninth transistor; the first electrode of the ninth transistor is connected to the second node, and the control electrode is connected to the fourth scan signal terminal; The driving sub-circuit also includes a fifteenth transistor; the first electrode of the fifteenth transistor is connected to the second electrode of the ninth transistor, the second electrode is connected to the control electrode of the third transistor, and the control electrode is connected to the fourth gate signal terminal; or the first electrode of the fifteenth transistor is connected to the second node, the second electrode is connected to the first electrode of the ninth transistor, and the control electrode is connected to the fourth gate signal terminal.

2. The pixel driving circuit according to claim 1, wherein: The data writing sub-circuit is further configured such that: when the display panel is in a low refresh mode, during a data writing phase, the high refresh scan signal terminal controls the first transistor to be disconnected, and the first scan signal terminal controls the second transistor to be turned on.

3. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a compensation sub-circuit, connected to the second node and the third node, and configured to compensate for the data signal; The compensation sub-circuit includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode is connected to the second node, and a control electrode is connected to the second scan signal terminal; The fourth transistor is a metal oxide thin film transistor.

4. The pixel driving circuit according to claim 3, wherein: The compensation sub-circuit further includes a tenth transistor; The first electrode of the tenth transistor is connected to the second electrode of the fourth transistor, the second electrode is connected to the second node, and the control electrode is connected to the second gate signal terminal; or the first electrode of the tenth transistor is connected to the third node, the second electrode is connected to the first electrode of the fourth transistor, and the control electrode is connected to the second gate signal terminal; The tenth transistor is a low-temperature polysilicon transistor.

5. The pixel driving circuit according to claim 1, wherein: The ninth transistor is a metal oxide thin film transistor.

6. The pixel driving circuit according to claim 5, wherein: The fifteenth transistor is a low-temperature polysilicon transistor.

7. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a first light emitting control subcircuit; The first light emitting control subcircuit includes a sixth transistor and an eleventh transistor, wherein one of the sixth transistor and the eleventh transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the sixth transistor is connected to the second electrode of the eleventh transistor, the second electrode is connected to the fourth node, and the control electrode is connected to the first light emitting control signal terminal; The first electrode of the eleventh transistor is connected to the first power signal terminal, and the control electrode is connected to the first gate control signal terminal.

8. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a second light emitting control subcircuit; The second light emitting control subcircuit includes a fifth transistor and a twelfth transistor, one of the fifth transistor and the twelfth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the fifth transistor is connected to the second electrode of the twelfth transistor, the second electrode is connected to the light-emitting unit, and the control electrode is connected to the second light-emitting control signal terminal; The first electrode of the twelfth transistor is connected to the third node, and the control electrode is connected to the second gate control signal terminal.

9. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a first reset subcircuit; The first reset sub-circuit includes an eighth transistor and a thirteenth transistor, one of the eighth transistor and the thirteenth transistor is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the eighth transistor is connected to the second electrode of the thirteenth transistor, the second electrode is connected to the light emitting unit, and the control electrode is connected to the third scan signal terminal; The first electrode of the thirteenth transistor is connected to the second reset signal terminal, and the control electrode is connected to the third gate signal terminal.

10. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a second reset subcircuit; The second reset sub-circuit includes a seventh transistor and a fourteenth transistor, one of the seventh transistor and the fourteenth transistor is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the seventh transistor is connected to the first reset signal terminal, the second electrode is connected to the first electrode of the fourteenth transistor, and the control electrode is connected to the third scan signal terminal; The second electrode of the fourteenth transistor is connected to the first node, and the control electrode is connected to the third gate signal terminal.

11. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes a pre-charging sub-circuit; The pre-charging sub-circuit is connected to the data signal terminal, the data writing sub-circuit is connected to the data signal terminal through a wire, and the pre-charging sub-circuit is configured to pre-charge the line between the data signal terminal and the data writing sub-circuit.

12. The pixel driving circuit according to claim 11, wherein: The pixel driving circuit further includes a first light emitting control subcircuit and a second light emitting control subcircuit, wherein the first light emitting control subcircuit is connected between the first power signal terminal and the fourth node and is connected to the first light emitting control signal terminal; The second light emitting control subcircuit is connected between the third node and the fourth node, and is connected to the second light emitting control signal terminal; The pre-charge sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor is connected to the pre-charge signal terminal, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to: control the seventeenth transistor to be turned on before the data writing stage.

13. The pixel driving circuit according to claim 12, wherein: The pre-charge sub-circuit further includes a sixteenth transistor; The first electrode of the sixteenth transistor is connected to the second electrode of the seventeenth transistor, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the control signal terminal.

14. The pixel driving circuit according to claim 13, wherein: The control signal terminal is configured to: control the sixteenth transistor to be turned on when the display panel is in a high refresh mode, and control the sixteenth transistor to be turned off when the pixel is in a low refresh mode.

15. A display panel, characterized in that: The display panel includes the pixel driving circuit according to any one of claims 1 to 14.

16. The display panel according to claim 15, wherein: The display panel includes a plurality of pixel driving circuits, a plurality of first light-emitting control signal lines, and a plurality of second light-emitting control signal lines, wherein the plurality of pixel driving circuits are arranged in a plurality of rows, wherein the first light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same first light-emitting control signal line, and the second light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same second light-emitting control signal line; When the pre-charging sub-circuit includes the seventeenth transistor, in the pixel driving circuit, the control electrode of the seventeenth transistor is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal of the upper n rows of pixel driving circuits, where n is an integer greater than 0.

17. A display device, characterized in that: The display device includes the display panel according to claim 15 or 16.

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