Writing word line enabling circuit and enabling control method, memory and electronic equipment

Abstract

The invention relates to a writing word line enabling circuit, a writing word line enabling control method, a memory and electronic equipment. The writing word line enabling circuit is used for being connected with a storage unit, the storage unit comprises a reading transistor, a writing transistor, a reading word line, a reading bit line, a writing word line and a writing bit line, the reading word line and the reading bit line are connected with the reading transistor, and the writing word line and the writing bit line are connected with the writing transistor. The write control circuit is configured to obtain a data signal transmitted by a write bit line and output a write control signal according to the data signal; and the starting control circuit is connected with the sensing control circuit and the writing word line, and is configured to output an enabling signal to the writing word line according to the writing control signal. By adopting the writing word line enabling circuit provided by the invention, the read-write fault tolerance rate can be improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a write word line enable circuit and enable control method, a memory, and an electronic device. Background Art

[0002] With the development of semiconductor technology, some new memory cells of dynamic random access memory (DRAM) have emerged, such as DRAM with 2T0C memory cells as the main memory cells. The 2T0C memory cell may include two transistors, one of which is a write transistor (Write Tr) and the other is a read transistor (Read Tr).

[0003] When writing data to the storage node (Storage Node, SN) of the 2T0C storage unit, it is necessary to open the write word line (Write Word Line, WWL), and in the data reading process of the 2T0C storage unit, the read word line (Read Word Line, RWL) needs to be selected, and after the reading is completed, it is also necessary to perform a write-back operation on the storage node SN. In the process of performing the write-back operation, it is first necessary to feed back the write-back data sensed on the read bit line (Read Bit Line, RBL) to the write bit line (WBL). Thereafter, the write word line WWL will be turned on to rewrite the write-back data to the storage node SN. If the write-back operation is not performed, the data stored on the storage node SN may gradually disappear over time, resulting in errors in the storage data of the storage unit. Summary of the invention

[0004] Based on this, it is necessary to provide a write word line enable circuit and a write word line enable control method, a memory, and an electronic device that can improve the read and write error tolerance.

[0005] In a first aspect, the present application provides a write word line enable circuit, which is used to connect to a storage unit, wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor, wherein the write word line enable circuit includes:

[0006] A sensing control circuit is connected to the write bit line and is configured to: obtain a data signal transmitted by the write bit line and output a write control signal according to the data signal;

[0007] The startup control circuit is connected to the sensing control circuit and the write word line, and is configured to output an enable signal to the write word line according to the write control signal.

[0008] The write word line enable circuit includes a sensing control circuit and a start control circuit. The sensing control circuit is connected to the write bit line and configured to obtain a data signal transmitted by the write bit line and output a write control signal according to the data signal. The start control circuit is connected to the sensing control circuit and the write word line and configured to output an enable signal to the write word line according to the write control signal. The enable signal sent by the start control circuit can control the write word line to respond accurately, so as to timely control the opening or disconnection of the write transistor, thereby eliminating the need for precise timing control of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate.

[0009] In one embodiment, the enable signal includes an enable signal and a disable signal, the working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage and a data writing stage, and the startup control circuit is further configured to: obtain a write disable instruction, determine the working stage of the storage unit according to the write control signal and the write disable instruction, when the storage unit works in the write-back stage and the data writing stage, output the enable signal to the write word line so that the write word line controls the write transistor to turn on; when the storage unit works in the preprocessing stage, the precharge stage, the reading stage and the sensing stage, output the disable signal to the write word line so that the write word line controls the write transistor to turn off

[0010] In one embodiment, the sensing control circuit includes:

[0011] A sensing amplifier circuit, comprising a first receiving end, a second receiving end, a first output end, and a second output end; wherein the first receiving end is connected to the write bit line for receiving a data signal transmitted by the write bit line, and the second receiving end is connected to the reference signal end for receiving a reference signal; the sensing amplifier circuit is configured to: when the data signal is greater than or less than the reference signal, the first output end and the second output end output different level signals; when the data signal is equal to the reference signal, the first output end and the second output end output the same level signal;

[0012] The NOR gate logic circuit has a first input terminal, a second input terminal and a first logic output terminal; wherein the first input terminal is connected to the first output terminal of the sensing amplifier circuit, the second input terminal is connected to the second output terminal of the sensing amplifier circuit, and the first logic output terminal is connected to the startup control circuit.

[0013] In one embodiment, the sensing amplifier circuit further has a control terminal; the control terminal is configured to receive a sensing enable signal.

[0014] In one embodiment, the startup control circuit includes:

[0015] A NAND gate logic circuit has a third input terminal, a fourth input terminal and a second logic output terminal; wherein the second logic output terminal is connected to the write word line, the third input terminal is connected to the first logic output terminal of the sensing control circuit, and the fourth input terminal is configured to receive the write disable instruction.

[0016] In a second aspect, the present application further provides a write word line enable control method, the write word line enable control method is applied to the write word line enable circuit in any one of the above embodiments, the write word line enable control method comprises:

[0017] A sensing control circuit is used to obtain a data signal transmitted by a write bit line in a storage unit; wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor;

[0018] Using the sensing control circuit to output a write control signal according to the data signal;

[0019] A start-up control circuit is used to output an enable signal to the write word line according to the write control signal.

[0020] The above-mentioned write word line enable control method obtains the data signal transmitted by the write bit line in the storage unit by using a sensing control circuit; wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; the sensing control circuit is used to output a write control signal according to the data signal; and the start control circuit is used to output an enable signal to the write word line according to the write control signal. The enable signal sent by the start control circuit can control the write word line to respond accurately, so as to timely control the opening or disconnection of the write transistor, thereby eliminating the need for precise timing control of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate.

[0021] In one embodiment, the enable signal includes an enable signal and a disable signal, the working phases of the storage unit include a preprocessing phase, a precharge phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase, and the outputting the enable signal to the write word line according to the write control signal includes:

[0022] Get write disable instruction;

[0023] The working phase of the storage unit is determined according to the write control signal and the write disable instruction. When the storage unit works in the write-back phase and the data writing phase, the enable signal is output to the write word line so that the write word line controls the write transistor to turn on. When the storage unit works in the preprocessing phase, the precharge phase, the reading phase and the sensing phase, the disable signal is output to the write word line so that the write word line controls the write transistor to turn off.

[0024] In one embodiment, the determining the working phase of the storage unit according to the write control signal and the write disable instruction includes:

[0025] A logical AND-NON operation is performed on the write control signal and the write disable instruction to obtain the enable signal, where the enable signal is used to determine the working phase of the storage unit.

[0026] In one of the embodiments, when the memory cell operates in the write-back phase, the data signal transmitted by the write bit line comes from the data signal fed back to the write bit line by the read bit line.

[0027] In one embodiment, outputting a write control signal according to the data signal includes:

[0028] Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal;

[0029] When the data signal is greater than or less than the reference signal, two different level signals are output as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, two same level signals are output as the first output signal and the second output signal respectively;

[0030] A logical negation operation is performed on the first output signal and the second output signal to obtain the write control signal.

[0031] In one embodiment, the working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage and a data writing stage. When the storage unit works in the preprocessing stage, the precharge stage, the reading stage and the sensing stage, the data signal is equal to the reference signal; when the storage unit works in the write-back and data writing stages, the data signal is greater than or less than the reference signal.

[0032] In one embodiment, when the data signal is greater than the reference signal, the first output signal is a high level signal and the second output signal is a low level signal; when the data signal is less than the reference signal, the first output signal is a low level signal and the second output signal is a high level signal.

[0033] In one embodiment, the method further comprises:

[0034] In response to the sensing enable signal, the steps of acquiring the data signal transmitted by the write bit line in the storage unit and outputting the write control signal according to the data signal are performed.

[0035] In a third aspect, the present application further provides a memory, including:

[0036] at least one memory array, the memory array comprising a plurality of memory cells, the memory cells comprising a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor;

[0037] At least one write word line enable circuit as described in any of the above embodiments, wherein the write word line enable circuit is respectively connected to the write bit line and the write word line in the corresponding memory array.

[0038] The above-mentioned memory comprises: at least one memory array, the memory array comprises a plurality of memory cells, the memory cells comprise read transistors and write transistors, and read word lines and read bit lines connected to the read transistors, and write word lines and write bit lines connected to the write transistors; at least one write word line enable circuit as described in any of the above-mentioned embodiments, the write word line enable circuit being respectively connected to the write bit lines and the write word lines in the corresponding memory array. By starting the enable signal sent by the control circuit, the write word line can be controlled to respond accurately, so as to timely control the opening or disconnection of the write transistor, thereby eliminating the need for precise timing control of the read and write process of the memory cell as required in the related art, thereby improving the read and write fault tolerance rate.

[0039] In one embodiment, the memory further includes a write word line driver and a write word line decoder, the start control circuit is connected to the write word line through the write word line driver, and the write word line driver is also connected to the write word decoder.

[0040] In a fourth aspect, the present application further provides an electronic device, comprising a memory as described in any of the above embodiments. The write word line enable circuit in the memory can control the write word line to respond accurately, and timely control the opening or disconnection of the write transistor, thereby eliminating the need for precise timing control of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a structural schematic diagram of an existing 2T0C storage unit;

[0043] Figure 2 A schematic diagram of the structure of a write word line enable circuit provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of another write word line enable circuit provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of a sensing amplifier circuit provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of another write word line enable circuit provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of another write word line enable circuit provided in an embodiment of the present application;

[0048] Figure 7 A flowchart of a write word line enable control method provided in an embodiment of the present application;

[0049] Figure 8 A flowchart of step S103 in a write word line enable control method provided in an embodiment of the present application;

[0050] Fig. 9 A flowchart of step S102 in a write word line enable control method provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0052] Fig.11 A schematic diagram of the structure of a storage array of a memory provided in an embodiment of the present application.

[0053] Explanation of the reference numerals: 10 - storage array, storage cell 11, 20 - sense amplifier, 101 - sense control circuit, 1011 - sense amplifier circuit, 1012 - NOR gate logic circuit, 201 - start control circuit, 2011 - NAND gate logic circuit, 301 - write word line driver, 401 - write word line decoder. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0059] With the development of semiconductor technology, some new memory cells of dynamic random access memory (DRAM) have emerged, such as DRAM with 2T0C memory cells as the main memory cells. The 2T0C memory cell contains two transistors, one of which is a write transistor (Write Tr) and the other is a read transistor (Read Tr). The read transistor is connected to the read bit line (Read Bit Line, RBL) and the read word line (Read Word Line, RWL), and the write transistor is connected to the write bit line (Write Bit Line, WBL) and the write word line (Write Word Line, WWL).

[0060] After the read phase of the 2T0C storage cell is completed, a write-back operation needs to be performed on the storage node SN. In the process of performing the write-back operation, the write-back data sensed on the read bit line (Read Bit Line, RBL) needs to be fed back to the write bit line (WBL). Thereafter, the write word line WWL will be turned on to rewrite the write-back data into the storage node SN.

[0061] like Figure 1 As shown, in some traditional technical solutions, a delay circuit is used to control the moment when the write word line WWL is reopened during the write-back phase. However, the delay circuit in the traditional technology only performs simple timing control on the entire read-write process of the storage unit. For example, assuming that the read-write process timing pre-set by the delay circuit at a certain moment indicates that the storage unit has entered the write-back phase at this time, then regardless of whether the data signal on the write bit line WBL is synchronized as a sensing signal, the delay circuit will control the write word line WWL to be reopened, which is very likely to cause errors in the write-back data. Therefore, the traditional method of using a delay circuit to implement write-back requires very precise control of the timing of the entire read-write process of the storage unit to ensure that the data written back into the storage node SN will not be erroneous, so that the read-write fault tolerance rate of the traditional technology is low.

[0062] The present application provides a write word line enable circuit for connecting to a storage unit. The write word line enable circuit of the present application is Figure 1 The improvement of the peripheral circuit outside the array composed of the memory cells shown in the figure. Wherein, the memory cell is a 2T memory cell, and the 2T memory cell has at least one read transistor and one write transistor, the read transistor is connected to the read word line RWL and the read bit line RBL, and the write transistor is connected to the write word line WWL and the write bit line WBL. In some embodiments, the above-mentioned 2T memory cell can be a 2T0C memory cell, a 2T1C memory cell, or a 3T memory cell, etc.

[0063] like Figure 2 As shown, the write word line enable circuit of the present application includes a sensing control circuit 101 and a start control circuit 201. The sensing control circuit 101 is connected to the write bit line WBL and is configured to: obtain a data signal transmitted by the write bit line WBL and output a write control signal according to the data signal. The start control circuit 201 is connected to the sensing control circuit 101 and the write word line WWL and is configured to: output an enable signal to the write word line WWL according to the write control signal.

[0064] The data signal transmitted by the write bit line WBL may change according to different stages of the memory cell in the read and write process. The sensing control circuit 101 can determine which stage of the read and write process the memory cell is in by acquiring the data signal transmitted by the write bit line WBL, thereby outputting a write control signal to the start control circuit 201, and the start control circuit 201 forms an enable signal according to the write control signal to instruct the write transistor of the memory cell to be turned on or off.

[0065] The write word line enable circuit includes a sensing control circuit 101 and a start control circuit 201. The sensing control circuit 101 is connected to the write bit line WBL and is configured to obtain a data signal transmitted by the write bit line WBL and output a write control signal according to the data signal. The start control circuit 201 is connected to the sensing control circuit 101 and the write word line WWL and is configured to output an enable signal to the write word line WWL according to the write control signal. The enable signal sent by the start control circuit 201 can control the write word line WWL to respond accurately to indicate whether the write transistor of the storage unit is turned on or off, thereby eliminating the need to accurately control the timing of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate.

[0066] In one embodiment, the enable signal includes a turn-on signal and a disable signal, and the working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage, and a data writing stage. The startup control circuit 201 is also configured to: obtain a write disable instruction, determine the working stage of the storage unit according to the write control signal and the write disable instruction, and when the storage unit works in the write-back stage and the data writing stage, output a turn-on signal to the write word line WBL so that the write word line WBL controls the write transistor to turn on; when the storage unit works in the preprocessing stage, the precharge stage, the reading stage, and the sensing stage, output a disable signal to the write word line WBL so that the write word line WBL controls the write transistor to turn off.

[0067] The working phases of the storage unit can be roughly divided into the following phases: (1) pre-processing phase; (2) pre-charging phase; (3) reading phase; (4) sensing phase; (5) writing back phase; (6) data writing phase. The following is an explanation of the main working phases (reading phase, sensing phase and writing back phase):

[0068] In the reading stage, the gate of the read transistor will determine whether it is turned on based on whether the data stored on SN is "0" or "1", and the voltage on the read bit line RBL connected to the read transistor will change instantaneously based on whether the gate of the read transistor is turned on. If it changes, it means that the read transistor is turned on, otherwise the read transistor is not turned on, and the stored data is determined to be 0 or 1 based on whether it is turned on.

[0069] In the sensing stage, by connecting the output end of the read bit line RBL to an input end of a sense amplifier (SenseAmplifier, SA) for reading, and connecting the other input end of the sense amplifier for reading to a reference signal end, the sense amplifier can compare the difference between the current or voltage on the read bit line RBL and the current or voltage at the reference signal end, and amplify the difference, so that the sense amplifier for reading can output a sensing signal. It can be understood that the magnitude of the current or voltage of the sensing signal can be used to indicate whether the data stored in the storage cell is "1" or "0". For example, if the output sensing signal is at a high level, it indicates that the data stored in the storage cell is "1". If the output sensing signal is at a low level, it indicates that the data stored in the storage cell is "0".

[0070] In addition, after the induction phase, the write-back phase will be entered. This is because the data stored in the storage node (Storage Node, SN) of the 2T0C storage unit is usually stored based on the gate of the read transistor as a capacitor. The characteristic of capacitor storage data is that if the write-back (refresh) operation is not performed, the charge stored in the capacitor will gradually disappear over time, which will cause errors in the stored data (for example, assuming that the data that the storage node of a storage unit should store is "1", but if the write-back operation is not performed for a long time, the charge stored in the gate of the read transistor corresponding to this storage node may disappear, causing the data stored in the SN to become "0", which in turn causes errors in the data stored in this storage unit).

[0071] In the write-back phase, the sense amplifier used for reading will also transmit the sense signal to the write bit line WBL, so that the data signal transmitted on the write bit line WBL is synchronized as the sense signal. Afterwards, by reopening the write word line WWL to turn on the write transistor again, the sense signal synchronized on the write bit line WBL can be transmitted to the storage node SN for storage to complete the write-back process. When the sense signal has not yet been synchronized to the write bit line WBL, the write word line WWL cannot be reopened, otherwise the data written back into the storage node SN will be erroneous.

[0072] The enable signal may include a start signal and a disable signal, and the start control circuit 201 may be connected to the write word line WWL, and control the read transistor of the storage unit to turn on through the start signal, and control the write transistor of the storage unit to turn off through the disable signal. When the 2T0C storage unit is in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage, the data signal transmitted by the write bit line WBL may be synchronized with the reference signal, so that the enable signal output by the start control circuit 201 is a disable signal; when the storage unit is in the write-back stage and the data writing stage, the data signal transmitted by the write bit line WBL may be synchronized with the sensing signal output by the sensing amplifier for reading, so that the enable signal output by the start control circuit 201 is a start signal. For example, when the storage unit is in the reading stage or the sensing stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and maintain it as the voltage or current value of the reference signal. At this time, the start control circuit 201 will determine that the enable signal is a disable signal according to the corresponding write control signal; when the storage unit is in the write-back stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and convert it into the voltage or current value of the sensing signal. At this time, the start control circuit 201 will determine that the enable signal is a start signal according to the corresponding write control signal.

[0073] Of course, in other suitable application scenarios, the storage unit may have other stages in the reading and writing process. In other stages not mentioned in the present application, the data signal transmitted by the write bit line WBL may also be adaptively changed according to the corresponding application scenario requirements or designs, and this embodiment does not limit this.

[0074] In one embodiment, Figure 3As shown, the sensing control circuit 101 includes a sensing amplifier circuit 1011 and a NOR gate logic circuit 1012. The sensing amplifier circuit 1011 has a first receiving terminal, a second receiving terminal, a first output terminal output1 and a second output terminal output2. The first receiving terminal is connected to the write bit line WBL for receiving the data signal transmitted by the write bit line WBL. The second receiving terminal is connected to the reference signal terminal for receiving the reference signal. The sensing amplifier circuit 1011 is configured to: when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal output different level signals; when the data signal is equal to the reference signal, the first output terminal and the second output terminal output the same level signal. The NOR gate logic circuit 1012 has a first input terminal, a second input terminal and a first logic output terminal output3. The first input terminal is connected to the first output terminal of the sensing amplifier circuit 1011, the second input terminal is connected to the second output terminal of the sensing amplifier circuit 1011, and the first logic output terminal is connected to the start control circuit 201.

[0075] The sensing amplifier circuit 1011 may be a sensing amplifier with a signal amplification function, which is used to amplify the difference between the data signal of the storage unit at different stages and the reference signal, so that the first output terminal and the second output terminal may output the same or different level signals. The signal type of the input terminal of the sensing amplifier circuit 1011 may be a voltage signal or a current signal. In some embodiments, the sensing amplifier may be a sensing voltage amplifier or a sensing current amplifier. The level signal may include a low level signal and a high level signal. The low level signal may be a level signal lower than the reference signal, and the high level signal may be a level signal higher than the reference signal.

[0076] For example, in the reading stage or the sensing stage, the sense amplifier used for reading has not yet output the sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized as the reference signal of the reference signal terminal. For the sensing amplifier circuit 1011, at this time, the voltage or current of the first receiving terminal and the second receiving terminal are the same, then the first output terminal of the sensing amplifier circuit 1011 will output a low-level signal, and the second output terminal will also output a low-level signal. In the write-back stage, the sense amplifier used for reading will also output the sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized as the sensing signal output by the sense amplifier used for reading. Assuming that the write-back data corresponding to the sensing signal in the write-back phase is "1", the data signal transmitted by the write word line WWL can be greater than the reference signal, which causes the data signal on the write word line WWL to be synchronized to be greater than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a high-level signal, and the second output end will also output a low-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will output different level signals; assuming that the write-back data corresponding to the sensing signal in the write-back phase is "0", the data signal transmitted by the write word line WWL can be less than the reference signal, which causes the data signal on the write word line WWL to be synchronized to be less than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a low-level signal, and the second output end will also output a high-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will also output different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output end and the second output end of the sensing amplifier circuit 1011 can always output different level signals.

[0077] Further, when the data signal is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same level signal, specifically, the same low level signal. After the two input terminals of the NAND gate receive the same low level signal, its first logic output terminal will output a high level signal to the startup control circuit 201; when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 will output different level signals. Specifically, the first output terminal outputs a low level signal and the second output terminal outputs a high level signal, or the first output terminal outputs a high level signal and the second output terminal outputs a low level signal. After the two input terminals of the NAND gate receive different level signals, its first logic output terminal will output a high level signal to the startup control circuit 201.

[0078] Optionally, the reference signal may be a voltage value of half the power supply voltage VDD, i.e., 1 / 2VDD, the low level signal may be 0, and the high level signal may be VDD. Alternatively, the reference signal may be VDD, the low level signal may be 1 / 2VDD, and the high level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low level signal, and the high level signal may have different settings, which are not limited in this embodiment.

[0079] In one embodiment, Figure 4 As shown, the sense amplifier circuit 1011 further has a control terminal; the control terminal is configured to receive a sense enable signal (Sense Amplifier Enable).

[0080] The sense amplifier circuit 1011 and the sense amplifier used for reading in the memory cell may be two separate sense amplifiers, and the sense enable signal of the sense amplifier circuit 1011 may be different from the enable signal of the sense amplifier used for reading.

[0081] Optionally, the structure of the sensing amplifier circuit 1011 and the sense amplifier used for reading can be the same. For example, the specific structure of the sensing amplifier circuit 1011 can be as follows: Figure 4 As shown, the control end of the sensing amplifier circuit 1011 can be the gates of the transistors T1, T2 and T3, the gate of the transistor T4 in the sensing amplifier circuit 1011 is used to receive the data signal output by the write bit line WBL, the gate of the transistor T5 is used to receive the reference signal, the gates of the transistors T6 and T7 serve as the first output end of the sensing amplifier circuit 1011, and the gates of the transistors T8 and T9 serve as the second output end of the sensing amplifier circuit 1011.

[0082] Of course, the structure of the sensing amplifier circuit 1011 can also be other suitable circuit structures, and the number of transistors contained therein is not limited to Figure 4 The 9 shown in the figure can be determined according to the specific SA circuit structure, and this embodiment does not limit this.

[0083] If the control end of the sensing amplifier circuit 1011 does not receive the sensing enable signal, the sensing amplifier circuit 1011 does not work, and the first output end and the second output end of the sensing amplifier circuit 1011 both output low-level signals. If the control end of the sensing amplifier circuit 1011 receives the sensing enable signal, the sensing amplifier circuit starts to work. Assuming that the data signal on the write bit line WBL is equal to the reference signal, the first output end and the second output end of the sensing amplifier circuit 1011 still output low-level signals; assuming that the data signal on the write bit line WBL is less than the reference signal, the first output end outputs a low-level signal and the second output end outputs a high-level signal; assuming that the data signal on the write bit line WBL is greater than the reference signal, the first output end outputs a low-level signal and the second output end outputs a high-level signal.

[0084] In one embodiment, Figure 5 As shown, the start control circuit 201 includes a NAND gate logic circuit 2011, and the NAND gate logic circuit 2011 has a third input terminal, a fourth input terminal and a second logic output terminal output4. The second logic output terminal is connected to the write word line WWL, the third input terminal is connected to the first logic output terminal of the sensing control circuit 101, and the fourth input terminal is configured to receive a write disable command (Write Disable Command).

[0085] The third input terminal of the start control circuit 201 may be connected to the first logic output terminal of the NOR gate logic circuit 1012 in the sensing control circuit 101. The write disable instruction may also include a low level signal and a high level signal. When the write disable instruction is a low level signal, it indicates that the write word line WWL is selected. When the write disable instruction is a high level signal, it indicates that the write word line WWL is not selected.

[0086] Exemplarily, the working process of the write word line enable circuit is described in detail based on this embodiment. Of course, the following description is only for a better understanding of this solution and does not constitute a limitation on other embodiments.

[0087] When the write disable instruction is a low level signal, it indicates that the write word line WWL is selected. At this time, no matter whether the third input terminal of the NAND gate logic circuit 2011 inputs a high level signal or a low level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL, so that the write word line WWL can control the write transistor of the storage unit to be turned on. At this time, the sensing enable signal can be configured not to be sent to the sensing amplifier circuit 1011, that is, the sensing amplifier circuit 1011 does not work, and the data signal on WBL can be a new data signal to be written. After the write transistor is turned on, the new data signal on WBL can be smoothly written to the storage node. Further, when the write disable instruction is a low level signal, the stage of the storage unit at this time can be a data writing stage, that is, in the data writing stage of the storage unit, the write word line enable circuit of this embodiment can automatically control the write transistor of the storage unit to remain turned on, so as to write new data to the storage node.

[0088] When the write disable instruction is a high level signal, it indicates that the write word line WWL is not selected. At this time, the sense enable signal can be configured to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 starts to work. At this time, there are two cases: (1) When the data signal on WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same low level signal, so that the output terminal of the NOR gate logic circuit 1012 will output a high level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a low level signal to the write word line WWL at this time, so as to disconnect the write transistor through the write word line WWL. At this time, the stage of the storage unit can be the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage, that is, in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage of the storage unit, the write transistor of the storage unit can be automatically controlled to be disconnected by the write word line enable circuit of this embodiment to avoid errors in the data stored in the storage node. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals, so that the output terminal of the NOR gate logic circuit 1012 will output a low level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011, and because the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL at this time, so as to turn on the write transistor through the write word line WWL. At this time, the stage that the storage unit is in may be the write-back stage, that is, in the write-back stage of the storage unit, the write word line enable circuit of this embodiment can automatically control the write transistor of the storage unit to be turned on, so that the data signal transmitted on the write bit line WBL can be rewritten into the storage node to complete the data write-back process.

[0089] Thus, in several stages of the 2T0C memory cell read and write process, the write word line enable circuit of this embodiment can realize the automatic turning on or off of the write transistor, so that the turning on or off of the write transistor can meet the requirements of each stage of the memory cell read and write process. And because this embodiment does not need to perform very precise control on the timing of the memory cell read and write process as required by the delay circuit of the traditional technology, it can improve the read and write fault tolerance rate.

[0090] Of course, in other suitable application scenarios, the storage unit may have other stages in the reading and writing process. In other stages not mentioned in the present application, the write word line enable circuit may realize automatic turning on or off of the write transistor and may be adaptively changed according to the corresponding application scenario requirements or designs. This embodiment is not limited here.

[0091] In one embodiment, Figure 6 As shown, the start control circuit 201 is connected to the write word line WWL through the write word line driver 301 ; wherein the write word line driver 301 is also connected to the write word line decoder 401 .

[0092] The input end of the write word line decoder 401 can be used to receive an address signal, and resolve the address signal into a write address signal and transmit it to the write word line driver 301. The write word line driver 301 can drive the write word line WWL according to the enable signal and the write address signal.

[0093] The present application also provides a write word line enable control method, such as Figure 7 As shown, the write word line enable control method includes the following steps:

[0094] S101: Using a sensing control circuit to obtain a data signal transmitted by a write bit line in a storage unit; wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor.

[0095] The data signal transmitted by the write bit line WBL may change according to different stages of the memory cell in the read and write process. By acquiring the data signal transmitted by the write bit line WBL, it is possible to determine which stage of the read and write process the memory cell is in at this time.

[0096] S102: using a sensing control circuit to output a write control signal according to the data signal, wherein the write control signal can be used to form an enable signal to instruct the write transistor of the memory cell to turn on or off.

[0097] S103: using the start control circuit to output an enable signal to the write word line according to the write control signal.

[0098] The enable signal may include a start signal and a disable signal. The start signal may control the read transistor of the storage unit to be turned on, and the disable signal may control the write transistor of the storage unit to be turned off.

[0099] The above-mentioned write word line enable control method obtains the data signal transmitted by the write bit line in the storage unit by using a sensing control circuit; wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; the sensing control circuit is used to output a write control signal according to the data signal; and the start control circuit is used to output an enable signal to the write word line according to the write control signal. The enable signal sent by the start control circuit can control the write word line to respond accurately, so as to timely control the opening or disconnection of the write transistor, thereby eliminating the need for precise timing control of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate.

[0100] In one embodiment, the enable signal includes an enable signal and a disable signal, and the working phases of the storage unit include a pre-processing phase, a pre-charging phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase. Figure 8 As shown, the above step S103 includes:

[0101] S1031: Get a write disable instruction.

[0102] The write disable instruction may also include a low level signal and a high level signal. When the write disable instruction is a low level signal, it indicates that the write word line WWL is selected. When the write disable instruction is a high level signal, it indicates that the write word line WWL is not selected.

[0103] S1032: Determine the working stage of the storage unit according to the write control signal and the write disable instruction. When the storage unit works in the write-back stage and the data writing stage, an enable signal is output to the write word line WWL, so that the write word line WWL controls the write transistor to turn on; when the storage unit works in the preprocessing stage, the precharge stage, the reading stage and the sensing stage, a disable signal is output to the write word line WWL, so that the write word line WWL controls the write transistor to turn off.

[0104] The working stages of the storage unit can be roughly divided into the following stages: (1) pre-processing stage; (2) pre-charging stage; (3) reading stage; (4) sensing stage; (5) writing back stage; (6) data writing stage. The description of the processes of the main stages of the storage unit can refer to the content recorded above, and will not be repeated here.

[0105] When the 2T0C memory cell is in the pre-processing stage, pre-charging stage, reading stage and sensing stage, the data signal transmitted by the write bit line WBL can be synchronized with the reference signal, so that the enable signal output by the start control circuit 201 is a disable signal; when the memory cell is in the write-back stage and the data writing stage, the data signal transmitted by the write bit line WBL can be synchronized with the sensing signal output by the sensing amplifier for reading, so that the enable signal output by the start control circuit 201 is a start signal. For example, when the memory cell is in the reading stage or the sensing stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and keep it as the voltage or current value of the reference signal. At this time, the start control circuit 201 will determine that the enable signal is a disable signal according to the corresponding write control signal; when the memory cell is in the write-back stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and change it to the voltage or current value of the sensing signal. At this time, the start control circuit 201 will determine that the enable signal is a start signal according to the corresponding write control signal.

[0106] Based on the above embodiment, in one embodiment, the above step S1032 includes: performing a logical AND-NOT operation on the write control signal and the write disable instruction to obtain an enable signal, and the enable signal is used to determine the working phase of the storage unit.

[0107] The working stage of the storage unit can be determined by the respective level states of the write control signal and the write disable instruction. For example, when the write disable instruction is a low-level signal, the stage in which the storage unit is located can be the data writing stage. When the write disable instruction is a high-level signal, it indicates that the write word line WWL is not selected. At this time, there are two cases: (1) When the data signal on the write bit line WBL is equal to the reference signal, the write control signal can be a high-level signal. At this time, the working stage of the storage unit can be the pre-processing stage, the pre-charging stage, the reading stage, and the sensing stage. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the write control signal can be a low-level signal. At this time, the working stage of the storage unit can be the write-back stage.

[0108] Based on the above embodiment, in one embodiment, in step S1032, when the memory cell operates in the write-back phase, the data signal transmitted by the write bit line WBL comes from the data signal fed back to the write bit line WBL by the read bit line RBL. That is, in the write-back phase, the sense amplifier used for reading will also transmit the sense signal to the write bit line WBL, so that the data signal transmitted on the write bit line WBL is synchronized as the sense signal.

[0109] In one embodiment, Fig. 9 As shown, the above step S102 includes:

[0110] S1021: Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal.

[0111] The reference signal may be obtained from an external reference signal terminal, or may be the same as the reference signal required to be used by the storage unit during the reading and writing process.

[0112] Optionally, when the storage unit is in the preprocessing stage, precharge stage, reading stage and sensing stage, the data signal may be the same as the reference signal; when the storage unit is in the write-back stage and the data writing stage, the data signal may be greater than or less than the reference signal. Of course, in other suitable application scenarios, the storage unit may also have other stages in the reading and writing process. In other stages not mentioned in this application, the data signal may also be adaptively changed according to the corresponding application scenario requirements or designs, and this embodiment is not limited here.

[0113] S1022: When the data signal is greater than or less than the reference signal, output two signals of different levels as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, output two signals of the same level as the first output signal and the second output signal respectively.

[0114] The level signal may include a low level signal and a high level signal. The low level signal may be a level signal lower than a reference signal, and the high level signal may be a level signal higher than the reference signal.

[0115] Exemplarily, when in the reading stage or the sensing stage, the data signal is equal to the reference signal, and the first output signal and the second output signal can be the same low-level signal. When in the write-back stage, assuming that the write-back data corresponding to the sensing signal in the write-back stage is "1", the data signal can be greater than the reference signal at this time, and the first output signal can be a high-level signal, and the second output signal can be a low-level signal, that is, the first output signal and the second output signal are different level signals; assuming that the write-back data corresponding to the sensing signal in the write-back stage is "0", the data signal can be less than the reference signal at this time, and the first output signal can be a low-level signal, and the second output signal can be a high-level signal, that is, the first output signal and the second output signal are still different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output signal and the second output signal can always be different level signals.

[0116] S1023: Perform a logical OR operation on the first output signal and the second output signal to obtain a write control signal.

[0117] When the first output signal and the second output signal are both the same low-level signal, after performing a logical OR operation, the obtained write control signal is a high-level signal, that is, the write control signal is a high-level signal at this time; when the first output signal and the second output signal are different-level signals, after performing a logical OR operation, the obtained write control signal is a low-level signal, that is, the write control signal is a low-level signal at this time.

[0118] Optionally, the reference signal may be a voltage value of half the power supply voltage (VDD), i.e., 1 / 2VDD, the low level signal may be 0, and the high level signal may be VDD. Alternatively, the reference signal may be VDD, the low level signal may be 1 / 2VDD, and the high level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low level signal, and the high level signal may have different settings, which are not limited in this embodiment.

[0119] In one embodiment, when the storage unit operates in the preprocessing stage, precharge stage, reading stage and sensing stage, the data signal is equal to the reference signal; when the storage unit operates in the write-back and data writing stages, the data signal is greater than or less than the reference signal.

[0120] For example, in the reading stage or the sensing stage, the sensing amplifier used for reading has not yet output the sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized as the reference signal of the reference signal end. For the sensing amplifier circuit 1011, at this time, the voltage or current of the first receiving end is the same as that of the second receiving end, then the first output end of the sensing amplifier circuit 1011 will output a low-level signal, and the second output end will also output a low-level signal. When in the write-back stage, the sensing amplifier used for reading will also output the sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized with the sensing signal output by the sensing amplifier used for reading. Assuming that the write-back data corresponding to the sensing signal in the write-back stage is "1", the data signal transmitted by the write word line WWL can be greater than the reference signal, causing the data signal on the write word line WWL to be synchronized to be greater than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a high-level signal, and the second output end will also output a low-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will output different level signals; assuming that the write-back data corresponding to the sensing signal in the write-back stage is "0", the data signal transmitted by the write word line WWL can be less than the reference signal, causing the data signal on the write word line WWL to be synchronized to be less than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a low-level signal, and the second output end will also output a high-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will also output different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 can always output signals of different levels.

[0121] Further, when the data signal is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same level signal, specifically, the same low level signal. After the two input terminals of the NAND gate receive the same low level signal, its first logic output terminal will output a high level signal to the startup control circuit 201; when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 will output different level signals. Specifically, the first output terminal outputs a low level signal and the second output terminal outputs a high level signal, or the first output terminal outputs a high level signal and the second output terminal outputs a low level signal. After the two input terminals of the NAND gate receive different level signals, its first logic output terminal will output a high level signal to the startup control circuit 201.

[0122] Optionally, the reference signal may be a voltage value of half the power supply voltage VDD, i.e., 1 / 2VDD, the low level signal may be 0, and the high level signal may be VDD. Alternatively, the reference signal may be VDD, the low level signal may be 1 / 2VDD, and the high level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low level signal, and the high level signal may have different settings, which are not limited in this embodiment.

[0123] In one embodiment, when the data signal is greater than the reference signal, the first output signal is a high level signal and the second output signal is a low level signal; when the data signal is less than the reference signal, the first output signal is a low level signal and the second output signal is a high level signal.

[0124] In one embodiment, the write word line enable control method further includes: in response to a sensing enable signal, executing the steps of acquiring a data signal transmitted by the write bit line and outputting a write control signal according to the data signal.

[0125] See also Figure 4 If the control end of the sensing amplifier circuit 1011 does not receive the sensing enable signal, the sensing amplifier circuit 1011 does not work, and the first output end and the second output end of the sensing amplifier circuit 1011 both output low-level signals. If the control end of the sensing amplifier circuit 1011 receives the sensing enable signal, the sensing amplifier circuit starts to work. Assuming that the data signal on the WBL is equal to the reference signal, the first output end and the second output end of the sensing amplifier circuit 1011 still output low-level signals; assuming that the data signal on the WBL is less than the reference signal, the first output end outputs a low-level signal and the second output end outputs a high-level signal; assuming that the data signal on the WBL is greater than the reference signal, the first output end outputs a low-level signal and the second output end outputs a high-level signal.

[0126] See also Figure 5 Based on this embodiment, the working process of the write word line enable control method applied to the write word line enable circuit in any of the above embodiments is described in detail. Of course, the following description is only for a better understanding of this solution and does not constitute a limitation on other embodiments.

[0127] When the write disable instruction is a low level signal, it indicates that the write word line WWL is selected. At this time, no matter whether the third input terminal of the NAND gate logic circuit 2011 inputs a high level signal or a low level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL, so that the write word line WWL can control the write transistor of the storage unit to be turned on. At this time, the sensing enable signal can be configured not to be sent to the sensing amplifier circuit 1011, that is, the sensing amplifier circuit 1011 does not work, and the data signal on the write bit line WBL can be a new data signal to be written. After the write transistor is turned on, the new data signal on the write bit line WBL can be smoothly written to the storage node. Further, when the write disable instruction is a low level signal, the stage of the storage unit at this time can be a data writing stage, that is, in the data writing stage of the storage unit, the write word line enable control method of this embodiment can automatically control the write transistor of the storage unit to remain turned on, so as to write new data to the storage node.

[0128] When the write disable instruction is a high level signal, it indicates that the write word line WWL is not selected. At this time, the sense enable signal can be configured to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 starts to work. At this time, there are two cases: (1) When the data signal on the write bit line WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same low level signal, so that the output terminal of the NOR gate logic circuit 1012 will output a high level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a low level signal to the write word line WWL at this time, so as to disconnect the write transistor through the write word line WWL. At this time, the stage of the storage unit can be the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage, that is, in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage of the storage unit, the write transistor of the storage unit can be automatically controlled to be disconnected through the write word line enable control method of this embodiment to avoid errors in the data stored in the storage node. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals, so that the output terminal of the NOR gate logic circuit 1012 will output a low level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011, and because the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL at this time, so as to turn on the write transistor through the write word line WWL. At this time, the stage that the storage unit is in may be the write-back stage, that is, in the write-back stage of the storage unit, the write word line enable control method of this embodiment can automatically control the write transistor of the storage unit to be turned on, so that the data signal transmitted on the write bit line WBL can be re-written into the storage node to complete the data write-back process.

[0129] Thus, in several stages of the 2T0C memory cell read and write process, the write word line enable control method of this embodiment can realize the automatic turning on or off of the write transistor, so that the turning on or off of the write transistor can meet the requirements of each stage of the 2T0C memory cell read and write process. And because this embodiment does not need to control the timing of the 2T0C memory cell read and write process very accurately as required in the traditional technology, it can improve the read and write fault tolerance rate.

[0130] The present application also provides a memory such as Fig.10As shown, the memory includes: at least one memory array, the memory array includes a plurality of memory cells, the memory cells include read transistors and write transistors, and read word lines and read bit lines connected to the read transistors, and write word lines and write bit lines connected to the write transistors. At least one write word line enable circuit as in any of the above embodiments, the write word line enable circuit is respectively connected to the write bit lines and write word lines in the corresponding memory array.

[0131] Generally, a memory may include at least one storage array, and a read bit line in a storage array may be connected to an SA circuit for reading, where SA is a sense amplifier (SA). The SA circuit amplifies and outputs the sensed signal of the read bit line, and the sensed signal is also output to the write bit line to implement data writeback. For example, see Fig.11 , Fig.11 The memory array 10 includes a memory array including at least one sense amplifier 20 for reading. The memory array 10 also includes a plurality of memory cells 11 arranged in an array, and each memory cell 11 includes two transistors. W-BL1, W-BL2, and W-BL3 are write bit lines, W-WL1, W-WL2, and W-WL3 are write word lines, R-BL1, R-BL2, and R-BL3 are read bit lines, R-WL1, R-WL2, and R-WL3 are read word lines, and VREF is a reference signal (the reference signal here is a voltage signal, and in other suitable embodiments, the reference signal may also be a current signal).

[0132] Each storage array also has a corresponding peripheral circuit. Of course, in some embodiments, two adjacent storage arrays can share a peripheral circuit or a portion of the circuit. The peripheral circuit includes a sense amplifier, which is used to perform a write-back operation in addition to amplifying the read signal. The write-back operation needs to be triggered by a write word line enable circuit.

[0133] The above-mentioned memory includes at least one memory array, the memory array includes a plurality of memory cells, the memory cells include read transistors and write transistors, and read word lines and read bit lines connected to the read transistors, and write word lines and write bit lines connected to the write transistors; at least one write word line enable circuit as in any of the above-mentioned embodiments, the write word line enable circuit is respectively connected to the write bit line and the write word line in the corresponding memory array. By starting the enable signal sent by the control circuit, the write word line can be controlled to respond accurately, so as to timely control the opening or disconnection of the write transistor, so that there is no need to accurately control the timing of the read and write process of the memory cell as required in the related art, thereby improving the read and write fault tolerance rate.

[0134] Optionally, a memory array may be equipped with only one write word line enable circuit, and the write word line enable circuit is connected to the write bit lines and write word lines in the memory array in a one-to-one correspondence. In other words, usually only one write word line enable circuit is needed to meet the write word line enable requirements of the entire memory array. Therefore, in the design of the actual physical location of the memory array, in a memory array, such as Fig. 9 As shown, the write word line enable circuit can be designed at the intersection area, so that the occupied design area is very small. Fig. 9 As shown, the periphery of the memory array can also be designed as the location of a write word line WWL decoder (WWL Decoder), a read word line sense amplifier (RBL SA) and a read word line decoder (RBL Decoder).

[0135] In one embodiment, Figure 6 As shown, the memory further includes a write word line driver and a write word line decoder. The start control circuit is connected to the write word line through the write word line driver, and the write word line driver is also connected to the write word line decoder.

[0136] The present application also provides an electronic device, which includes the memory in the above embodiment. The write word line enabling circuit in the memory can control the write word line to respond accurately, and timely control the opening or disconnection of the write transistor, so that there is no need to accurately control the timing of the read and write process of the storage unit as required in the related art, thereby improving the read and write fault tolerance rate.

[0137] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0138] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A write word line enable circuit, used to connect to a storage unit, the storage unit comprising a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor, characterized in that: include: A sensing control circuit is connected to the write bit line and is configured to: obtain a data signal transmitted by the write bit line and output a write control signal according to the data signal; The startup control circuit is connected to the sensing control circuit and the write word line, and is configured to output an enable signal to the write word line according to the write control signal.

2. The write word line enable circuit according to claim 1, characterized in that: The enable signal includes a turn-on signal and a disable signal. The working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage and a data writing stage. The startup control circuit is further configured to: obtain a write disable instruction, determine the working stage of the storage unit according to the write control signal and the write disable instruction, and when the storage unit works in the write-back stage and the data writing stage, output the turn-on signal to the write word line so that the write word line controls the write transistor to turn on; when the storage unit works in the preprocessing stage, the precharge stage, the reading stage and the sensing stage, output the disable signal to the write word line so that the write word line controls the write transistor to turn off.

3. The write word line enable circuit according to claim 1, characterized in that: The sensing control circuit comprises: A sensing amplifier circuit, comprising a first receiving end, a second receiving end, a first output end, and a second output end; wherein the first receiving end is connected to the write bit line for receiving a data signal transmitted by the write bit line, and the second receiving end is connected to the reference signal end for receiving a reference signal; the sensing amplifier circuit is configured to: when the data signal is greater than or less than the reference signal, the first output end and the second output end output different level signals; when the data signal is equal to the reference signal, the first output end and the second output end output the same level signal; The NOR gate logic circuit has a first input terminal, a second input terminal and a first logic output terminal; wherein the first input terminal is connected to the first output terminal of the sensing amplifier circuit, the second input terminal is connected to the second output terminal of the sensing amplifier circuit, and the first logic output terminal is connected to the startup control circuit.

4. The write word line enable circuit according to claim 3, characterized in that: The sensing amplifier circuit also has a control terminal; the control terminal is configured to receive a sensing enable signal.

5. The write word line enable circuit according to any one of claims 1 to 4, characterized in that: The startup control circuit comprises: A NAND gate logic circuit has a third input terminal, a fourth input terminal and a second logic output terminal; wherein the second logic output terminal is connected to the write word line, the third input terminal is connected to the first logic output terminal of the sensing control circuit, and the fourth input terminal is configured to receive the write disable instruction.

6. A write word line enable control method, characterized in that: The write word line enable control method is applied to the write word line enable circuit according to any one of claims 1 to 5, and the write word line enable control method comprises: A sensing control circuit is used to obtain a data signal transmitted by a write bit line in a storage unit; wherein the storage unit includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; Using the sensing control circuit to output a write control signal according to the data signal; A start-up control circuit is used to output an enable signal to the write word line according to the write control signal.

7. The write word line enable control method according to claim 6, characterized in that: The enable signal includes a start signal and a disable signal, the working phases of the storage unit include a pre-processing phase, a pre-charging phase, a reading phase, a sensing phase, a write-back phase and a data writing phase, and the outputting of the enable signal to the write word line according to the write control signal includes: Get write disable instruction; The working phase of the storage unit is determined according to the write control signal and the write disable instruction. When the storage unit works in the write-back phase and the data writing phase, the enable signal is output to the write word line so that the write word line controls the write transistor to turn on. When the storage unit works in the preprocessing phase, the precharge phase, the reading phase and the sensing phase, the disable signal is output to the write word line so that the write word line controls the write transistor to turn off.

8. The write word line enable control method according to claim 7, characterized in that: The step of determining the working phase of the storage unit according to the write control signal and the write disable instruction comprises: A logical AND-NON operation is performed on the write control signal and the write disable instruction to obtain the enable signal, where the enable signal is used to determine the working phase of the storage unit.

9. The write word line enable control method according to claim 7, characterized in that: When the memory cell operates in the write-back phase, the data signal transmitted by the write bit line comes from the data signal fed back to the write bit line by the read bit line.

10. The write word line enable control method according to claim 6, characterized in that: The step of outputting a write control signal according to the data signal comprises: Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal; When the data signal is greater than or less than the reference signal, two different level signals are output as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, two same level signals are output as the first output signal and the second output signal respectively; A logical negation operation is performed on the first output signal and the second output signal to obtain the write control signal.

11. The write word line enable control method according to claim 10, characterized in that: The working phases of the storage unit include a preprocessing phase, a precharging phase, a reading phase, a sensing phase, a write-back phase and a data writing phase. When the storage unit works in the preprocessing phase, the precharging phase, the reading phase and the sensing phase, the data signal is equal to the reference signal; When the storage unit operates in the write-back and data writing phases, the data signal is greater than or less than the reference signal.

12. The write word line enable control method according to claim 10, characterized in that: When the data signal is greater than the reference signal, the first output signal is a high level signal and the second output signal is a low level signal; when the data signal is less than the reference signal, the first output signal is a low level signal and the second output signal is a high level signal.

13. The write word line enable control method according to claim 6, characterized in that: Also includes: In response to the sensing enable signal, the steps of acquiring the data signal transmitted by the write bit line in the storage unit and outputting the write control signal according to the data signal are performed.

14. A memory, characterized in that: include: at least one memory array, the memory array comprising a plurality of memory cells, the memory cells comprising a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; At least one write word line enable circuit according to any one of claims 1 to 5, wherein the write word line enable circuit is respectively connected to the write bit line and the write word line in the corresponding memory array.

15. The memory according to claim 14, characterized in that: The memory further comprises a write word line driver and a write word line decoder. The start control circuit is connected to the write word line through the write word line driver. The write word line driver is also connected to the write word decoder.

16. An electronic device, characterized in that: Comprising a memory as described in any one of claims 14-15.

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