Display device

Abstract

A display device is disclosed. The display device includes: a driving transistor including a first semiconductor layer and a first gate electrode, the first semiconductor layer including silicon; a first switching transistor including a second semiconductor layer and a second gate electrode, the second semiconductor layer including an oxide; a first shielding layer overlapping the driving transistor, the first shielding layer being interposed between the substrate and the first semiconductor layer; a second shielding layer overlapping the first switching transistor, the second shielding layer being interposed between the substrate and the second semiconductor layer; and a first capacitor including a first electrode and a second electrode, in which: the first electrode of the first capacitor is at least a part of the first gate electrode of the driving transistor, and the second electrode of the first capacitor is on and overlaps the first gate electrode of the driving transistor; and the second electrode is positioned on the same layer as the second shielding layer.

Description

[0001] This application is a divisional application of the invention patent application with application number 2019106383895, application date July 16, 2019, and invention name “display device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0107379, filed on September 7, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0004] Exemplary embodiments of the present invention generally relate to display devices. Background Art

[0005] A display device such as an organic light emitting display device, a liquid crystal display (LCD) device, etc. includes an array substrate including a thin film transistor (TFT), a capacitor, and a plurality of wirings. The array substrate includes fine patterns such as TFTs, capacitors, and wirings, and such a display device is driven by complex connections between TFTs, capacitors, and wirings.

[0006] As the demand for display devices having compact size and high resolution increases, the demand for efficient spatial arrangement between TFTs, capacitors and wirings of the display devices, their connection structures, driving methods and improvement in quality of images achieved is also increasing.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] A device constructed according to an exemplary embodiment of the present invention discloses a display device including a transistor having improved characteristics.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] According to one or more embodiments, a display device includes: a driving transistor, the driving transistor includes a first semiconductor layer and a first gate electrode, the first semiconductor layer includes silicon; a first switching transistor, the first switching transistor includes a second semiconductor layer and a second gate electrode, the second semiconductor layer includes an oxide; a first shielding layer, the first shielding layer overlaps with the driving transistor, and the first shielding layer is between a substrate and the first semiconductor layer; a second shielding layer, the second shielding layer overlaps with the first switching transistor, and the second shielding layer is between the substrate and the second semiconductor layer; and a first capacitor, the first capacitor includes a first electrode and a second electrode, wherein: the first electrode of the first capacitor is at least a portion of the first gate electrode of the driving transistor, and the second electrode of the first capacitor is located on the first gate electrode of the driving transistor and overlaps with the first gate electrode of the driving transistor; and the second electrode and the second shielding layer are positioned on the same layer.

[0011] The first shielding layer and the second shielding layer include different materials.

[0012] The second electrode and the second shielding layer include the same material.

[0013] The same voltage is applied to the second gate electrode and the second shielding layer.

[0014] The display device further includes a second switching transistor including a third semiconductor layer and a third gate electrode, the third semiconductor layer including an oxide, wherein the same voltage is applied to the third gate electrode and the second shielding layer.

[0015] The display device also includes a second capacitor, which includes a first electrode and a second electrode overlapping the first electrode of the second capacitor, wherein the first electrode of the second capacitor is positioned on the same layer as the first gate electrode of the driving transistor, and the second electrode of the second capacitor is positioned on the same layer as the second semiconductor layer of the first switching transistor.

[0016] The second electrode of the second capacitor and the second semiconductor layer include the same material.

[0017] The second shielding layer is interposed between the first electrode and the second electrode of the second capacitor.

[0018] The display device further includes a power supply line overlapping the first shielding layer.

[0019] According to one or more embodiments, a display device includes: a substrate; a first insulating layer, the first insulating layer is located on the substrate; a driving transistor, the driving transistor includes a first gate electrode and a first semiconductor layer; a first capacitor, the first capacitor overlaps with the driving transistor and includes a first electrode and a second electrode, the first electrode is a first gate electrode and the second electrode overlaps with the first electrode; a first switching transistor, the first switching transistor includes a second gate electrode and a second semiconductor layer, the second gate electrode is arranged on the first gate electrode of the driving transistor; a second insulating layer, the second insulating layer is arranged between the first gate electrode and the first semiconductor layer; a third insulating layer, the third insulating layer is arranged between the first electrode and the second electrode; a Four insulating layers, a fourth insulating layer is arranged on the second electrode, and the fourth insulating layer is arranged between the first gate electrode and the second gate electrode; a fifth insulating layer, the fifth insulating layer is arranged between the second gate electrode and the second semiconductor layer; a first shielding layer, the first shielding layer overlaps with the driving transistor, and the first shielding layer is between the substrate and the first semiconductor layer; a second shielding layer, the second shielding layer overlaps with the first switching transistor, and the second shielding layer is between the third insulating layer and the second semiconductor layer; a first connecting electrode, the first connecting electrode is located on the second gate electrode and connected to the first gate electrode and the second semiconductor layer; and a second connecting electrode, the second connecting electrode is located on the second gate electrode and connected to the first gate electrode and the second semiconductor layer.

[0020] The display device further includes a second switching transistor, the second switching transistor includes a third semiconductor layer and a third gate electrode, the third semiconductor layer includes oxide, wherein the second semiconductor layer and the third semiconductor layer are integrated.

[0021] The display device also includes a second capacitor including a first electrode and a second electrode overlapping the first electrode of the second capacitor, wherein the first electrode of the second capacitor is positioned at the same layer as the first gate electrode, and the second electrode of the second capacitor is positioned at the same layer as the second semiconductor layer.

[0022] The second electrode of the second capacitor and the second semiconductor layer include the same material.

[0023] The display device further includes a power supply line overlapping the first shielding layer.

[0024] The same voltage is applied to the second gate electrode and the second shielding layer.

[0025] The second shielding layer is interposed between the first electrode and the second electrode of the second capacitor.

[0026] According to one or more embodiments, a display device includes a first pixel and a second pixel located in a display area, each of the first pixel and the second pixel including: a driving transistor, the driving transistor including a first semiconductor layer and a first gate electrode, the first semiconductor layer including silicon; a switching transistor, the switching transistor including a second semiconductor layer and a second gate electrode, the second semiconductor layer including oxide; a first shielding layer, the first shielding layer overlapping the driving transistor, the first shielding layer being between a substrate and the first semiconductor layer; and a second shielding layer, the second shielding layer overlapping the switching transistor, the second shielding layer being between the substrate and the second semiconductor layer, wherein: the first shielding layer of the first pixel and the first shielding layer of the second pixel adjacent to the first pixel are spaced apart from each other; and the second shielding layer of the first pixel and the second shielding layer of the second pixel are integrated.

[0027] The display device further includes a power supply line overlapping the first shielding layer and the second shielding layer of the first pixel and the second pixel.

[0028] Each of the first pixel and the second pixel also includes a capacitor overlapping the driving transistor.

[0029] The capacitor includes a first electrode and a second electrode, the second electrode being positioned at the same layer as the second shielding layer.

[0030] According to one or more embodiments, the display device includes a first thin film transistor (TFT) (e.g., T1 discussed with reference to the figure), a second TFT (e.g., T3 discussed with reference to the figure), a first shielding layer and a second shielding layer, the first TFT includes a first semiconductor layer, the first semiconductor layer includes a silicon semiconductor; the second TFT includes a second semiconductor layer, the second semiconductor layer includes an oxide semiconductor, one end of the second semiconductor layer is connected to one end of the first semiconductor layer of the first TFT, and the other end of the second semiconductor layer is connected to the gate electrode of the first TFT; the first shielding layer is configured to overlap with the first TFT, the first shielding layer is interposed between the substrate and the first TFT; and the second shielding layer is configured to overlap with the second TFT, the second shielding layer is interposed between the substrate and the second TFT.

[0031] The first shielding layer and the second shielding layer may be positioned on the same layer.

[0032] The first shielding layer and the second shielding layer may be positioned on different layers.

[0033] The second shielding layer may be positioned on the same layer as the first semiconductor layer.

[0034] The second shielding layer may be positioned on the same layer as the gate electrode of the first TFT.

[0035] The display device may further include a capacitor overlapping the first TFT, wherein the second shielding layer may be positioned on the same layer as one electrode of the capacitor.

[0036] The display device may further include a capacitor overlapping the second shielding layer and positioned between the second shielding layer and the second TFT.

[0037] One electrode of the capacitor may be positioned on the same layer as one of a first semiconductor layer of the first TFT and a gate electrode of the first TFT overlapping a channel region of the first semiconductor layer.

[0038] The display device may further include at least one of a first touch sensor and a second touch sensor, the first touch sensor overlaps the first TFT, and the second touch sensor overlaps the second shielding layer and is positioned between the second shielding layer and the substrate.

[0039] The first shielding layer may be electrically connected to a power supply line for applying a power supply voltage.

[0040] The first shielding layer may be electrically connected to a power supply line for applying an initialization voltage.

[0041] The first shielding layer may be electrically connected to the first semiconductor layer.

[0042] The first shielding layer may be electrically connected to a gate electrode of the first TFT.

[0043] The second shielding layer may be electrically connected to a power supply line for applying an initialization voltage.

[0044] The second shielding layer may be electrically connected to a gate electrode of the second TFT.

[0045] The first TFT may be a driving transistor, and the second TFT may be a switching transistor.

[0046] The first TFT may be a switching transistor, and the second TFT may be a driving transistor.

[0047] According to one or more embodiments, the display device includes a first thin film transistor (TFT), a second TFT, a capacitor, a first shielding layer, and a second shielding layer, the first TFT includes a first semiconductor layer, the first semiconductor layer includes a silicon semiconductor; the second TFT includes a second semiconductor layer, the second semiconductor layer includes an oxide semiconductor; the capacitor overlaps with the first TFT; the first shielding layer overlaps with the first TFT, the first shielding layer is interposed between the substrate and the first TFT; and the second shielding layer overlaps with the second TFT, the second shielding layer is interposed between the substrate and the second TFT.

[0048] The same voltage may be applied to the first shielding layer and the second shielding layer.

[0049] Different voltages may be applied to the first shielding layer and the second shielding layer.

[0050] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0052] Figure 1 is a plan view schematically showing a display device according to an exemplary embodiment;

[0053] Figure 2A , Figure 2B , Figure 2C and Figure 2D is a cross-sectional view showing a pixel structure constructed according to an exemplary embodiment;

[0054] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment;

[0055] Figure 4A , Figure 4B and Figure 4C is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment;

[0056] Figure 5 is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment;

[0057] Fig. 6A , Figure 6B and Figure 6C is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment;

[0058] Figure 7 According to an exemplary embodiment Figure 1 An equivalent circuit diagram of a pixel shown in ;

[0059] Figure 8 is a view schematically showing a pixel arrangement according to an exemplary embodiment;

[0060] Fig. 9 is a schematic diagram showing a Figure 7 Layout diagram of transistors and capacitors of a pixel shown in FIG.

[0061] Fig.10 is along Fig. 9 A cross-sectional view taken along section lines I-I' and II-II';

[0062] Fig.11 is a schematic diagram showing a method according to another exemplary embodiment Figure 7 Layout diagram of transistors and capacitors of a pixel shown in FIG.

[0063] Fig.12 is along Fig.11 A cross-sectional view taken along section lines III-III' and IV-IV';

[0064] Fig.13 is a schematic diagram showing a method according to another exemplary embodiment Figure 7 A layout diagram of transistors and capacitors of a pixel shown in FIG. 1 ; and

[0065] Fig.14 is along Fig.13 Cross-sectional view taken along section lines V-V' and VI-VI'. DETAILED DESCRIPTION

[0066] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "implementation" and "implementation" are interchangeable words, which are non-limiting examples of one or more devices or methods using the inventive concept disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment.

[0067] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details that can implement some ways of the inventive concept in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0068] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading will not convey or indicate any preference or requirement for a specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0069] When an element (e.g., a layer) is referred to as being "on," "connected to," or "coupled to" another element or layer, the element (e.g., a layer) may be directly on, connected to, or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may indicate a physical, electrical, and / or fluid connection with or without intermediate elements. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from a cluster consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0070] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0071] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0072] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the words "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements, parts and / or clusters thereof is indicated, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the words "substantially", "about" and other similar words are used as approximate words rather than words of degree, and thus, are used to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0073] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0074] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform some functions to perform other functions. Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0076] Figure 1 is a plan view schematically illustrating a display device according to an exemplary embodiment.

[0077] Pixels PX including various display devices such as organic light emitting devices (OLEDs) may be positioned in the first direction and the second direction in the display area DA of the substrate 110. The pixels PX may include the display device and a pixel circuit for driving the display device. Various wirings and driving circuits (i.e., a scan driver, a multiplexer (MUX), and a data driver) for transmitting electrical signals to the display area DA may be positioned in the peripheral area PA of the substrate 110.

[0078] The pixel circuit and the driving circuit may be implemented using a plurality of thin film transistors (TFTs) and formed over the substrate 110. Depending on the semiconductor material used to form the active layer, the plurality of TFTs may be implemented using oxide semiconductor TFTs or silicon (Si) semiconductor TFTs. Appropriate types of TFTs that meet required standards such as leakage current, switching speed, driving strength, and uniformity may be used in the pixel circuit and the driving circuit, thereby enhancing display performance.

[0079] In the display device according to the embodiment, at least two types of TFTs may be formed over the substrate 110. The at least two types of TFTs include a silicon (Si) semiconductor TFT having a semiconductor layer including Si material and an oxide semiconductor TFT having a semiconductor layer including oxide. The Si semiconductor TFT may be a low temperature polycrystalline silicon (LTPS) TFT, an amorphous silicon (a-si) TFT, or a polycrystalline silicon (p-si) TFT.

[0080] Since Si material has relatively high electron mobility and thus has low energy consumption and excellent reliability, Si semiconductor TFTs may be applied to driving TFTs of pixel circuits and TFTs of driving circuits.

[0081] Oxide semiconductor materials have an off current lower than that of Si materials. Therefore, oxide semiconductor TFTs can be applied to switching TFTs that have a short on time and maintain a long off time. Moreover, since the off current is small and the size of the auxiliary capacitor can be reduced, oxide semiconductor TFTs are suitable for high-resolution display devices.

[0082] In a display device according to one or more embodiments, different types of TFTs such as an oxide semiconductor TFT (hereinafter referred to as an "oxide TFT") and a silicon semiconductor TFT (hereinafter referred to as a "Si TFT") may be applied to a pixel circuit and a driving circuit. In one or more embodiments, the oxide TFT may be an n-channel TFT (ie, an n-channel metal oxide semiconductor (NMOS) TFT), and the Si TFT may be a p-channel TFT or an n-channel TFT (ie, a p-channel metal oxide semiconductor (PMOS) TFT or an NMOS TFT).

[0083] In the display device according to various embodiments, different types of silicon TFTs and oxide TFTs are positioned over the same substrate, thereby providing optimal functions.

[0084] Figure 2A , Figure 2B , Figure 2C and Figure 2D is a cross-sectional view showing a pixel structure constructed according to an exemplary embodiment. Figure 2A , Figure 2B , Figure 2C and Figure 2D 2 shows an embodiment in which the positions of the second shielding layers are different from each other. Figure 2A Exemplary embodiments are described and FIG. 2B to FIG. 2D In the Figure 2A Redundant description of .

[0085] Reference Figure 2A , the pixel PX1 according to the exemplary embodiment may include a first transistor M1, a second transistor M2, and a capacitor Cst positioned above the substrate 110. The top surface of the substrate 110 may be Figure 1 ) and the second direction (see Figure 1 )limited.

[0086] The first transistor M1 and the second transistor M2 may be positioned on different layers. The second transistor M2 may be positioned on an upper layer of the first transistor M1. The capacitor Cst may overlap the first transistor M1. The first transistor M1 may be a Si TFT. The second transistor M2 may be an oxide TFT.

[0087] The first transistor M1 may include a first semiconductor layer 21, a first gate electrode 22, a first source electrode 23, and a first drain electrode 24. The second transistor M2 may include a second semiconductor layer 31, a second gate electrode 32, a second source electrode 33, and a second drain electrode 34. The capacitor Cst may include a first electrode 41 and a second electrode 43.

[0088] A first shielding layer 120 may be positioned between the first transistor M1 and the substrate 110, and a second shielding layer 130a may be positioned between the second transistor M2 and the substrate 110. The first shielding layer 120 may be positioned to overlap the first transistor M1, and the second shielding layer 130a may be positioned to overlap the second transistor M2.

[0089] Due to the change of light introduced from the outside and the voltage applied to the circuit device, charges may be induced to the substrate 110, which may affect the semiconductor layer of the TFT. Therefore, the characteristics of the TFT (such as the threshold voltage) are changed, so that afterimages may occur and / or the light emission uniformity may be reduced.

[0090] In an exemplary embodiment, each of the first shielding layer 120 and the second shielding layer 130a may be positioned between the substrate 110 and the first transistor M1 and the second transistor M2, and an appropriate voltage is applied to each of the first shielding layer 120 and the second shielding layer 130a according to the semiconductor type and the channel type of the transistor, so that the first transistor M1 and the second transistor M2 are not affected by external light and the potential of the substrate 110, and the transistor characteristics can be enhanced.

[0091] A buffer layer 10 may be positioned on the substrate 110 , and the first transistor M1 , the second transistor M2 , and the capacitor Cst may be positioned on the buffer layer 10 .

[0092] The first shielding layer 120 in a region corresponding to the first transistor M1 and the second shielding layer 130 a in a region corresponding to the second transistor M2 may be positioned on the buffer layer 10 .

[0093] Each of the first shielding layer 120 and the second shielding layer 130a may include a metal and may have a single-layer or multi-layer structure. For example, the first shielding layer 120 and the second shielding layer 130a may have a single-layer structure including molybdenum (Mo). In another exemplary embodiment, the first shielding layer 120 and the second shielding layer 130a may have a three-layer structure including a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including Ti sequentially positioned on the buffer layer 10.

[0094] A first insulating layer 11 may be positioned on the first shielding layer 120 and the second shielding layer 130a. A first semiconductor layer 21 of the first transistor M1 may be positioned on the first insulating layer 11. The first semiconductor layer 21 may include polysilicon.

[0095] A second insulating layer 12 may be positioned on the first semiconductor layer 21. A first gate electrode 22 may be positioned on the second insulating layer 12. The first gate electrode 22 may serve as a first electrode 41 of the capacitor Cst. A third insulating layer 13 may be positioned on the first gate electrode 22. A second electrode 43 of the capacitor Cst may be positioned on the third insulating layer 13. A fourth insulating layer 14 may be positioned on the second electrode 43 of the capacitor Cst.

[0096] The second semiconductor layer 31 of the second transistor M2 may be positioned on the fourth insulating layer 14. The second semiconductor layer 31 may include an oxide semiconductor. The oxide semiconductor may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and Ti, or a mixture of a metal such as Zn, In, Ga, Sn, Ti and their oxides. For example, the oxide semiconductor may be formed of a zinc oxide-based material, such as zinc oxide, indium zinc oxide, or gallium indium zinc oxide. In some exemplary embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor, in which metals such as In and Ga are contained in ZnO.

[0097] A fifth insulating layer 15 may be positioned on the second semiconductor layer 31. A second gate electrode 32 may be positioned on the fifth insulating layer 15. A sixth insulating layer 16 may be positioned on the second gate electrode 32.

[0098] The first source electrode 23 and the first drain electrode 24 of the first transistor M1 and the second source electrode 33 and the second drain electrode 34 of the second transistor M2 may be positioned on the sixth insulating layer 16 .

[0099] A seventh insulating layer 17 may be positioned above the first transistor M1 and the second transistor M2. A conductive layer 140 may be positioned on the seventh insulating layer 17. The conductive layer 140 may be a connection electrode for electrically connecting one electrode among a plurality of transistors including the first transistor M1 and the second transistor M2 of the pixel PX and the capacitor Cst to the pixel electrode PE. An eighth insulating layer 18 may be positioned on the conductive layer 140. The pixel electrode PE may be positioned on the eighth insulating layer 18. A ninth insulating layer 19 may be positioned at an edge of the pixel electrode PE. The pixel electrode PE may be electrically connected to the conductive layer 140.

[0100] exist Figure 2B In the pixel PX2 shown in FIG. 1 , the second shielding layer 130b is formed on the same layer as the first semiconductor layer 21 of the first transistor M1. The first semiconductor layer 21 of the first transistor M1 and the second shielding layer 130b may be positioned on the first insulating layer 11. The first semiconductor layer 21 may include polysilicon.

[0101] The first shielding layer 120 may include metal and have a single layer or multi-layer structure. The second shielding layer 130b may be formed of the same material as the first semiconductor layer 21 and may include polysilicon. The second insulating layer 12 may be positioned on the first semiconductor layer 21 and the second shielding layer 130b.

[0102] exist Figure 2C In the pixel PX3 shown in FIG. 1 , the second shielding layer 130 c is formed on the same layer as the first gate electrode 22 of the first transistor M1 . The first gate electrode 22 of the first transistor M1 and the second shielding layer 130 c may be positioned on the second insulating layer 12 .

[0103] The first shielding layer 120 may include metal, and may have a single layer or multi-layer structure. The second shielding layer 130c may include the same material as that of the first gate electrode 22. The third insulating layer 13 may be positioned on the first gate electrode 22 and the second shielding layer 130c.

[0104] exist Figure 2D In the pixel PX4 shown in FIG. 1 , the second shielding layer 130 d is formed on the same layer as the second electrode 43 of the capacitor Cst. The second electrode 43 of the capacitor Cst and the second shielding layer 130 d may be positioned on the third insulating layer 13 .

[0105] The first shielding layer 120 may include metal, and may have a single layer or multi-layer structure. The second shielding layer 130d may include the same material as that of the second electrode 43. The fourth insulating layer 14 may be positioned on the second electrode 43 and the second shielding layer 130d.

[0106] Figure 2A , Figure 2B , Figure 2C and Figure 2D Each of the first shielding layer 120 and the second shielding layer 130a, 130b, 130c, and 130d shown in FIG. 1 may be electrically connected to a different conductive layer so that different voltages may be applied from the conductive layer to the first shielding layer 120 and the second shielding layer 130a, 130b, 130c, and 130d. The conductive layer may be an electrode of a circuit device within the pixel PX, or a wiring for applying a signal or voltage to the pixel PX.

[0107] In an exemplary embodiment, Figure 2A , Figure 2B , Figure 2C and Figure 2D The first transistor M1 shown in FIG. 1 may be a p-channel transistor, and Figure 2A , Figure 2B , Figure 2C and Figure 2D The second transistor M2 shown in the figure may be an n-channel transistor. In this case, the first shielding layer 120 may be electrically connected to a power line electrically connected to a positive (+) constant voltage source or to a power line electrically connected to a negative (-) constant voltage source. Each of the second shielding layers 130a, 130b, 130c and 130d may be electrically connected to the second gate electrode 32 of the second transistor M2, or to a power line electrically connected to a negative (-) constant voltage source.

[0108] In another exemplary embodiment, Figure 2A , Figure 2B , Figure 2C and Figure 2D The first transistor M1 shown in FIG. 1 may be an n-channel transistor, and Figure 2A , Figure 2B , Figure 2C and Figure 2D The second transistor M2 shown in the figure may be an n-channel transistor. In this case, the first shielding layer 120 may be electrically connected to the first gate electrode 22 or the first source electrode 23 of the first transistor M1, or to a power line electrically connected to a negative (-) constant voltage source. Each of the second shielding layers 130a, 130b, 130c and 130d may be electrically connected to the second gate electrode 32 of the second transistor M2, or to a power line electrically connected to a negative (-) constant voltage source.

[0109] In another exemplary embodiment, Figure 2A , Figure 2B , Figure 2C and Figure 2D The first shielding layer 120 and the second shielding layers 130a, 130b, 130c, and 130d shown in FIG. 1 may also be electrically floating.

[0110] When the same voltage is applied to Figure 2A , Figure 2B , Figure 2C and Figure 2D The first shielding layer 120 and the second shielding layers 130a, 130b, 130c and 130d shown, or Figure 2A , Figure 2B , Figure 2C and Figure 2D When the first shielding layer 120 and the second shielding layer 130a, 130b, 130c and 130d shown in FIG. are electrically floated, the first shielding layer 120 and the second shielding layer 130a, 130b, 130c and 130d may be electrically connected to each other. At this time, the first shielding layer 120 and the second shielding layer 130a may not be separated from each other, but may be integrally formed.

[0111] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment. Due to the capacitors C1, C2 and C3 configured to further improve the optical characteristics of the second transistor M2 and disposed under the second transistor M2, Figure 3A , Figure 3B and Figure 3C The pixels PX5, PX6 and PX7 shown in FIG. Figure 2A The pixel PX1 shown in FIG. 1 is different. In the following, the pixel PX1 will be omitted. Figure 2A 's redundant description and their differences will be described.

[0112] exist Figure 3A In the pixel PX5 shown in FIG. 1 , the first capacitor C1 may be disposed between the second transistor M2 and the second shielding layer 130 a. The first capacitor C1 may include a lower electrode 181 and an upper electrode 182. The lower electrode 181 may be positioned on the first insulating layer 11, and the upper electrode 182 may be positioned on the second insulating layer 12. The lower electrode 181 may include the same material as the material used to form the first semiconductor layer 21 of the first transistor M1. The upper electrode 182 may include the same material as the material used to form the first gate electrode 22 of the first transistor M1.

[0113] The upper electrode 182 of the first capacitor C1 may be electrically connected to the second shielding layer 130a, and the lower electrode 181 of the first capacitor C1 may be electrically floated. In another exemplary embodiment, both the upper electrode 182 and the lower electrode 181 of the first capacitor C1 may be electrically floated.

[0114] exist Figure 3B In the pixel PX6 shown in FIG. 1 , the second capacitor C2 may be disposed between the second transistor M2 and the second shielding layer 130a. The second capacitor C2 may include a lower electrode 183 and an upper electrode 184. The lower electrode 183 may be positioned on the first insulating layer 11, and the upper electrode 184 may be positioned on the third insulating layer 13. The lower electrode 183 may include the same material as the material used to form the first semiconductor layer 21 of the first transistor M1. The upper electrode 184 may include the same material as the material used to form the second electrode 43 of the capacitor Cst.

[0115] The upper electrode 184 of the second capacitor C2 may be electrically connected to the second shielding layer 130a, and the lower electrode 183 of the second capacitor C2 may be electrically floated. In another exemplary embodiment, both the upper electrode 184 and the lower electrode 183 of the second capacitor C2 may be electrically floated.

[0116] exist Figure 3C In the pixel PX7 shown in FIG. 1 , the third capacitor C3 may be disposed between the second transistor M2 and the second shielding layer 130a. The third capacitor C3 may include a lower electrode 185 and an upper electrode 186. The lower electrode 185 may be positioned on the second insulating layer 12, and the upper electrode 186 may be positioned on the third insulating layer 13. The lower electrode 185 may include the same material as the material used to form the first gate electrode 22 of the first transistor M1. The upper electrode 186 may include the same material as the material used to form the second electrode 43 of the capacitor Cst.

[0117] The upper electrode 186 of the third capacitor C3 may be electrically connected to the second shielding layer 130a, and the lower electrode 185 of the third capacitor C3 may be electrically floated. In another exemplary embodiment, both the upper electrode 186 and the lower electrode 185 of the third capacitor C3 may be electrically floated.

[0118] Figure 4A , Figure 4B and Figure 4C is a cross-sectional view showing a pixel structure constructed according to an exemplary embodiment. Figure 4A , Figure 4B and Figure 4C In the pixel shown in FIG. 1 , a touch sensor TS is disposed under the second transistor M2. Figure 2A 's redundant description and their differences will be described.

[0119] exist Figure 4A , Figure 4B and Figure 4C In the pixels PX8, PX9, and PX10 shown in FIG, the touch sensor TS may be positioned under the second transistor M2. The touch sensor TS may include a first touch electrode TE1 and a second touch electrode TE2 positioned above the buffer layer 10 and separated from each other. The first touch electrode TE1 and the second touch electrode TE2 may include the same material as that used to form the first shielding layer 120 under the first transistor M1. Each of the first touch electrode TE1 and the second touch electrode TE2 may be one of a transmission electrode and a reception electrode.

[0120] Reference Figure 4A , a second shielding layer 130b may be positioned on the touch sensor TS. That is, the second shielding layer 130b may be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130b may be positioned on the first insulating layer 11 and may be formed of the same material as the first semiconductor layer 21 forming the first transistor M1.

[0121] Reference Figure 4B , a second shielding layer 130c may be positioned on the touch sensor TS. That is, the second shielding layer 130c may be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130c may be positioned on the second insulating layer 12 and may be formed of the same material as the material used to form the first gate electrode 22 of the first transistor M1.

[0122] Reference Figure 4C , a second shielding layer 130d may be positioned on the touch sensor TS. That is, the second shielding layer 130d may be positioned between the touch sensor TS and the second transistor M2. The second shielding layer 130d may be positioned on the third insulating layer 13 and may be formed of the same material as that used to form the second electrode 43 of the capacitor Cst.

[0123] Figure 5 is a cross-sectional view showing a pixel structure constructed according to an exemplary embodiment. Figure 5 In the pixel PX11 shown in FIG. 1 , the touch sensor TS is disposed above the first transistor M1. Figure 2A 's redundant description and their differences will be described.

[0124] exist Figure 5 In the pixel PX11 shown in FIG, a first touch electrode TE1 may be positioned above the fifth insulating layer 15, a sixth insulating layer 16 may be positioned above the first touch electrode TE1, and a second touch electrode TE2 may be positioned above the sixth insulating layer 16. Each of the first touch electrode TE1 and the second touch electrode TE2 may be one of a transmission electrode and a reception electrode.

[0125] Fig. 6A , Figure 6B and Figure 6C is a cross-sectional view showing a pixel structure constructed according to another exemplary embodiment. Fig. 6A , Figure 6B and Figure 6C In the embodiment, the second touch sensor TS2 is disposed below the second transistor M2, and the first touch sensor TS1 is disposed above the first transistor M1.

[0126] Reference Fig. 6A , in the pixel PX12, a first shielding layer 120 may be provided under the first transistor M1, and a second shielding layer 130b may be provided under the second transistor M2. The second touch sensor TS2 may be provided under the second shielding layer 130b. The second touch sensor TS2 includes a first touch electrode TE21 and a second touch electrode TE22 that are positioned above the buffer layer 10 and are separated from each other, and may be positioned on the same layer as the first shielding layer 120. The first touch sensor TS1 may be provided above the first transistor M1. The first touch sensor TS1 may include a first touch electrode TE11 above the fifth insulating layer 15 and a second touch electrode TE12 above the sixth insulating layer 16.

[0127] Reference Figure 6B , in the pixel PX13, the first shielding layer 120 may be disposed under the first transistor M1, and the second shielding layer 130c may be disposed under the second transistor M2. The second touch sensor TS2 may be disposed under the second shielding layer 130c. The second touch sensor TS2 may include a first touch electrode TE21 and a second touch electrode TE22 that are positioned above the buffer layer 10 and are separated from each other, and may be positioned on the same layer as the first shielding layer 120. The first touch sensor TS1 may be disposed above the first transistor M1. The first touch sensor TS1 may include a first touch electrode TE11 above the fifth insulating layer 15 and a second touch electrode TE12 above the sixth insulating layer 16.

[0128] Reference Figure 6C, in the pixel PX14, the first shielding layer 120 may be disposed under the first transistor M1, and the second shielding layer 130d may be disposed under the second transistor M2. The second touch sensor TS2 may be disposed under the second shielding layer 130d. The second touch sensor TS2 may include a first touch electrode TE21 and a second touch electrode TE22 that are positioned above the buffer layer 10 and are separated from each other, and may be positioned on the same layer as the first shielding layer 120. The first touch sensor TS1 may be disposed above the first transistor M1. The first touch sensor TS1 may include a first touch electrode TE11 above the fifth insulating layer 15 and a second touch electrode TE12 above the sixth insulating layer 16.

[0129] Figure 7 According to an exemplary embodiment Figure 1 Equivalent circuit diagram of the pixel shown in .

[0130] Reference Figure 7 The pixel PX includes a display device and a pixel circuit for driving the display device by receiving signals from a plurality of wirings. Hereinafter, a pixel PX having an OLED as a display device will be described as an exemplary embodiment.

[0131] exist Figure 7 In the embodiment, each pixel PX is provided with a first scan line 131, a light emission control line 133, a second scan line 151, a third scan line 153, a data line 171, an initialization voltage line 141, and a power supply voltage line 161. However, exemplary embodiments are not limited thereto. In another exemplary embodiment, at least one of the first scan line 131, the light emission control line 133, the second scan line 151, the third scan line 153, and the data line 171, the initialization voltage line 141, and the power supply voltage line 161 may be shared in adjacent pixels.

[0132] In an exemplary embodiment, it is applicable Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5 , Fig. 6A , Figure 6B and Figure 6C, so that the performance of the pixel PX can be optimized. For example, the driving transistor (e.g., T1) can be formed with a silicon transistor (e.g., an NMOS silicon transistor or a PMOS silicon transistor), and the switch transistor (such as other transistors, e.g., T2, T3, T4, T5, T6, and T7) can be formed with an oxide transistor (e.g., an NMOS oxide transistor, or a combination of an NMOS and / or PMOS silicon transistor and an NMOS oxide transistor). In another example, the driving transistor (e.g., T1) can be formed with an NMOS oxide transistor, and the other transistors (e.g., T2, T3, T4, T5, T6, and T7) can be formed with a silicon transistor, or a combination of an NMOS and / or PMOS silicon transistor and an NMOS oxide transistor.

[0133] exist Figure 7 In the embodiment, the third transistor T3 and the fourth transistor T4 among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are NMOS oxide transistors, and the other transistors are PMOS silicon transistors.

[0134] The signal lines include a first scan line 131 for transmitting a first scan signal GWP, a second scan line 151 for transmitting a second scan signal GWN, a third scan line 153 for transmitting a third scan signal GI, a light emitting control line 133 for transmitting a light emitting control signal EM, and a data line 171 for transmitting a data signal DATA while crossing the first scan line 131.

[0135] The power supply voltage line 161 transmits the first power supply voltage ELVDD to the first transistor T1 , and the initialization voltage line 141 transmits the initialization voltage VINT for initializing the first transistor T1 and the pixel electrode to the pixel PX.

[0136] The pixel circuit of the pixel PX may include a plurality of transistors T1 to T7 and a capacitor Cst. Depending on the type (p-type or n-type) of the transistor and / or the operating conditions, Figure 7 The first electrodes E11, E21, E31, E41, E51, E61 and E71 and the second electrodes E12, E22, E32, E42, E52, E62 and E72 may be source electrodes (source regions) or drain electrodes (drain regions). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be implemented by TFTs.

[0137] The first transistor T1 includes a gate electrode G1 connected to a first electrode Cst1 of the capacitor Cst, a first electrode E11 connected to a power supply voltage line 161 via a fifth transistor T5, and a second electrode E12 electrically connected to a pixel electrode of the OLED via a sixth transistor T6. The first transistor T1 functions as a driving transistor, receives a data signal DATA according to a switching operation of the second transistor T2, and supplies current to the OLED.

[0138] The second transistor T2 includes a gate electrode G2 connected to the first scan line 131, a first electrode E21 connected to the data line 171, and a second electrode E22 connected to the first electrode E11 of the first transistor T1. The second transistor T2 is turned on according to the first scan signal GWP transmitted via the first scan line 131, and performs a switching operation of transmitting the data signal DATA transmitted from the data line 171 to the first electrode E11 of the first transistor T1.

[0139] The third transistor T3 includes a gate electrode G3 connected to the second scan line 151, a first electrode E31 connected to the second electrode E12 of the first transistor T1, and a first electrode Cst1 connected to the capacitor Cst, a second electrode E42 of the fourth transistor T4, and a second electrode E32 of the gate electrode G1 of the first transistor T1. The first electrode E31 is connected to the pixel electrode of the OLED via the sixth transistor T6. The third transistor T3 is turned on according to the second scan signal GWN transmitted via the second scan line 151, and the diode is connected to the first transistor T1.

[0140] The fourth transistor T4 includes a gate electrode G4 connected to the third scan line 153, a first electrode E41 connected to the initialization voltage line 141, and a second electrode E42 connected to the first electrode Cst1 of the capacitor Cst, the second electrode E32 of the third transistor T3, and the gate electrode G1 of the first transistor T1. The fourth transistor T4 is turned on according to the third scan signal GI transmitted via the third scan line 153, and transmits the initialization voltage VINT to the gate electrode G1 of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0141] The fifth transistor T5 includes a gate electrode G5 connected to the light emission control line 133, a first electrode E51 connected to the power supply voltage line 161, and a second electrode E52 connected to the first electrode E11 of the first transistor T1 and the second electrode E22 of the second transistor T2.

[0142] The sixth transistor T6 includes a gate electrode G6 connected to the light emission control line 133, a first electrode E61 connected to the second electrode E12 of the first transistor T1 and the first electrode E31 of the third transistor T3, and a second electrode E62 connected to a pixel electrode of the OLED.

[0143] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emitting control signal EM transmitted through the light emitting control line 133 , thereby allowing current to flow through the OLED.

[0144] The seventh transistor T7 includes a gate electrode G7 connected to the first scan line 131, a first electrode E71 connected to the second electrode E62 of the sixth transistor T6 and the pixel electrode of the OLED, and a second electrode E72 connected to the initialization voltage line 141. The seventh transistor T7 is turned on according to the first scan signal GWP transmitted via the first scan line 131, so that the voltage of the pixel electrode of the OLED is initialized.

[0145] The capacitor Cst includes a first electrode Cst1 connected to the gate electrode G1 of the first transistor T1 and a second electrode Cst2 connected to the power supply voltage line 161. The first electrode Cst1 of the capacitor Cst is connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4.

[0146] The OLED includes a pixel electrode and a common electrode facing the pixel electrode, and the second power voltage ELVSS may be applied to the common electrode of the OLED. The OLED receives current from the first transistor T1 and emits light, thereby displaying an image.

[0147] Figure 8 is a view schematically showing a pixel arrangement according to an exemplary embodiment.

[0148] Figure 8 , a pixel PX(k,p) in the k row and p column, a pixel PX(k,p+1) in the k row and (p+1) column, a pixel PX(k,p+2) in the k row and (p+2) column, a pixel PX(k+1,p) in the (k+1) row and p column, a pixel PX(k+1,p+1) in the (k+1) row and (p+1) column, and a pixel PX(k+1,p+1) in the (k+1) row and (p+1) column are shown. Here, k and p are odd numbers.

[0149] Reference Figure 8, the pixel circuit of the pixel PX connected to the scan line SLk in the odd-numbered rows in each column and the pixel circuit of the pixel PX connected to the scan line SLk+1 in the even-numbered rows in each column may have a left-right symmetrical structure. For example, the left-right arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 of the pixel PX(k,p) and the pixel PX(k+1,p) are opposite to each other, and the left-right arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 of the pixel PX(k,p+1) and the pixel PX(k+1,p+1) are opposite to each other. However, the connection relationship between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 and the capacitor Cst is the same.

[0150] Moreover, the pixel circuit of a pair of pixels PX arranged in the same row in adjacent columns may have left-right symmetry. For example, the left-right arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 of the pixel PX (k, p) and the pixel PX (k, p + 1) is opposite to each other, and the left-right arrangement of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 of the pixel PX (k + 1, p + 1) and the pixel PX (k + 1, p + 2) is opposite to each other. However, the connection relationship between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 and the capacitor Cst is the same. A pair of pixels PX arranged in the same row in adjacent columns can share the initialization voltage line VLk or VLk + 1, where k is an odd number.

[0151] The first data line DL1 and the second data line DL2 may be separated from each other in each column. A pair of first data lines DL1 and a pair of second data lines DL2 may be adjacent to each other between two adjacent columns. The two data lines DL1 and DL2 in each column include a first data line DL1 connected to a pixel PX in an odd row and a second data line DL2 connected to a pixel PX in an even row. That is, the pixel PX in the odd row is connected to the first data line DL1, and the pixel PX in the even row is connected to the second data line DL2.

[0152] Fig. 9 is a schematic diagram showing a Figure 7 Layout diagram of the transistors and capacitors of a pixel shown in FIG. Fig.10is along Fig. 9 Cross-sectional views taken along section lines II' and II-II'.

[0153] Fig. 9 2 shows a pair of pixels PX arranged in the same row in adjacent columns. The pair of pixels PX has a bilaterally symmetrical structure, and the positions where the pair of pixels PX contact the initialization voltage line 141 are the same (overlapping each other). Fig. 9 In the figure, the second shielding layer 130a is an island shape in each pixel PX. That is, the second shielding layer 130a of the left pixel PX and the second shielding layer 130a of the right pixel PX are separated from each other. Hereinafter, the left pixel PX in the figure will be described, and of course, this applies to the right pixel PX.

[0154] The pixel PX of the display device according to the exemplary embodiment may include a plurality of wirings extending in a first direction and a plurality of wirings extending in a second direction intersecting the first direction. The first scan line 131, the second scan line 151, the third scan line 153, the light emitting control line 133, and the initialization voltage line 141 extend in the first direction. The data line (not shown) and the power supply voltage line 161 extend in the second direction.

[0155] Moreover, the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a semiconductor layer and a gate electrode, the semiconductor layer including a source region, a drain region, and a channel region located between the source region and the drain region, and the gate electrode is isolated from the semiconductor layer at a position corresponding to the channel region.

[0156] In the current embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be silicon TFTs and p-channel transistors. The third transistor T3 and the fourth transistor T4 may be oxide TFTs and n-channel transistors.

[0157] Fig. 9 Each of the first electrode and the second electrode of the transistor shown in may be a source electrode (source region) or a drain electrode (drain region).

[0158] The buffer layer 10 is positioned over the substrate 110 , and the first shielding layer 120 and the second shielding layer 130 a are positioned on the buffer layer 10 .

[0159] The substrate 110 may include a glass material, a ceramic material, a metal material, a plastic material, or a flexible or bendable material. The substrate 110 may have a single layer or a multilayer structure of the above materials, and when the substrate 110 has a multilayer structure, the substrate 110 may further include an inorganic layer. In some exemplary embodiments, the substrate 110 may have a structure of organic / inorganic / organic materials.

[0160] The buffer layer 10 may include an oxide layer (such as silicon oxide (SiO x )) and / or a nitride layer (such as silicon nitride (SiN x )). The buffer layer 10 may be omitted.

[0161] The first shielding layer 120 may be positioned to overlap at least the first transistor T1 , and the second shielding layer 130 a may be positioned to overlap at least the third transistor T3 and the fourth transistor T4 .

[0162] The first shielding layer 120 may be electrically connected to a power supply voltage line 161 electrically connected to a positive (+) constant voltage source via a contact hole CH1 penetrating the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15, and the sixth insulating layer 16. The second shielding layer 130a may be electrically connected to an initialization voltage line 141 electrically connected to a negative (-) constant voltage source via a contact hole CH2 penetrating the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13.

[0163] The first shielding layer 120 and the second shielding layer 130a may include metal and have a single-layer or multi-layer structure. For example, the first shielding layer 120 and the second shielding layer 130a may have a single-layer structure including Mo. In another exemplary embodiment, the first shielding layer 120 and the second shielding layer 130a may have a three-layer structure including a first layer including Ti, a second layer including Al, and a third layer including Ti, which are sequentially positioned above the buffer layer 10.

[0164] The first insulating layer 11 may be positioned over the first shielding layer 120 and the second shielding layer 130 a , and semiconductor layers of the first, second, fifth, sixth, and seventh transistors T1 , T2 , T5 , T6 , and T7 are positioned over the first insulating layer 11 .

[0165] The first insulating layer 11 may include an inorganic material, and the inorganic material may include an oxide or a nitride. For example, the first insulating layer 11 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0166] The semiconductor layers of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be positioned on the same layer and include the same material. For example, the semiconductor layer may include polysilicon.

[0167] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be connected to each other and bent in various forms. The semiconductor layer of the seventh transistor T7 may be connected to the semiconductor layer of the sixth transistor T6 in the previous row.

[0168] Each of the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a channel region, a source region and a drain region located at both sides of the channel region. A first doping in the channel region and a second doping in the source region and the drain region where the gate electrode is used as a mask may be performed. In an exemplary embodiment, the first doping may be omitted.

[0169] The second insulating layer 12 may be positioned over the semiconductor layer of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the gate electrodes G1, G2, G5, G6, and G7 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be positioned over the second insulating layer 12. The first scan line 131 and the light emission control line 133 may be formed of the same material as that used to form the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and may extend in the first direction.

[0170] The second insulating layer 12 may include an inorganic material, and the inorganic material may include an oxide or a nitride. For example, the second insulating layer 12 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ).

[0171] The gate electrodes G1, G2, G5, G6, and G7 may include Mo, copper (Cu), and Ti, and have a single-layer or multi-layer structure.

[0172] The semiconductor layer (A1, see Fig.10 ) of the first transistor T1 includes a first electrode E11, a second electrode E12, and a channel region located between the first electrode E11 and the second electrode E12. In a plane, the gate electrode G1 of the first transistor T1 overlaps with the channel region. The semiconductor layer A1 of the first transistor T1 has a curve such that the channel region can be formed to be long, and thus the driving range of the gate voltage applied to the gate electrode G1 of the first transistor T1 can be increased. Various embodiments of the shape of the semiconductor layer A1 of the first transistor T1, such as "匚", "己", "S", "M", and "W" shapes, are possible. The gate electrode G1 of the first transistor T1 is island-shaped and overlaps with the channel region of the first transistor T1. The second insulating layer 12 is located between the gate electrode G1 of the first transistor T1 and the semiconductor layer A1 of the first transistor T1.

[0173] The gate electrode G1 of the first transistor T1 is electrically connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 via a connection electrode 162. The connection electrode 162 is provided on the sixth insulating layer 16 and can contact each of the gate electrode G1 of the first transistor T1, the second electrode E32 of the third transistor T3, and the second electrode E42 of the fourth transistor T4 via a contact hole that at least penetrates the sixth insulating layer 16.

[0174] The semiconductor layer of the second transistor T2 includes a first electrode E21, a second electrode E22, and a channel region located between the first electrode E21 and the second electrode E22. In a plane, the gate electrode G2 of the second transistor T2 overlaps with the channel region and is formed by a part of the first scan line 131. The first electrode E21 of the second transistor T2 is electrically connected to a data line (not shown) via a connection electrode 163. The connection electrode 163 can be provided on the sixth insulating layer 16 and can contact the first electrode E21 of the second transistor T2 via a contact hole that at least penetrates the sixth insulating layer 16. The data line can be formed above the seventh insulating layer 17 on the connection electrode 163. The data line can contact the connection electrode 163 via a contact hole in the seventh insulating layer 17. The second electrode E22 of the second transistor T2 is connected to the first electrode E11 of the first transistor T1.

[0175] The semiconductor layer of the fifth transistor T5 includes a first electrode E51, a second electrode E52, and a channel region between the first electrode E51 and the second electrode E52. In a plane, the gate electrode G5 of the fifth transistor T5 overlaps the channel region and is formed by a portion of the light emitting control line 133. The first electrode E51 of the fifth transistor T5 is electrically connected to the power supply voltage line 161 via a contact hole that at least penetrates the sixth insulating layer 16. The power supply voltage line 161 may be disposed above the sixth insulating layer 16. The second electrode E52 of the fifth transistor T5 is connected to the first electrode E11 of the first transistor T1.

[0176] The semiconductor layer of the sixth transistor T6 includes a first electrode E61, a second electrode E62, and a channel region between the first electrode E61 and the second electrode E62. In a plane, the gate electrode G6 of the sixth transistor T6 overlaps the channel region and is formed by a portion of the light emitting control line 133. The first electrode E61 of the sixth transistor T6 is connected to the second electrode E12 of the first transistor T1. The first electrode E61 of the sixth transistor T6 is electrically connected to the first electrode E31 of the third transistor T3 via a connecting electrode 164. The connecting electrode 164 may be disposed on the sixth insulating layer 16 and may contact the first electrode E31 of the third transistor T3 via a contact hole that at least penetrates the sixth insulating layer 16. The first electrode E31 of the third transistor T3 is disposed on the fourth insulating layer 14. The second electrode E62 of the sixth transistor T6 is electrically connected to the pixel electrode PE of the OLED via a connecting electrode 165. The connecting electrode 165 may be disposed on the sixth insulating layer 16 and may contact the second electrode 62 of the sixth transistor T6 via a contact hole that at least penetrates the sixth insulating layer 16.

[0177] The semiconductor layer of the seventh transistor T7 includes a first electrode E71, a second electrode E72, and a channel region between the first electrode E71 and the second electrode E72. In a plane, the gate electrode G7 of the seventh transistor T7 overlaps the channel region and is formed by a portion of the first scan line 131. The second electrode E72 of the seventh transistor T7 is electrically connected to the first electrode E41 of the fourth transistor T4 and the initialization voltage line 141 via a connection electrode 166. The connection electrode 166 may be disposed on the sixth insulating layer 16, and may be in contact with each of the first electrode E41 of the fourth transistor T4, the second electrode E72 of the seventh transistor T7, and the initialization voltage line 141 via a contact hole that at least penetrates the sixth insulating layer 16. The first electrode E71 of the seventh transistor T7 is connected to the second electrode E62 of the sixth transistor T6 in the previous row.

[0178] The third insulating layer 13 is positioned over the gate electrodes G1, G2, G5, G6, and G7 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The second electrode Cst2 of the capacitor Cst is positioned over the third insulating layer 13. The initialization voltage line 141 positioned on the same layer as the second electrode Cst2 of the capacitor Cst and formed of the same material as that used to form the second electrode Cst2 of the capacitor Cst extends in the first direction.

[0179] The third insulating layer 13 may include an inorganic material including the above-mentioned oxide or nitride. The second electrode Cst2 of the capacitor Cst may include Mo, Cu, and Ti, and may have a single-layer or multi-layer structure.

[0180] The capacitor Cst overlaps the first transistor T1. The capacitor Cst includes a first electrode Cst1 and a second electrode Cst2. The first electrode Cst1 of the capacitor Cst is the gate electrode G1 of the first transistor T1. That is, it should be understood that the first electrode Cst1 of the capacitor Cst and the gate electrode G1 of the first transistor T1 may be formed as one body. The first electrode Cst1 of the capacitor Cst is separated from the adjacent pixel PX, has a rectangular shape, and is positioned on the same layer as the first scan line 131 and the light emitting control line 133 using the same material as the material used to form the first scan line 131 and the light emitting control line 133. In a state where the third insulating layer 13 is located between the first electrode Cst1 and the second electrode Cst2, the second electrode Cst2 of the capacitor Cst covers the entire first electrode Cst1 and overlaps the first electrode Cst1. In this case, the third insulating layer 13 serves as a dielectric layer of the capacitor Cst. The second electrode Cst2 of the capacitor Cst may include an open SOP. The opening SOP is formed by removing a portion of the second electrode Cst2 at a position corresponding to the contact hole for exposing a portion of the first electrode Cst1, and may have a closed curve shape. The connection electrode 162 may be connected to the first electrode Cst1 via a contact hole located in the opening SOP. The second electrode Cst2 may be connected to the power supply voltage line 161 via a contact hole penetrating at least the sixth insulating layer 16.

[0181] The transistors T3 and T4 including an oxide semiconductor may be positioned over the transistors T1 , T2 , T5 , T6 , and T7 including a silicon semiconductor and the capacitor Cst.

[0182] A fourth insulating layer 14 is positioned above the second electrode Cst2 of the capacitor Cst. Fig.10 ) and the semiconductor layer (A4, see Fig.10) is positioned above the fourth insulating layer 14. The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 are positioned on the same layer and include the same material. For example, the semiconductor layer may include an oxide semiconductor.

[0183] The fourth insulating layer 14 may include an inorganic material including the above-mentioned oxide or nitride.

[0184] The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 may include a channel region and a source region and a drain region located at both sides of the channel region. In an example, the source region and the drain region may be regions where the carrier concentration is improved by plasma treatment. The source region and the drain region may be formed by adjusting the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the source region and the drain region may be formed by increasing the carrier concentration in the oxide semiconductor using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof by plasma treatment.

[0185] The gate electrodes G3 and G4 of the third and fourth transistors T3 and T4 are positioned on the semiconductor layer A3 and A4 of the third and fourth transistors T3 and T4, respectively. The fifth insulating layer 15 is positioned between the semiconductor layer A3 and the gate electrode G3 of the third transistor T3 and between the semiconductor layer A4 and the gate electrode G4 of the fourth transistor T4.

[0186] The gate electrodes G3 and G4 include Mo, Cu, and Ti, and may have a single-layer or multi-layer structure.

[0187] In the figure, the fifth insulating layer 15 is positioned on the entire surface of the substrate 110. However, the fifth insulating layer 15 may be an insulating pattern patterned to correspond to the gate electrodes G3 and G4. For example, the fifth insulating layer 15 may be formed with an insulating pattern using the same mask process as that of the gate electrodes G3 and G4. The fifth insulating layer 15 may include an inorganic material including the above-mentioned oxide or nitride.

[0188] The second scan line 151 and the third scan line 153 , which are positioned on the same layer as the gate electrodes G3 and G4 of the third and fourth transistors T3 and T4 using the same material, extend in the first direction.

[0189] The third transistor T3 includes a semiconductor layer A3 and a gate electrode G3, and the semiconductor layer A3 includes an oxide semiconductor. The semiconductor layer A3 includes a first electrode E31, a second electrode E32, and a channel region located between the first electrode E31 and the second electrode E32. In a plane, the gate electrode G3 of the third transistor T3 overlaps with the channel region and is formed by a portion of the second scan line 151. The first electrode E31 of the third transistor T3 is electrically connected to the first electrode E61 of the sixth transistor T6 via the connecting electrode 164. The second electrode E32 of the third transistor T3 can be bridged to the gate electrode G1 of the first transistor T1 via the connecting electrode 162.

[0190] The fourth transistor T4 includes a semiconductor layer A4 and a gate electrode G4, and the semiconductor layer A4 includes an oxide semiconductor. The semiconductor layer A4 includes a first electrode E41, a second electrode E42, and a channel region between the first electrode E41 and the second electrode E42. In a plane, the gate electrode G4 of the fourth transistor T4 overlaps the channel region and is formed by a portion of the third scan line 153. The first electrode E41 of the fourth transistor T4 may contact the initialization voltage line 141 via a contact hole. The second electrode E42 of the fourth transistor T4 may be bridged to the gate electrode G1 of the first transistor T1 via the connection electrode 162.

[0191] A boost capacitor Cb may be formed in a region where the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 overlap the first scan line 131. The boost capacitor Cb includes a first electrode Cb1 and a second electrode Cb2, the first electrode Cb1 includes at least a portion of the first scan line 131, protrudes from the first scan line 131 and has a predetermined area, and the second electrode Cb2 extends from the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4 and overlaps the first electrode Cb1. The second electrode Cb2 may include an oxide semiconductor. The second electrode Cb2 may be electrically connected to the gate electrode G1 of the first transistor T1 via the connection electrode 162. The boost capacitor Cb may compensate for the kickback of the third transistor T3 and may increase the voltage of the gate electrode G1 of the first transistor T1.

[0192] A sixth insulating layer 16 may be positioned above the transistors T3 and T4 including the oxide semiconductor, and a power supply voltage line 161 and connection electrodes (162, 163, 164, 165, and 166) may be positioned on the sixth insulating layer 16. The sixth insulating layer 16 may include an inorganic material including the above-mentioned oxide or nitride.

[0193] The power supply voltage line 161 and the connection electrodes 162, 163, 164, 165, and 166 may be formed of a material having high conductivity, such as a metal, a conductive oxide, etc. For example, the power supply voltage line 161 and the connection electrodes 162, 163, 164, 165, and 166 may have a single-layer or multi-layer structure including Al, Cu, and Ti. In some exemplary embodiments, the power supply voltage line 161 and the connection electrodes 162, 163, 164, 165, and 166 may be provided with three layers of Ti / Al / Ti positioned sequentially.

[0194] A seventh insulating layer 17 may be positioned on the power supply voltage line 161 and the connection electrodes 162, 163, 164, 165, and 166, and a data line and a conductive layer may be positioned on the seventh insulating layer 17. The data line may extend in the second direction. The data line may be positioned at the left side or the right side of the pixel PX. The data line may be positioned at the left side or the right side of the first transistor T1. The data line may be the first data line DL1 or the second data line DL2. A through hole for exposing a portion of the connection electrode 165 may be formed in the seventh insulating layer 17. The conductive layer may contact the connection electrode 165 through the through hole.

[0195] The seventh insulating layer 17 may include an organic material such as acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). In another exemplary embodiment, the seventh insulating layer 17 may include the above-mentioned inorganic material.

[0196] The data line and the conductive layer may be formed of a material having high conductivity, such as metal, conductive oxide, etc. For example, the data line and the conductive layer may have a single-layer or multi-layer structure including Al, Cu, and Ti.

[0197] An eighth insulating layer 18 may be positioned on the data line and the conductive layer. The eighth insulating layer 18 may have a through hole formed therein for exposing a portion of the conductive layer.

[0198] The eighth insulating layer 18 may include an organic material such as acryl, BCB, polyimide, or HMDSO. In another exemplary embodiment, the eighth insulating layer 18 may include the above-mentioned inorganic material. The eighth insulating layer 18 is used as a protective layer for covering the transistors T1, T2, T3, T4, T5, T6, and T7, and is formed so that the top surface of the eighth insulating layer 18 is planarized. The eighth insulating layer 18 may have a single-layer or multi-layer structure.

[0199] The OLED may be positioned above the eighth insulating layer 18. The OLED may include a pixel electrode PE, an opposing electrode CE facing the pixel electrode PE, and an intermediate layer IL between the pixel electrode PE and the opposing electrode CE. The ninth insulating layer 19 is positioned on the eighth insulating layer 18 and covers the edge of the pixel electrode PE. The ninth insulating layer 19 has an opening for exposing a portion of the pixel electrode PE, thereby defining a pixel PX.

[0200] The pixel electrode PE of the OLED may contact the conductive layer electrically connected to the connection electrode 165 through the through hole. The pixel electrode PE may be a reflective layer including a reflective conductive material such as silver (Ag), magnesium (Mg), Al, platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof. In an exemplary embodiment, the pixel electrode PE may be a reflective layer including a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), a transparent conductive layer of at least one transparent conductive oxide selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode PE may have a stacked structure of a reflective layer and a transparent conductive layer.

[0201] The ninth insulating layer 19 may include an organic material such as acryl, BCB, polyimide, or HMDSO.

[0202] The intermediate layer IL of the OLED includes at least an emission layer (EML), and may further include one or more functional layers selected from a group consisting of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The EML may be a red EML, a green EML, or a blue EML. In another exemplary embodiment, the EML may have a multilayer structure in which a red EML, a green EML, and a blue EML are stacked, or a single-layer structure including a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light.

[0203] The counter electrode CE of the OLED may be formed of various conductive materials. For example, the counter electrode CE may include a semi-transparent reflective layer including at least one selected from a group consisting of lithium (Li), calcium (Ca), lithium fluoride (LiF), Al, Mg, and Ag, or a light-transmitting metal oxide such as ITO, IZO, and ZnO, and the counter electrode CE may include a single layer or multiple layers.

[0204] A thin film encapsulation layer (not shown) may be positioned on the OLED. The thin film encapsulation layer may cover the display area DA and may extend to the outside of the display area DA. The thin film encapsulation layer may include an inorganic encapsulation layer formed of at least one inorganic material and an organic encapsulation layer formed of at least one organic material. In some exemplary embodiments, the thin film encapsulation layer may have a stacked structure of a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer.

[0205] Moreover, spacers for preventing or reducing mask punching may be positioned on the ninth insulating layer 19, and various functional layers such as a polarizing layer for reducing external light reflection, a black matrix, a color filter and / or a touch screen layer including touch electrodes may be arranged on the thin film encapsulation layer.

[0206] Fig.11 is a schematic diagram showing a method according to another exemplary embodiment Figure 7 Layout diagram of the transistors and capacitors of a pixel shown in FIG. Fig.12 is along Fig.11 Cross-sectional views taken along section lines III-III' and IV-IV'.

[0207] Fig.11 and Fig.12 The pixel PX of the display device shown in FIG. Fig. 9 and Fig.10 The pixel PX of the display device shown in FIG. 1 is different in that the second shielding layer 130a under the third transistor T3 and the fourth transistor T4 is electrically connected to the second scan line 151 via a contact hole CH3 penetrating the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15. A portion of the second scan line 151 is used as the gate electrode G3 of the third transistor T3. Therefore, the same voltage as the voltage applied to the gate electrode G3 of the third transistor T3 is applied to the second shielding layer 130a. Fig.11 , the second shielding layer 130a of the left pixel PX and the second shielding layer 130a of the right pixel PX are connected to each other as a whole. That is, the left pixel PX and the right pixel PX may share the second shielding layer 130a. And therefore, the second shielding layer 130a may be connected to the second scan line 151 via a contact hole CH3 of one pixel PX of the left pixel PX and the right pixel PX.

[0208] In another exemplary embodiment, the second shielding layer 130a may be electrically connected to the third scan line 153 via a contact hole penetrating the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15. A portion of the third scan line 153 is used as the gate electrode G4 of the fourth transistor T4. Therefore, the same voltage as that applied to the gate electrode G4 of the fourth transistor T4 is applied to the second shielding layer 130a.

[0209] Fig.13 is a schematic diagram showing a method according to another exemplary embodiment Figure 7 Layout diagram of the transistors and capacitors of a pixel shown in FIG. Fig.14 is along Fig.13 Cross-sectional view taken along section lines V-V' and VI-VI'.

[0210] Fig.13 and Fig.14 The pixel PX of the display device shown in FIG. Fig. 9 and Fig.10 The pixel PX of the display device shown in is different in that the second shielding layer 130d under the third transistor T3 and the fourth transistor T4 is positioned on the same layer as the second electrode Cst2 of the capacitor Cst, and is electrically connected to the second scan line 151 via a contact hole CH4 penetrating the third insulating layer 13, the fourth insulating layer 14 and the fifth insulating layer 15. The second shielding layer 130d may include the same material as the material used to form the second electrode Cst2 of the capacitor Cst. A portion of the second scan line 151 serves as the gate electrode G3 of the third transistor T3. Therefore, the same voltage as the voltage applied to the gate electrode G3 of the third transistor T3 is applied to the second shielding layer 130d. Fig.13 , the second shielding layer 130d of the left pixel PX and the second shielding layer 130d of the right pixel PX are connected to each other as a whole. That is, the left pixel PX and the right pixel PX can share the second shielding layer 130d. Therefore, the second shielding layer 130d can be connected to the second scan line 151 via a contact hole CH4 of one pixel PX of the left pixel PX and the right pixel PX.

[0211] In another exemplary embodiment, the second shielding layer 130d may be positioned on the same layer as the second electrode Cst2 of the capacitor Cst, and may be electrically connected to the third scan line 153 via a contact hole CH4 penetrating the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15. A portion of the third scan line 153 is used as the gate electrode G4 of the fourth transistor T4. Therefore, the same voltage as that applied to the gate electrode G4 of the fourth transistor T4 is applied to the second shielding layer 130d.

[0212] In an exemplary embodiment, the second shielding layer may be positioned on the same layer as the semiconductor layer A1 of the first transistor T1, and may be electrically connected to the initialization voltage line 141 via a contact hole penetrating the second insulating layer 12 and the third insulating layer 13. In another exemplary embodiment, the second shielding layer may be positioned on the same layer as the semiconductor layer A1 of the first transistor T1, and may be electrically connected to the second scan line 151 or the third scan line 153 via a contact hole penetrating the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15.

[0213] Furthermore, in another exemplary embodiment, considering the position with other wirings, the second shielding layer 130a is Figure 3A , Figure 3B and Figure 3C The capacitors C1, C2 and C3 may be positioned as shown in FIG. 1 , or below the second shielding layers 130b, 130c, 130d as shown in FIG. Figure 4A , Figure 4B and Figure 4C The touch sensor TS can be positioned as shown in FIG. Figure 5 As shown in FIG. 1 , a touch sensor TS may be positioned on the first shielding layer 120 .

[0214] In one or more embodiments, at least one silicon thin film transistor using a silicon semiconductor with excellent reliability as a semiconductor layer and at least one oxide thin film transistor using an oxide semiconductor with low leakage current as a semiconductor layer are used together, thereby providing a display device with high reliability and low power consumption.

[0215] Furthermore, in one or more embodiments, a voltage applied to a shielding layer under a transistor is controlled according to a channel type and a semiconductor type of the transistor, so that optical characteristics of the transistor can be maintained and / or enhanced, and thus high-quality images can be provided.

[0216] For convenience, the display device according to one or more embodiments has been described as a display device including an organic light emitting device (OLED) as a display device. However, the exemplary embodiments are not limited thereto, and the display device according to one or more embodiments may be applied to various types of display devices such as a liquid crystal display (LCD) device, an electrophoretic display device, an inorganic EL display device, etc.

[0217] The display device according to the exemplary embodiment can be applied to portable terminals such as tablet PCs, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), gaming devices, and wrist watches. The display device is not limited to portable terminals, but can be used for large electronic devices such as televisions (TVs) and external advertising boards or small and medium-sized electronic devices such as personal computers (PCs), notebook computers, car navigation units, and cameras. The embodiment is not limited to the above-mentioned embodiment, but can be adopted in other electronic devices without departing from the concept of the present disclosure.

[0218] According to one or more exemplary embodiments, a display device may include a transistor having improved characteristics, thereby preventing or reducing degradation in image quality that may be caused by using different types of transistors.

[0219] Although certain exemplary embodiments and implementations have been described herein, other embodiments and variations will be apparent from this description. Accordingly, it will be apparent to those skilled in the art that the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and various obvious variations and equivalent arrangements.

Claims

1. A display device, comprising: a driving transistor, the driving transistor comprising a first semiconductor layer and a first gate electrode, the first semiconductor layer comprising silicon; a first switch transistor, the first switch transistor comprising a second semiconductor layer and a second gate electrode, the second semiconductor layer comprising an oxide; a first shielding layer, the first shielding layer overlaps with the driving transistor, and the first shielding layer is between the substrate and the first semiconductor layer; a second shielding layer, the second shielding layer overlaps with the first switch transistor, and the second shielding layer is between the substrate and the second semiconductor layer; as well as a first capacitor, the first capacitor comprising a first electrode and a second electrode, in: The first electrode of the first capacitor is at least a portion of the first gate electrode of the driving transistor, and the second electrode of the first capacitor is located on and overlaps the first gate electrode of the driving transistor; as well as The second electrode is positioned at the same layer as the second shielding layer.

2. The display device according to claim 1, wherein: The first shielding layer and the second shielding layer include different materials.

3. The display device according to claim 1, wherein: The second electrode and the second shielding layer include the same material.

4. The display device according to claim 1, wherein: The same voltage is applied to the second gate electrode and the second shielding layer.

5. The display device according to claim 1, further comprising a second switch transistor, the second switch transistor comprising a third semiconductor layer and a third gate electrode, the third semiconductor layer comprising an oxide, in, The same voltage is applied to the third gate electrode and the second shielding layer.

6. The display device according to claim 1, further comprising a second capacitor including a first electrode and a second electrode overlapping the first electrode of the second capacitor, in, The first electrode of the second capacitor is positioned at the same layer as the first gate electrode of the driving transistor, and the second electrode of the second capacitor is positioned at the same layer as the second semiconductor layer of the first switching transistor.

7. The display device according to claim 6, wherein: The second electrode and the second semiconductor layer of the second capacitor include the same material.

8. The display device according to claim 6, wherein: The second shielding layer is interposed between the first electrode and the second electrode of the second capacitor.

9. The display device according to claim 1, further comprising: A power line overlaps with the first shielding layer.

10. A display device, comprising: substrate; a first insulating layer, wherein the first insulating layer is located on the substrate; a driving transistor, the driving transistor comprising a first gate electrode and a first semiconductor layer; a first capacitor overlapping the driving transistor and including a first electrode and a second electrode, the first electrode being the first gate electrode and the second electrode overlapping the first electrode; a first switch transistor, the first switch transistor comprising a second gate electrode and a second semiconductor layer, the second gate electrode being arranged on the first gate electrode of the driving transistor; a second insulating layer disposed between the first gate electrode and the first semiconductor layer; a third insulating layer, the third insulating layer being arranged between the first electrode and the second electrode; a fourth insulating layer, the fourth insulating layer being arranged on the second electrode and between the first gate electrode and the second gate electrode; a fifth insulating layer disposed between the second gate electrode and the second semiconductor layer; a first shielding layer, the first shielding layer overlaps with the driving transistor, and the first shielding layer is between the substrate and the first semiconductor layer; a second shielding layer, the second shielding layer overlaps with the first switch transistor, and the second shielding layer is between the third insulating layer and the second semiconductor layer; a first connection electrode, the first connection electrode being located on the second gate electrode and connected to the first semiconductor layer and the second semiconductor layer; as well as A second connection electrode is located on the second gate electrode and is connected to the first gate electrode and the second semiconductor layer.

11. The display device according to claim 10, further comprising a second switch transistor, the second switch transistor comprising a third semiconductor layer and a third gate electrode, the third semiconductor layer comprising an oxide, in, The second semiconductor layer and the third semiconductor layer are integrated.

12. The display device of claim 10 , further comprising a second capacitor including a first electrode and a second electrode overlapping the first electrode of the second capacitor, in, The first electrode of the second capacitor is positioned at the same layer as the first gate electrode, and the second electrode of the second capacitor is positioned at the same layer as the second semiconductor layer.

13. The display device according to claim 12, wherein: The second electrode and the second semiconductor layer of the second capacitor include the same material.

14. The display device according to claim 10, further comprising: A power line overlaps with the first shielding layer.

15. The display device according to claim 10, wherein: The same voltage is applied to the second gate electrode and the second shielding layer.

16. The display device according to claim 12, wherein: The second shielding layer is interposed between the first electrode and the second electrode of the second capacitor.

17. A display device, comprising a first pixel and a second pixel located in a display area, each of the first pixel and the second pixel comprising: a driving transistor, the driving transistor comprising a first semiconductor layer and a first gate electrode, the first semiconductor layer comprising silicon; a switching transistor, the switching transistor comprising a second semiconductor layer and a second gate electrode, the second semiconductor layer comprising an oxide; a first shielding layer, the first shielding layer overlaps with the driving transistor, and the first shielding layer is between the substrate and the first semiconductor layer; as well as a second shielding layer, the second shielding layer overlaps with the switch transistor, and the second shielding layer is between the substrate and the second semiconductor layer, in: The first shielding layer of the first pixel and the first shielding layer of the second pixel adjacent to the first pixel are spaced apart from each other; and The second shielding layer of the first pixel and the second shielding layer of the second pixel are integrated.

18. The display device according to claim 17, further comprising: A power supply line overlaps the first shielding layer and the second shielding layer of the first pixel and the second pixel.

19. The display device according to claim 17, wherein: Each of the first pixel and the second pixel further includes a capacitor overlapping the driving transistor.

20. The display device according to claim 19, wherein: The capacitor includes a first electrode and a second electrode, the second electrode being positioned at the same layer as the second shielding layer.

Images