Thin film transistor substrate, method of manufacturing same, and display device using same

Abstract

The present disclosure relates to a thin film transistor substrate, a method of manufacturing the same, and a display device using the same. The thin film transistor substrate includes: a substrate; a light blocking layer disposed on the substrate; an active layer disposed on the light blocking layer and having a lower hole on one side; a gate electrode disposed on the active layer; a source electrode disposed on the gate electrode and electrically connected to the light blocking layer; and an insulating layer disposed between the active layer and the source electrode and including an upper hole, in which the source electrode includes a lower electrode disposed in the lower hole and an upper electrode disposed in the upper hole, and an area of a lower surface of the upper electrode is larger than an area of an upper surface of the lower electrode.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor substrate and a method for manufacturing the same, and a display device using the thin film transistor substrate. Background Art

[0002] Since thin film transistors can be manufactured on a glass substrate or a plastic substrate, they are widely used as switching elements or driving elements of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] Based on the material constituting the active layer, the thin film transistor can be divided into an amorphous silicon thin film transistor using amorphous silicon as the active layer, a polycrystalline silicon thin film transistor using polycrystalline silicon as the active layer, and an oxide semiconductor thin film transistor using an oxide semiconductor as the active layer.

[0004] Among them, oxide semiconductor thin film transistors (oxide semiconductor TFTs) have the advantage of being able to easily obtain desired physical properties because they have high mobility and can have a large resistance change depending on the oxygen content. In addition, since the oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin film transistor, the manufacturing cost is low. Due to the properties of the oxide, since the oxide semiconductor is transparent, it is also advantageous to realize a transparent display device.

[0005] Recently, in order to realize a high-resolution display device, the size of the pixel has been further reduced. In order to realize such a high-resolution display device, it is important to minimize or reduce the size of the thin film transistor provided in the pixel. In addition, in order to express the grayscale of the driving thin film transistor for driving the pixel, a method of electrically connecting the active layer, the source electrode and the light blocking layer to increase the size of the capacitor is mainly used, but in this case, due to the size of the source electrode for connecting the active layer and the light blocking layer, it is difficult to ensure the space for realizing the high-resolution display device. Summary of the invention

[0006] The present disclosure provides a thin film transistor substrate having a thin film transistor that easily expresses grayscale by connecting a source electrode, an active layer, and a light blocking layer through a lower hole provided in an active layer of the thin film transistor, and a display device including the same.

[0007] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor substrate, which includes: a substrate; a light blocking layer, which is arranged on the substrate; an active layer, which is arranged on the light blocking layer and has a lower hole on one side; a gate electrode, which is arranged on the active layer; a source electrode, which is arranged on the gate electrode and is electrically connected to the light blocking layer; and an insulating layer, which is arranged between the active layer and the source electrode and includes an upper hole, wherein the source electrode includes a lower electrode arranged in the lower hole and an upper electrode arranged in the upper hole, and the area of ​​the lower surface of the upper electrode is larger than the area of ​​the upper surface of the lower electrode.

[0008] And the above and other purposes can be achieved by providing a method for manufacturing a thin film transistor substrate, which method for manufacturing a thin film transistor substrate includes the following steps: a step of forming a light blocking layer on a substrate; a step of forming an active layer on the light blocking layer; a step of forming an active hole on one side of the active layer; a step of forming a gate insulating layer on the active layer having the active hole formed therein; a step of forming a gate electrode on the gate insulating layer; a step of forming an interlayer insulating layer on the gate electrode; a step of forming an upper hole in the gate insulating layer and the interlayer insulating layer; a step of forming a lower hole exposing a portion of the light blocking layer by extending the active hole; and a step of forming a source electrode inside the lower hole and inside the upper hole.

[0009] And the above and other purposes can be achieved by providing a display device, which includes: a substrate, which includes a display area and a non-display area; a first thin film transistor, which is arranged on the substrate; and a second thin film transistor, which has a structure different from that of the first thin film transistor, wherein the first thin film transistor includes: a first light blocking layer; a first active layer, which is arranged on the first light blocking layer and has a lower hole on one side of the first active layer; a first gate electrode, which is arranged on the first active layer; a first source electrode, which is arranged on the first gate electrode and is electrically connected to the first active layer and the first light blocking layer; and an insulating layer, which is arranged between the first active layer and the first source electrode and has an upper hole, the first source electrode includes a lower electrode arranged in the lower hole and an upper electrode arranged in the upper hole, the first active layer and the first light blocking layer are electrically connected through the lower electrode, and the area of ​​the lower surface of the upper electrode is larger than the area of ​​the upper surface of the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view of a thin film transistor substrate according to one embodiment of the present disclosure.

[0012] Figure 2A is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view along Figure 1 It corresponds to the cross-sectional view taken along line II'.

[0013] Figure 2B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view along Figure 1 It corresponds to the cross-sectional view taken along line II'.

[0014] Figure 3 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0015] Figure 4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 4 The cross-sectional view along Figure 3 It corresponds to the cross-sectional view taken along line II-II'.

[0016] Figure 5 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0017] Figure 6 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 6 The cross-sectional view along Figure 5 It corresponds to the cross-sectional view taken along line III-III'.

[0018] Figure 7 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0019] Figure 8 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 8 The cross-sectional view along Figure 7 It corresponds to the cross-sectional view taken along line IV-IV'.

[0020] Fig. 9 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0021] Fig.10 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.10 The cross-sectional view of Fig. 9 The cross-sectional view of V-V' corresponds to the cross-sectional view of V-V'.

[0022] Fig.11 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0023] Fig.12 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.12 The cross-sectional view of Fig.11 It corresponds to the cross-sectional view taken along line VI-VI'.

[0024] Fig.13 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0025] Fig.14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0026] FIG. 15A to FIG. 15E is a cross-sectional view illustrating a method of forming a thin film transistor substrate according to an embodiment of the present disclosure.

[0027] Fig.16 is a cross-sectional view of a display device including a thin film transistor substrate according to another embodiment of the present disclosure.

[0028] Fig.17 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0029] Fig.18 is a circuit diagram of a pixel included in a display device according to one embodiment of the present disclosure.

[0030] Fig.19 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0031] Fig. 20 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0033] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. The same reference numerals always refer to the same elements. In the following description, when the detailed description of the related known functions or configurations is determined to be unnecessary to obscure the focus of the present disclosure, the detailed description will be omitted.

[0034] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may also be present unless “only” is used. Terms in the singular form may include plural forms unless described otherwise.

[0035] When configuring an element, the element is interpreted as including an error region although there is no explicit description thereof.

[0036] In describing a positional relationship, for example, when a positional order is described as “on,” “above,” “below,” “under,” and “beside,” a case where there is no contact therebetween may be included unless “only” or “directly” is used.

[0037] If a first element is mentioned as being positioned "on" a second element, it does not mean that the first element is positioned substantially above the second element in the figure. The upper and lower parts of the objects involved may change depending on the orientation of the objects. Therefore, the case where a first element is positioned "on" a second element includes the case where the first element is positioned "below" the second element and the case where the first element is positioned "above" the second element in the figure or in the actual configuration.

[0038] When describing a temporal relationship, for example, when a temporal order is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0039] It should be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0040] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each element of the first element, the second element, and the third element.

[0041] The features of various embodiments of the present disclosure may be partially or entirely coupled or combined with each other, and may interoperate and technically drive each other differently. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0042] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are shown in different drawings.

[0043] In the embodiments of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. Therefore, the source electrode may be a drain electrode, and the drain electrode may be a source electrode. Furthermore, the source electrode in any one embodiment of the present disclosure may be a drain electrode in another embodiment of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be a source electrode in another embodiment of the present disclosure.

[0044] In one or more embodiments of the present disclosure, for ease of explanation, the source region and the source electrode are distinguished from each other, and the drain region and the drain electrode are distinguished from each other. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0045] Figure 1 is a plan view of a thin film transistor substrate according to one embodiment of the present disclosure.

[0046] like Figure 1 As shown, the thin film transistor substrate according to one embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 170 , and a drain electrode 180 .

[0047] The light blocking layer 110 and the active layer 130 may extend in a first direction (eg, horizontal direction), and the gate electrode 150 may extend in a second direction (eg, vertical direction). In this case, the first direction and the second direction may be orthogonal to each other.

[0048] The active layer 130 may be provided with a drain hole DH at one side (eg, left side thereof), and an upper hole TH and a lower hole BH may be provided at the other side (eg, right side thereof) of the active layer 130. In this case, the lower hole BH and the upper hole TH may overlap each other.

[0049] One side of the active layer 130 may be electrically connected to the drain electrode 180 through the drain hole DH, the other side of the active layer 130 may be electrically connected to the light blocking layer 110 through the lower hole BH, and the other side of the active layer 130 may be electrically connected to the source electrode 170 through the upper hole TH. In this case, the light blocking layer 110, the active layer 130, and the source electrode 170 may be electrically connected through the upper hole TH and the lower hole BH, thereby facilitating the grayscale representation of the thin film transistor substrate according to one embodiment of the present disclosure, which will be Figure 2A Described in detail in.

[0050] Figure 2A is a cross-sectional view of a thin film transistor substrate according to one embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view along Figure 1 It corresponds to the cross-sectional view taken along line II'.

[0051] like Figure 2A As shown, a thin film transistor substrate according to an embodiment of the present disclosure may include a substrate 100 , a light blocking layer 110 , a buffer layer 120 , an active layer 130 , a gate insulating layer 140 , a gate electrode 150 , an interlayer insulating layer 160 , a source electrode 170 , and a drain electrode 180 .

[0052] The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of a transparent plastic having a flexible property, such as polyimide. When polyimide is used as the substrate 100, considering that a high temperature deposition process is performed on the substrate 100, a heat-resistant polyimide capable of withstanding high temperatures may be used.

[0053] The light blocking layer 110 may be disposed on the substrate 100. The light blocking layer 110 may include a metal or a metal oxide, and may be formed of one metal layer or a metal oxide layer, or may be formed of two or more metal layers or metal oxide layers.

[0054] The light blocking layer 110 is disposed under the active layer 130 and overlaps the active layer 130, thereby preventing light introduced from outside the thin film transistor substrate from being introduced into the active layer 130. Specifically, the light blocking layer 110 can prevent external light from being introduced into the channel portion 131 of the active layer 130. In addition, although not shown, a separate insulating layer may be additionally disposed between the light blocking layer 110 and the substrate 100.

[0055] The buffer layer 120 is formed on the substrate 100 and the light blocking layer 110. The buffer layer 120 can protect the active layer 130 by blocking air and moisture. The buffer layer 120 can be made of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto, and can be made of an organic insulating material. The buffer layer 120 can be formed of a single layer or a multilayer.

[0056] The active layer 130 may be disposed on the buffer layer 120 .

[0057] The active layer 130 may include a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0058] In this case, the active layer 130 may preferably include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IZTO (InZnSnO)-based oxide semiconductor material, and a ZnO-based oxide semiconductor material. When the active layer 130 is formed to include the above materials, the lower hole BH can be more easily formed in one side of the active layer 130.

[0059] The active layer 130 includes a channel portion 131, a first connection portion 132a connected to one side of the channel portion 131, and a second connection portion 132b connected to the other side of the channel portion 131. The first connection portion 132a and the second connection portion 132b may have conductive properties through a conductive process of ion doping or plasma treatment of a semiconductor material using the gate electrode 150 as a mask.

[0060] The conductive process can be defined as a process for imparting conductive properties to the oxide semiconductor material. The oxide semiconductor material on which the conductive process has been performed can have conductive properties. The conductive process can include, for example, a doping process using doping ions and a plasma process applying plasma to become a conductor. Through the conductive process, a partial area of ​​the active layer 130 can be conductive to have conductive properties. In this case, the first connection portion 132a and the second connection portion 132b can be conductive through the conductive process to have conductive properties, and the first connection portion 132a and the second connection portion 132b can have better conductivity than the channel portion 131, and each can be used as a wiring or a source electrode / drain electrode.

[0061] A lower hole BH may be provided at one side of the active layer 130. Specifically, a region of one side of the active layer 130 may be patterned to form the lower hole BH.

[0062] The lower hole BH may be provided in the first connection portion 132a of the active layer 130. The lower hole BH is formed by patterning a partial region of the active layer 130 and a partial region of the buffer layer 120, and the lower hole BH may expose a portion of the upper surface of the light blocking layer 110 provided below the active layer 130. By forming the lower hole BH, the source electrode 170 may penetrate the lower hole BH to electrically connect the first connection portion 132a of the active layer 130 with the light blocking layer 110.

[0063] The gate insulating layer 140 may be disposed on the active layer 130. Specifically, the gate insulating layer 140 may be disposed on the entire surface of the substrate 100 and may be disposed on the active layer 130 and the buffer layer 120. As a result, the active layer 130 may be surrounded by the buffer layer 120 and the gate insulating layer 140.

[0064] The upper hole TH and the drain hole DH may be provided in the gate insulating layer 140 .

[0065] The gate insulating layer 140 may include a silicon nitride layer SiNx or a silicon oxide layer SiOx, but is not limited thereto. The gate insulating layer 140 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0066] The gate electrode 150 may be disposed on the gate insulating layer 140. The gate electrode 150 may be disposed on the active layer 130. Specifically, the gate electrode 150 may overlap the channel portion 131 of the active layer 130.

[0067] The gate electrode 150 may include at least one of an aluminum-based metal such as aluminum Al or an aluminum alloy, a silver-based metal such as silver Ag or a silver alloy, a copper-based metal such as copper Cu or a copper alloy, a molybdenum-based metal such as molybdenum Mo or a molybdenum alloy, chromium Cr, tantalum Ta, neodymium Nd, and titanium Ti. The gate electrode 150 may have a structure including one metal layer or a multi-layer structure including at least two metal layers each having different physical properties.

[0068] The interlayer insulating layer 160 may insulate the gate electrode 150 from the source electrode 170, and also insulate the gate electrode 150 from the drain electrode 180. The interlayer insulating layer 160 may be formed of a single layer or a multilayer including an inorganic insulating material and / or an organic insulating material.

[0069] The upper hole TH and the drain hole DH may be provided in the interlayer insulating layer 160. Therefore, a portion of the upper surface of the first connection portion 132a of the active layer 130 may be exposed by the upper hole TH, and the lower hole BH of the active layer 130 may be exposed by the upper hole TH. In addition, a portion of the upper surface of the second connection portion 132b of the active layer 130 may be exposed by the drain hole DH.

[0070] The source electrode 170 and the drain electrode 180 may be disposed on the interlayer insulating layer 160. The source electrode 170 and the drain electrode 180 may be formed of the same material as the gate electrode 150, but are not limited thereto and may be formed of a material according to knowledge in the art.

[0071] The source electrode 170 may be electrically connected to one side (e.g., the first connection portion 132a) of the active layer 130, and the drain electrode 180 may be electrically connected to the other side (e.g., the second connection portion 132b) of the active layer 130. Specifically, the source electrode 170 may be connected to the first connection portion 132a of the active layer 130 through an upper hole TH provided in the gate insulating layer 140 and the interlayer insulating layer 160, and the drain electrode 180 may be connected to the second connection portion 132b of the active layer 130 through a drain hole DH provided in the gate insulating layer 140 and the interlayer insulating layer 160.

[0072] According to one embodiment of the present disclosure, the source electrode 170 can be electrically connected to the first connection portion 132a of the active layer 130 and the light blocking layer 110 through an upper hole TH set in the gate insulating layer 140 and the interlayer insulating layer 160 and a lower hole BH set in the buffer layer 120 and the first connection portion 132a of the active layer 130. This will be described in detail below through the relationship between the upper hole TH, the lower hole BH, and the source electrode 170 set in the upper hole TH and the lower hole BH.

[0073] As described above, the upper hole TH can be formed by etching a portion of the gate insulating layer 140 and the interlayer insulating layer 160 from the upper surface of the active layer 130 (specifically, the first connection portion 132a), and the lower hole BH can be formed by etching a portion of the buffer layer 120 and the first connection portion 132a of the active layer 130 from the upper surface of the light blocking layer 110.

[0074] The upper hole TH may overlap with the lower hole BH. Specifically, the entire lower hole BH may overlap with the upper hole TH. In addition, the upper hole TH and the lower hole BH may be continuously formed and connected to each other. Therefore, a portion of the upper surface of the light blocking layer 110 may be exposed through the upper hole TH and the lower hole BH.

[0075] The upper hole TH and the lower hole BH may be formed to have different areas, and in this case, the upper hole TH may be formed to be larger than the lower hole BH. Specifically, the lower area of ​​the upper hole TH may be formed to be larger than the upper area of ​​the lower hole BH. By forming in this manner, the upper hole TH may expose a portion of the upper surface of the first connection portion 132a. Specifically, a portion of the upper surface of the first connection portion 132a that overlaps with the upper hole TH but not with the lower hole BH may be exposed by the upper hole TH.

[0076] According to one embodiment of the present disclosure, since the upper hole TH and the lower hole BH are continuously formed and connected to each other, the source electrode 170 may be electrically connected to the first connection portion 132a through the upper hole TH, and may be electrically connected to the light blocking layer 110 through the lower hole BH. Therefore, the light blocking layer 110 and the first connection portion 132a may be electrically connected through the upper hole TH and the lower hole BH.

[0077] According to the configuration of the present disclosure, since the source electrode 170 penetrates a portion of the active layer 130 through the upper hole TH and the lower hole BH to be electrically connected to the light blocking layer 110 and the active layer 130, the overall area of ​​the thin film transistor substrate according to the present disclosure can be reduced. If the source electrode, the active layer, and the light blocking layer are to be electrically connected without the upper hole TH and the lower hole BH, the overall area of ​​the thin film transistor substrate can be increased by the area for forming the connection electrode.

[0078] The source electrode 170 may include an upper electrode 171 and a lower electrode 172. In this case, the upper electrode 171 may be defined as a portion of the source electrode 170 disposed in the upper hole TH and on the interlayer insulating layer 160, and the lower electrode 172 may be defined as a portion of the source electrode 170 disposed in the lower hole BH. Therefore, the upper electrode 171 may be defined as a portion of the source electrode 170 disposed in the gate insulating layer 140 and the interlayer insulating layer 160 and on the interlayer insulating layer 160 from the top surface of the active layer 130. The lower electrode 172 may be defined as a portion of the source electrode 170 disposed in the buffer layer 120 and in the first connection portion 132a from the top surface of the light blocking layer 110.

[0079] According to an embodiment of the present disclosure, since the size of the upper hole TH is larger than that of the lower hole BH, the size of the upper electrode 171 may be larger than that of the lower electrode 172. Specifically, the lower area of ​​the upper electrode 171 may be larger than the upper area of ​​the lower electrode 172.

[0080] Since the lower area of ​​the upper electrode 171 is larger than the upper area of ​​the lower electrode 172, the entire lower electrode 172 may overlap with the upper electrode 171 in a plan view. In addition, the upper electrode 171 may contact the lower electrode 172 and may contact a portion of the upper surface of the first connection portion 132a of the active layer 130.

[0081] Since the lower electrode 172 may be disposed in the lower hole BH, the lower electrode 172 may contact the inside of the first connection portion 132a of the active layer 130. In this case, the inside of the first connection portion 132a may be defined as a region of the first connection portion 132a exposed by the lower hole BH.

[0082] Since the upper electrode 171 contacts a portion of the upper surface of the first connection portion 132a, and the lower electrode 172 contacts the inside of the first connection portion 132a, the contact area between the source electrode 170 and the active layer 130 (specifically, the first connection portion 132a) can be increased, and thus the contact resistance between the active layer 130 and the source electrode 170 can be reduced. In this case, when the thin film transistor substrate according to one embodiment of the present disclosure is driven by reducing the contact resistance between the active layer 130 and the source electrode 170, the on-current can be increased.

[0083] Figure 2B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view along Figure 1 In addition, in addition to the configuration of the gate insulating layer and the interlayer insulating layer, Figure 2B Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0084] like Figure 2B As shown, the gate insulating layer 140 may not be provided on the entire surface of the substrate 100, but may be patterned to coincide with one end and the other end of the gate electrode 150. Specifically, one end (e.g., the right end) of the gate insulating layer 140 may coincide with one end of the gate electrode 150, and the other end (e.g., the left end) of the gate insulating layer 140 may coincide with the other end of the gate electrode 150.

[0085] Since the gate insulating layer 140 is formed as described above, the upper hole TH and the drain hole DH may not be provided in the gate insulating layer 140 but may be provided only in the interlayer insulating layer 160 .

[0086] The interlayer insulating layer 160 may be disposed on the active layer 130 and the gate electrode 150 and may contact a portion of an upper surface of the active layer 130. As a result, the active layer 130 and the gate electrode 150 may be surrounded by the buffer layer 120 and the interlayer insulating layer 160.

[0087] In addition, according to Figure 2B The configuration of the gate insulating layer and the interlayer insulating layer may be applied to a thin film transistor substrate according to another embodiment described later.

[0088] Figure 3 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the upper hole, according to Figure 3 The thin film transistor substrate and the Figure 1 The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0089] like Figure 3 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 170 , and a drain electrode 180 .

[0090] One end of the active layer 130 may be electrically connected to the source electrode 170 through the upper hole TH, and one end of the active layer 130 may be electrically connected to the light blocking layer 110 through the lower hole BH. In this case, since the upper hole TH and the lower hole BH overlap each other, the light blocking layer 110, the active layer 130, and the source electrode 170 may be electrically connected.

[0091] According to another embodiment of the present disclosure, one side (e.g., the right end side) of the upper hole TH may coincide with one side (e.g., the right end side) of the active layer 130. By forming in this way, the contact area between the source electrode 170 formed in the upper hole TH and the active layer 130 is increased, so that the contact resistance between the active layer 130 and the source electrode 170 can be further reduced. In addition, in Figure 3 , only an embodiment in which one side of the upper hole TH coincides with one side of the active layer 130 is shown, but the present disclosure is not limited thereto.

[0092] Figure 4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 4 The cross-sectional view of Figure 3 In addition, in addition to the configuration of the upper hole and the upper electrode, Figure 4 Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0093] like Figure 4 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 170 and a drain electrode 180.

[0094] According to another embodiment of the present disclosure, the upper hole TH may be formed asymmetrically relative to the center of the lower hole BH while the upper hole TH overlaps the lower hole BH. Specifically, when the upper hole TH overlaps the lower hole BH, one end (e.g., the right end) of the lower surface of the upper hole TH may coincide with one end of the first connection portion 132a. By forming as described above, one end (e.g., the right end) of the upper electrode 171 disposed in the upper hole TH may coincide with one end of the active layer 130. More specifically, the right end of the lower surface of the upper electrode 171 may coincide with the right end of the upper surface of the active layer 130. In addition, in the figure, only one end of the upper electrode 171 coincides with one end of the active layer 130, but is not limited thereto.

[0095] Since the upper hole TH is formed asymmetrically with respect to the center of the lower hole BH, the distance from one end (e.g., the right end) of the upper electrode 171 to the lower hole BH may be different from the distance from the other end (e.g., the left end) of the upper electrode 171 to the lower hole BH. Figure 4 This is depicted in the enlarged view of .

[0096] As from Figure 4 It can be seen from the enlarged view that the distance from one end of the upper electrode 171 to the lower hole BH can be defined as the second distance d2, and the distance from the other end of the upper electrode 171 to the lower hole BH can be defined as the first distance d1. In short, the first distance d1 and the second distance d2 can be defined as the distance from the center of the lower hole BH to one end of the upper electrode 171 or the other end of the upper electrode 171, respectively. In this case, the first distance d1 can be smaller than the second distance d2. In addition, although not illustrated in the figure, the first distance d1 can be larger than the second distance d2.

[0097] When one end of the upper electrode 171 coincides with one end of the active layer 130, one end (e.g., the left end) of the drain electrode 180 may not coincide with the other end of the active layer 130. In this case, the size of the upper hole TH where the upper electrode 171 is disposed may be larger than the size of the drain hole DH where the drain electrode 180 is disposed.

[0098] According to another embodiment of the present disclosure, since one end of the upper electrode 171 coincides with one end of the active layer 130, the contact area between the upper electrode 171 and the active layer 130 can be increased, and the contact resistance between the active layer 130 and the source electrode 170 of the thin film transistor substrate according to another embodiment of the present disclosure can be further reduced.

[0099] Figure 5 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the lower hole, according to Figure 5 The thin film transistor substrate and the Figure 1The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0100] like Figure 5 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 170 , and a drain electrode 180 .

[0101] An upper hole TH and a lower hole BH are provided at one side of the active layer 130, and one side of the active layer 130 and the source electrode 170 may be electrically connected through the upper hole TH, and one side of the active layer 130 and the light blocking layer 110 may be electrically connected through the lower hole BH. In this case, since the upper hole TH and the lower hole BH overlap each other, the light blocking layer 110, the active layer 130, and the source electrode 170 may be electrically connected.

[0102] According to another embodiment of the present disclosure, the lower hole BH may include an active hole AH and a buffer hole BufH. In this case, the active hole AH, the buffer hole BufH, and the upper hole TH may overlap with each other.

[0103] Figure 6 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 6 The cross-sectional view along Figure 5 In addition, in addition to the configuration of the lower hole and the lower electrode, according to Figure 6 The thin film transistor substrate and the Figure 2A The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0104] like Figure 6 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 170 and a drain electrode 180.

[0105] According to another embodiment of the present disclosure, the lower hole BH may include an active hole AH and a buffer hole BufH, and the lower electrode 172 may include a first portion 172p1 and a second portion 172p2.

[0106] The buffer hole BufH may be defined as a region formed by etching a portion of the buffer layer 120 from the upper surface of the light blocking layer 110, and the active hole AH may be defined as a region formed by etching a portion of the active layer 130 from the upper surface of the buffer layer 120. The buffer hole BufH may overlap with the active hole AH, and the size of the buffer hole BufH may be formed to be smaller than that of the active hole AH.

[0107] Specifically, an area of ​​an upper surface of the buffer hole BufH may be smaller than an area of ​​a lower surface of the active hole AH.

[0108] The first portion 172p1 of the lower electrode 172 may be defined as a portion of the source electrode 170 disposed in the active hole AH, and the second portion 172p2 of the lower electrode 172 may be defined as a portion of the source electrode 170 disposed in the buffer hole BufH. In this case, the size of the first portion 172p1 may be larger than the size of the second portion 172p2. Therefore, a portion of the lower surface of the first portion 172p1 may contact a portion of the buffer layer 120 exposed by the active hole AH.

[0109] Figure 7 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the upper hole and the lower hole, according to Figure 7 The thin film transistor substrate and the Figure 1 The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0110] like Figure 7 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 170 , and a drain electrode 180 .

[0111] According to another embodiment of the present disclosure, one side of the active layer 130 may be electrically connected to the source electrode 170 and the light blocking layer 110 through a plurality of upper holes TH and a plurality of lower holes BH. Specifically, one side of the active layer 130 may be electrically connected to the source electrode 170 through the first upper hole THa, the second upper hole THb, and the third upper hole THc, and one side of the active layer 130 may be electrically connected to the light blocking layer 110 through the first lower hole BHa, the second lower hole BHb, and the third lower hole BHc.

[0112] By being formed as described above, a contact area between the active layer 130 and the source electrode 170 may be increased, and thus a contact resistance between the active layer 130 and the source electrode 170 may be reduced.

[0113] The first upper hole THa and the second upper hole THb may be spaced apart from each other by a third distance d3, and the second upper hole THb and the third upper hole THc may be spaced apart from each other by a fourth distance d4. In this case, the third distance d3 and the fourth distance d4 may be the same as or different from each other.

[0114] On the other hand, although Figure 7A plurality of upper holes TH and a plurality of lower holes BH are shown arranged in a row in a first direction (e.g., horizontal direction), but the plurality of upper holes TH and the plurality of lower holes BH may be arranged in a row in a second direction (e.g., vertical direction) orthogonal to the first direction, and n upper holes TH and lower holes BH in the first direction and m upper holes TH and lower holes BH in the second direction may be arranged in a number of n×m.

[0115] Figure 8 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 8 The cross-sectional view of Figure 7 In addition, in addition to the configuration of the upper hole, the lower hole, the upper electrode and the lower electrode, Figure 8 Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0116] like Figure 8 As shown, the first connection portion 132a of the active layer 130 may be electrically connected to the source electrode 170 through the plurality of upper holes TH, and the first connection portion 132a of the active layer 130 may be electrically connected to the light blocking layer 110 through the source electrode 170 disposed in the plurality of lower holes BH.

[0117] The plurality of upper holes TH may include a first upper hole THa, a second upper hole THb, and a third upper hole THc, and the plurality of lower holes BH may include a first lower hole BHa, a second lower hole BHb, and a third lower hole BHc.

[0118] The plurality of upper holes TH may be formed by etching a portion of the gate insulating layer 140 and a portion of the interlayer insulating layer 160 from the upper surface of the active layer 130 , and the plurality of lower holes BH may be formed by etching a portion of the buffer layer 120 and a portion of the active layer 130 from the upper surface of the light blocking layer 110 .

[0119] The first upper hole THa may be connected to the first lower hole BHa, the second upper hole THb may be connected to the second lower hole BHb, and the third upper hole THc may be connected to the third lower hole BHc. In other words, each of the plurality of upper holes TH may correspond to the plurality of lower holes BH on a one-to-one basis. However, the present disclosure is not limited thereto, and one upper hole may correspond to a plurality of lower holes, as described in reference to Fig.10 In the embodiment described. Fig.10 Describe this aspect in detail.

[0120] Since the upper hole TH and the lower hole BH are formed in plural, the upper electrode 171 and the lower electrode 172 may also be formed in plural. In addition, in the drawings, for illustration, the upper electrode 171 and the lower electrode 172 are respectively formed in three, but the present disclosure is not limited thereto.

[0121] Specifically, the upper electrode 171 may include a first upper electrode 171a, a second upper electrode 171b, and a third upper electrode 171c, and the lower electrode 172 may include a first lower electrode 172a, a second lower electrode 172b, and a third lower electrode 172c. In this case, each of the plurality of upper electrodes 171a, 171b, and 171c may be defined as a portion of the source electrode 170 disposed in the plurality of upper holes THa, THb, and THc, and may be defined as a portion of the source electrode 170 disposed on the interlayer insulating layer 160, and each of the plurality of lower electrodes 172a, 172b, and 172c may be defined as a portion of the source electrode 170 disposed in the plurality of lower holes BHa, BHb, and BHc.

[0122] According to another embodiment of the present disclosure, since the source electrode 170 includes a plurality of upper electrodes 171a, 171b, and 171c and a plurality of lower electrodes 172a, 172b, and 172c, the contact area between some of the lower surfaces of the plurality of upper electrodes 171a, 171b, and 171c and the first connection portion 132a of the active layer 130 can be further increased. Therefore, since the contact resistance between the active layer 130 and the source electrode 170 is further reduced, when the thin film transistor substrate according to another embodiment of the present disclosure is driven, an improved on-current can be obtained.

[0123] Fig. 9 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the upper hole, according to Fig. 9 The thin film transistor substrate and the Figure 7 The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0124] like Fig. 9 As shown, the plurality of upper holes TH and the plurality of lower holes BH may not correspond to each other on a one-to-one basis. Specifically, the plurality of upper holes TH may include a first upper hole THa and a second upper hole THb, and the plurality of lower holes BH may include a first lower hole BHa, a second lower hole BHb, and a third lower hole BHc. In this case, the first upper hole THa may overlap with the first lower hole BHa and the second lower hole BHb, and the second upper hole THb may overlap with the third lower hole BHc.

[0125] According to another embodiment of the present disclosure, since the plurality of upper holes TH and the plurality of lower holes BH do not correspond to each other in a one-to-one manner, as in Figure 7Compared with the case where the plurality of upper holes and the plurality of lower holes overlap in a one-to-one manner in the embodiment of the present invention, the contact area between the active layer 130 and the source electrode 170 can be increased. Therefore, the contact resistance between the active layer 130 and the source electrode 170 can be further reduced.

[0126] Fig.10 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.10 The cross-sectional view of Fig. 9 In addition, in addition to the configuration of the upper hole and the upper electrode, Fig.10 Thin film transistor substrate and Figure 8 The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0127] like Fig.10 As shown, the first connection portion 132a of the active layer 130 may be electrically connected to the source electrode 170 through the plurality of upper holes TH, and the first connection portion 132a of the active layer 130 may be electrically connected to the light blocking layer 110 through the source electrode 170 disposed in the plurality of lower holes BH.

[0128] The plurality of upper holes TH may include first and second upper holes THa and THb, and the plurality of lower holes BH may include first, second, and third lower holes BHa, BHb, and BHc.

[0129] According to another embodiment of the present disclosure, the first upper hole THa may be connected to the first lower hole BHa and the second lower hole BHb, and the second upper hole THb may be connected to the third lower hole BHc. In other words, the plurality of upper holes TH may not correspond to the plurality of lower holes BH on a one-to-one basis.

[0130] Since the upper hole TH and the lower hole BH are formed in plural, the upper electrode 171 and the lower electrode 172 may also be formed in plural.

[0131] Specifically, the upper electrode 171 may include a first upper electrode 171 a and a second upper electrode 171 b , and the lower electrode 172 may include a first lower electrode 172 a , a second lower electrode 172 b , and a third lower electrode 172 c .

[0132] Since the first upper hole THa is connected to the first and second lower holes BHa and BHb, the first upper electrode 171 a may overlap with the first and second lower electrodes 172 a and 172 b and may be electrically connected.

[0133] The lower surface of the first upper electrode 171a may be in contact with a portion of the upper surface of the first connection portion 132a of the first active layer 130, the upper surface of the first lower electrode 172a, and the upper surface of the second lower electrode 172b. In this case, the lower surface of the first upper electrode 171a in contact with a portion of the upper surface of the first connection portion 132a may be in contact with the upper surface of the first connection portion 132a outside the first lower electrode 172a (e.g., on the left side), may be in contact with the upper surface of the first connection portion 132a outside the second lower electrode 172b (e.g., on the right side), and further, may be in contact with a portion of the upper surface of the first connection portion 132a between the first lower electrode 172a and the second lower electrode 172b.

[0134] In this case, a portion of the lower surface of the first upper electrode 171a that is in contact with the first connecting portion 132a between the first lower electrode 172a and the second lower electrode 172b can be said to be the lower surface of the first upper electrode 171a that is continuously connected to adjacent lower electrodes 172a and 172b among the multiple lower electrodes 172 and is in contact with a portion of the upper surface of the first connecting portion.

[0135] Since a portion of the lower surface of the first upper electrode 171a contacts a portion of the upper surface of the first connection portion 132a between the first lower electrode 172a and the second lower electrode 172b, a contact area between a portion of the upper surface of the first connection portion 132a of the active layer 130 and the lower surface of the upper electrode 171 can be increased. Therefore, according to another embodiment of the present disclosure, since the contact resistance between the active layer 130 and the source electrode 170 is further reduced, when the thin film transistor substrate according to another embodiment of the present disclosure is driven, an improved on-current can be obtained.

[0136] In addition, since the second upper electrode 171b and the third lower electrode 172c are Figure 2A or Figure 8 The configurations of the upper electrodes and the lower electrodes corresponding to each other on a one-to-one basis are the same, and thus a detailed description thereof will be omitted.

[0137] Fig.11 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the upper hole and the lower hole, according to Fig.11 The thin film transistor substrate and the Figure 1 The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0138] like Fig.11 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 170 , and a drain electrode 180 .

[0139] According to another embodiment of the present disclosure, one side of the active layer 130 may be electrically connected to the source electrode 170 and the light blocking layer 110 through a plurality of upper holes TH and a plurality of lower holes BH. Specifically, one side of the active layer 130 may be electrically connected to the source electrode 170 through the first upper hole THa and the second upper hole THb, and one side of the active layer 130 may be electrically connected to the light blocking layer 110 through the first lower hole BHa and the second lower hole BHb.

[0140] By being formed as described above, a contact area between the active layer 130 and the source electrode 170 may be increased, and thus a contact resistance between the active layer 130 and the source electrode 170 may be reduced.

[0141] According to another embodiment of the present disclosure, the area of ​​each of the plurality of upper holes TH may be different, and the area of ​​each of the plurality of lower holes BH may be different. Specifically, the area of ​​the second upper hole THb may be larger than the area of ​​the first upper hole THa, and the area of ​​the second lower hole BHb may be larger than the area of ​​the first lower hole BHa. By forming in this way, the contact area between the active layer 130 and the source electrode 170 may be increased compared to the case where the area of ​​each of the plurality of upper holes TH is the same and the area of ​​each of the plurality of lower holes BH is the same. Therefore, the contact resistance between the active layer 130 and the source electrode 170 may be reduced.

[0142] Fig.12 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.12 The cross-sectional view of Fig.11 In addition, in addition to the configuration of the upper hole, the lower hole, the upper electrode and the lower electrode, Fig.12 Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same, so the different configurations will be mainly described below.

[0143] like Fig.12 As shown, the first connection portion 132a of the active layer 130 may be electrically connected to the source electrode 170 through the plurality of upper holes TH, and the first connection portion 132a of the active layer 130 may be electrically connected to the light blocking layer 110 through the source electrode 170 disposed in the plurality of lower holes BH.

[0144] The plurality of upper holes TH may include first and second upper holes THa and THb, and the plurality of lower holes BH may include first and second lower holes BHa and BHb.

[0145] The plurality of upper holes TH may be formed by etching a portion of the gate insulating layer 140 and a portion of the interlayer insulating layer 160 from the upper surface of the active layer 130 , and the plurality of lower holes BH may be formed by etching a portion of the buffer layer 120 and a portion of the active layer 130 from the upper surface of the light blocking layer 110 .

[0146] The first upper hole THa may be connected to the first lower hole BHa, and the second upper hole THb may be connected to the second lower hole BHb. In other words, each of the plurality of upper holes TH may correspond to the plurality of lower holes BH on a one-to-one basis.

[0147] According to another embodiment of the present disclosure, since the contact area between the second upper electrode 171b and a portion of the upper surface of the first connection portion 132a of the active layer 130 is larger than the contact area between the first upper electrode 171a and a portion of the upper surface of the first connection portion 132a of the active layer 130, the contact area between the active layer 130 and the source electrode 170 can be increased, and the contact resistance between the active layer 130 and the source electrode 170 can be reduced. Therefore, when the thin film transistor substrate according to another embodiment of the present disclosure is driven, an improved on-current can be obtained.

[0148] Fig.13 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0149] like Fig.13 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a first thin film transistor TR1 and a second thin film transistor TR2.

[0150] The display device may include a display area and a non-display area, a plurality of pixels may be disposed in the display area, and a gate driving circuit may be disposed in the non-display area.

[0151] Any one of the plurality of pixels includes a plurality of thin film transistors, any of the plurality of thin film transistors may include a driving thin film transistor for driving the pixel, and another thin film transistor among the plurality of thin film transistors may include a switching thin film transistor for transmitting a data signal to the driving thin film transistor. In addition, the gate drive circuit may also include a plurality of thin film transistors.

[0152] like Fig.13 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a first thin film transistor TR1 and a second thin film transistor TR2, the first thin film transistor TR1 may be a driving thin film transistor set in any one of a plurality of pixels, and the second thin film transistor TR2 may be a switching thin film transistor set in any one of a plurality of pixels or any one of a plurality of thin film transistors set in a selection drive circuit.

[0153] The first thin film transistor TR1 may include a substrate 100, a first light blocking layer 110, a buffer layer 120, a first active layer 130, a gate insulating layer 140, a first gate electrode 150, an interlayer insulating layer 160, a first source electrode 170, and a first drain electrode 180. In addition, the first light blocking layer 110, the first active layer 130, the first gate electrode 150, the first source electrode 170, and the first drain electrode 180 of the first thin film transistor are the same as those described above. Figure 8 The thin film transistor substrate of the embodiment is the same as those in FIG. 1 , and thus a repeated description thereof will be omitted.

[0154] The second thin film transistor TR2 may include a substrate 100, a buffer layer 120, a second active layer 230, a gate insulating layer 140, a second gate electrode 250, an interlayer insulating layer 160, a second source electrode 270, and a second drain electrode 280. In addition, the substrate 100, the buffer layer 120, the gate insulating layer 140, and the interlayer insulating layer 160 are connected to Figure 8 The configurations are the same as those described in , so the following will mainly describe different configurations.

[0155] The second active layer 230 may be disposed on the buffer layer 120 .

[0156] The second active layer 230 may include a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0157] The second active layer 230 may include a channel portion 231, a first connection portion 232a connected to one side (e.g., right side) of the channel portion 231, and a second connection portion 232b connected to the other side (e.g., left side) of the channel portion 231. The first connection portion 232a and the second connection portion 232b may have conductive properties through a conductive process in which ion doping or plasma treatment is performed on a semiconductor material using the second gate electrode 250 as a mask, and the first connection portion 232a and the second connection portion 232b have better conductivity than the channel portion 231, and each may be used as a wiring or a source / drain electrode.

[0158] The second gate electrode 250 may be disposed on the gate insulating layer 140. The second gate electrode 250 may be disposed on the second active layer 230. Specifically, the second gate electrode 250 may overlap the channel portion 231 of the second active layer 230.

[0159] The second gate electrode 250 may include at least one of an aluminum-based metal such as aluminum Al or an aluminum alloy, a silver-based metal such as silver Ag or a silver alloy, a copper-based metal such as copper Cu or a copper alloy, a molybdenum-based metal such as molybdenum Mo or a molybdenum alloy, chromium Cr, tantalum Ta, neodymium Nd, and titanium Ti. The second gate electrode 250 may have a structure including one metal layer or a multi-layer structure including at least two metal layers each having different physical properties.

[0160] A first contact hole CH1 and a second contact hole CH2 may be provided in the interlayer insulating layer 160, and thus a portion of an upper surface of the first connection portion 232a of the second active layer 230 may be exposed by the first contact hole CH1, and a portion of an upper surface of the second connection portion 232b of the second active layer 230 may be exposed by the second contact hole CH2.

[0161] The second source electrode 270 and the second drain electrode 280 may be disposed on the interlayer insulating layer 160. The second source electrode 270 and the second drain electrode 280 may be formed of the same material as the second gate electrode, but are not limited thereto and may be formed of a material according to knowledge in the art.

[0162] The second source electrode 270 may be electrically connected to the first connection portion 232 a of the second active layer 230 through the first contact hole CH1 , and the second drain electrode 280 may be electrically connected to the second connection portion 232 b of the second active layer through the second contact hole CH2 .

[0163] According to another configuration of the present disclosure, when the first thin film transistor TR1 can be any one of the driving thin film transistors set in a plurality of pixels, and the second thin film transistor TR2 can be a switching thin film transistor set in a plurality of pixels or any one of a plurality of thin film transistors set in a gate drive circuit, the driving thin film transistor made of the first thin film transistor TR1 can easily express grayscale through a large capacitor, and the switching thin film transistor made of the second thin film transistor TR2 or the thin film transistor set in the gate drive circuit can maintain the on-current characteristics.

[0164] Fig.14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the first buffer layer and the second light blocking layer being disposed in the second thin film transistor, Fig.14 The implementation method and Fig.13 The implementation methods are the same, so the following will mainly describe different configurations.

[0165] like Fig.14 As shown, the second thin film transistor TR2 may include a substrate 100, a second light blocking layer 210, a first buffer layer 120a, a second buffer layer 120b, a second active layer 230, a gate insulating layer 140, a second gate electrode 250, an interlayer insulating layer 160, a second source electrode 270, and a second drain electrode 280.

[0166] The second light blocking layer 210 may be disposed on the substrate 100. The second light blocking layer 210 may be formed of a metal or a metal oxide, and may be formed of one metal layer or a metal oxide layer, or may be formed of two or more metal layers or metal oxide layers. The material of the second light blocking layer 210 may be different from that of the first light blocking layer 110, but is not limited thereto.

[0167] The second light blocking layer 210 may be disposed below the second active layer 230 and overlap the second active layer 230, thereby preventing light introduced from outside the thin film transistor substrate from being introduced into the second active layer 230. Specifically, the second light blocking layer 210 may prevent external light from being introduced into the channel portion 231 of the second active layer 230. In addition, although not shown, the second light blocking layer 210 may be electrically connected to the second gate electrode 250. When the second light blocking layer 210 is electrically connected to the second gate electrode 250, the second thin film transistor TR2 may have a double gate structure in which gate electrodes are disposed above and below the second active layer 230.

[0168] The first buffer layer 120a may be disposed on the second light blocking layer 210. The first buffer layer 120a may be formed of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto, and may be formed of an organic insulating material. The first buffer layer 120a may be formed of a single layer or a plurality of layers.

[0169] The second buffer layer 120b may be disposed on the first buffer layer 120a and the first light blocking layer 110. Figure 2A , Figure 2B , Figure 4 , Figure 6 , Figure 8 , Fig.10 and Fig.12 The configuration of the buffer layer is the same as that described in , so its detailed description will be omitted.

[0170] According to another configuration of the present disclosure, the second thin film transistor TR2 may be any one of the switching thin film transistors provided in the plurality of pixels, and in this case, since the second thin film transistor TR2 has a dual-gate structure, the on-current characteristic can be further increased. Therefore, the driving thin film transistor of any one of the plurality of pixels is made of the first thin film transistor TR1, and the switching thin film transistor of any one of the plurality of pixels is made of the second thin film transistor TR2, so that the thin film transistor substrate according to the configuration of the present disclosure can easily express grayscale and improve the on-current characteristic.

[0171] FIG. 15A to FIG. 15E is a cross-sectional view illustrating a method of forming a thin film transistor substrate according to an embodiment of the present disclosure.

[0172] First, if Fig.15A As shown, a light blocking layer 110 is formed on a substrate 100 , a buffer layer 120 is formed on the light blocking layer 110 , and then an oxide semiconductor layer 130 a is formed to form an active layer on the buffer layer 120 .

[0173] Next, if Fig. 15B As shown, the active layer 130 may be formed by patterning the oxide semiconductor layer 130a using a mask 130b. In this case, the mask 130b is provided with an opening OP, and when the active layer 130 is patterned, an active hole AH may be formed in a region corresponding to the opening OP on the active layer 130. The active hole AH may expose an inner region of the active layer 130 to the outside, and may expose a portion of the upper surface of the buffer layer 120 to the outside.

[0174] Next, if Fig. 15C As shown, a gate insulating layer 140 may be formed on the active layer 130 , a gate electrode 150 may be formed on the gate insulating layer 140 , and an interlayer insulating layer 160 may be formed on the gate electrode 150 .

[0175] Then, after forming the interlayer insulating layer 160, the active layer 130 performs a conductive process using the gate electrode 150 as a mask, so that conductive properties can be provided in a partial region of the active layer 130. Therefore, the active layer 130 may include a channel portion 131, a first connection portion 132a provided at one side of the channel portion 131, and a second connection portion 132b provided at the other side of the channel portion 131.

[0176] After the conduction process of the active layer 130, the upper hole TH may be formed by etching a portion of the gate insulating layer 140 and a portion of the interlayer insulating layer 160 disposed on the first connection portion 132a, and the drain hole DH may be formed by etching a portion of the gate insulating layer 140 and a portion of the interlayer insulating layer 160 disposed on the second connection portion 132b. The upper hole TH may expose a portion of the upper surface of the first connection portion 132a of the active layer 130, the active hole AH, and a portion of the buffer layer 120 to the outside, and the drain hole DH may expose a portion of the upper surface of the second connection portion 132b of the active layer 130 to the outside.

[0177] Next, if Fig.15D As shown, the lower hole BH can be formed by dry etching the portion of the buffer layer 120 exposed by the upper hole TH and the active hole AH. In this case, by forming the lower hole BH using dry etching, the partial area of ​​the etched buffer layer 120 can be accurately controlled. Specifically, when the lower hole BH is formed using wet etching, the size of the active hole AH of the active layer 130 may be changed, and by using dry etching, the partial area of ​​the buffer layer 120 can be etched while the size of the active hole AH is constantly maintained.

[0178] When the lower hole BH is formed, a partial area of ​​the upper surface of the light blocking layer 110 may be exposed to the outside.

[0179] Next, if Fig.15E As shown, a source electrode 170 may be formed in the upper hole TH and the lower hole BH, and a drain electrode 180 may be formed in the drain hole DH to form a thin film transistor substrate according to one embodiment of the present disclosure.

[0180] Fig.16 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present disclosure.

[0181] like Fig.16 As shown, a display device according to an embodiment of the present disclosure may include a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 170, a drain electrode 180, a planarization layer 190, a first electrode 300, a dam layer 310, a light emitting layer 320 and a second electrode 330.

[0182] The substrate 100 , the light blocking layer 110 , the buffer layer 120 , the active layer 130 , the gate insulating layer 140 , the gate electrode 150 , the interlayer insulating layer 160 , the source electrode 170 , and the drain electrode 180 are the same as those described above, and a repeated description thereof will be omitted.

[0183] The third contact hole CH3 may be provided on the planarization layer 190 such that the source electrode 170 is exposed by the third contact hole CH3. However, in some cases, the drain electrode 180 may be exposed by the third contact hole CH3.

[0184] The first electrode 300 may be formed on the planarization layer 190, and may be connected to the source electrode 170 or the drain electrode 180 through the third contact hole CH3. The first electrode 300 may function as an anode.

[0185] The bank layer 310 may be provided to cover the edge of the first electrode 300 to define a light emitting region. Therefore, an upper surface region of the first electrode 300 that is not covered by the bank layer 310 and is exposed becomes a light emitting region.

[0186] The light emitting layer 320 may be disposed on the first electrode 300. The light emitting layer 320 may include a red light emitting layer, a green light emitting layer, and a blue light emitting layer patterned for each pixel, or may be formed of a white light emitting layer connected from all pixels. When the light emitting layer 320 is formed of a white light emitting layer, the light emitting layer 320 may include, for example, a first stack including a blue light emitting layer, a second stack including a yellow-green light emitting layer, and a charge generation layer disposed between the first stack and the second stack, but is not limited thereto.

[0187] The second electrode 330 may be disposed on the light emitting layer 320. The second electrode 330 may function as a cathode.

[0188] Although not shown, an encapsulation layer for preventing penetration of moisture or oxygen may be additionally formed on the second electrode 330 .

[0189] Fig.17 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0190] like Fig.17 As shown, the display device according to one embodiment of the present disclosure may include a display panel 410 , a gate driver 420 , a data driver 430 , and a controller 440 .

[0191] The display panel 410 includes gate lines GL and data lines DL, and pixels P are disposed in respective crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on the substrate 100 .

[0192] The controller 440 controls the gate driver 420 and the data driver 430. The controller 440 outputs a gate control signal GCS for controlling the gate driver 420 and a data control signal DCS for controlling the data driver 430 by using a signal supplied from an external system (not shown). In addition, the controller 440 samples input video data input from the external system and rearranges the sampled input video data, and supplies the rearranged digital video data RGB to the data driver 430.

[0193] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0194] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0195] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. Specifically, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0196] The gate driver 420 may be mounted on the display panel 410. As described above, the structure in which the gate driver 420 is directly mounted on the display panel 410 is called a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 420 may be disposed on the substrate 100.

[0197] The gate driver 420 may include a shift register 450 .

[0198] The shift register 450 sequentially supplies a gate pulse to the gate line GL during one frame by using a start signal and a gate clock transmitted from the controller 440. Herein, one frame refers to a period during which one image is output through the display panel 410. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0199] In addition, during the remaining period of one frame in which the gate pulse is not supplied, the shift register 450 supplies a gate-off signal capable of turning off the switching device to the gate line GL. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a gate signal GS.

[0200] Fig.18 is a circuit diagram of one pixel provided in a display device according to one embodiment of the present disclosure.

[0201] like Fig.18 As shown, the display device according to one embodiment of the present disclosure includes a first thin film transistor T1 and a second thin film transistor T2 and a capacitor Cst.

[0202] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 may be formed of the above-described various thin film transistors.

[0203] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage Vdd supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0204] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0205] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is disposed between a gate electrode and a source electrode of the first thin film transistor T1.

[0206] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0207] Fig.19 is a circuit diagram of one pixel provided in a display device according to another embodiment of the present disclosure.

[0208] like Fig.19 As shown, a display device according to another embodiment of the present disclosure includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3 and a capacitor Cst.

[0209] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 and the third thin film transistor T3 are switching thin film transistors. At least one of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 may be formed of the above-mentioned various thin film transistors.

[0210] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage Vdd supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0211] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0212] The third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL in response to the sensing control signal SENSE supplied from the scan line SCL. A reference voltage Vref is supplied to the reference line RL.

[0213] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is disposed between a gate electrode and a source electrode of the first thin film transistor T1.

[0214] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0215] Fig. 20 is a circuit diagram of one pixel provided in a display device according to another embodiment of the present disclosure.

[0216] like Fig. 20 As shown, a display device according to another embodiment of the present disclosure includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4, and a capacitor Cst.

[0217] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are switching thin film transistors. At least one of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 may be formed by the above-mentioned various thin film transistors.

[0218] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage Vdd supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0219] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0220] The third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL in response to the sensing control signal SENSE supplied from the scan line SCL. A reference voltage Vref is supplied to the reference line RL.

[0221] The fourth thin film transistor T4 is switched according to the emission control signal EM supplied to the emission control line EML, and supplies the driving voltage Vdd supplied from the power line PL to the first thin film transistor T1 .

[0222] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is disposed between a gate electrode and a source electrode of the first thin film transistor T1.

[0223] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0224] Therefore, the present disclosure may have the following advantages.

[0225] According to one embodiment of the present disclosure, since a lower hole is provided at one side of the active layer and the source electrode is formed to penetrate the lower hole, the active layer, the source electrode and the light blocking layer provided under the active layer are connected to each other, so that the active layer and the light blocking layer can be electrically connected without connecting electrodes.

[0226] According to one embodiment of the present disclosure, an active layer and a light blocking layer are electrically connected through a source electrode provided in a lower hole provided in one side of the active layer, thereby reducing the size of a thin film transistor and securing an additional space for forming other wirings and electrodes.

[0227] According to one embodiment of the present disclosure, since the active layer and the light blocking layer are electrically connected through the source electrode disposed in the lower hole, the S factor of the driving thin film transistor may be improved to facilitate grayscale expression.

[0228] According to one embodiment of the present disclosure, since the lower surface of the upper electrode contacts a portion of the upper surface of the active layer, and the lower electrode contacts the side surface of the active layer, the contact area between the active layer and the source electrode is increased, thereby reducing the contact resistance between the active layer and the source electrode.

[0229] It is obvious to those skilled in the art that various substitutions, modifications and variations within the scope of the present disclosure are possible without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is represented by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims should be interpreted as included within the scope of the present disclosure.

[0230] CROSS-REFERENCE TO RELATED APPLICATIONS

[0231] This application claims the benefit of Korean Patent Application No. 10-2023-0081683, filed on Jun. 26, 2023, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A thin film transistor substrate, comprising: substrate; a light blocking layer, the light blocking layer being disposed on the substrate; an active layer disposed on the light blocking layer and comprising a lower hole disposed on one side of the active layer; a gate electrode, the gate electrode being disposed on the active layer; a source electrode disposed on the gate electrode and electrically connected to the active layer and the light blocking layer; as well as an insulating layer, the insulating layer being disposed between the active layer and the source electrode and comprising an upper hole, The source electrode includes a lower electrode disposed in the lower hole and an upper electrode disposed in the upper hole. The active layer and the light blocking layer are electrically connected through the lower electrode, And the area of ​​the lower surface of the upper electrode is larger than the area of ​​the upper surface of the lower electrode.

2. The thin film transistor substrate according to claim 1, in, The upper hole and the lower hole are continuous.

3. The thin film transistor substrate according to claim 1, in, The upper electrode contacts an entire upper surface of the lower electrode and a portion of an upper surface of the active layer.

4. The thin film transistor substrate according to claim 1, in, A distance from one end of the lower surface of the upper electrode to the lower hole is greater than a distance from the other end of the lower surface of the upper electrode to the lower hole.

5. The thin film transistor substrate according to claim 1, further comprising: a drain hole, wherein the drain hole is arranged in the insulating layer; as well as a drain electrode disposed on the gate electrode and connected to one side of the active layer through the drain hole, Wherein, the size of the upper hole is larger than the size of the drain hole.

6. The thin film transistor substrate according to claim 1, further comprising: a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode, wherein one end of the gate insulating layer coincides with one end of the gate electrode, and the other end of the gate insulating layer coincides with the other end of the gate electrode, And the insulating layer includes an interlayer insulating layer contacting a portion of an upper surface of the active layer.

7. The thin film transistor substrate according to claim 1, in, The insulating layer comprises: a gate insulating layer disposed between the active layer and the gate electrode and disposed on the entire surface of the substrate; and An interlayer insulating layer is disposed on the gate insulating layer.

8. The thin film transistor substrate according to claim 1, in, The lower holes include active holes and buffer holes. The lower electrode comprises: A first portion disposed in the active hole and a second portion disposed in the buffer hole, and An area of ​​a lower surface of the first portion is larger than an area of ​​an upper surface of the second portion.

9. The thin film transistor substrate according to claim 1, in, The lower hole and the upper hole do not overlap with the gate electrode.

10. The thin film transistor substrate according to claim 1, in, The active layer includes a channel portion, a first connection portion disposed on one side of the channel portion, and a second connection portion disposed on the other side of the channel portion, And the lower electrode is provided in one of the first connection portion and the second connection portion, but is not provided in the other of the first connection portion and the second connection portion.

11. The thin film transistor substrate according to claim 1, in, The active layer includes at least one of an indium zinc oxide (IZO)-based oxide semiconductor material, an indium gallium zinc oxide (IGZO)-based oxide semiconductor material, an indium zinc tin oxide (IZTO)-based oxide semiconductor material, and a ZnO-based oxide semiconductor material.

12. The thin film transistor substrate according to claim 1, in, The lower electrode comprises a plurality of lower electrodes, And each of the plurality of lower electrodes is spaced apart from each other.

13. The thin film transistor substrate according to claim 12, in, The upper electrode includes a plurality of upper electrodes, And the plurality of upper electrodes and the plurality of lower electrodes correspond to each other on a one-to-one basis.

14. The thin film transistor substrate according to claim 12, in, The upper electrode is continuous between adjacent lower electrodes among the plurality of lower electrodes.

15. The thin film transistor substrate according to claim 12, in, The plurality of lower electrodes have different sizes.

16. A method for manufacturing a thin film transistor substrate, the method comprising the following steps: forming a light blocking layer on the substrate; forming an active layer on the light blocking layer; A step of forming an active hole on one side of the active layer; forming a gate insulating layer on the active layer having the active hole formed therein; forming a gate electrode on the gate insulating layer; forming an interlayer insulating layer on the gate electrode; forming an upper hole in the gate insulating layer and the interlayer insulating layer; forming a lower hole exposing a portion of the light blocking layer by extending the active hole; as well as The step of forming source electrodes inside the lower hole and inside the upper hole.

17. The method for manufacturing a thin film transistor substrate according to claim 16, in, The area of ​​the lower surface of the upper hole is larger than the area of ​​the upper surface of the lower hole.

18. The method for manufacturing a thin film transistor substrate according to claim 16, in, The step of forming the active hole on one side of the active layer comprises: The step of forming a plurality of active holes; and The step of forming the lower holes includes the step of forming a plurality of lower holes exposing the light blocking layer by extending the plurality of active holes.

19. The method for manufacturing a thin film transistor substrate according to claim 16, further comprising the following steps: forming drain holes in the gate insulating layer and the interlayer insulating layer, wherein the drain hole is formed to face the upper hole relative to the gate electrode, And the drain hole is formed to have a size smaller than that of the upper hole.

20. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; a first thin film transistor, wherein the first thin film transistor is disposed on the substrate; as well as a second thin film transistor having a structure different from that of the first thin film transistor, Wherein, the first thin film transistor comprises: a first light blocking layer; a first active layer, the first active layer being disposed on the first light blocking layer and having a lower hole disposed on one side of the first active layer; a first gate electrode, wherein the first gate electrode is disposed on the first active layer; a first source electrode disposed on the first gate electrode and electrically connected to the first active layer and the first light blocking layer; and an insulating layer, the insulating layer being disposed between the first active layer and the first source electrode and having an upper hole, The first source electrode includes a lower electrode disposed in the lower hole and an upper electrode disposed in the upper hole. The first active layer and the first light blocking layer are electrically connected through the lower electrode, And the area of ​​the lower surface of the upper electrode is larger than the area of ​​the upper surface of the lower electrode.

21. The display device according to claim 20, in, The first thin film transistor comprises: a driving thin film transistor, the driving thin film transistor being arranged in the display area, and The second thin film transistor includes a switching thin film transistor disposed in the display area or any thin film transistor in a gate driver disposed in the non-display area.

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